/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loops/insertion_sort-1.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-34549b5 [2022-04-07 21:59:25,044 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-07 21:59:25,045 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-07 21:59:25,070 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-07 21:59:25,070 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-07 21:59:25,072 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-07 21:59:25,074 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-07 21:59:25,079 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-07 21:59:25,081 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-07 21:59:25,085 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-07 21:59:25,086 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-07 21:59:25,088 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-07 21:59:25,088 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-07 21:59:25,090 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-07 21:59:25,091 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-07 21:59:25,092 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-07 21:59:25,092 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-07 21:59:25,093 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-07 21:59:25,096 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-07 21:59:25,101 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-07 21:59:25,103 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-07 21:59:25,104 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-07 21:59:25,105 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-07 21:59:25,106 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-07 21:59:25,107 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-07 21:59:25,112 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-07 21:59:25,121 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-07 21:59:25,121 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-07 21:59:25,122 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-07 21:59:25,123 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-07 21:59:25,148 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-07 21:59:25,149 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-07 21:59:25,149 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-07 21:59:25,149 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-07 21:59:25,150 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-07 21:59:25,150 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-07 21:59:25,150 INFO L138 SettingsManager]: * Use SBE=true [2022-04-07 21:59:25,151 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-07 21:59:25,151 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-07 21:59:25,151 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-07 21:59:25,151 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-07 21:59:25,152 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-07 21:59:25,152 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 21:59:25,153 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-07 21:59:25,153 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-07 21:59:25,153 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-07 21:59:25,153 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-07 21:59:25,153 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-07 21:59:25,153 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-07 21:59:25,154 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-07 21:59:25,154 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-07 21:59:25,155 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-07 21:59:25,155 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-07 21:59:25,348 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-07 21:59:25,369 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-07 21:59:25,371 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-07 21:59:25,371 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-07 21:59:25,372 INFO L275 PluginConnector]: CDTParser initialized [2022-04-07 21:59:25,373 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops/insertion_sort-1.c [2022-04-07 21:59:25,421 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/64ae6c16d/f7a7ed81376f4f1aa0b839c915267539/FLAG8223e755c [2022-04-07 21:59:25,766 INFO L306 CDTParser]: Found 1 translation units. [2022-04-07 21:59:25,767 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c [2022-04-07 21:59:25,770 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/64ae6c16d/f7a7ed81376f4f1aa0b839c915267539/FLAG8223e755c [2022-04-07 21:59:25,779 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/64ae6c16d/f7a7ed81376f4f1aa0b839c915267539 [2022-04-07 21:59:25,780 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-07 21:59:25,781 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-07 21:59:25,782 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-07 21:59:25,782 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-07 21:59:25,785 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-07 21:59:25,789 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:25,790 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6f7771fa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25, skipping insertion in model container [2022-04-07 21:59:25,790 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:25,794 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-07 21:59:25,804 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-07 21:59:25,931 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c[328,341] [2022-04-07 21:59:25,951 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 21:59:25,957 INFO L203 MainTranslator]: Completed pre-run [2022-04-07 21:59:25,968 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c[328,341] [2022-04-07 21:59:25,980 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-07 21:59:25,990 INFO L208 MainTranslator]: Completed translation [2022-04-07 21:59:25,991 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25 WrapperNode [2022-04-07 21:59:25,991 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-07 21:59:25,992 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-07 21:59:25,992 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-07 21:59:25,992 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-07 21:59:26,008 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,008 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,012 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,012 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,018 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,022 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,023 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,024 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-07 21:59:26,025 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-07 21:59:26,025 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-07 21:59:26,025 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-07 21:59:26,026 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (1/1) ... [2022-04-07 21:59:26,034 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-07 21:59:26,042 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:26,052 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-07 21:59:26,058 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-07 21:59:26,079 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-07 21:59:26,079 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-07 21:59:26,080 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-07 21:59:26,080 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-07 21:59:26,081 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-07 21:59:26,081 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-07 21:59:26,081 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-07 21:59:26,082 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-07 21:59:26,082 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-07 21:59:26,082 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-07 21:59:26,082 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-07 21:59:26,082 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2022-04-07 21:59:26,083 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-07 21:59:26,083 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-07 21:59:26,083 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-07 21:59:26,083 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-07 21:59:26,085 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-07 21:59:26,085 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-07 21:59:26,086 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-07 21:59:26,086 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-07 21:59:26,131 INFO L234 CfgBuilder]: Building ICFG [2022-04-07 21:59:26,132 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-07 21:59:26,339 INFO L275 CfgBuilder]: Performing block encoding [2022-04-07 21:59:26,343 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-07 21:59:26,343 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-07 21:59:26,345 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 09:59:26 BoogieIcfgContainer [2022-04-07 21:59:26,345 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-07 21:59:26,345 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-07 21:59:26,345 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-07 21:59:26,346 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-07 21:59:26,348 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 09:59:26" (1/1) ... [2022-04-07 21:59:26,352 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-07 21:59:26,375 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 09:59:26 BasicIcfg [2022-04-07 21:59:26,375 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-07 21:59:26,376 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-07 21:59:26,377 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-07 21:59:26,378 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-07 21:59:26,379 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 07.04 09:59:25" (1/4) ... [2022-04-07 21:59:26,379 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2f36bac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 09:59:26, skipping insertion in model container [2022-04-07 21:59:26,379 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 07.04 09:59:25" (2/4) ... [2022-04-07 21:59:26,379 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2f36bac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 07.04 09:59:26, skipping insertion in model container [2022-04-07 21:59:26,379 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 07.04 09:59:26" (3/4) ... [2022-04-07 21:59:26,380 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2f36bac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 07.04 09:59:26, skipping insertion in model container [2022-04-07 21:59:26,380 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 07.04 09:59:26" (4/4) ... [2022-04-07 21:59:26,380 INFO L111 eAbstractionObserver]: Analyzing ICFG insertion_sort-1.cqvasr [2022-04-07 21:59:26,397 INFO L203 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-07 21:59:26,398 INFO L162 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-07 21:59:26,444 INFO L339 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-07 21:59:26,449 INFO L340 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP [2022-04-07 21:59:26,449 INFO L341 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-07 21:59:26,466 INFO L276 IsEmpty]: Start isEmpty. Operand has 33 states, 25 states have (on average 1.48) internal successors, (37), 26 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:26,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-07 21:59:26,469 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:26,470 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:26,470 INFO L403 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:26,475 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:26,475 INFO L85 PathProgramCache]: Analyzing trace with hash -1926103570, now seen corresponding path program 1 times [2022-04-07 21:59:26,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:26,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [495423021] [2022-04-07 21:59:26,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:26,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:26,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:26,624 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:26,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:26,636 INFO L290 TraceCheckUtils]: 0: Hoare triple {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {36#true} is VALID [2022-04-07 21:59:26,636 INFO L290 TraceCheckUtils]: 1: Hoare triple {36#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 21:59:26,636 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {36#true} {36#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 21:59:26,638 INFO L272 TraceCheckUtils]: 0: Hoare triple {36#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:26,638 INFO L290 TraceCheckUtils]: 1: Hoare triple {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {36#true} is VALID [2022-04-07 21:59:26,638 INFO L290 TraceCheckUtils]: 2: Hoare triple {36#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 21:59:26,638 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {36#true} {36#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 21:59:26,639 INFO L272 TraceCheckUtils]: 4: Hoare triple {36#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-07 21:59:26,639 INFO L290 TraceCheckUtils]: 5: Hoare triple {36#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {36#true} is VALID [2022-04-07 21:59:26,647 INFO L290 TraceCheckUtils]: 6: Hoare triple {36#true} [103] L17-3-->L17-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 21:59:26,648 INFO L290 TraceCheckUtils]: 7: Hoare triple {37#false} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {37#false} is VALID [2022-04-07 21:59:26,648 INFO L290 TraceCheckUtils]: 8: Hoare triple {37#false} [108] L19-3-->L19-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 21:59:26,648 INFO L290 TraceCheckUtils]: 9: Hoare triple {37#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {37#false} is VALID [2022-04-07 21:59:26,648 INFO L290 TraceCheckUtils]: 10: Hoare triple {37#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {37#false} is VALID [2022-04-07 21:59:26,649 INFO L272 TraceCheckUtils]: 11: Hoare triple {37#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {37#false} is VALID [2022-04-07 21:59:26,649 INFO L290 TraceCheckUtils]: 12: Hoare triple {37#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {37#false} is VALID [2022-04-07 21:59:26,649 INFO L290 TraceCheckUtils]: 13: Hoare triple {37#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 21:59:26,649 INFO L290 TraceCheckUtils]: 14: Hoare triple {37#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-07 21:59:26,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:26,650 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:26,650 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [495423021] [2022-04-07 21:59:26,650 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [495423021] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 21:59:26,651 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 21:59:26,651 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-07 21:59:26,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [882994710] [2022-04-07 21:59:26,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 21:59:26,655 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 21:59:26,656 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:26,658 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:26,676 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:26,677 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-07 21:59:26,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:26,689 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-07 21:59:26,689 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 21:59:26,691 INFO L87 Difference]: Start difference. First operand has 33 states, 25 states have (on average 1.48) internal successors, (37), 26 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:26,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:26,794 INFO L93 Difference]: Finished difference Result 58 states and 77 transitions. [2022-04-07 21:59:26,794 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-07 21:59:26,794 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 21:59:26,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:26,795 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:26,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 77 transitions. [2022-04-07 21:59:26,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:26,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 77 transitions. [2022-04-07 21:59:26,810 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 77 transitions. [2022-04-07 21:59:26,884 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 77 edges. 77 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:26,890 INFO L225 Difference]: With dead ends: 58 [2022-04-07 21:59:26,890 INFO L226 Difference]: Without dead ends: 28 [2022-04-07 21:59:26,892 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-07 21:59:26,894 INFO L913 BasicCegarLoop]: 37 mSDtfsCounter, 29 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:26,895 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [30 Valid, 40 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 21:59:26,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-07 21:59:26,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2022-04-07 21:59:26,914 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:26,914 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:26,915 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:26,915 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:26,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:26,917 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-07 21:59:26,917 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-07 21:59:26,918 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:26,918 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:26,918 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-07 21:59:26,918 INFO L87 Difference]: Start difference. First operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-07 21:59:26,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:26,920 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-07 21:59:26,920 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-07 21:59:26,920 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:26,920 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:26,921 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:26,921 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:26,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:26,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2022-04-07 21:59:26,924 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 15 [2022-04-07 21:59:26,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:26,924 INFO L478 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-04-07 21:59:26,925 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:26,925 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-07 21:59:26,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-07 21:59:26,925 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:26,925 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:26,925 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-07 21:59:26,926 INFO L403 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:26,926 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:26,926 INFO L85 PathProgramCache]: Analyzing trace with hash 1448912944, now seen corresponding path program 1 times [2022-04-07 21:59:26,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:26,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001600800] [2022-04-07 21:59:26,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:26,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:26,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:27,073 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:27,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:27,096 INFO L290 TraceCheckUtils]: 0: Hoare triple {219#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {211#true} is VALID [2022-04-07 21:59:27,097 INFO L290 TraceCheckUtils]: 1: Hoare triple {211#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-07 21:59:27,097 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {211#true} {211#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-07 21:59:27,098 INFO L272 TraceCheckUtils]: 0: Hoare triple {211#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {219#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:27,098 INFO L290 TraceCheckUtils]: 1: Hoare triple {219#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {211#true} is VALID [2022-04-07 21:59:27,098 INFO L290 TraceCheckUtils]: 2: Hoare triple {211#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-07 21:59:27,099 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {211#true} {211#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-07 21:59:27,099 INFO L272 TraceCheckUtils]: 4: Hoare triple {211#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-07 21:59:27,099 INFO L290 TraceCheckUtils]: 5: Hoare triple {211#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {216#(= main_~j~0 0)} is VALID [2022-04-07 21:59:27,100 INFO L290 TraceCheckUtils]: 6: Hoare triple {216#(= main_~j~0 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-07 21:59:27,101 INFO L290 TraceCheckUtils]: 7: Hoare triple {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-07 21:59:27,101 INFO L290 TraceCheckUtils]: 8: Hoare triple {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-07 21:59:27,102 INFO L290 TraceCheckUtils]: 9: Hoare triple {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {218#(and (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:27,103 INFO L290 TraceCheckUtils]: 10: Hoare triple {218#(and (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {212#false} is VALID [2022-04-07 21:59:27,103 INFO L272 TraceCheckUtils]: 11: Hoare triple {212#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {212#false} is VALID [2022-04-07 21:59:27,103 INFO L290 TraceCheckUtils]: 12: Hoare triple {212#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {212#false} is VALID [2022-04-07 21:59:27,103 INFO L290 TraceCheckUtils]: 13: Hoare triple {212#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {212#false} is VALID [2022-04-07 21:59:27,103 INFO L290 TraceCheckUtils]: 14: Hoare triple {212#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {212#false} is VALID [2022-04-07 21:59:27,104 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:27,104 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:27,104 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001600800] [2022-04-07 21:59:27,104 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001600800] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 21:59:27,105 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 21:59:27,105 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-07 21:59:27,105 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281151009] [2022-04-07 21:59:27,105 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 21:59:27,106 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 21:59:27,106 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:27,106 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:27,118 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:27,118 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-07 21:59:27,119 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:27,120 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-07 21:59:27,121 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-04-07 21:59:27,121 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:27,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:27,354 INFO L93 Difference]: Finished difference Result 53 states and 64 transitions. [2022-04-07 21:59:27,354 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-07 21:59:27,354 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-07 21:59:27,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:27,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:27,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 64 transitions. [2022-04-07 21:59:27,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:27,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 64 transitions. [2022-04-07 21:59:27,364 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 64 transitions. [2022-04-07 21:59:27,421 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:27,423 INFO L225 Difference]: With dead ends: 53 [2022-04-07 21:59:27,423 INFO L226 Difference]: Without dead ends: 30 [2022-04-07 21:59:27,426 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-04-07 21:59:27,428 INFO L913 BasicCegarLoop]: 28 mSDtfsCounter, 34 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 89 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 45 SdHoareTripleChecker+Invalid, 93 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 89 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:27,429 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [35 Valid, 45 Invalid, 93 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 89 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-07 21:59:27,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2022-04-07 21:59:27,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2022-04-07 21:59:27,435 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:27,437 INFO L82 GeneralOperation]: Start isEquivalent. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:27,438 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:27,438 INFO L87 Difference]: Start difference. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:27,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:27,441 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-07 21:59:27,441 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-07 21:59:27,441 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:27,442 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:27,442 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 30 states. [2022-04-07 21:59:27,442 INFO L87 Difference]: Start difference. First operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 30 states. [2022-04-07 21:59:27,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:27,447 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-07 21:59:27,447 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-07 21:59:27,448 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:27,448 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:27,448 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:27,448 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:27,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:27,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 34 transitions. [2022-04-07 21:59:27,449 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 34 transitions. Word has length 15 [2022-04-07 21:59:27,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:27,449 INFO L478 AbstractCegarLoop]: Abstraction has 29 states and 34 transitions. [2022-04-07 21:59:27,450 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:27,450 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 34 transitions. [2022-04-07 21:59:27,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-07 21:59:27,450 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:27,450 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:27,450 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-07 21:59:27,451 INFO L403 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:27,451 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:27,451 INFO L85 PathProgramCache]: Analyzing trace with hash 1246349198, now seen corresponding path program 1 times [2022-04-07 21:59:27,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:27,451 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677232286] [2022-04-07 21:59:27,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:27,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:27,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:27,588 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:27,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:27,598 INFO L290 TraceCheckUtils]: 0: Hoare triple {410#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {401#true} is VALID [2022-04-07 21:59:27,598 INFO L290 TraceCheckUtils]: 1: Hoare triple {401#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:27,598 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {401#true} {401#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:27,599 INFO L272 TraceCheckUtils]: 0: Hoare triple {401#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {410#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:27,600 INFO L290 TraceCheckUtils]: 1: Hoare triple {410#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {401#true} is VALID [2022-04-07 21:59:27,600 INFO L290 TraceCheckUtils]: 2: Hoare triple {401#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:27,600 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {401#true} {401#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:27,601 INFO L272 TraceCheckUtils]: 4: Hoare triple {401#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:27,601 INFO L290 TraceCheckUtils]: 5: Hoare triple {401#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {406#(= main_~j~0 0)} is VALID [2022-04-07 21:59:27,602 INFO L290 TraceCheckUtils]: 6: Hoare triple {406#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {406#(= main_~j~0 0)} is VALID [2022-04-07 21:59:27,602 INFO L290 TraceCheckUtils]: 7: Hoare triple {406#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {407#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:27,603 INFO L290 TraceCheckUtils]: 8: Hoare triple {407#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:27,604 INFO L290 TraceCheckUtils]: 9: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:27,607 INFO L290 TraceCheckUtils]: 10: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:27,608 INFO L290 TraceCheckUtils]: 11: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 21:59:27,608 INFO L290 TraceCheckUtils]: 12: Hoare triple {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {402#false} is VALID [2022-04-07 21:59:27,609 INFO L272 TraceCheckUtils]: 13: Hoare triple {402#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {402#false} is VALID [2022-04-07 21:59:27,609 INFO L290 TraceCheckUtils]: 14: Hoare triple {402#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {402#false} is VALID [2022-04-07 21:59:27,609 INFO L290 TraceCheckUtils]: 15: Hoare triple {402#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-07 21:59:27,609 INFO L290 TraceCheckUtils]: 16: Hoare triple {402#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-07 21:59:27,610 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:27,610 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:27,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [677232286] [2022-04-07 21:59:27,610 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [677232286] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:27,610 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1431066167] [2022-04-07 21:59:27,610 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:27,610 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:27,611 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:27,627 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:27,628 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-07 21:59:27,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:27,676 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-07 21:59:27,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:27,704 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:28,114 INFO L272 TraceCheckUtils]: 0: Hoare triple {401#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:28,114 INFO L290 TraceCheckUtils]: 1: Hoare triple {401#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {401#true} is VALID [2022-04-07 21:59:28,114 INFO L290 TraceCheckUtils]: 2: Hoare triple {401#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:28,115 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {401#true} {401#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:28,115 INFO L272 TraceCheckUtils]: 4: Hoare triple {401#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:28,115 INFO L290 TraceCheckUtils]: 5: Hoare triple {401#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {401#true} is VALID [2022-04-07 21:59:28,115 INFO L290 TraceCheckUtils]: 6: Hoare triple {401#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {401#true} is VALID [2022-04-07 21:59:28,115 INFO L290 TraceCheckUtils]: 7: Hoare triple {401#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {401#true} is VALID [2022-04-07 21:59:28,115 INFO L290 TraceCheckUtils]: 8: Hoare triple {401#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-07 21:59:28,116 INFO L290 TraceCheckUtils]: 9: Hoare triple {401#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {441#(= main_~j~0 1)} is VALID [2022-04-07 21:59:28,117 INFO L290 TraceCheckUtils]: 10: Hoare triple {441#(= main_~j~0 1)} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:28,117 INFO L290 TraceCheckUtils]: 11: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 21:59:28,118 INFO L290 TraceCheckUtils]: 12: Hoare triple {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {402#false} is VALID [2022-04-07 21:59:28,119 INFO L272 TraceCheckUtils]: 13: Hoare triple {402#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {402#false} is VALID [2022-04-07 21:59:28,119 INFO L290 TraceCheckUtils]: 14: Hoare triple {402#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {402#false} is VALID [2022-04-07 21:59:28,119 INFO L290 TraceCheckUtils]: 15: Hoare triple {402#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-07 21:59:28,119 INFO L290 TraceCheckUtils]: 16: Hoare triple {402#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-07 21:59:28,119 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 21:59:28,119 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-07 21:59:28,120 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1431066167] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 21:59:28,120 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-07 21:59:28,120 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 8 [2022-04-07 21:59:28,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766465528] [2022-04-07 21:59:28,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 21:59:28,120 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 21:59:28,127 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:28,127 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:28,138 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:28,141 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-04-07 21:59:28,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:28,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-04-07 21:59:28,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2022-04-07 21:59:28,142 INFO L87 Difference]: Start difference. First operand 29 states and 34 transitions. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:28,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:28,245 INFO L93 Difference]: Finished difference Result 49 states and 58 transitions. [2022-04-07 21:59:28,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-04-07 21:59:28,246 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-07 21:59:28,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:28,246 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:28,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 57 transitions. [2022-04-07 21:59:28,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:28,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 57 transitions. [2022-04-07 21:59:28,250 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 5 states and 57 transitions. [2022-04-07 21:59:28,289 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:28,292 INFO L225 Difference]: With dead ends: 49 [2022-04-07 21:59:28,293 INFO L226 Difference]: Without dead ends: 37 [2022-04-07 21:59:28,294 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 16 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2022-04-07 21:59:28,295 INFO L913 BasicCegarLoop]: 30 mSDtfsCounter, 13 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:28,297 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [13 Valid, 81 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 18 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 21:59:28,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-07 21:59:28,305 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 30. [2022-04-07 21:59:28,305 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:28,305 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:28,305 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:28,305 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:28,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:28,310 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2022-04-07 21:59:28,310 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-07 21:59:28,311 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:28,311 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:28,311 INFO L74 IsIncluded]: Start isIncluded. First operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-07 21:59:28,311 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-07 21:59:28,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:28,314 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2022-04-07 21:59:28,314 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-07 21:59:28,318 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:28,318 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:28,318 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:28,318 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:28,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:28,320 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 35 transitions. [2022-04-07 21:59:28,320 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 35 transitions. Word has length 17 [2022-04-07 21:59:28,320 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:28,320 INFO L478 AbstractCegarLoop]: Abstraction has 30 states and 35 transitions. [2022-04-07 21:59:28,320 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:28,320 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-07 21:59:28,321 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-07 21:59:28,322 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:28,322 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:28,341 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:28,539 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:28,539 INFO L403 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:28,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:28,540 INFO L85 PathProgramCache]: Analyzing trace with hash 931318849, now seen corresponding path program 1 times [2022-04-07 21:59:28,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:28,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815979061] [2022-04-07 21:59:28,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:28,540 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:28,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:28,735 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:28,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:28,750 INFO L290 TraceCheckUtils]: 0: Hoare triple {657#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-07 21:59:28,751 INFO L290 TraceCheckUtils]: 1: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:28,751 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:28,752 INFO L272 TraceCheckUtils]: 0: Hoare triple {648#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {657#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:28,752 INFO L290 TraceCheckUtils]: 1: Hoare triple {657#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-07 21:59:28,752 INFO L290 TraceCheckUtils]: 2: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:28,752 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:28,752 INFO L272 TraceCheckUtils]: 4: Hoare triple {648#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:28,753 INFO L290 TraceCheckUtils]: 5: Hoare triple {648#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {653#(= main_~j~0 0)} is VALID [2022-04-07 21:59:28,753 INFO L290 TraceCheckUtils]: 6: Hoare triple {653#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {653#(= main_~j~0 0)} is VALID [2022-04-07 21:59:28,754 INFO L290 TraceCheckUtils]: 7: Hoare triple {653#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {654#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:28,755 INFO L290 TraceCheckUtils]: 8: Hoare triple {654#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:28,755 INFO L290 TraceCheckUtils]: 9: Hoare triple {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 21:59:28,756 INFO L290 TraceCheckUtils]: 10: Hoare triple {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {649#false} is VALID [2022-04-07 21:59:28,756 INFO L290 TraceCheckUtils]: 11: Hoare triple {649#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {649#false} is VALID [2022-04-07 21:59:28,757 INFO L290 TraceCheckUtils]: 12: Hoare triple {649#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-07 21:59:28,757 INFO L290 TraceCheckUtils]: 13: Hoare triple {649#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-07 21:59:28,757 INFO L290 TraceCheckUtils]: 14: Hoare triple {649#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {649#false} is VALID [2022-04-07 21:59:28,757 INFO L290 TraceCheckUtils]: 15: Hoare triple {649#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {649#false} is VALID [2022-04-07 21:59:28,757 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:28,757 INFO L290 TraceCheckUtils]: 17: Hoare triple {649#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {649#false} is VALID [2022-04-07 21:59:28,758 INFO L290 TraceCheckUtils]: 18: Hoare triple {649#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {649#false} is VALID [2022-04-07 21:59:28,758 INFO L272 TraceCheckUtils]: 19: Hoare triple {649#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {649#false} is VALID [2022-04-07 21:59:28,758 INFO L290 TraceCheckUtils]: 20: Hoare triple {649#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {649#false} is VALID [2022-04-07 21:59:28,758 INFO L290 TraceCheckUtils]: 21: Hoare triple {649#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:28,758 INFO L290 TraceCheckUtils]: 22: Hoare triple {649#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:28,759 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:28,759 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:28,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815979061] [2022-04-07 21:59:28,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815979061] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:28,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1210717283] [2022-04-07 21:59:28,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:28,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:28,760 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:28,763 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:28,764 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-07 21:59:28,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:28,806 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-07 21:59:28,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:28,821 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:29,115 INFO L272 TraceCheckUtils]: 0: Hoare triple {648#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,116 INFO L290 TraceCheckUtils]: 1: Hoare triple {648#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-07 21:59:29,116 INFO L290 TraceCheckUtils]: 2: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,116 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,116 INFO L272 TraceCheckUtils]: 4: Hoare triple {648#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,118 INFO L290 TraceCheckUtils]: 5: Hoare triple {648#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {653#(= main_~j~0 0)} is VALID [2022-04-07 21:59:29,118 INFO L290 TraceCheckUtils]: 6: Hoare triple {653#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {653#(= main_~j~0 0)} is VALID [2022-04-07 21:59:29,119 INFO L290 TraceCheckUtils]: 7: Hoare triple {653#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {682#(= main_~j~0 1)} is VALID [2022-04-07 21:59:29,119 INFO L290 TraceCheckUtils]: 8: Hoare triple {682#(= main_~j~0 1)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:29,120 INFO L290 TraceCheckUtils]: 9: Hoare triple {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 10: Hoare triple {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {649#false} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 11: Hoare triple {649#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {649#false} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 12: Hoare triple {649#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 13: Hoare triple {649#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 14: Hoare triple {649#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {649#false} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 15: Hoare triple {649#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {649#false} is VALID [2022-04-07 21:59:29,121 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L290 TraceCheckUtils]: 17: Hoare triple {649#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L290 TraceCheckUtils]: 18: Hoare triple {649#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L272 TraceCheckUtils]: 19: Hoare triple {649#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L290 TraceCheckUtils]: 20: Hoare triple {649#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L290 TraceCheckUtils]: 21: Hoare triple {649#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L290 TraceCheckUtils]: 22: Hoare triple {649#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:29,122 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:29,123 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:29,491 INFO L290 TraceCheckUtils]: 22: Hoare triple {649#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:29,491 INFO L290 TraceCheckUtils]: 21: Hoare triple {649#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:29,491 INFO L290 TraceCheckUtils]: 20: Hoare triple {649#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L272 TraceCheckUtils]: 19: Hoare triple {649#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 18: Hoare triple {649#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 17: Hoare triple {649#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 15: Hoare triple {649#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 14: Hoare triple {649#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 13: Hoare triple {649#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-07 21:59:29,492 INFO L290 TraceCheckUtils]: 12: Hoare triple {649#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-07 21:59:29,493 INFO L290 TraceCheckUtils]: 11: Hoare triple {649#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {649#false} is VALID [2022-04-07 21:59:29,493 INFO L290 TraceCheckUtils]: 10: Hoare triple {764#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {649#false} is VALID [2022-04-07 21:59:29,494 INFO L290 TraceCheckUtils]: 9: Hoare triple {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {764#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-07 21:59:29,494 INFO L290 TraceCheckUtils]: 8: Hoare triple {771#(<= 0 (div (+ (* (- 1) (mod main_~j~0 4294967296)) 1) 4294967296))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:29,495 INFO L290 TraceCheckUtils]: 7: Hoare triple {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {771#(<= 0 (div (+ (* (- 1) (mod main_~j~0 4294967296)) 1) 4294967296))} is VALID [2022-04-07 21:59:29,496 INFO L290 TraceCheckUtils]: 6: Hoare triple {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} is VALID [2022-04-07 21:59:29,496 INFO L290 TraceCheckUtils]: 5: Hoare triple {648#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} is VALID [2022-04-07 21:59:29,496 INFO L272 TraceCheckUtils]: 4: Hoare triple {648#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,497 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,497 INFO L290 TraceCheckUtils]: 2: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,497 INFO L290 TraceCheckUtils]: 1: Hoare triple {648#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-07 21:59:29,497 INFO L272 TraceCheckUtils]: 0: Hoare triple {648#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-07 21:59:29,497 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:29,497 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1210717283] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 21:59:29,497 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 21:59:29,497 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 11 [2022-04-07 21:59:29,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [324978529] [2022-04-07 21:59:29,498 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 21:59:29,498 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-07 21:59:29,498 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:29,499 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:29,523 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 33 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:29,524 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-04-07 21:59:29,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:29,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-04-07 21:59:29,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2022-04-07 21:59:29,527 INFO L87 Difference]: Start difference. First operand 30 states and 35 transitions. Second operand has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:29,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:29,848 INFO L93 Difference]: Finished difference Result 61 states and 74 transitions. [2022-04-07 21:59:29,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-07 21:59:29,848 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-07 21:59:29,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:29,848 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:29,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 74 transitions. [2022-04-07 21:59:29,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:29,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 74 transitions. [2022-04-07 21:59:29,851 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 74 transitions. [2022-04-07 21:59:29,904 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 74 edges. 74 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:29,905 INFO L225 Difference]: With dead ends: 61 [2022-04-07 21:59:29,905 INFO L226 Difference]: Without dead ends: 40 [2022-04-07 21:59:29,906 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 42 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=58, Invalid=152, Unknown=0, NotChecked=0, Total=210 [2022-04-07 21:59:29,906 INFO L913 BasicCegarLoop]: 26 mSDtfsCounter, 70 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 145 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 53 SdHoareTripleChecker+Invalid, 160 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 145 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:29,906 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [70 Valid, 53 Invalid, 160 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 145 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-07 21:59:29,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2022-04-07 21:59:29,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 32. [2022-04-07 21:59:29,911 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:29,911 INFO L82 GeneralOperation]: Start isEquivalent. First operand 40 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:29,911 INFO L74 IsIncluded]: Start isIncluded. First operand 40 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:29,911 INFO L87 Difference]: Start difference. First operand 40 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:29,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:29,913 INFO L93 Difference]: Finished difference Result 40 states and 48 transitions. [2022-04-07 21:59:29,913 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 48 transitions. [2022-04-07 21:59:29,913 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:29,913 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:29,913 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 40 states. [2022-04-07 21:59:29,913 INFO L87 Difference]: Start difference. First operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 40 states. [2022-04-07 21:59:29,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:29,916 INFO L93 Difference]: Finished difference Result 40 states and 48 transitions. [2022-04-07 21:59:29,916 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 48 transitions. [2022-04-07 21:59:29,916 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:29,916 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:29,917 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:29,917 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:29,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-07 21:59:29,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 37 transitions. [2022-04-07 21:59:29,918 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 37 transitions. Word has length 23 [2022-04-07 21:59:29,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:29,919 INFO L478 AbstractCegarLoop]: Abstraction has 32 states and 37 transitions. [2022-04-07 21:59:29,919 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:29,920 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 37 transitions. [2022-04-07 21:59:29,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-07 21:59:29,924 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:29,924 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:29,944 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:30,139 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-07 21:59:30,139 INFO L403 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:30,140 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:30,140 INFO L85 PathProgramCache]: Analyzing trace with hash -1459507809, now seen corresponding path program 2 times [2022-04-07 21:59:30,140 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:30,140 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1445863744] [2022-04-07 21:59:30,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:30,140 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:30,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:30,592 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:30,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:30,600 INFO L290 TraceCheckUtils]: 0: Hoare triple {1031#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-07 21:59:30,600 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:30,600 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:30,601 INFO L272 TraceCheckUtils]: 0: Hoare triple {1013#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1031#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:30,601 INFO L290 TraceCheckUtils]: 1: Hoare triple {1031#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-07 21:59:30,601 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:30,601 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:30,601 INFO L272 TraceCheckUtils]: 4: Hoare triple {1013#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:30,602 INFO L290 TraceCheckUtils]: 5: Hoare triple {1013#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:30,602 INFO L290 TraceCheckUtils]: 6: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:30,603 INFO L290 TraceCheckUtils]: 7: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:30,603 INFO L290 TraceCheckUtils]: 8: Hoare triple {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:30,604 INFO L290 TraceCheckUtils]: 9: Hoare triple {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:30,604 INFO L290 TraceCheckUtils]: 10: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:30,604 INFO L290 TraceCheckUtils]: 11: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:30,605 INFO L290 TraceCheckUtils]: 12: Hoare triple {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1021#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:30,606 INFO L290 TraceCheckUtils]: 13: Hoare triple {1021#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1022#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-07 21:59:30,606 INFO L290 TraceCheckUtils]: 14: Hoare triple {1022#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1023#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 21:59:30,607 INFO L290 TraceCheckUtils]: 15: Hoare triple {1023#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1024#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:30,607 INFO L290 TraceCheckUtils]: 16: Hoare triple {1024#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1025#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:30,608 INFO L290 TraceCheckUtils]: 17: Hoare triple {1025#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:30,608 INFO L290 TraceCheckUtils]: 18: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:30,609 INFO L290 TraceCheckUtils]: 19: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 21:59:30,610 INFO L290 TraceCheckUtils]: 20: Hoare triple {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1028#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:30,610 INFO L272 TraceCheckUtils]: 21: Hoare triple {1028#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1029#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 21:59:30,611 INFO L290 TraceCheckUtils]: 22: Hoare triple {1029#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1030#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 21:59:30,611 INFO L290 TraceCheckUtils]: 23: Hoare triple {1030#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-07 21:59:30,611 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-07 21:59:30,612 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:30,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:30,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1445863744] [2022-04-07 21:59:30,612 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1445863744] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:30,612 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1849905488] [2022-04-07 21:59:30,612 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 21:59:30,612 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:30,612 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:30,615 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:30,616 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-07 21:59:30,662 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 21:59:30,662 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 21:59:30,663 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 26 conjunts are in the unsatisfiable core [2022-04-07 21:59:30,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:30,675 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:30,719 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-04-07 21:59:30,770 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-04-07 21:59:31,067 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 21:59:31,068 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-07 21:59:31,162 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 21:59:31,163 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-07 21:59:31,222 INFO L272 TraceCheckUtils]: 0: Hoare triple {1013#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:31,223 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-07 21:59:31,223 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:31,223 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:31,223 INFO L272 TraceCheckUtils]: 4: Hoare triple {1013#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:31,223 INFO L290 TraceCheckUtils]: 5: Hoare triple {1013#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:31,225 INFO L290 TraceCheckUtils]: 6: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:31,225 INFO L290 TraceCheckUtils]: 7: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1056#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0))} is VALID [2022-04-07 21:59:31,226 INFO L290 TraceCheckUtils]: 8: Hoare triple {1056#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:31,226 INFO L290 TraceCheckUtils]: 9: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:31,226 INFO L290 TraceCheckUtils]: 10: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:31,226 INFO L290 TraceCheckUtils]: 11: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1069#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:31,229 INFO L290 TraceCheckUtils]: 12: Hoare triple {1069#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1073#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-07 21:59:31,229 INFO L290 TraceCheckUtils]: 13: Hoare triple {1073#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1077#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 21:59:31,230 INFO L290 TraceCheckUtils]: 14: Hoare triple {1077#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1081#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 21:59:31,230 INFO L290 TraceCheckUtils]: 15: Hoare triple {1081#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1085#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:31,231 INFO L290 TraceCheckUtils]: 16: Hoare triple {1085#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:31,231 INFO L290 TraceCheckUtils]: 17: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:31,232 INFO L290 TraceCheckUtils]: 18: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:31,232 INFO L290 TraceCheckUtils]: 19: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 21:59:31,233 INFO L290 TraceCheckUtils]: 20: Hoare triple {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1028#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:31,233 INFO L272 TraceCheckUtils]: 21: Hoare triple {1028#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 21:59:31,233 INFO L290 TraceCheckUtils]: 22: Hoare triple {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1108#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 21:59:31,234 INFO L290 TraceCheckUtils]: 23: Hoare triple {1108#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-07 21:59:31,234 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-07 21:59:31,234 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:31,234 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:32,157 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-07 21:59:32,158 INFO L290 TraceCheckUtils]: 23: Hoare triple {1108#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-07 21:59:32,159 INFO L290 TraceCheckUtils]: 22: Hoare triple {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1108#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 21:59:32,159 INFO L272 TraceCheckUtils]: 21: Hoare triple {1028#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 21:59:32,160 INFO L290 TraceCheckUtils]: 20: Hoare triple {1127#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1028#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:32,160 INFO L290 TraceCheckUtils]: 19: Hoare triple {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1127#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 21:59:32,160 INFO L290 TraceCheckUtils]: 18: Hoare triple {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:32,161 INFO L290 TraceCheckUtils]: 17: Hoare triple {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:32,162 INFO L290 TraceCheckUtils]: 16: Hoare triple {1141#(forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:32,162 INFO L290 TraceCheckUtils]: 15: Hoare triple {1145#(or (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45)))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1141#(forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45))))} is VALID [2022-04-07 21:59:32,167 INFO L290 TraceCheckUtils]: 14: Hoare triple {1149#(or (not |main_#t~short10|) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1145#(or (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45)))) |main_#t~short10|)} is VALID [2022-04-07 21:59:32,168 INFO L290 TraceCheckUtils]: 13: Hoare triple {1153#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1149#(or (not |main_#t~short10|) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-07 21:59:32,173 INFO L290 TraceCheckUtils]: 12: Hoare triple {1157#(forall ((v_main_~i~0_12 Int)) (or (not (<= 0 v_main_~i~0_12)) (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4)))))) (not (<= (+ v_main_~i~0_12 1) main_~j~0))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1153#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-07 21:59:32,174 INFO L290 TraceCheckUtils]: 11: Hoare triple {1013#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1157#(forall ((v_main_~i~0_12 Int)) (or (not (<= 0 v_main_~i~0_12)) (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4)))))) (not (<= (+ v_main_~i~0_12 1) main_~j~0))))} is VALID [2022-04-07 21:59:32,174 INFO L290 TraceCheckUtils]: 10: Hoare triple {1013#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:32,174 INFO L290 TraceCheckUtils]: 9: Hoare triple {1013#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1013#true} is VALID [2022-04-07 21:59:32,174 INFO L290 TraceCheckUtils]: 8: Hoare triple {1013#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L290 TraceCheckUtils]: 7: Hoare triple {1013#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L290 TraceCheckUtils]: 6: Hoare triple {1013#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L290 TraceCheckUtils]: 5: Hoare triple {1013#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L272 TraceCheckUtils]: 4: Hoare triple {1013#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-07 21:59:32,175 INFO L272 TraceCheckUtils]: 0: Hoare triple {1013#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-07 21:59:32,176 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:32,176 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1849905488] provided 1 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:32,176 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-04-07 21:59:32,176 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [16, 15] total 31 [2022-04-07 21:59:32,176 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1185371156] [2022-04-07 21:59:32,176 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 21:59:32,177 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-07 21:59:32,177 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:32,177 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,197 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:32,197 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-04-07 21:59:32,197 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:32,197 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-04-07 21:59:32,198 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=775, Unknown=0, NotChecked=0, Total=930 [2022-04-07 21:59:32,198 INFO L87 Difference]: Start difference. First operand 32 states and 37 transitions. Second operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:32,434 INFO L93 Difference]: Finished difference Result 49 states and 57 transitions. [2022-04-07 21:59:32,434 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-04-07 21:59:32,435 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-07 21:59:32,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:32,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 54 transitions. [2022-04-07 21:59:32,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 54 transitions. [2022-04-07 21:59:32,437 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 14 states and 54 transitions. [2022-04-07 21:59:32,480 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:32,481 INFO L225 Difference]: With dead ends: 49 [2022-04-07 21:59:32,481 INFO L226 Difference]: Without dead ends: 47 [2022-04-07 21:59:32,482 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 36 SyntacticMatches, 4 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 450 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=181, Invalid=1009, Unknown=0, NotChecked=0, Total=1190 [2022-04-07 21:59:32,482 INFO L913 BasicCegarLoop]: 22 mSDtfsCounter, 15 mSDsluCounter, 144 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 166 SdHoareTripleChecker+Invalid, 85 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:32,482 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [15 Valid, 166 Invalid, 85 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 33 Invalid, 0 Unknown, 50 Unchecked, 0.0s Time] [2022-04-07 21:59:32,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2022-04-07 21:59:32,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2022-04-07 21:59:32,496 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:32,496 INFO L82 GeneralOperation]: Start isEquivalent. First operand 47 states. Second operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:32,496 INFO L74 IsIncluded]: Start isIncluded. First operand 47 states. Second operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:32,496 INFO L87 Difference]: Start difference. First operand 47 states. Second operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:32,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:32,497 INFO L93 Difference]: Finished difference Result 47 states and 55 transitions. [2022-04-07 21:59:32,497 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 55 transitions. [2022-04-07 21:59:32,497 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:32,498 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:32,498 INFO L74 IsIncluded]: Start isIncluded. First operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 47 states. [2022-04-07 21:59:32,498 INFO L87 Difference]: Start difference. First operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 47 states. [2022-04-07 21:59:32,499 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:32,499 INFO L93 Difference]: Finished difference Result 47 states and 55 transitions. [2022-04-07 21:59:32,499 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 55 transitions. [2022-04-07 21:59:32,499 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:32,499 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:32,499 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:32,499 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:32,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:32,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2022-04-07 21:59:32,500 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 53 transitions. Word has length 25 [2022-04-07 21:59:32,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:32,501 INFO L478 AbstractCegarLoop]: Abstraction has 45 states and 53 transitions. [2022-04-07 21:59:32,501 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,501 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 53 transitions. [2022-04-07 21:59:32,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-07 21:59:32,501 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:32,501 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:32,519 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:32,717 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:32,717 INFO L403 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:32,718 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:32,718 INFO L85 PathProgramCache]: Analyzing trace with hash 1038508128, now seen corresponding path program 1 times [2022-04-07 21:59:32,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:32,718 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [862493877] [2022-04-07 21:59:32,718 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:32,718 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:32,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:32,771 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:32,773 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:32,777 INFO L290 TraceCheckUtils]: 0: Hoare triple {1436#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1428#true} is VALID [2022-04-07 21:59:32,777 INFO L290 TraceCheckUtils]: 1: Hoare triple {1428#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-07 21:59:32,777 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1428#true} {1428#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L272 TraceCheckUtils]: 0: Hoare triple {1428#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1436#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:32,778 INFO L290 TraceCheckUtils]: 1: Hoare triple {1436#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L290 TraceCheckUtils]: 2: Hoare triple {1428#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1428#true} {1428#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L272 TraceCheckUtils]: 4: Hoare triple {1428#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L290 TraceCheckUtils]: 5: Hoare triple {1428#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L290 TraceCheckUtils]: 6: Hoare triple {1428#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1428#true} is VALID [2022-04-07 21:59:32,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {1428#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1428#true} is VALID [2022-04-07 21:59:32,779 INFO L290 TraceCheckUtils]: 8: Hoare triple {1428#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1428#true} is VALID [2022-04-07 21:59:32,779 INFO L290 TraceCheckUtils]: 9: Hoare triple {1428#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1428#true} is VALID [2022-04-07 21:59:32,779 INFO L290 TraceCheckUtils]: 10: Hoare triple {1428#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-07 21:59:32,779 INFO L290 TraceCheckUtils]: 11: Hoare triple {1428#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1433#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:32,780 INFO L290 TraceCheckUtils]: 12: Hoare triple {1433#(= (+ (- 1) main_~j~0) 0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1434#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-07 21:59:32,780 INFO L290 TraceCheckUtils]: 13: Hoare triple {1434#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1435#(and (= (+ (- 1) main_~j~0) 0) |main_#t~short10|)} is VALID [2022-04-07 21:59:32,781 INFO L290 TraceCheckUtils]: 14: Hoare triple {1435#(and (= (+ (- 1) main_~j~0) 0) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-07 21:59:32,781 INFO L290 TraceCheckUtils]: 15: Hoare triple {1429#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1429#false} is VALID [2022-04-07 21:59:32,784 INFO L290 TraceCheckUtils]: 16: Hoare triple {1429#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1429#false} is VALID [2022-04-07 21:59:32,785 INFO L290 TraceCheckUtils]: 17: Hoare triple {1429#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1429#false} is VALID [2022-04-07 21:59:32,785 INFO L290 TraceCheckUtils]: 18: Hoare triple {1429#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-07 21:59:32,786 INFO L290 TraceCheckUtils]: 19: Hoare triple {1429#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1429#false} is VALID [2022-04-07 21:59:32,788 INFO L290 TraceCheckUtils]: 20: Hoare triple {1429#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1429#false} is VALID [2022-04-07 21:59:32,788 INFO L272 TraceCheckUtils]: 21: Hoare triple {1429#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1429#false} is VALID [2022-04-07 21:59:32,788 INFO L290 TraceCheckUtils]: 22: Hoare triple {1429#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1429#false} is VALID [2022-04-07 21:59:32,790 INFO L290 TraceCheckUtils]: 23: Hoare triple {1429#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-07 21:59:32,790 INFO L290 TraceCheckUtils]: 24: Hoare triple {1429#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-07 21:59:32,790 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:32,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:32,790 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [862493877] [2022-04-07 21:59:32,790 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [862493877] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-07 21:59:32,791 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-07 21:59:32,791 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-07 21:59:32,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180895663] [2022-04-07 21:59:32,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-07 21:59:32,791 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-07 21:59:32,791 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:32,792 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,804 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:32,804 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-07 21:59:32,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:32,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-07 21:59:32,805 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-04-07 21:59:32,805 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. Second operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:32,959 INFO L93 Difference]: Finished difference Result 78 states and 96 transitions. [2022-04-07 21:59:32,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-07 21:59:32,960 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-07 21:59:32,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:32,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 77 transitions. [2022-04-07 21:59:32,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:32,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 77 transitions. [2022-04-07 21:59:32,964 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 77 transitions. [2022-04-07 21:59:33,015 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 77 edges. 77 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:33,019 INFO L225 Difference]: With dead ends: 78 [2022-04-07 21:59:33,019 INFO L226 Difference]: Without dead ends: 59 [2022-04-07 21:59:33,020 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2022-04-07 21:59:33,021 INFO L913 BasicCegarLoop]: 24 mSDtfsCounter, 64 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 65 SdHoareTripleChecker+Valid, 31 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:33,021 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [65 Valid, 31 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 57 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-07 21:59:33,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2022-04-07 21:59:33,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 47. [2022-04-07 21:59:33,040 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:33,040 INFO L82 GeneralOperation]: Start isEquivalent. First operand 59 states. Second operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,040 INFO L74 IsIncluded]: Start isIncluded. First operand 59 states. Second operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,040 INFO L87 Difference]: Start difference. First operand 59 states. Second operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:33,042 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2022-04-07 21:59:33,042 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 72 transitions. [2022-04-07 21:59:33,042 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:33,042 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:33,042 INFO L74 IsIncluded]: Start isIncluded. First operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 59 states. [2022-04-07 21:59:33,042 INFO L87 Difference]: Start difference. First operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 59 states. [2022-04-07 21:59:33,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:33,044 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2022-04-07 21:59:33,044 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 72 transitions. [2022-04-07 21:59:33,044 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:33,044 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:33,044 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:33,044 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:33,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 55 transitions. [2022-04-07 21:59:33,045 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 55 transitions. Word has length 25 [2022-04-07 21:59:33,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:33,045 INFO L478 AbstractCegarLoop]: Abstraction has 47 states and 55 transitions. [2022-04-07 21:59:33,045 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:33,045 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 55 transitions. [2022-04-07 21:59:33,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-04-07 21:59:33,046 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:33,046 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:33,046 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-04-07 21:59:33,046 INFO L403 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:33,046 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:33,046 INFO L85 PathProgramCache]: Analyzing trace with hash 1031689277, now seen corresponding path program 1 times [2022-04-07 21:59:33,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:33,046 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795045673] [2022-04-07 21:59:33,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:33,047 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:33,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:33,120 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:33,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:33,127 INFO L290 TraceCheckUtils]: 0: Hoare triple {1741#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-07 21:59:33,128 INFO L290 TraceCheckUtils]: 1: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,128 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,129 INFO L272 TraceCheckUtils]: 0: Hoare triple {1732#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1741#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:33,131 INFO L290 TraceCheckUtils]: 1: Hoare triple {1741#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-07 21:59:33,131 INFO L290 TraceCheckUtils]: 2: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L272 TraceCheckUtils]: 4: Hoare triple {1732#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L290 TraceCheckUtils]: 5: Hoare triple {1732#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L290 TraceCheckUtils]: 6: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L290 TraceCheckUtils]: 7: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L290 TraceCheckUtils]: 8: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L290 TraceCheckUtils]: 9: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-07 21:59:33,132 INFO L290 TraceCheckUtils]: 10: Hoare triple {1732#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,133 INFO L290 TraceCheckUtils]: 11: Hoare triple {1732#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1737#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:33,134 INFO L290 TraceCheckUtils]: 12: Hoare triple {1737#(= (+ (- 1) main_~j~0) 0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:33,134 INFO L290 TraceCheckUtils]: 13: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:33,135 INFO L290 TraceCheckUtils]: 14: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:33,135 INFO L290 TraceCheckUtils]: 15: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:33,135 INFO L290 TraceCheckUtils]: 16: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 21:59:33,136 INFO L290 TraceCheckUtils]: 17: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1739#(and (<= (+ main_~i~0 2) main_~j~0) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-07 21:59:33,136 INFO L290 TraceCheckUtils]: 18: Hoare triple {1739#(and (<= (+ main_~i~0 2) main_~j~0) (= (+ (- 1) main_~j~0) 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1740#(not |main_#t~short10|)} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 19: Hoare triple {1740#(not |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 20: Hoare triple {1733#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 21: Hoare triple {1733#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 22: Hoare triple {1733#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 23: Hoare triple {1733#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 24: Hoare triple {1733#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 25: Hoare triple {1733#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L272 TraceCheckUtils]: 26: Hoare triple {1733#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 27: Hoare triple {1733#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 28: Hoare triple {1733#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,137 INFO L290 TraceCheckUtils]: 29: Hoare triple {1733#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,139 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:33,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:33,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795045673] [2022-04-07 21:59:33,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795045673] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:33,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [472942615] [2022-04-07 21:59:33,140 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:33,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:33,140 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:33,143 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:33,143 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-07 21:59:33,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:33,192 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-07 21:59:33,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:33,200 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:33,274 INFO L272 TraceCheckUtils]: 0: Hoare triple {1732#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L290 TraceCheckUtils]: 1: Hoare triple {1732#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L290 TraceCheckUtils]: 2: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L272 TraceCheckUtils]: 4: Hoare triple {1732#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L290 TraceCheckUtils]: 5: Hoare triple {1732#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L290 TraceCheckUtils]: 6: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L290 TraceCheckUtils]: 7: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-07 21:59:33,275 INFO L290 TraceCheckUtils]: 8: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-07 21:59:33,276 INFO L290 TraceCheckUtils]: 9: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-07 21:59:33,276 INFO L290 TraceCheckUtils]: 10: Hoare triple {1732#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,276 INFO L290 TraceCheckUtils]: 11: Hoare triple {1732#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1778#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:33,276 INFO L290 TraceCheckUtils]: 12: Hoare triple {1778#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,277 INFO L290 TraceCheckUtils]: 13: Hoare triple {1782#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,277 INFO L290 TraceCheckUtils]: 14: Hoare triple {1782#(<= main_~i~0 0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,277 INFO L290 TraceCheckUtils]: 15: Hoare triple {1782#(<= main_~i~0 0)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,278 INFO L290 TraceCheckUtils]: 16: Hoare triple {1782#(<= main_~i~0 0)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,278 INFO L290 TraceCheckUtils]: 17: Hoare triple {1782#(<= main_~i~0 0)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1798#(<= (+ main_~i~0 1) 0)} is VALID [2022-04-07 21:59:33,278 INFO L290 TraceCheckUtils]: 18: Hoare triple {1798#(<= (+ main_~i~0 1) 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1740#(not |main_#t~short10|)} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 19: Hoare triple {1740#(not |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 20: Hoare triple {1733#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 21: Hoare triple {1733#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 22: Hoare triple {1733#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 23: Hoare triple {1733#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 24: Hoare triple {1733#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 25: Hoare triple {1733#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L272 TraceCheckUtils]: 26: Hoare triple {1733#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 27: Hoare triple {1733#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 28: Hoare triple {1733#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,279 INFO L290 TraceCheckUtils]: 29: Hoare triple {1733#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,280 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:33,280 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:33,349 INFO L290 TraceCheckUtils]: 29: Hoare triple {1733#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,349 INFO L290 TraceCheckUtils]: 28: Hoare triple {1733#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 27: Hoare triple {1733#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L272 TraceCheckUtils]: 26: Hoare triple {1733#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 25: Hoare triple {1733#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 24: Hoare triple {1733#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 23: Hoare triple {1733#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 22: Hoare triple {1733#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 21: Hoare triple {1733#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 20: Hoare triple {1733#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-07 21:59:33,350 INFO L290 TraceCheckUtils]: 19: Hoare triple {1740#(not |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-07 21:59:33,351 INFO L290 TraceCheckUtils]: 18: Hoare triple {1798#(<= (+ main_~i~0 1) 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1740#(not |main_#t~short10|)} is VALID [2022-04-07 21:59:33,351 INFO L290 TraceCheckUtils]: 17: Hoare triple {1782#(<= main_~i~0 0)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1798#(<= (+ main_~i~0 1) 0)} is VALID [2022-04-07 21:59:33,351 INFO L290 TraceCheckUtils]: 16: Hoare triple {1782#(<= main_~i~0 0)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,354 INFO L290 TraceCheckUtils]: 15: Hoare triple {1782#(<= main_~i~0 0)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,354 INFO L290 TraceCheckUtils]: 14: Hoare triple {1782#(<= main_~i~0 0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,355 INFO L290 TraceCheckUtils]: 13: Hoare triple {1782#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,355 INFO L290 TraceCheckUtils]: 12: Hoare triple {1778#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1782#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 11: Hoare triple {1732#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1778#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 10: Hoare triple {1732#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 9: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 8: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 7: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 6: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 5: Hoare triple {1732#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L272 TraceCheckUtils]: 4: Hoare triple {1732#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 2: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L290 TraceCheckUtils]: 1: Hoare triple {1732#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-07 21:59:33,356 INFO L272 TraceCheckUtils]: 0: Hoare triple {1732#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-07 21:59:33,357 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:33,357 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [472942615] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 21:59:33,357 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 21:59:33,357 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-07 21:59:33,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119992243] [2022-04-07 21:59:33,357 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 21:59:33,357 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-07 21:59:33,358 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:33,358 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:33,377 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:33,377 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-07 21:59:33,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:33,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-07 21:59:33,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-04-07 21:59:33,378 INFO L87 Difference]: Start difference. First operand 47 states and 55 transitions. Second operand has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:33,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:33,771 INFO L93 Difference]: Finished difference Result 91 states and 113 transitions. [2022-04-07 21:59:33,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-07 21:59:33,771 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-07 21:59:33,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:33,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:33,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 93 transitions. [2022-04-07 21:59:33,774 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:33,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 93 transitions. [2022-04-07 21:59:33,775 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 93 transitions. [2022-04-07 21:59:33,853 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:33,854 INFO L225 Difference]: With dead ends: 91 [2022-04-07 21:59:33,854 INFO L226 Difference]: Without dead ends: 72 [2022-04-07 21:59:33,854 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 59 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=92, Invalid=214, Unknown=0, NotChecked=0, Total=306 [2022-04-07 21:59:33,855 INFO L913 BasicCegarLoop]: 30 mSDtfsCounter, 69 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 208 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:33,855 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [70 Valid, 52 Invalid, 208 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-07 21:59:33,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2022-04-07 21:59:33,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 53. [2022-04-07 21:59:33,886 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:33,886 INFO L82 GeneralOperation]: Start isEquivalent. First operand 72 states. Second operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,886 INFO L74 IsIncluded]: Start isIncluded. First operand 72 states. Second operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,887 INFO L87 Difference]: Start difference. First operand 72 states. Second operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,889 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:33,889 INFO L93 Difference]: Finished difference Result 72 states and 86 transitions. [2022-04-07 21:59:33,889 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 86 transitions. [2022-04-07 21:59:33,889 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:33,889 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:33,890 INFO L74 IsIncluded]: Start isIncluded. First operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 72 states. [2022-04-07 21:59:33,890 INFO L87 Difference]: Start difference. First operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 72 states. [2022-04-07 21:59:33,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:33,892 INFO L93 Difference]: Finished difference Result 72 states and 86 transitions. [2022-04-07 21:59:33,892 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 86 transitions. [2022-04-07 21:59:33,892 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:33,892 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:33,892 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:33,892 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:33,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:33,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 62 transitions. [2022-04-07 21:59:33,893 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 62 transitions. Word has length 30 [2022-04-07 21:59:33,893 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:33,894 INFO L478 AbstractCegarLoop]: Abstraction has 53 states and 62 transitions. [2022-04-07 21:59:33,894 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:33,894 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 62 transitions. [2022-04-07 21:59:33,894 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-04-07 21:59:33,894 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:33,894 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:33,911 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:34,101 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:34,101 INFO L403 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:34,102 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:34,102 INFO L85 PathProgramCache]: Analyzing trace with hash -765262082, now seen corresponding path program 1 times [2022-04-07 21:59:34,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:34,102 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1698910568] [2022-04-07 21:59:34,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:34,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:34,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:34,554 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:34,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:34,558 INFO L290 TraceCheckUtils]: 0: Hoare triple {2302#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-07 21:59:34,558 INFO L290 TraceCheckUtils]: 1: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:34,558 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:34,559 INFO L272 TraceCheckUtils]: 0: Hoare triple {2281#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2302#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:34,559 INFO L290 TraceCheckUtils]: 1: Hoare triple {2302#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-07 21:59:34,559 INFO L290 TraceCheckUtils]: 2: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:34,559 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:34,559 INFO L272 TraceCheckUtils]: 4: Hoare triple {2281#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:34,560 INFO L290 TraceCheckUtils]: 5: Hoare triple {2281#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:34,560 INFO L290 TraceCheckUtils]: 6: Hoare triple {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:34,560 INFO L290 TraceCheckUtils]: 7: Hoare triple {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:34,561 INFO L290 TraceCheckUtils]: 8: Hoare triple {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:34,561 INFO L290 TraceCheckUtils]: 9: Hoare triple {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2288#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:34,562 INFO L290 TraceCheckUtils]: 10: Hoare triple {2288#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2288#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:34,569 INFO L290 TraceCheckUtils]: 11: Hoare triple {2288#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:34,570 INFO L290 TraceCheckUtils]: 12: Hoare triple {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2289#(and (= |main_~#v~0.offset| 0) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (and (<= (+ main_~i~0 1) 0) (= (+ (- 1) main_~j~0) 0))))} is VALID [2022-04-07 21:59:34,572 INFO L290 TraceCheckUtils]: 13: Hoare triple {2289#(and (= |main_~#v~0.offset| 0) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (and (<= (+ main_~i~0 1) 0) (= (+ (- 1) main_~j~0) 0))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2290#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:34,572 INFO L290 TraceCheckUtils]: 14: Hoare triple {2290#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2291#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:34,573 INFO L290 TraceCheckUtils]: 15: Hoare triple {2291#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2292#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:34,573 INFO L290 TraceCheckUtils]: 16: Hoare triple {2292#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {2293#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:34,574 INFO L290 TraceCheckUtils]: 17: Hoare triple {2293#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {2294#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-07 21:59:34,574 INFO L290 TraceCheckUtils]: 18: Hoare triple {2294#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2295#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} is VALID [2022-04-07 21:59:34,575 INFO L290 TraceCheckUtils]: 19: Hoare triple {2295#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-07 21:59:34,575 INFO L290 TraceCheckUtils]: 20: Hoare triple {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-07 21:59:34,576 INFO L290 TraceCheckUtils]: 21: Hoare triple {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:34,576 INFO L290 TraceCheckUtils]: 22: Hoare triple {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:34,577 INFO L290 TraceCheckUtils]: 23: Hoare triple {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:34,578 INFO L290 TraceCheckUtils]: 24: Hoare triple {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2298#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 21:59:34,579 INFO L290 TraceCheckUtils]: 25: Hoare triple {2298#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 21:59:34,579 INFO L272 TraceCheckUtils]: 26: Hoare triple {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2300#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 21:59:34,581 INFO L290 TraceCheckUtils]: 27: Hoare triple {2300#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2301#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 21:59:34,582 INFO L290 TraceCheckUtils]: 28: Hoare triple {2301#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-07 21:59:34,582 INFO L290 TraceCheckUtils]: 29: Hoare triple {2282#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-07 21:59:34,583 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 21:59:34,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:34,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1698910568] [2022-04-07 21:59:34,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1698910568] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:34,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2046848963] [2022-04-07 21:59:34,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:34,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:34,583 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:34,584 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:34,585 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-07 21:59:34,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:34,635 INFO L263 TraceCheckSpWp]: Trace formula consists of 124 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-07 21:59:34,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:34,646 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:34,907 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-07 21:59:34,907 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-07 21:59:35,667 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-07 21:59:35,667 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-07 21:59:36,549 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-07 21:59:36,550 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-07 21:59:36,688 INFO L272 TraceCheckUtils]: 0: Hoare triple {2281#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L290 TraceCheckUtils]: 1: Hoare triple {2281#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L290 TraceCheckUtils]: 2: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L272 TraceCheckUtils]: 4: Hoare triple {2281#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L290 TraceCheckUtils]: 5: Hoare triple {2281#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L290 TraceCheckUtils]: 6: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-07 21:59:36,688 INFO L290 TraceCheckUtils]: 7: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-07 21:59:36,689 INFO L290 TraceCheckUtils]: 8: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-07 21:59:36,689 INFO L290 TraceCheckUtils]: 9: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-07 21:59:36,689 INFO L290 TraceCheckUtils]: 10: Hoare triple {2281#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:36,700 INFO L290 TraceCheckUtils]: 11: Hoare triple {2281#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2339#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:36,701 INFO L290 TraceCheckUtils]: 12: Hoare triple {2339#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2343#(<= main_~i~0 0)} is VALID [2022-04-07 21:59:36,702 INFO L290 TraceCheckUtils]: 13: Hoare triple {2343#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2347#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 21:59:36,702 INFO L290 TraceCheckUtils]: 14: Hoare triple {2347#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2351#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:36,703 INFO L290 TraceCheckUtils]: 15: Hoare triple {2351#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2355#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:36,704 INFO L290 TraceCheckUtils]: 16: Hoare triple {2355#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= 0 main_~i~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {2359#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:36,704 INFO L290 TraceCheckUtils]: 17: Hoare triple {2359#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {2363#(exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-07 21:59:36,706 INFO L290 TraceCheckUtils]: 18: Hoare triple {2363#(exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2367#(and (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 21:59:36,707 INFO L290 TraceCheckUtils]: 19: Hoare triple {2367#(and (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} is VALID [2022-04-07 21:59:36,709 INFO L290 TraceCheckUtils]: 20: Hoare triple {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} is VALID [2022-04-07 21:59:36,710 INFO L290 TraceCheckUtils]: 21: Hoare triple {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-07 21:59:36,711 INFO L290 TraceCheckUtils]: 22: Hoare triple {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-07 21:59:36,711 INFO L290 TraceCheckUtils]: 23: Hoare triple {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-07 21:59:36,711 INFO L290 TraceCheckUtils]: 24: Hoare triple {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2388#(and (exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (= main_~k~0 1))} is VALID [2022-04-07 21:59:36,712 INFO L290 TraceCheckUtils]: 25: Hoare triple {2388#(and (exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 21:59:36,713 INFO L272 TraceCheckUtils]: 26: Hoare triple {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 21:59:36,713 INFO L290 TraceCheckUtils]: 27: Hoare triple {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2399#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 21:59:36,714 INFO L290 TraceCheckUtils]: 28: Hoare triple {2399#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-07 21:59:36,714 INFO L290 TraceCheckUtils]: 29: Hoare triple {2282#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-07 21:59:36,714 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:36,714 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:39,283 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 61 [2022-04-07 21:59:39,374 INFO L356 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-04-07 21:59:39,374 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 771 treesize of output 711 [2022-04-07 21:59:41,167 INFO L290 TraceCheckUtils]: 29: Hoare triple {2282#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-07 21:59:41,168 INFO L290 TraceCheckUtils]: 28: Hoare triple {2399#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-07 21:59:41,168 INFO L290 TraceCheckUtils]: 27: Hoare triple {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2399#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 21:59:41,168 INFO L272 TraceCheckUtils]: 26: Hoare triple {2415#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 21:59:41,169 INFO L290 TraceCheckUtils]: 25: Hoare triple {2419#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2415#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:41,169 INFO L290 TraceCheckUtils]: 24: Hoare triple {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2419#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 21:59:41,170 INFO L290 TraceCheckUtils]: 23: Hoare triple {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:41,170 INFO L290 TraceCheckUtils]: 22: Hoare triple {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:41,171 INFO L290 TraceCheckUtils]: 21: Hoare triple {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:41,171 INFO L290 TraceCheckUtils]: 20: Hoare triple {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 21:59:41,172 INFO L290 TraceCheckUtils]: 19: Hoare triple {2440#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 21:59:41,173 INFO L290 TraceCheckUtils]: 18: Hoare triple {2444#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2440#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-07 21:59:41,174 INFO L290 TraceCheckUtils]: 17: Hoare triple {2448#(forall ((v_main_~i~0_17 Int)) (or (<= 0 v_main_~i~0_17) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {2444#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:41,175 INFO L290 TraceCheckUtils]: 16: Hoare triple {2452#(forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {2448#(forall ((v_main_~i~0_17 Int)) (or (<= 0 v_main_~i~0_17) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))))} is VALID [2022-04-07 21:59:41,176 INFO L290 TraceCheckUtils]: 15: Hoare triple {2456#(or (not |main_#t~short10|) (forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0)))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2452#(forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0))))} is VALID [2022-04-07 21:59:41,176 INFO L290 TraceCheckUtils]: 14: Hoare triple {2460#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2456#(or (not |main_#t~short10|) (forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0)))))} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 13: Hoare triple {2281#true} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2460#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 12: Hoare triple {2281#true} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2281#true} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 11: Hoare triple {2281#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2281#true} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 10: Hoare triple {2281#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 9: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 8: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 7: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-07 21:59:41,177 INFO L290 TraceCheckUtils]: 6: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L290 TraceCheckUtils]: 5: Hoare triple {2281#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L272 TraceCheckUtils]: 4: Hoare triple {2281#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L290 TraceCheckUtils]: 2: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L290 TraceCheckUtils]: 1: Hoare triple {2281#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L272 TraceCheckUtils]: 0: Hoare triple {2281#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-07 21:59:41,178 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:41,178 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2046848963] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 21:59:41,178 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 21:59:41,178 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 16, 14] total 42 [2022-04-07 21:59:41,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [131825892] [2022-04-07 21:59:41,179 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 21:59:41,179 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-07 21:59:41,179 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:41,179 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:41,250 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 70 edges. 70 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:41,250 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-04-07 21:59:41,250 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:41,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-04-07 21:59:41,251 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=187, Invalid=1532, Unknown=3, NotChecked=0, Total=1722 [2022-04-07 21:59:41,251 INFO L87 Difference]: Start difference. First operand 53 states and 62 transitions. Second operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:49,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:49,362 INFO L93 Difference]: Finished difference Result 115 states and 140 transitions. [2022-04-07 21:59:49,362 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2022-04-07 21:59:49,362 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-07 21:59:49,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:49,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:49,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 116 transitions. [2022-04-07 21:59:49,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:49,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 116 transitions. [2022-04-07 21:59:49,367 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 44 states and 116 transitions. [2022-04-07 21:59:49,467 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 116 edges. 116 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:49,469 INFO L225 Difference]: With dead ends: 115 [2022-04-07 21:59:49,469 INFO L226 Difference]: Without dead ends: 113 [2022-04-07 21:59:49,470 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 43 SyntacticMatches, 3 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1743 ImplicationChecksByTransitivity, 9.9s TimeCoverageRelationStatistics Valid=591, Invalid=5106, Unknown=3, NotChecked=0, Total=5700 [2022-04-07 21:59:49,470 INFO L913 BasicCegarLoop]: 26 mSDtfsCounter, 121 mSDsluCounter, 122 mSDsCounter, 0 mSdLazyCounter, 685 mSolverCounterSat, 84 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 122 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 1082 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 84 IncrementalHoareTripleChecker+Valid, 685 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 313 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:49,471 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [122 Valid, 148 Invalid, 1082 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [84 Valid, 685 Invalid, 0 Unknown, 313 Unchecked, 0.6s Time] [2022-04-07 21:59:49,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2022-04-07 21:59:49,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 60. [2022-04-07 21:59:49,504 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:49,504 INFO L82 GeneralOperation]: Start isEquivalent. First operand 113 states. Second operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:49,505 INFO L74 IsIncluded]: Start isIncluded. First operand 113 states. Second operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:49,505 INFO L87 Difference]: Start difference. First operand 113 states. Second operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:49,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:49,507 INFO L93 Difference]: Finished difference Result 113 states and 138 transitions. [2022-04-07 21:59:49,507 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 138 transitions. [2022-04-07 21:59:49,508 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:49,508 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:49,508 INFO L74 IsIncluded]: Start isIncluded. First operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 113 states. [2022-04-07 21:59:49,508 INFO L87 Difference]: Start difference. First operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 113 states. [2022-04-07 21:59:49,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:49,510 INFO L93 Difference]: Finished difference Result 113 states and 138 transitions. [2022-04-07 21:59:49,510 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 138 transitions. [2022-04-07 21:59:49,510 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:49,510 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:49,510 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:49,511 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:49,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:49,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 71 transitions. [2022-04-07 21:59:49,512 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 71 transitions. Word has length 30 [2022-04-07 21:59:49,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:49,512 INFO L478 AbstractCegarLoop]: Abstraction has 60 states and 71 transitions. [2022-04-07 21:59:49,512 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:49,512 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 71 transitions. [2022-04-07 21:59:49,512 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-07 21:59:49,512 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:49,513 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:49,531 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:49,727 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:49,727 INFO L403 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:49,728 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:49,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1650775123, now seen corresponding path program 1 times [2022-04-07 21:59:49,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:49,728 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882710079] [2022-04-07 21:59:49,728 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:49,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:49,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:49,794 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:49,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:49,798 INFO L290 TraceCheckUtils]: 0: Hoare triple {3051#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-07 21:59:49,798 INFO L290 TraceCheckUtils]: 1: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,798 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,798 INFO L272 TraceCheckUtils]: 0: Hoare triple {3042#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3051#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:49,798 INFO L290 TraceCheckUtils]: 1: Hoare triple {3051#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-07 21:59:49,798 INFO L290 TraceCheckUtils]: 2: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,798 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L272 TraceCheckUtils]: 4: Hoare triple {3042#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 5: Hoare triple {3042#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 6: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 7: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 8: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 9: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 10: Hoare triple {3042#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,799 INFO L290 TraceCheckUtils]: 11: Hoare triple {3042#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:49,800 INFO L290 TraceCheckUtils]: 12: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:49,800 INFO L290 TraceCheckUtils]: 13: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:49,800 INFO L290 TraceCheckUtils]: 14: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:49,801 INFO L290 TraceCheckUtils]: 15: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:49,801 INFO L290 TraceCheckUtils]: 16: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-07 21:59:49,801 INFO L290 TraceCheckUtils]: 17: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3048#(<= 2 main_~j~0)} is VALID [2022-04-07 21:59:49,802 INFO L290 TraceCheckUtils]: 18: Hoare triple {3048#(<= 2 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3049#(<= 1 main_~i~0)} is VALID [2022-04-07 21:59:49,802 INFO L290 TraceCheckUtils]: 19: Hoare triple {3049#(<= 1 main_~i~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3050#|main_#t~short10|} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 20: Hoare triple {3050#|main_#t~short10|} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 21: Hoare triple {3043#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 22: Hoare triple {3043#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 23: Hoare triple {3043#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 24: Hoare triple {3043#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 25: Hoare triple {3043#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 26: Hoare triple {3043#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L272 TraceCheckUtils]: 27: Hoare triple {3043#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 28: Hoare triple {3043#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 29: Hoare triple {3043#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L290 TraceCheckUtils]: 30: Hoare triple {3043#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,803 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:49,804 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:49,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882710079] [2022-04-07 21:59:49,804 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882710079] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:49,804 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [805183107] [2022-04-07 21:59:49,804 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:49,804 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:49,804 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:49,805 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:49,805 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-07 21:59:49,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:49,851 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-07 21:59:49,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:49,859 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:49,941 INFO L272 TraceCheckUtils]: 0: Hoare triple {3042#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,941 INFO L290 TraceCheckUtils]: 1: Hoare triple {3042#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 2: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L272 TraceCheckUtils]: 4: Hoare triple {3042#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 5: Hoare triple {3042#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 6: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 7: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 8: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 9: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-07 21:59:49,942 INFO L290 TraceCheckUtils]: 10: Hoare triple {3042#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:49,943 INFO L290 TraceCheckUtils]: 11: Hoare triple {3042#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:49,943 INFO L290 TraceCheckUtils]: 12: Hoare triple {3088#(<= 1 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:49,944 INFO L290 TraceCheckUtils]: 13: Hoare triple {3088#(<= 1 main_~j~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:49,944 INFO L290 TraceCheckUtils]: 14: Hoare triple {3088#(<= 1 main_~j~0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:49,944 INFO L290 TraceCheckUtils]: 15: Hoare triple {3088#(<= 1 main_~j~0)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:49,945 INFO L290 TraceCheckUtils]: 16: Hoare triple {3088#(<= 1 main_~j~0)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:49,945 INFO L290 TraceCheckUtils]: 17: Hoare triple {3088#(<= 1 main_~j~0)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3048#(<= 2 main_~j~0)} is VALID [2022-04-07 21:59:49,946 INFO L290 TraceCheckUtils]: 18: Hoare triple {3048#(<= 2 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3049#(<= 1 main_~i~0)} is VALID [2022-04-07 21:59:49,946 INFO L290 TraceCheckUtils]: 19: Hoare triple {3049#(<= 1 main_~i~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3050#|main_#t~short10|} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 20: Hoare triple {3050#|main_#t~short10|} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 21: Hoare triple {3043#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 22: Hoare triple {3043#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 23: Hoare triple {3043#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 24: Hoare triple {3043#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 25: Hoare triple {3043#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 26: Hoare triple {3043#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L272 TraceCheckUtils]: 27: Hoare triple {3043#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 28: Hoare triple {3043#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 29: Hoare triple {3043#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,947 INFO L290 TraceCheckUtils]: 30: Hoare triple {3043#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:49,948 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:49,948 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:50,065 INFO L290 TraceCheckUtils]: 30: Hoare triple {3043#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:50,065 INFO L290 TraceCheckUtils]: 29: Hoare triple {3043#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:50,065 INFO L290 TraceCheckUtils]: 28: Hoare triple {3043#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3043#false} is VALID [2022-04-07 21:59:50,065 INFO L272 TraceCheckUtils]: 27: Hoare triple {3043#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3043#false} is VALID [2022-04-07 21:59:50,065 INFO L290 TraceCheckUtils]: 26: Hoare triple {3043#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3043#false} is VALID [2022-04-07 21:59:50,066 INFO L290 TraceCheckUtils]: 25: Hoare triple {3043#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3043#false} is VALID [2022-04-07 21:59:50,066 INFO L290 TraceCheckUtils]: 24: Hoare triple {3043#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:50,066 INFO L290 TraceCheckUtils]: 23: Hoare triple {3043#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3043#false} is VALID [2022-04-07 21:59:50,066 INFO L290 TraceCheckUtils]: 22: Hoare triple {3043#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3043#false} is VALID [2022-04-07 21:59:50,066 INFO L290 TraceCheckUtils]: 21: Hoare triple {3043#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3043#false} is VALID [2022-04-07 21:59:50,066 INFO L290 TraceCheckUtils]: 20: Hoare triple {3050#|main_#t~short10|} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-07 21:59:50,067 INFO L290 TraceCheckUtils]: 19: Hoare triple {3179#(<= 0 main_~i~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3050#|main_#t~short10|} is VALID [2022-04-07 21:59:50,068 INFO L290 TraceCheckUtils]: 18: Hoare triple {3088#(<= 1 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3179#(<= 0 main_~i~0)} is VALID [2022-04-07 21:59:50,068 INFO L290 TraceCheckUtils]: 17: Hoare triple {3186#(<= 0 main_~j~0)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3088#(<= 1 main_~j~0)} is VALID [2022-04-07 21:59:50,068 INFO L290 TraceCheckUtils]: 16: Hoare triple {3186#(<= 0 main_~j~0)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3186#(<= 0 main_~j~0)} is VALID [2022-04-07 21:59:50,069 INFO L290 TraceCheckUtils]: 15: Hoare triple {3186#(<= 0 main_~j~0)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3186#(<= 0 main_~j~0)} is VALID [2022-04-07 21:59:50,069 INFO L290 TraceCheckUtils]: 14: Hoare triple {3186#(<= 0 main_~j~0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3186#(<= 0 main_~j~0)} is VALID [2022-04-07 21:59:50,069 INFO L290 TraceCheckUtils]: 13: Hoare triple {3186#(<= 0 main_~j~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3186#(<= 0 main_~j~0)} is VALID [2022-04-07 21:59:50,070 INFO L290 TraceCheckUtils]: 12: Hoare triple {3186#(<= 0 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3186#(<= 0 main_~j~0)} is VALID [2022-04-07 21:59:50,070 INFO L290 TraceCheckUtils]: 11: Hoare triple {3042#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3186#(<= 0 main_~j~0)} is VALID [2022-04-07 21:59:50,070 INFO L290 TraceCheckUtils]: 10: Hoare triple {3042#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:50,070 INFO L290 TraceCheckUtils]: 9: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-07 21:59:50,070 INFO L290 TraceCheckUtils]: 8: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-07 21:59:50,070 INFO L290 TraceCheckUtils]: 7: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L290 TraceCheckUtils]: 6: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L290 TraceCheckUtils]: 5: Hoare triple {3042#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L272 TraceCheckUtils]: 4: Hoare triple {3042#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L290 TraceCheckUtils]: 2: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L290 TraceCheckUtils]: 1: Hoare triple {3042#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L272 TraceCheckUtils]: 0: Hoare triple {3042#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-07 21:59:50,071 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-07 21:59:50,071 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [805183107] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 21:59:50,072 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 21:59:50,072 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-07 21:59:50,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136731077] [2022-04-07 21:59:50,072 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 21:59:50,073 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-07 21:59:50,073 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:50,074 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:50,104 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:50,105 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-07 21:59:50,105 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:50,105 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-07 21:59:50,105 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-04-07 21:59:50,105 INFO L87 Difference]: Start difference. First operand 60 states and 71 transitions. Second operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:50,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:50,661 INFO L93 Difference]: Finished difference Result 132 states and 162 transitions. [2022-04-07 21:59:50,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-07 21:59:50,662 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-07 21:59:50,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:50,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:50,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 110 transitions. [2022-04-07 21:59:50,663 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:50,664 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 110 transitions. [2022-04-07 21:59:50,665 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 110 transitions. [2022-04-07 21:59:50,740 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 110 edges. 110 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:50,741 INFO L225 Difference]: With dead ends: 132 [2022-04-07 21:59:50,741 INFO L226 Difference]: Without dead ends: 98 [2022-04-07 21:59:50,742 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=260, Unknown=0, NotChecked=0, Total=380 [2022-04-07 21:59:50,742 INFO L913 BasicCegarLoop]: 28 mSDtfsCounter, 141 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 219 mSolverCounterSat, 53 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 55 SdHoareTripleChecker+Invalid, 272 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 53 IncrementalHoareTripleChecker+Valid, 219 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:50,742 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [141 Valid, 55 Invalid, 272 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [53 Valid, 219 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-07 21:59:50,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2022-04-07 21:59:50,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 63. [2022-04-07 21:59:50,793 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:50,793 INFO L82 GeneralOperation]: Start isEquivalent. First operand 98 states. Second operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:50,793 INFO L74 IsIncluded]: Start isIncluded. First operand 98 states. Second operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:50,793 INFO L87 Difference]: Start difference. First operand 98 states. Second operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:50,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:50,802 INFO L93 Difference]: Finished difference Result 98 states and 118 transitions. [2022-04-07 21:59:50,802 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 118 transitions. [2022-04-07 21:59:50,802 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:50,802 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:50,802 INFO L74 IsIncluded]: Start isIncluded. First operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 98 states. [2022-04-07 21:59:50,802 INFO L87 Difference]: Start difference. First operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 98 states. [2022-04-07 21:59:50,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:50,805 INFO L93 Difference]: Finished difference Result 98 states and 118 transitions. [2022-04-07 21:59:50,805 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 118 transitions. [2022-04-07 21:59:50,805 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:50,805 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:50,805 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:50,805 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:50,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:50,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 74 transitions. [2022-04-07 21:59:50,806 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 74 transitions. Word has length 31 [2022-04-07 21:59:50,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:50,806 INFO L478 AbstractCegarLoop]: Abstraction has 63 states and 74 transitions. [2022-04-07 21:59:50,806 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:50,806 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 74 transitions. [2022-04-07 21:59:50,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-07 21:59:50,807 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:50,807 INFO L499 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:50,822 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:51,007 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:51,007 INFO L403 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:51,008 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:51,008 INFO L85 PathProgramCache]: Analyzing trace with hash -547485170, now seen corresponding path program 1 times [2022-04-07 21:59:51,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:51,008 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724849108] [2022-04-07 21:59:51,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:51,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:51,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:51,119 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:51,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:51,123 INFO L290 TraceCheckUtils]: 0: Hoare triple {3735#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-07 21:59:51,123 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,123 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,123 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-04-07 21:59:51,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:51,128 INFO L290 TraceCheckUtils]: 0: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-07 21:59:51,128 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,128 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,129 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:51,129 INFO L272 TraceCheckUtils]: 0: Hoare triple {3720#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3735#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:51,129 INFO L290 TraceCheckUtils]: 1: Hoare triple {3735#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-07 21:59:51,129 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,129 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,130 INFO L272 TraceCheckUtils]: 4: Hoare triple {3720#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,130 INFO L290 TraceCheckUtils]: 5: Hoare triple {3720#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3725#(= main_~j~0 0)} is VALID [2022-04-07 21:59:51,130 INFO L290 TraceCheckUtils]: 6: Hoare triple {3725#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3725#(= main_~j~0 0)} is VALID [2022-04-07 21:59:51,131 INFO L290 TraceCheckUtils]: 7: Hoare triple {3725#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:51,131 INFO L290 TraceCheckUtils]: 8: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:51,132 INFO L290 TraceCheckUtils]: 9: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 21:59:51,132 INFO L290 TraceCheckUtils]: 10: Hoare triple {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,132 INFO L290 TraceCheckUtils]: 11: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,133 INFO L290 TraceCheckUtils]: 12: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,133 INFO L290 TraceCheckUtils]: 13: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,133 INFO L290 TraceCheckUtils]: 14: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,134 INFO L290 TraceCheckUtils]: 15: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,134 INFO L290 TraceCheckUtils]: 16: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,134 INFO L290 TraceCheckUtils]: 17: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,135 INFO L290 TraceCheckUtils]: 18: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:51,135 INFO L290 TraceCheckUtils]: 19: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:51,135 INFO L290 TraceCheckUtils]: 20: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:51,136 INFO L272 TraceCheckUtils]: 21: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3720#true} is VALID [2022-04-07 21:59:51,136 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-07 21:59:51,136 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,136 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:51,136 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3720#true} {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:51,137 INFO L290 TraceCheckUtils]: 26: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:51,137 INFO L290 TraceCheckUtils]: 27: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 21:59:51,138 INFO L290 TraceCheckUtils]: 28: Hoare triple {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3721#false} is VALID [2022-04-07 21:59:51,138 INFO L272 TraceCheckUtils]: 29: Hoare triple {3721#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3721#false} is VALID [2022-04-07 21:59:51,138 INFO L290 TraceCheckUtils]: 30: Hoare triple {3721#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3721#false} is VALID [2022-04-07 21:59:51,138 INFO L290 TraceCheckUtils]: 31: Hoare triple {3721#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-07 21:59:51,138 INFO L290 TraceCheckUtils]: 32: Hoare triple {3721#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-07 21:59:51,139 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 21:59:51,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:51,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [724849108] [2022-04-07 21:59:51,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [724849108] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:51,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [60282681] [2022-04-07 21:59:51,139 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:51,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:51,139 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:51,140 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:51,141 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-07 21:59:51,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:51,184 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-07 21:59:51,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:51,195 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:53,451 INFO L272 TraceCheckUtils]: 0: Hoare triple {3720#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:53,452 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-07 21:59:53,452 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:53,452 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:53,452 INFO L272 TraceCheckUtils]: 4: Hoare triple {3720#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:53,452 INFO L290 TraceCheckUtils]: 5: Hoare triple {3720#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3725#(= main_~j~0 0)} is VALID [2022-04-07 21:59:53,452 INFO L290 TraceCheckUtils]: 6: Hoare triple {3725#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3725#(= main_~j~0 0)} is VALID [2022-04-07 21:59:53,453 INFO L290 TraceCheckUtils]: 7: Hoare triple {3725#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:53,453 INFO L290 TraceCheckUtils]: 8: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:53,453 INFO L290 TraceCheckUtils]: 9: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 21:59:53,454 INFO L290 TraceCheckUtils]: 10: Hoare triple {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,454 INFO L290 TraceCheckUtils]: 11: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,455 INFO L290 TraceCheckUtils]: 12: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,455 INFO L290 TraceCheckUtils]: 13: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,455 INFO L290 TraceCheckUtils]: 14: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,455 INFO L290 TraceCheckUtils]: 15: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,456 INFO L290 TraceCheckUtils]: 16: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,456 INFO L290 TraceCheckUtils]: 17: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,456 INFO L290 TraceCheckUtils]: 18: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:53,456 INFO L290 TraceCheckUtils]: 19: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:53,457 INFO L290 TraceCheckUtils]: 20: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:53,457 INFO L272 TraceCheckUtils]: 21: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3720#true} is VALID [2022-04-07 21:59:53,457 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-07 21:59:53,457 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:53,457 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:53,458 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3720#true} {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:53,458 INFO L290 TraceCheckUtils]: 26: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 21:59:53,458 INFO L290 TraceCheckUtils]: 27: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3820#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= main_~k~0 2))} is VALID [2022-04-07 21:59:53,459 INFO L290 TraceCheckUtils]: 28: Hoare triple {3820#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= main_~k~0 2))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3721#false} is VALID [2022-04-07 21:59:53,459 INFO L272 TraceCheckUtils]: 29: Hoare triple {3721#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3721#false} is VALID [2022-04-07 21:59:53,459 INFO L290 TraceCheckUtils]: 30: Hoare triple {3721#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3721#false} is VALID [2022-04-07 21:59:53,459 INFO L290 TraceCheckUtils]: 31: Hoare triple {3721#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-07 21:59:53,459 INFO L290 TraceCheckUtils]: 32: Hoare triple {3721#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-07 21:59:53,459 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 21:59:53,460 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:54,521 INFO L290 TraceCheckUtils]: 32: Hoare triple {3721#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-07 21:59:54,521 INFO L290 TraceCheckUtils]: 31: Hoare triple {3721#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-07 21:59:54,521 INFO L290 TraceCheckUtils]: 30: Hoare triple {3721#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3721#false} is VALID [2022-04-07 21:59:54,521 INFO L272 TraceCheckUtils]: 29: Hoare triple {3721#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3721#false} is VALID [2022-04-07 21:59:54,522 INFO L290 TraceCheckUtils]: 28: Hoare triple {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3721#false} is VALID [2022-04-07 21:59:54,523 INFO L290 TraceCheckUtils]: 27: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 21:59:54,523 INFO L290 TraceCheckUtils]: 26: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:54,524 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3720#true} {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:54,524 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:54,524 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:54,524 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-07 21:59:54,524 INFO L272 TraceCheckUtils]: 21: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3720#true} is VALID [2022-04-07 21:59:54,525 INFO L290 TraceCheckUtils]: 20: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:54,525 INFO L290 TraceCheckUtils]: 19: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-07 21:59:54,525 INFO L290 TraceCheckUtils]: 18: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,526 INFO L290 TraceCheckUtils]: 17: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,526 INFO L290 TraceCheckUtils]: 16: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,526 INFO L290 TraceCheckUtils]: 15: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,527 INFO L290 TraceCheckUtils]: 14: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,527 INFO L290 TraceCheckUtils]: 13: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,527 INFO L290 TraceCheckUtils]: 12: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,527 INFO L290 TraceCheckUtils]: 11: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,528 INFO L290 TraceCheckUtils]: 10: Hoare triple {3903#(<= 0 (+ 1 (div (+ (- 4294967294) (* (- 1) (mod main_~j~0 4294967296))) 4294967296)))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-07 21:59:54,529 INFO L290 TraceCheckUtils]: 9: Hoare triple {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3903#(<= 0 (+ 1 (div (+ (- 4294967294) (* (- 1) (mod main_~j~0 4294967296))) 4294967296)))} is VALID [2022-04-07 21:59:54,529 INFO L290 TraceCheckUtils]: 8: Hoare triple {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-07 21:59:54,530 INFO L290 TraceCheckUtils]: 7: Hoare triple {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-07 21:59:54,530 INFO L290 TraceCheckUtils]: 6: Hoare triple {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-07 21:59:54,531 INFO L290 TraceCheckUtils]: 5: Hoare triple {3720#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-07 21:59:54,531 INFO L272 TraceCheckUtils]: 4: Hoare triple {3720#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:54,531 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:54,531 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:54,531 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-07 21:59:54,531 INFO L272 TraceCheckUtils]: 0: Hoare triple {3720#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-07 21:59:54,531 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 21:59:54,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [60282681] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 21:59:54,532 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 21:59:54,532 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 14 [2022-04-07 21:59:54,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372231753] [2022-04-07 21:59:54,532 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 21:59:54,533 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-07 21:59:54,533 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:54,533 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:54,606 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:54,606 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-07 21:59:54,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:54,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-07 21:59:54,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2022-04-07 21:59:54,607 INFO L87 Difference]: Start difference. First operand 63 states and 74 transitions. Second operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:55,457 INFO L93 Difference]: Finished difference Result 160 states and 193 transitions. [2022-04-07 21:59:55,457 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-07 21:59:55,457 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-07 21:59:55,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 21:59:55,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 105 transitions. [2022-04-07 21:59:55,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 105 transitions. [2022-04-07 21:59:55,459 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 105 transitions. [2022-04-07 21:59:55,543 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 105 edges. 105 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:55,544 INFO L225 Difference]: With dead ends: 160 [2022-04-07 21:59:55,544 INFO L226 Difference]: Without dead ends: 95 [2022-04-07 21:59:55,545 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 60 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=90, Invalid=330, Unknown=0, NotChecked=0, Total=420 [2022-04-07 21:59:55,545 INFO L913 BasicCegarLoop]: 32 mSDtfsCounter, 126 mSDsluCounter, 42 mSDsCounter, 0 mSdLazyCounter, 314 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 127 SdHoareTripleChecker+Valid, 74 SdHoareTripleChecker+Invalid, 340 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 314 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-07 21:59:55,546 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [127 Valid, 74 Invalid, 340 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 314 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-07 21:59:55,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2022-04-07 21:59:55,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 72. [2022-04-07 21:59:55,598 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 21:59:55,598 INFO L82 GeneralOperation]: Start isEquivalent. First operand 95 states. Second operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,598 INFO L74 IsIncluded]: Start isIncluded. First operand 95 states. Second operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,598 INFO L87 Difference]: Start difference. First operand 95 states. Second operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:55,600 INFO L93 Difference]: Finished difference Result 95 states and 112 transitions. [2022-04-07 21:59:55,600 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 112 transitions. [2022-04-07 21:59:55,600 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:55,600 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:55,600 INFO L74 IsIncluded]: Start isIncluded. First operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 95 states. [2022-04-07 21:59:55,600 INFO L87 Difference]: Start difference. First operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 95 states. [2022-04-07 21:59:55,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 21:59:55,603 INFO L93 Difference]: Finished difference Result 95 states and 112 transitions. [2022-04-07 21:59:55,603 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 112 transitions. [2022-04-07 21:59:55,603 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 21:59:55,603 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 21:59:55,603 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 21:59:55,603 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 21:59:55,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 83 transitions. [2022-04-07 21:59:55,605 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 83 transitions. Word has length 33 [2022-04-07 21:59:55,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 21:59:55,605 INFO L478 AbstractCegarLoop]: Abstraction has 72 states and 83 transitions. [2022-04-07 21:59:55,605 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 21:59:55,605 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 83 transitions. [2022-04-07 21:59:55,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-04-07 21:59:55,608 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 21:59:55,608 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 21:59:55,626 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-07 21:59:55,824 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:55,824 INFO L403 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 21:59:55,824 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 21:59:55,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1553999756, now seen corresponding path program 2 times [2022-04-07 21:59:55,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 21:59:55,825 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [491745147] [2022-04-07 21:59:55,825 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 21:59:55,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 21:59:55,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:56,144 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 21:59:56,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:56,156 INFO L290 TraceCheckUtils]: 0: Hoare triple {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-07 21:59:56,156 INFO L290 TraceCheckUtils]: 1: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,156 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,157 INFO L272 TraceCheckUtils]: 0: Hoare triple {4451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 21:59:56,157 INFO L290 TraceCheckUtils]: 1: Hoare triple {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-07 21:59:56,157 INFO L290 TraceCheckUtils]: 2: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,157 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,157 INFO L272 TraceCheckUtils]: 4: Hoare triple {4451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,158 INFO L290 TraceCheckUtils]: 5: Hoare triple {4451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:56,158 INFO L290 TraceCheckUtils]: 6: Hoare triple {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 21:59:56,159 INFO L290 TraceCheckUtils]: 7: Hoare triple {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,159 INFO L290 TraceCheckUtils]: 8: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,159 INFO L290 TraceCheckUtils]: 9: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,160 INFO L290 TraceCheckUtils]: 10: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,160 INFO L290 TraceCheckUtils]: 11: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,160 INFO L290 TraceCheckUtils]: 12: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,161 INFO L290 TraceCheckUtils]: 13: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,161 INFO L290 TraceCheckUtils]: 14: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,162 INFO L290 TraceCheckUtils]: 15: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,163 INFO L290 TraceCheckUtils]: 16: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,163 INFO L290 TraceCheckUtils]: 17: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,166 INFO L290 TraceCheckUtils]: 18: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,166 INFO L290 TraceCheckUtils]: 19: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4459#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} is VALID [2022-04-07 21:59:56,166 INFO L290 TraceCheckUtils]: 20: Hoare triple {4459#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,167 INFO L290 TraceCheckUtils]: 21: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,167 INFO L290 TraceCheckUtils]: 22: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,168 INFO L290 TraceCheckUtils]: 23: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,168 INFO L290 TraceCheckUtils]: 24: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,168 INFO L290 TraceCheckUtils]: 25: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,169 INFO L290 TraceCheckUtils]: 26: Hoare triple {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:56,175 INFO L290 TraceCheckUtils]: 27: Hoare triple {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 21:59:56,176 INFO L290 TraceCheckUtils]: 28: Hoare triple {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:56,181 INFO L290 TraceCheckUtils]: 29: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:56,184 INFO L290 TraceCheckUtils]: 30: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:56,184 INFO L290 TraceCheckUtils]: 31: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:56,185 INFO L290 TraceCheckUtils]: 32: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 21:59:56,185 INFO L290 TraceCheckUtils]: 33: Hoare triple {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:56,186 INFO L272 TraceCheckUtils]: 34: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4467#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 21:59:56,186 INFO L290 TraceCheckUtils]: 35: Hoare triple {4467#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4468#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 21:59:56,186 INFO L290 TraceCheckUtils]: 36: Hoare triple {4468#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-07 21:59:56,186 INFO L290 TraceCheckUtils]: 37: Hoare triple {4452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-07 21:59:56,187 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-07 21:59:56,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 21:59:56,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [491745147] [2022-04-07 21:59:56,187 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [491745147] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 21:59:56,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [319791156] [2022-04-07 21:59:56,187 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 21:59:56,187 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 21:59:56,187 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 21:59:56,188 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 21:59:56,203 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-07 21:59:56,258 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 21:59:56,258 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 21:59:56,259 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 21 conjunts are in the unsatisfiable core [2022-04-07 21:59:56,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 21:59:56,272 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 21:59:56,695 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 21:59:56,696 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-07 21:59:56,802 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 21:59:56,803 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-07 21:59:56,867 INFO L272 TraceCheckUtils]: 0: Hoare triple {4451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,867 INFO L290 TraceCheckUtils]: 1: Hoare triple {4451#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-07 21:59:56,867 INFO L290 TraceCheckUtils]: 2: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,867 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,867 INFO L272 TraceCheckUtils]: 4: Hoare triple {4451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:56,874 INFO L290 TraceCheckUtils]: 5: Hoare triple {4451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,874 INFO L290 TraceCheckUtils]: 6: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,874 INFO L290 TraceCheckUtils]: 7: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,875 INFO L290 TraceCheckUtils]: 8: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,875 INFO L290 TraceCheckUtils]: 9: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,875 INFO L290 TraceCheckUtils]: 10: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,875 INFO L290 TraceCheckUtils]: 11: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,876 INFO L290 TraceCheckUtils]: 12: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 21:59:56,876 INFO L290 TraceCheckUtils]: 13: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,876 INFO L290 TraceCheckUtils]: 14: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,877 INFO L290 TraceCheckUtils]: 15: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,877 INFO L290 TraceCheckUtils]: 16: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,877 INFO L290 TraceCheckUtils]: 17: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,878 INFO L290 TraceCheckUtils]: 18: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-07 21:59:56,878 INFO L290 TraceCheckUtils]: 19: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4531#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} is VALID [2022-04-07 21:59:56,879 INFO L290 TraceCheckUtils]: 20: Hoare triple {4531#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 21:59:56,879 INFO L290 TraceCheckUtils]: 21: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 21:59:56,879 INFO L290 TraceCheckUtils]: 22: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 21:59:56,880 INFO L290 TraceCheckUtils]: 23: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 21:59:56,880 INFO L290 TraceCheckUtils]: 24: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-07 21:59:56,891 INFO L290 TraceCheckUtils]: 25: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4551#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-07 21:59:56,892 INFO L290 TraceCheckUtils]: 26: Hoare triple {4551#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4555#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 21:59:56,892 INFO L290 TraceCheckUtils]: 27: Hoare triple {4555#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 21:59:56,893 INFO L290 TraceCheckUtils]: 28: Hoare triple {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-07 21:59:56,894 INFO L290 TraceCheckUtils]: 29: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:56,894 INFO L290 TraceCheckUtils]: 30: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:56,894 INFO L290 TraceCheckUtils]: 31: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 21:59:56,895 INFO L290 TraceCheckUtils]: 32: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 21:59:56,895 INFO L290 TraceCheckUtils]: 33: Hoare triple {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:56,896 INFO L272 TraceCheckUtils]: 34: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 21:59:56,896 INFO L290 TraceCheckUtils]: 35: Hoare triple {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4584#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 21:59:56,896 INFO L290 TraceCheckUtils]: 36: Hoare triple {4584#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-07 21:59:56,897 INFO L290 TraceCheckUtils]: 37: Hoare triple {4452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-07 21:59:56,897 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 21:59:56,897 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 21:59:59,231 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-07 21:59:59,265 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-07 21:59:59,265 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-07 21:59:59,526 INFO L290 TraceCheckUtils]: 37: Hoare triple {4452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-07 21:59:59,527 INFO L290 TraceCheckUtils]: 36: Hoare triple {4584#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-07 21:59:59,527 INFO L290 TraceCheckUtils]: 35: Hoare triple {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4584#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 21:59:59,528 INFO L272 TraceCheckUtils]: 34: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 21:59:59,528 INFO L290 TraceCheckUtils]: 33: Hoare triple {4603#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 21:59:59,529 INFO L290 TraceCheckUtils]: 32: Hoare triple {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4603#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 21:59:59,529 INFO L290 TraceCheckUtils]: 31: Hoare triple {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:59,529 INFO L290 TraceCheckUtils]: 30: Hoare triple {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:59,530 INFO L290 TraceCheckUtils]: 29: Hoare triple {4617#(forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 21:59:59,531 INFO L290 TraceCheckUtils]: 28: Hoare triple {4621#(or (forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4617#(forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 21:59:59,531 INFO L290 TraceCheckUtils]: 27: Hoare triple {4625#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4621#(or (forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-07 21:59:59,532 INFO L290 TraceCheckUtils]: 26: Hoare triple {4629#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4625#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:59,532 INFO L290 TraceCheckUtils]: 25: Hoare triple {4633#(<= main_~i~0 1)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4629#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 21:59:59,533 INFO L290 TraceCheckUtils]: 24: Hoare triple {4633#(<= main_~i~0 1)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4633#(<= main_~i~0 1)} is VALID [2022-04-07 21:59:59,533 INFO L290 TraceCheckUtils]: 23: Hoare triple {4633#(<= main_~i~0 1)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4633#(<= main_~i~0 1)} is VALID [2022-04-07 21:59:59,533 INFO L290 TraceCheckUtils]: 22: Hoare triple {4633#(<= main_~i~0 1)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4633#(<= main_~i~0 1)} is VALID [2022-04-07 21:59:59,533 INFO L290 TraceCheckUtils]: 21: Hoare triple {4633#(<= main_~i~0 1)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4633#(<= main_~i~0 1)} is VALID [2022-04-07 21:59:59,534 INFO L290 TraceCheckUtils]: 20: Hoare triple {4649#(<= main_~j~0 2)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4633#(<= main_~i~0 1)} is VALID [2022-04-07 21:59:59,534 INFO L290 TraceCheckUtils]: 19: Hoare triple {4653#(<= main_~j~0 1)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4649#(<= main_~j~0 2)} is VALID [2022-04-07 21:59:59,535 INFO L290 TraceCheckUtils]: 18: Hoare triple {4653#(<= main_~j~0 1)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4653#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:59,535 INFO L290 TraceCheckUtils]: 17: Hoare triple {4653#(<= main_~j~0 1)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4653#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:59,535 INFO L290 TraceCheckUtils]: 16: Hoare triple {4653#(<= main_~j~0 1)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4653#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:59,535 INFO L290 TraceCheckUtils]: 15: Hoare triple {4653#(<= main_~j~0 1)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4653#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 14: Hoare triple {4653#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4653#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 13: Hoare triple {4451#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4653#(<= main_~j~0 1)} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 12: Hoare triple {4451#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 11: Hoare triple {4451#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 10: Hoare triple {4451#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 9: Hoare triple {4451#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 8: Hoare triple {4451#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 7: Hoare triple {4451#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 6: Hoare triple {4451#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L290 TraceCheckUtils]: 5: Hoare triple {4451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4451#true} is VALID [2022-04-07 21:59:59,536 INFO L272 TraceCheckUtils]: 4: Hoare triple {4451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:59,537 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:59,537 INFO L290 TraceCheckUtils]: 2: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:59,537 INFO L290 TraceCheckUtils]: 1: Hoare triple {4451#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-07 21:59:59,537 INFO L272 TraceCheckUtils]: 0: Hoare triple {4451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-07 21:59:59,537 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 21:59:59,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [319791156] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 21:59:59,537 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 21:59:59,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 14] total 32 [2022-04-07 21:59:59,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005798242] [2022-04-07 21:59:59,537 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 21:59:59,538 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-07 21:59:59,538 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 21:59:59,538 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 21:59:59,593 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 21:59:59,593 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-04-07 21:59:59,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 21:59:59,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-04-07 21:59:59,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=861, Unknown=1, NotChecked=0, Total=992 [2022-04-07 21:59:59,594 INFO L87 Difference]: Start difference. First operand 72 states and 83 transitions. Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:00:02,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:00:02,685 INFO L93 Difference]: Finished difference Result 211 states and 257 transitions. [2022-04-07 22:00:02,685 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-04-07 22:00:02,686 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-07 22:00:02,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 22:00:02,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:00:02,688 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 195 transitions. [2022-04-07 22:00:02,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:00:02,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 195 transitions. [2022-04-07 22:00:02,690 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 50 states and 195 transitions. [2022-04-07 22:00:02,855 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 195 edges. 195 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:00:02,857 INFO L225 Difference]: With dead ends: 211 [2022-04-07 22:00:02,857 INFO L226 Difference]: Without dead ends: 174 [2022-04-07 22:00:02,858 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 65 SyntacticMatches, 7 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1703 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=1045, Invalid=5116, Unknown=1, NotChecked=0, Total=6162 [2022-04-07 22:00:02,859 INFO L913 BasicCegarLoop]: 22 mSDtfsCounter, 317 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 823 mSolverCounterSat, 290 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 317 SdHoareTripleChecker+Valid, 79 SdHoareTripleChecker+Invalid, 1224 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 290 IncrementalHoareTripleChecker+Valid, 823 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 111 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-04-07 22:00:02,859 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [317 Valid, 79 Invalid, 1224 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [290 Valid, 823 Invalid, 0 Unknown, 111 Unchecked, 1.0s Time] [2022-04-07 22:00:02,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2022-04-07 22:00:02,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 84. [2022-04-07 22:00:02,952 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 22:00:02,952 INFO L82 GeneralOperation]: Start isEquivalent. First operand 174 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:00:02,953 INFO L74 IsIncluded]: Start isIncluded. First operand 174 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:00:02,953 INFO L87 Difference]: Start difference. First operand 174 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:00:02,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:00:02,956 INFO L93 Difference]: Finished difference Result 174 states and 206 transitions. [2022-04-07 22:00:02,956 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 206 transitions. [2022-04-07 22:00:02,956 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:00:02,956 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:00:02,956 INFO L74 IsIncluded]: Start isIncluded. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 174 states. [2022-04-07 22:00:02,956 INFO L87 Difference]: Start difference. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 174 states. [2022-04-07 22:00:02,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:00:02,959 INFO L93 Difference]: Finished difference Result 174 states and 206 transitions. [2022-04-07 22:00:02,959 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 206 transitions. [2022-04-07 22:00:02,960 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:00:02,960 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:00:02,960 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 22:00:02,960 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 22:00:02,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:00:02,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 98 transitions. [2022-04-07 22:00:02,961 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 98 transitions. Word has length 38 [2022-04-07 22:00:02,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 22:00:02,961 INFO L478 AbstractCegarLoop]: Abstraction has 84 states and 98 transitions. [2022-04-07 22:00:02,961 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:00:02,961 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 98 transitions. [2022-04-07 22:00:02,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-04-07 22:00:02,962 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 22:00:02,962 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 22:00:02,980 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-07 22:00:03,167 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable10 [2022-04-07 22:00:03,167 INFO L403 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 22:00:03,168 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 22:00:03,168 INFO L85 PathProgramCache]: Analyzing trace with hash -1626243309, now seen corresponding path program 2 times [2022-04-07 22:00:03,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 22:00:03,168 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1178209773] [2022-04-07 22:00:03,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:00:03,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 22:00:03,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:00:03,755 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 22:00:03,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:00:03,764 INFO L290 TraceCheckUtils]: 0: Hoare triple {5578#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-07 22:00:03,764 INFO L290 TraceCheckUtils]: 1: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:03,764 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:03,765 INFO L272 TraceCheckUtils]: 0: Hoare triple {5553#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5578#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 22:00:03,765 INFO L290 TraceCheckUtils]: 1: Hoare triple {5578#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-07 22:00:03,765 INFO L290 TraceCheckUtils]: 2: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:03,765 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:03,765 INFO L272 TraceCheckUtils]: 4: Hoare triple {5553#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:03,766 INFO L290 TraceCheckUtils]: 5: Hoare triple {5553#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 22:00:03,766 INFO L290 TraceCheckUtils]: 6: Hoare triple {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 22:00:03,767 INFO L290 TraceCheckUtils]: 7: Hoare triple {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:00:03,767 INFO L290 TraceCheckUtils]: 8: Hoare triple {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:00:03,768 INFO L290 TraceCheckUtils]: 9: Hoare triple {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:00:03,768 INFO L290 TraceCheckUtils]: 10: Hoare triple {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:00:03,769 INFO L290 TraceCheckUtils]: 11: Hoare triple {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5561#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:00:03,769 INFO L290 TraceCheckUtils]: 12: Hoare triple {5561#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5561#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:00:03,769 INFO L290 TraceCheckUtils]: 13: Hoare triple {5561#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:00:03,770 INFO L290 TraceCheckUtils]: 14: Hoare triple {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5562#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 22:00:03,771 INFO L290 TraceCheckUtils]: 15: Hoare triple {5562#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5563#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 22:00:03,771 INFO L290 TraceCheckUtils]: 16: Hoare triple {5563#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5564#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:00:03,772 INFO L290 TraceCheckUtils]: 17: Hoare triple {5564#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5565#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:00:03,773 INFO L290 TraceCheckUtils]: 18: Hoare triple {5565#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5566#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:00:03,773 INFO L290 TraceCheckUtils]: 19: Hoare triple {5566#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5567#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} is VALID [2022-04-07 22:00:03,774 INFO L290 TraceCheckUtils]: 20: Hoare triple {5567#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5568#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} is VALID [2022-04-07 22:00:03,774 INFO L290 TraceCheckUtils]: 21: Hoare triple {5568#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,775 INFO L290 TraceCheckUtils]: 22: Hoare triple {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,775 INFO L290 TraceCheckUtils]: 23: Hoare triple {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5570#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,776 INFO L290 TraceCheckUtils]: 24: Hoare triple {5570#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5571#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,777 INFO L290 TraceCheckUtils]: 25: Hoare triple {5571#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-07 22:00:03,777 INFO L290 TraceCheckUtils]: 26: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-07 22:00:03,778 INFO L290 TraceCheckUtils]: 27: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-07 22:00:03,778 INFO L290 TraceCheckUtils]: 28: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-07 22:00:03,779 INFO L290 TraceCheckUtils]: 29: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,780 INFO L290 TraceCheckUtils]: 30: Hoare triple {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,780 INFO L290 TraceCheckUtils]: 31: Hoare triple {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:00:03,780 INFO L290 TraceCheckUtils]: 32: Hoare triple {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5574#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 22:00:03,781 INFO L290 TraceCheckUtils]: 33: Hoare triple {5574#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5575#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:00:03,781 INFO L272 TraceCheckUtils]: 34: Hoare triple {5575#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5576#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 22:00:03,782 INFO L290 TraceCheckUtils]: 35: Hoare triple {5576#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5577#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 22:00:03,782 INFO L290 TraceCheckUtils]: 36: Hoare triple {5577#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-07 22:00:03,782 INFO L290 TraceCheckUtils]: 37: Hoare triple {5554#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-07 22:00:03,782 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 22:00:03,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 22:00:03,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1178209773] [2022-04-07 22:00:03,783 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1178209773] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 22:00:03,783 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [168572965] [2022-04-07 22:00:03,783 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 22:00:03,783 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:00:03,783 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 22:00:03,784 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 22:00:03,785 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-07 22:00:03,831 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 22:00:03,831 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 22:00:03,832 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 30 conjunts are in the unsatisfiable core [2022-04-07 22:00:03,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:00:03,859 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 22:00:04,156 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-07 22:00:04,157 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-07 22:00:04,911 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-07 22:00:04,912 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-07 22:00:06,471 INFO L356 Elim1Store]: treesize reduction 88, result has 22.1 percent of original size [2022-04-07 22:00:06,471 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 37 [2022-04-07 22:00:07,485 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-07 22:00:07,485 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-07 22:00:07,651 INFO L272 TraceCheckUtils]: 0: Hoare triple {5553#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 1: Hoare triple {5553#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 2: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L272 TraceCheckUtils]: 4: Hoare triple {5553#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 5: Hoare triple {5553#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 6: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 7: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 8: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 9: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-07 22:00:07,652 INFO L290 TraceCheckUtils]: 10: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-07 22:00:07,653 INFO L290 TraceCheckUtils]: 11: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-07 22:00:07,653 INFO L290 TraceCheckUtils]: 12: Hoare triple {5553#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:00:07,653 INFO L290 TraceCheckUtils]: 13: Hoare triple {5553#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5621#(= main_~j~0 1)} is VALID [2022-04-07 22:00:07,653 INFO L290 TraceCheckUtils]: 14: Hoare triple {5621#(= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5625#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:00:07,654 INFO L290 TraceCheckUtils]: 15: Hoare triple {5625#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5629#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 22:00:07,655 INFO L290 TraceCheckUtils]: 16: Hoare triple {5629#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5633#(and (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:00:07,655 INFO L290 TraceCheckUtils]: 17: Hoare triple {5633#(and (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5637#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:00:07,656 INFO L290 TraceCheckUtils]: 18: Hoare triple {5637#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5641#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:00:07,657 INFO L290 TraceCheckUtils]: 19: Hoare triple {5641#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5645#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))))} is VALID [2022-04-07 22:00:07,660 INFO L290 TraceCheckUtils]: 20: Hoare triple {5645#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5649#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 22:00:07,662 INFO L290 TraceCheckUtils]: 21: Hoare triple {5649#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} is VALID [2022-04-07 22:00:07,664 INFO L290 TraceCheckUtils]: 22: Hoare triple {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} is VALID [2022-04-07 22:00:07,668 INFO L290 TraceCheckUtils]: 23: Hoare triple {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5660#(and (= main_~j~0 1) (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} is VALID [2022-04-07 22:00:07,668 INFO L290 TraceCheckUtils]: 24: Hoare triple {5660#(and (= main_~j~0 1) (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5664#(and (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:00:07,682 INFO L290 TraceCheckUtils]: 25: Hoare triple {5664#(and (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))) (= (+ (- 1) main_~j~0) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-07 22:00:07,685 INFO L290 TraceCheckUtils]: 26: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-07 22:00:07,688 INFO L290 TraceCheckUtils]: 27: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-07 22:00:07,691 INFO L290 TraceCheckUtils]: 28: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-07 22:00:07,694 INFO L290 TraceCheckUtils]: 29: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} is VALID [2022-04-07 22:00:07,697 INFO L290 TraceCheckUtils]: 30: Hoare triple {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} is VALID [2022-04-07 22:00:07,700 INFO L290 TraceCheckUtils]: 31: Hoare triple {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} is VALID [2022-04-07 22:00:07,703 INFO L290 TraceCheckUtils]: 32: Hoare triple {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5691#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~k~0 1))} is VALID [2022-04-07 22:00:07,704 INFO L290 TraceCheckUtils]: 33: Hoare triple {5691#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5695#(< |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:00:07,705 INFO L272 TraceCheckUtils]: 34: Hoare triple {5695#(< |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:00:07,706 INFO L290 TraceCheckUtils]: 35: Hoare triple {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5703#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:00:07,706 INFO L290 TraceCheckUtils]: 36: Hoare triple {5703#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-07 22:00:07,706 INFO L290 TraceCheckUtils]: 37: Hoare triple {5554#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-07 22:00:07,706 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 22:00:07,706 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 22:00:29,193 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (let ((.cse0 (store (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |c_main_~#v~0.offset| (* c_main_~j~0 4) 4) v_ArrVal_198))) (<= (select .cse0 |c_main_~#v~0.offset|) (select .cse0 (+ |c_main_~#v~0.offset| 4)))) (not (<= v_ArrVal_195 c_main_~key~0)))) (not (<= c_main_~i~0 (+ v_main_~i~0_29 1))))) is different from false [2022-04-07 22:00:35,378 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 77 [2022-04-07 22:00:35,495 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-07 22:00:35,496 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 5803 treesize of output 5609 [2022-04-07 22:01:57,893 INFO L290 TraceCheckUtils]: 37: Hoare triple {5554#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-07 22:01:57,894 INFO L290 TraceCheckUtils]: 36: Hoare triple {5703#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-07 22:01:57,894 INFO L290 TraceCheckUtils]: 35: Hoare triple {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5703#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:01:57,895 INFO L272 TraceCheckUtils]: 34: Hoare triple {5575#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:01:57,895 INFO L290 TraceCheckUtils]: 33: Hoare triple {5722#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5575#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:01:57,895 INFO L290 TraceCheckUtils]: 32: Hoare triple {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5722#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 22:01:57,896 INFO L290 TraceCheckUtils]: 31: Hoare triple {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:01:57,896 INFO L290 TraceCheckUtils]: 30: Hoare triple {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:01:57,897 INFO L290 TraceCheckUtils]: 29: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:01:57,897 INFO L290 TraceCheckUtils]: 28: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:01:57,898 INFO L290 TraceCheckUtils]: 27: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:01:57,898 INFO L290 TraceCheckUtils]: 26: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:01:57,900 INFO L290 TraceCheckUtils]: 25: Hoare triple {5749#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:01:57,903 INFO L290 TraceCheckUtils]: 24: Hoare triple {5753#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5749#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:01:57,904 INFO L290 TraceCheckUtils]: 23: Hoare triple {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5753#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:01:57,904 INFO L290 TraceCheckUtils]: 22: Hoare triple {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 22:01:57,905 INFO L290 TraceCheckUtils]: 21: Hoare triple {5764#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 22:01:57,905 INFO L290 TraceCheckUtils]: 20: Hoare triple {5768#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5764#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-07 22:01:57,907 INFO L290 TraceCheckUtils]: 19: Hoare triple {5772#(forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5768#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} is VALID [2022-04-07 22:01:57,909 INFO L290 TraceCheckUtils]: 18: Hoare triple {5776#(forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5772#(forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} is VALID [2022-04-07 22:01:57,909 INFO L290 TraceCheckUtils]: 17: Hoare triple {5780#(or (forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1))))) (not |main_#t~short10|))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5776#(forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} is VALID [2022-04-07 22:01:57,911 INFO L290 TraceCheckUtils]: 16: Hoare triple {5784#(or (not |main_#t~short10|) (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0)) (= 0 (* main_~i~0 4))) (<= 1 main_~i~0))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5780#(or (forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1))))) (not |main_#t~short10|))} is VALID [2022-04-07 22:01:57,911 INFO L290 TraceCheckUtils]: 15: Hoare triple {5788#(or (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0))) (not (<= 0 main_~i~0)) (<= 1 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5784#(or (not |main_#t~short10|) (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0)) (= 0 (* main_~i~0 4))) (<= 1 main_~i~0))} is VALID [2022-04-07 22:01:57,912 INFO L290 TraceCheckUtils]: 14: Hoare triple {5553#true} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5788#(or (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0))) (not (<= 0 main_~i~0)) (<= 1 main_~i~0))} is VALID [2022-04-07 22:01:57,912 INFO L290 TraceCheckUtils]: 13: Hoare triple {5553#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5553#true} is VALID [2022-04-07 22:01:57,912 INFO L290 TraceCheckUtils]: 12: Hoare triple {5553#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:01:57,912 INFO L290 TraceCheckUtils]: 11: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-07 22:01:57,912 INFO L290 TraceCheckUtils]: 10: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-07 22:01:57,912 INFO L290 TraceCheckUtils]: 9: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L290 TraceCheckUtils]: 8: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L290 TraceCheckUtils]: 7: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L290 TraceCheckUtils]: 6: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L290 TraceCheckUtils]: 5: Hoare triple {5553#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L272 TraceCheckUtils]: 4: Hoare triple {5553#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L290 TraceCheckUtils]: 2: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L290 TraceCheckUtils]: 1: Hoare triple {5553#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L272 TraceCheckUtils]: 0: Hoare triple {5553#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-07 22:01:57,913 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 11 refuted. 1 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 22:01:57,914 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [168572965] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 22:01:57,915 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 22:01:57,915 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19, 18] total 53 [2022-04-07 22:01:57,915 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749494826] [2022-04-07 22:01:57,915 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 22:01:57,917 INFO L78 Accepts]: Start accepts. Automaton has has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-07 22:01:57,918 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 22:01:57,918 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:02:00,048 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 90 edges. 89 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 22:02:00,048 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 53 states [2022-04-07 22:02:00,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 22:02:00,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-04-07 22:02:00,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=285, Invalid=2355, Unknown=16, NotChecked=100, Total=2756 [2022-04-07 22:02:00,049 INFO L87 Difference]: Start difference. First operand 84 states and 98 transitions. Second operand has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:02:02,783 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse5 (select |c_#memory_int| |c_main_~#v~0.base|)) (.cse3 (* c_main_~i~0 4))) (let ((.cse1 (select .cse5 (+ .cse3 |c_main_~#v~0.offset| 4))) (.cse4 (+ c_main_~key~0 1)) (.cse0 (select .cse5 (+ .cse3 |c_main_~#v~0.offset|)))) (and (= |c_#NULL.base| |c_old(#NULL.base)|) (<= (+ c_main_~i~0 1) c_main_~j~0) (<= .cse0 .cse1) (forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (let ((.cse2 (store (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |c_main_~#v~0.offset| (* c_main_~j~0 4) 4) v_ArrVal_198))) (<= (select .cse2 |c_main_~#v~0.offset|) (select .cse2 (+ |c_main_~#v~0.offset| 4)))) (not (<= v_ArrVal_195 c_main_~key~0)))) (not (<= c_main_~i~0 (+ v_main_~i~0_29 1))))) (< c_main_~key~0 .cse0) (<= 0 c_main_~i~0) (= c_main_~j~0 1) (= |c_main_~#v~0.offset| 0) (= .cse3 0) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (<= .cse4 .cse1) (<= .cse4 .cse0)))) is different from false [2022-04-07 22:02:05,079 WARN L833 $PredicateComparison]: unable to prove that (let ((.cse1 (select |c_#memory_int| |c_main_~#v~0.base|)) (.cse2 (* c_main_~i~0 4))) (let ((.cse0 (select .cse1 (+ .cse2 |c_main_~#v~0.offset|)))) (and (= |c_#NULL.base| |c_old(#NULL.base)|) (<= (+ c_main_~i~0 1) c_main_~j~0) (<= .cse0 (select .cse1 (+ .cse2 |c_main_~#v~0.offset| 4))) (forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (let ((.cse3 (store (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |c_main_~#v~0.offset| (* c_main_~j~0 4) 4) v_ArrVal_198))) (<= (select .cse3 |c_main_~#v~0.offset|) (select .cse3 (+ |c_main_~#v~0.offset| 4)))) (not (<= v_ArrVal_195 c_main_~key~0)))) (not (<= c_main_~i~0 (+ v_main_~i~0_29 1))))) (< c_main_~key~0 .cse0) (<= 0 c_main_~i~0) (= c_main_~j~0 1) (= |c_#NULL.offset| |c_old(#NULL.offset)|)))) is different from false [2022-04-07 22:02:17,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:02:17,484 INFO L93 Difference]: Finished difference Result 129 states and 149 transitions. [2022-04-07 22:02:17,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2022-04-07 22:02:17,484 INFO L78 Accepts]: Start accepts. Automaton has has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-07 22:02:17,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 22:02:17,485 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:02:17,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 114 transitions. [2022-04-07 22:02:17,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:02:17,487 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 114 transitions. [2022-04-07 22:02:17,487 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 52 states and 114 transitions. [2022-04-07 22:02:19,631 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 114 edges. 113 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-07 22:02:19,632 INFO L225 Difference]: With dead ends: 129 [2022-04-07 22:02:19,632 INFO L226 Difference]: Without dead ends: 127 [2022-04-07 22:02:19,634 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 51 SyntacticMatches, 2 SemanticMatches, 91 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 2527 ImplicationChecksByTransitivity, 56.6s TimeCoverageRelationStatistics Valid=761, Invalid=7236, Unknown=25, NotChecked=534, Total=8556 [2022-04-07 22:02:19,635 INFO L913 BasicCegarLoop]: 29 mSDtfsCounter, 57 mSDsluCounter, 112 mSDsCounter, 0 mSdLazyCounter, 375 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 58 SdHoareTripleChecker+Valid, 141 SdHoareTripleChecker+Invalid, 656 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 375 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 241 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-04-07 22:02:19,635 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [58 Valid, 141 Invalid, 656 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 375 Invalid, 0 Unknown, 241 Unchecked, 0.4s Time] [2022-04-07 22:02:19,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2022-04-07 22:02:19,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 84. [2022-04-07 22:02:19,723 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 22:02:19,723 INFO L82 GeneralOperation]: Start isEquivalent. First operand 127 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:02:19,723 INFO L74 IsIncluded]: Start isIncluded. First operand 127 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:02:19,723 INFO L87 Difference]: Start difference. First operand 127 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:02:19,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:02:19,725 INFO L93 Difference]: Finished difference Result 127 states and 147 transitions. [2022-04-07 22:02:19,725 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 147 transitions. [2022-04-07 22:02:19,725 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:02:19,725 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:02:19,725 INFO L74 IsIncluded]: Start isIncluded. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 127 states. [2022-04-07 22:02:19,726 INFO L87 Difference]: Start difference. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 127 states. [2022-04-07 22:02:19,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:02:19,727 INFO L93 Difference]: Finished difference Result 127 states and 147 transitions. [2022-04-07 22:02:19,727 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 147 transitions. [2022-04-07 22:02:19,727 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:02:19,727 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:02:19,727 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 22:02:19,727 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 22:02:19,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-07 22:02:19,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 98 transitions. [2022-04-07 22:02:19,729 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 98 transitions. Word has length 38 [2022-04-07 22:02:19,729 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 22:02:19,729 INFO L478 AbstractCegarLoop]: Abstraction has 84 states and 98 transitions. [2022-04-07 22:02:19,729 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:02:19,729 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 98 transitions. [2022-04-07 22:02:19,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2022-04-07 22:02:19,729 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 22:02:19,729 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 22:02:19,745 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-04-07 22:02:19,943 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:02:19,944 INFO L403 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 22:02:19,944 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 22:02:19,944 INFO L85 PathProgramCache]: Analyzing trace with hash -1062518689, now seen corresponding path program 2 times [2022-04-07 22:02:19,944 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 22:02:19,944 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [400876535] [2022-04-07 22:02:19,944 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:02:19,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 22:02:19,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:02:20,208 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 22:02:20,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:02:20,212 INFO L290 TraceCheckUtils]: 0: Hoare triple {6478#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6457#true} is VALID [2022-04-07 22:02:20,212 INFO L290 TraceCheckUtils]: 1: Hoare triple {6457#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,212 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {6457#true} {6457#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,212 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 29 [2022-04-07 22:02:20,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:02:20,215 INFO L290 TraceCheckUtils]: 0: Hoare triple {6457#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6457#true} is VALID [2022-04-07 22:02:20,216 INFO L290 TraceCheckUtils]: 1: Hoare triple {6457#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,216 INFO L290 TraceCheckUtils]: 2: Hoare triple {6457#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,216 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6457#true} {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:20,217 INFO L272 TraceCheckUtils]: 0: Hoare triple {6457#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6478#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 22:02:20,217 INFO L290 TraceCheckUtils]: 1: Hoare triple {6478#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6457#true} is VALID [2022-04-07 22:02:20,217 INFO L290 TraceCheckUtils]: 2: Hoare triple {6457#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,217 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6457#true} {6457#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,217 INFO L272 TraceCheckUtils]: 4: Hoare triple {6457#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,218 INFO L290 TraceCheckUtils]: 5: Hoare triple {6457#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6462#(= main_~j~0 0)} is VALID [2022-04-07 22:02:20,218 INFO L290 TraceCheckUtils]: 6: Hoare triple {6462#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6462#(= main_~j~0 0)} is VALID [2022-04-07 22:02:20,218 INFO L290 TraceCheckUtils]: 7: Hoare triple {6462#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,219 INFO L290 TraceCheckUtils]: 8: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,220 INFO L290 TraceCheckUtils]: 9: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:02:20,221 INFO L290 TraceCheckUtils]: 10: Hoare triple {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:02:20,221 INFO L290 TraceCheckUtils]: 11: Hoare triple {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:20,221 INFO L290 TraceCheckUtils]: 12: Hoare triple {6457#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,221 INFO L290 TraceCheckUtils]: 13: Hoare triple {6457#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,222 INFO L290 TraceCheckUtils]: 14: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,222 INFO L290 TraceCheckUtils]: 15: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,223 INFO L290 TraceCheckUtils]: 16: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,223 INFO L290 TraceCheckUtils]: 17: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,223 INFO L290 TraceCheckUtils]: 18: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:20,224 INFO L290 TraceCheckUtils]: 19: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:02:20,225 INFO L290 TraceCheckUtils]: 20: Hoare triple {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6465#(= 4 (* main_~i~0 4))} is VALID [2022-04-07 22:02:20,225 INFO L290 TraceCheckUtils]: 21: Hoare triple {6465#(= 4 (* main_~i~0 4))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6465#(= 4 (* main_~i~0 4))} is VALID [2022-04-07 22:02:20,226 INFO L290 TraceCheckUtils]: 22: Hoare triple {6465#(= 4 (* main_~i~0 4))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6466#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 22:02:20,226 INFO L290 TraceCheckUtils]: 23: Hoare triple {6466#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6467#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:02:20,227 INFO L290 TraceCheckUtils]: 24: Hoare triple {6467#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:20,227 INFO L290 TraceCheckUtils]: 25: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:20,227 INFO L290 TraceCheckUtils]: 26: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:20,228 INFO L290 TraceCheckUtils]: 27: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:20,228 INFO L290 TraceCheckUtils]: 28: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:20,228 INFO L272 TraceCheckUtils]: 29: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6457#true} is VALID [2022-04-07 22:02:20,228 INFO L290 TraceCheckUtils]: 30: Hoare triple {6457#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6457#true} is VALID [2022-04-07 22:02:20,228 INFO L290 TraceCheckUtils]: 31: Hoare triple {6457#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,228 INFO L290 TraceCheckUtils]: 32: Hoare triple {6457#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:20,229 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {6457#true} {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:20,230 INFO L290 TraceCheckUtils]: 34: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:20,230 INFO L290 TraceCheckUtils]: 35: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {6474#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 22:02:20,231 INFO L290 TraceCheckUtils]: 36: Hoare triple {6474#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6475#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:02:20,231 INFO L272 TraceCheckUtils]: 37: Hoare triple {6475#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6476#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 22:02:20,231 INFO L290 TraceCheckUtils]: 38: Hoare triple {6476#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6477#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 22:02:20,232 INFO L290 TraceCheckUtils]: 39: Hoare triple {6477#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6458#false} is VALID [2022-04-07 22:02:20,232 INFO L290 TraceCheckUtils]: 40: Hoare triple {6458#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6458#false} is VALID [2022-04-07 22:02:20,232 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 22:02:20,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 22:02:20,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [400876535] [2022-04-07 22:02:20,232 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [400876535] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 22:02:20,232 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1454527620] [2022-04-07 22:02:20,232 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 22:02:20,232 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:02:20,233 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 22:02:20,236 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 22:02:20,237 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-04-07 22:02:20,290 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 22:02:20,290 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 22:02:20,291 INFO L263 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 26 conjunts are in the unsatisfiable core [2022-04-07 22:02:20,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:02:20,305 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 22:02:20,485 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 12 [2022-04-07 22:02:20,662 INFO L356 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2022-04-07 22:02:20,662 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 22 [2022-04-07 22:02:22,719 WARN L855 $PredicateComparison]: unable to prove that (exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (let ((.cse0 (select |c_#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|))) (<= (select .cse0 (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select .cse0 (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))) is different from true [2022-04-07 22:02:22,877 INFO L356 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2022-04-07 22:02:22,878 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 10 [2022-04-07 22:02:22,951 INFO L272 TraceCheckUtils]: 0: Hoare triple {6457#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 1: Hoare triple {6457#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 2: Hoare triple {6457#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6457#true} {6457#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L272 TraceCheckUtils]: 4: Hoare triple {6457#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 5: Hoare triple {6457#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 6: Hoare triple {6457#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 7: Hoare triple {6457#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 8: Hoare triple {6457#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 9: Hoare triple {6457#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 10: Hoare triple {6457#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 11: Hoare triple {6457#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:22,952 INFO L290 TraceCheckUtils]: 12: Hoare triple {6457#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:22,953 INFO L290 TraceCheckUtils]: 13: Hoare triple {6457#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:22,956 INFO L290 TraceCheckUtils]: 14: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6524#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:22,957 INFO L290 TraceCheckUtils]: 15: Hoare triple {6524#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6528#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 22:02:22,957 INFO L290 TraceCheckUtils]: 16: Hoare triple {6528#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6532#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:22,957 INFO L290 TraceCheckUtils]: 17: Hoare triple {6532#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6532#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:22,958 INFO L290 TraceCheckUtils]: 18: Hoare triple {6532#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:22,958 INFO L290 TraceCheckUtils]: 19: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:02:22,959 INFO L290 TraceCheckUtils]: 20: Hoare triple {6464#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6465#(= 4 (* main_~i~0 4))} is VALID [2022-04-07 22:02:22,959 INFO L290 TraceCheckUtils]: 21: Hoare triple {6465#(= 4 (* main_~i~0 4))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6465#(= 4 (* main_~i~0 4))} is VALID [2022-04-07 22:02:22,960 INFO L290 TraceCheckUtils]: 22: Hoare triple {6465#(= 4 (* main_~i~0 4))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6466#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 22:02:22,960 INFO L290 TraceCheckUtils]: 23: Hoare triple {6466#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6467#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:02:22,961 INFO L290 TraceCheckUtils]: 24: Hoare triple {6467#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:22,961 INFO L290 TraceCheckUtils]: 25: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:22,962 INFO L290 TraceCheckUtils]: 26: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:22,962 INFO L290 TraceCheckUtils]: 27: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:22,963 INFO L290 TraceCheckUtils]: 28: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:22,964 INFO L272 TraceCheckUtils]: 29: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-07 22:02:22,964 INFO L290 TraceCheckUtils]: 30: Hoare triple {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-07 22:02:22,964 INFO L290 TraceCheckUtils]: 31: Hoare triple {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-07 22:02:22,965 INFO L290 TraceCheckUtils]: 32: Hoare triple {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-07 22:02:22,965 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {6572#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:22,966 INFO L290 TraceCheckUtils]: 34: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:22,966 INFO L290 TraceCheckUtils]: 35: Hoare triple {6469#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {6591#(and (= (+ (- 1) main_~k~0) 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-07 22:02:22,966 INFO L290 TraceCheckUtils]: 36: Hoare triple {6591#(and (= (+ (- 1) main_~k~0) 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6475#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:02:22,967 INFO L272 TraceCheckUtils]: 37: Hoare triple {6475#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6598#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:02:22,967 INFO L290 TraceCheckUtils]: 38: Hoare triple {6598#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6602#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:02:22,967 INFO L290 TraceCheckUtils]: 39: Hoare triple {6602#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6458#false} is VALID [2022-04-07 22:02:22,968 INFO L290 TraceCheckUtils]: 40: Hoare triple {6458#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6458#false} is VALID [2022-04-07 22:02:22,968 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 9 trivial. 2 not checked. [2022-04-07 22:02:22,968 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 22:02:27,769 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 61 [2022-04-07 22:02:27,832 INFO L356 Elim1Store]: treesize reduction 25, result has 39.0 percent of original size [2022-04-07 22:02:27,832 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 903 treesize of output 848 [2022-04-07 22:02:28,615 INFO L290 TraceCheckUtils]: 40: Hoare triple {6458#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6458#false} is VALID [2022-04-07 22:02:28,616 INFO L290 TraceCheckUtils]: 39: Hoare triple {6602#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6458#false} is VALID [2022-04-07 22:02:28,616 INFO L290 TraceCheckUtils]: 38: Hoare triple {6598#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6602#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:02:28,617 INFO L272 TraceCheckUtils]: 37: Hoare triple {6475#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6598#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:02:28,617 INFO L290 TraceCheckUtils]: 36: Hoare triple {6474#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6475#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:02:28,619 INFO L290 TraceCheckUtils]: 35: Hoare triple {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {6474#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 22:02:28,619 INFO L290 TraceCheckUtils]: 34: Hoare triple {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:02:28,620 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {6457#true} {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:02:28,620 INFO L290 TraceCheckUtils]: 32: Hoare triple {6457#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,620 INFO L290 TraceCheckUtils]: 31: Hoare triple {6457#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,620 INFO L290 TraceCheckUtils]: 30: Hoare triple {6457#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6457#true} is VALID [2022-04-07 22:02:28,620 INFO L272 TraceCheckUtils]: 29: Hoare triple {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6457#true} is VALID [2022-04-07 22:02:28,622 INFO L290 TraceCheckUtils]: 28: Hoare triple {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:02:28,623 INFO L290 TraceCheckUtils]: 27: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6624#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:02:28,623 INFO L290 TraceCheckUtils]: 26: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:28,624 INFO L290 TraceCheckUtils]: 25: Hoare triple {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:28,626 INFO L290 TraceCheckUtils]: 24: Hoare triple {6658#(forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6468#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:02:28,626 INFO L290 TraceCheckUtils]: 23: Hoare triple {6662#(or (forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6658#(forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8)))))} is VALID [2022-04-07 22:02:28,628 INFO L290 TraceCheckUtils]: 22: Hoare triple {6666#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6662#(or (forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))))) |main_#t~short10|)} is VALID [2022-04-07 22:02:28,629 INFO L290 TraceCheckUtils]: 21: Hoare triple {6666#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6666#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} is VALID [2022-04-07 22:02:28,634 INFO L290 TraceCheckUtils]: 20: Hoare triple {6673#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6666#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} is VALID [2022-04-07 22:02:28,639 INFO L290 TraceCheckUtils]: 19: Hoare triple {6677#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4))))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6673#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))))))} is VALID [2022-04-07 22:02:28,641 INFO L290 TraceCheckUtils]: 18: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6677#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4))))))} is VALID [2022-04-07 22:02:28,641 INFO L290 TraceCheckUtils]: 17: Hoare triple {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:28,642 INFO L290 TraceCheckUtils]: 16: Hoare triple {6687#(or (not |main_#t~short10|) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6463#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:02:28,642 INFO L290 TraceCheckUtils]: 15: Hoare triple {6691#(or (not (<= 0 main_~i~0)) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6687#(or (not |main_#t~short10|) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} is VALID [2022-04-07 22:02:28,643 INFO L290 TraceCheckUtils]: 14: Hoare triple {6695#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6691#(or (not (<= 0 main_~i~0)) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 13: Hoare triple {6457#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6695#(<= main_~j~0 1)} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 12: Hoare triple {6457#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 11: Hoare triple {6457#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 10: Hoare triple {6457#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6457#true} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 9: Hoare triple {6457#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 8: Hoare triple {6457#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6457#true} is VALID [2022-04-07 22:02:28,644 INFO L290 TraceCheckUtils]: 7: Hoare triple {6457#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L290 TraceCheckUtils]: 6: Hoare triple {6457#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L290 TraceCheckUtils]: 5: Hoare triple {6457#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L272 TraceCheckUtils]: 4: Hoare triple {6457#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6457#true} {6457#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L290 TraceCheckUtils]: 2: Hoare triple {6457#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L290 TraceCheckUtils]: 1: Hoare triple {6457#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6457#true} is VALID [2022-04-07 22:02:28,645 INFO L272 TraceCheckUtils]: 0: Hoare triple {6457#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6457#true} is VALID [2022-04-07 22:02:28,646 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 22:02:28,646 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1454527620] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 22:02:28,646 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 22:02:28,646 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 17] total 31 [2022-04-07 22:02:28,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1499873754] [2022-04-07 22:02:28,646 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 22:02:28,647 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 41 [2022-04-07 22:02:28,649 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 22:02:28,649 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:02:28,737 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:02:28,737 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-04-07 22:02:28,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 22:02:28,739 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-04-07 22:02:28,739 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=773, Unknown=2, NotChecked=56, Total=930 [2022-04-07 22:02:28,740 INFO L87 Difference]: Start difference. First operand 84 states and 98 transitions. Second operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:04,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:04,918 INFO L93 Difference]: Finished difference Result 128 states and 150 transitions. [2022-04-07 22:03:04,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2022-04-07 22:03:04,918 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 41 [2022-04-07 22:03:04,921 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 22:03:04,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:04,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 95 transitions. [2022-04-07 22:03:04,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:04,923 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 95 transitions. [2022-04-07 22:03:04,924 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 26 states and 95 transitions. [2022-04-07 22:03:05,027 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:03:05,029 INFO L225 Difference]: With dead ends: 128 [2022-04-07 22:03:05,029 INFO L226 Difference]: Without dead ends: 126 [2022-04-07 22:03:05,030 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 72 SyntacticMatches, 9 SemanticMatches, 51 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 577 ImplicationChecksByTransitivity, 41.1s TimeCoverageRelationStatistics Valid=297, Invalid=2341, Unknown=18, NotChecked=100, Total=2756 [2022-04-07 22:03:05,030 INFO L913 BasicCegarLoop]: 30 mSDtfsCounter, 115 mSDsluCounter, 93 mSDsCounter, 0 mSdLazyCounter, 726 mSolverCounterSat, 47 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 116 SdHoareTripleChecker+Valid, 123 SdHoareTripleChecker+Invalid, 1112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 47 IncrementalHoareTripleChecker+Valid, 726 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 339 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-04-07 22:03:05,030 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [116 Valid, 123 Invalid, 1112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [47 Valid, 726 Invalid, 0 Unknown, 339 Unchecked, 0.7s Time] [2022-04-07 22:03:05,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2022-04-07 22:03:05,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 99. [2022-04-07 22:03:05,151 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 22:03:05,151 INFO L82 GeneralOperation]: Start isEquivalent. First operand 126 states. Second operand has 99 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 90 states have internal predecessors, (106), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:05,151 INFO L74 IsIncluded]: Start isIncluded. First operand 126 states. Second operand has 99 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 90 states have internal predecessors, (106), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:05,151 INFO L87 Difference]: Start difference. First operand 126 states. Second operand has 99 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 90 states have internal predecessors, (106), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:05,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:05,153 INFO L93 Difference]: Finished difference Result 126 states and 148 transitions. [2022-04-07 22:03:05,153 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 148 transitions. [2022-04-07 22:03:05,153 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:03:05,153 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:03:05,154 INFO L74 IsIncluded]: Start isIncluded. First operand has 99 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 90 states have internal predecessors, (106), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 126 states. [2022-04-07 22:03:05,154 INFO L87 Difference]: Start difference. First operand has 99 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 90 states have internal predecessors, (106), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 126 states. [2022-04-07 22:03:05,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:05,156 INFO L93 Difference]: Finished difference Result 126 states and 148 transitions. [2022-04-07 22:03:05,156 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 148 transitions. [2022-04-07 22:03:05,156 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:03:05,156 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:03:05,157 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 22:03:05,157 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 22:03:05,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99 states, 89 states have (on average 1.1910112359550562) internal successors, (106), 90 states have internal predecessors, (106), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:05,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 115 transitions. [2022-04-07 22:03:05,158 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 115 transitions. Word has length 41 [2022-04-07 22:03:05,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 22:03:05,158 INFO L478 AbstractCegarLoop]: Abstraction has 99 states and 115 transitions. [2022-04-07 22:03:05,158 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:05,158 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 115 transitions. [2022-04-07 22:03:05,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2022-04-07 22:03:05,159 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 22:03:05,159 INFO L499 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 22:03:05,174 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-04-07 22:03:05,363 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-04-07 22:03:05,363 INFO L403 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 22:03:05,364 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 22:03:05,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1915025960, now seen corresponding path program 1 times [2022-04-07 22:03:05,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 22:03:05,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101754505] [2022-04-07 22:03:05,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:03:05,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 22:03:05,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:05,546 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 22:03:05,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:05,550 INFO L290 TraceCheckUtils]: 0: Hoare triple {7360#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7347#true} is VALID [2022-04-07 22:03:05,550 INFO L290 TraceCheckUtils]: 1: Hoare triple {7347#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:05,550 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {7347#true} {7347#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:05,550 INFO L272 TraceCheckUtils]: 0: Hoare triple {7347#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7360#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 22:03:05,551 INFO L290 TraceCheckUtils]: 1: Hoare triple {7360#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7347#true} is VALID [2022-04-07 22:03:05,551 INFO L290 TraceCheckUtils]: 2: Hoare triple {7347#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:05,551 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {7347#true} {7347#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:05,551 INFO L272 TraceCheckUtils]: 4: Hoare triple {7347#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:05,551 INFO L290 TraceCheckUtils]: 5: Hoare triple {7347#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {7352#(= main_~j~0 0)} is VALID [2022-04-07 22:03:05,551 INFO L290 TraceCheckUtils]: 6: Hoare triple {7352#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7352#(= main_~j~0 0)} is VALID [2022-04-07 22:03:05,552 INFO L290 TraceCheckUtils]: 7: Hoare triple {7352#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:05,552 INFO L290 TraceCheckUtils]: 8: Hoare triple {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:05,553 INFO L290 TraceCheckUtils]: 9: Hoare triple {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:05,553 INFO L290 TraceCheckUtils]: 10: Hoare triple {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:05,554 INFO L290 TraceCheckUtils]: 11: Hoare triple {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7355#(and (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-07 22:03:05,555 INFO L290 TraceCheckUtils]: 12: Hoare triple {7355#(and (<= 3 main_~j~0) (<= main_~j~0 3))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {7356#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,555 INFO L290 TraceCheckUtils]: 13: Hoare triple {7356#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:05,556 INFO L290 TraceCheckUtils]: 14: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:05,556 INFO L290 TraceCheckUtils]: 15: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:05,557 INFO L290 TraceCheckUtils]: 16: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:05,557 INFO L290 TraceCheckUtils]: 17: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:05,557 INFO L290 TraceCheckUtils]: 18: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:05,558 INFO L290 TraceCheckUtils]: 19: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,559 INFO L290 TraceCheckUtils]: 20: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,559 INFO L290 TraceCheckUtils]: 21: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,560 INFO L290 TraceCheckUtils]: 22: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,560 INFO L290 TraceCheckUtils]: 23: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,560 INFO L290 TraceCheckUtils]: 24: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,561 INFO L290 TraceCheckUtils]: 25: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7359#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:05,562 INFO L290 TraceCheckUtils]: 26: Hoare triple {7359#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7348#false} is VALID [2022-04-07 22:03:05,562 INFO L290 TraceCheckUtils]: 27: Hoare triple {7348#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7348#false} is VALID [2022-04-07 22:03:05,562 INFO L290 TraceCheckUtils]: 28: Hoare triple {7348#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 29: Hoare triple {7348#false} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 30: Hoare triple {7348#false} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 31: Hoare triple {7348#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 32: Hoare triple {7348#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 33: Hoare triple {7348#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 34: Hoare triple {7348#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 35: Hoare triple {7348#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 36: Hoare triple {7348#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 37: Hoare triple {7348#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 38: Hoare triple {7348#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 39: Hoare triple {7348#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L272 TraceCheckUtils]: 40: Hoare triple {7348#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 41: Hoare triple {7348#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {7348#false} is VALID [2022-04-07 22:03:05,563 INFO L290 TraceCheckUtils]: 42: Hoare triple {7348#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:05,564 INFO L290 TraceCheckUtils]: 43: Hoare triple {7348#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:05,564 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 19 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-07 22:03:05,564 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 22:03:05,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2101754505] [2022-04-07 22:03:05,564 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2101754505] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 22:03:05,564 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1251439425] [2022-04-07 22:03:05,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:03:05,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:03:05,564 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 22:03:05,565 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 22:03:05,566 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-04-07 22:03:05,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:05,618 INFO L263 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 16 conjunts are in the unsatisfiable core [2022-04-07 22:03:05,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:05,627 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 22:03:06,129 INFO L272 TraceCheckUtils]: 0: Hoare triple {7347#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,130 INFO L290 TraceCheckUtils]: 1: Hoare triple {7347#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7347#true} is VALID [2022-04-07 22:03:06,130 INFO L290 TraceCheckUtils]: 2: Hoare triple {7347#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,130 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {7347#true} {7347#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,130 INFO L272 TraceCheckUtils]: 4: Hoare triple {7347#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,130 INFO L290 TraceCheckUtils]: 5: Hoare triple {7347#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {7352#(= main_~j~0 0)} is VALID [2022-04-07 22:03:06,130 INFO L290 TraceCheckUtils]: 6: Hoare triple {7352#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7352#(= main_~j~0 0)} is VALID [2022-04-07 22:03:06,131 INFO L290 TraceCheckUtils]: 7: Hoare triple {7352#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:06,131 INFO L290 TraceCheckUtils]: 8: Hoare triple {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:06,132 INFO L290 TraceCheckUtils]: 9: Hoare triple {7353#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:06,132 INFO L290 TraceCheckUtils]: 10: Hoare triple {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:06,132 INFO L290 TraceCheckUtils]: 11: Hoare triple {7354#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7355#(and (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-07 22:03:06,133 INFO L290 TraceCheckUtils]: 12: Hoare triple {7355#(and (<= 3 main_~j~0) (<= main_~j~0 3))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {7356#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,134 INFO L290 TraceCheckUtils]: 13: Hoare triple {7356#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:06,134 INFO L290 TraceCheckUtils]: 14: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:06,134 INFO L290 TraceCheckUtils]: 15: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:06,135 INFO L290 TraceCheckUtils]: 16: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:06,135 INFO L290 TraceCheckUtils]: 17: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:06,135 INFO L290 TraceCheckUtils]: 18: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-07 22:03:06,136 INFO L290 TraceCheckUtils]: 19: Hoare triple {7357#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,136 INFO L290 TraceCheckUtils]: 20: Hoare triple {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,137 INFO L290 TraceCheckUtils]: 21: Hoare triple {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,137 INFO L290 TraceCheckUtils]: 22: Hoare triple {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,137 INFO L290 TraceCheckUtils]: 23: Hoare triple {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,138 INFO L290 TraceCheckUtils]: 24: Hoare triple {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,138 INFO L290 TraceCheckUtils]: 25: Hoare triple {7421#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7440#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 2) main_~j~0) 1))} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 26: Hoare triple {7440#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 2) main_~j~0) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 27: Hoare triple {7348#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 28: Hoare triple {7348#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 29: Hoare triple {7348#false} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 30: Hoare triple {7348#false} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 31: Hoare triple {7348#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 32: Hoare triple {7348#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 33: Hoare triple {7348#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 34: Hoare triple {7348#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 35: Hoare triple {7348#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 36: Hoare triple {7348#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 37: Hoare triple {7348#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,139 INFO L290 TraceCheckUtils]: 38: Hoare triple {7348#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {7348#false} is VALID [2022-04-07 22:03:06,140 INFO L290 TraceCheckUtils]: 39: Hoare triple {7348#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {7348#false} is VALID [2022-04-07 22:03:06,140 INFO L272 TraceCheckUtils]: 40: Hoare triple {7348#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {7348#false} is VALID [2022-04-07 22:03:06,140 INFO L290 TraceCheckUtils]: 41: Hoare triple {7348#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {7348#false} is VALID [2022-04-07 22:03:06,140 INFO L290 TraceCheckUtils]: 42: Hoare triple {7348#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,140 INFO L290 TraceCheckUtils]: 43: Hoare triple {7348#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,140 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 19 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-07 22:03:06,140 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 22:03:06,555 INFO L290 TraceCheckUtils]: 43: Hoare triple {7348#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,555 INFO L290 TraceCheckUtils]: 42: Hoare triple {7348#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,555 INFO L290 TraceCheckUtils]: 41: Hoare triple {7348#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {7348#false} is VALID [2022-04-07 22:03:06,555 INFO L272 TraceCheckUtils]: 40: Hoare triple {7348#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 39: Hoare triple {7348#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 38: Hoare triple {7348#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 37: Hoare triple {7348#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 36: Hoare triple {7348#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 35: Hoare triple {7348#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 34: Hoare triple {7348#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 33: Hoare triple {7348#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 32: Hoare triple {7348#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 31: Hoare triple {7348#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 30: Hoare triple {7348#false} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 29: Hoare triple {7348#false} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 28: Hoare triple {7348#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7348#false} is VALID [2022-04-07 22:03:06,556 INFO L290 TraceCheckUtils]: 27: Hoare triple {7348#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7348#false} is VALID [2022-04-07 22:03:06,557 INFO L290 TraceCheckUtils]: 26: Hoare triple {7359#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7348#false} is VALID [2022-04-07 22:03:06,558 INFO L290 TraceCheckUtils]: 25: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7359#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,559 INFO L290 TraceCheckUtils]: 24: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,559 INFO L290 TraceCheckUtils]: 23: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,559 INFO L290 TraceCheckUtils]: 22: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,560 INFO L290 TraceCheckUtils]: 21: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,560 INFO L290 TraceCheckUtils]: 20: Hoare triple {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,561 INFO L290 TraceCheckUtils]: 19: Hoare triple {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7358#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,561 INFO L290 TraceCheckUtils]: 18: Hoare triple {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-07 22:03:06,562 INFO L290 TraceCheckUtils]: 17: Hoare triple {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-07 22:03:06,562 INFO L290 TraceCheckUtils]: 16: Hoare triple {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-07 22:03:06,563 INFO L290 TraceCheckUtils]: 15: Hoare triple {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-07 22:03:06,563 INFO L290 TraceCheckUtils]: 14: Hoare triple {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-07 22:03:06,564 INFO L290 TraceCheckUtils]: 13: Hoare triple {7356#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {7567#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-07 22:03:06,564 INFO L290 TraceCheckUtils]: 12: Hoare triple {7589#(<= 0 (div (+ 3 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {7356#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-07 22:03:06,565 INFO L290 TraceCheckUtils]: 11: Hoare triple {7593#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7589#(<= 0 (div (+ 3 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} is VALID [2022-04-07 22:03:06,565 INFO L290 TraceCheckUtils]: 10: Hoare triple {7593#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7593#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} is VALID [2022-04-07 22:03:06,566 INFO L290 TraceCheckUtils]: 9: Hoare triple {7600#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7593#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} is VALID [2022-04-07 22:03:06,567 INFO L290 TraceCheckUtils]: 8: Hoare triple {7600#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7600#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-07 22:03:06,568 INFO L290 TraceCheckUtils]: 7: Hoare triple {7607#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7600#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-07 22:03:06,568 INFO L290 TraceCheckUtils]: 6: Hoare triple {7607#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7607#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} is VALID [2022-04-07 22:03:06,569 INFO L290 TraceCheckUtils]: 5: Hoare triple {7347#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {7607#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} is VALID [2022-04-07 22:03:06,569 INFO L272 TraceCheckUtils]: 4: Hoare triple {7347#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,569 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {7347#true} {7347#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,569 INFO L290 TraceCheckUtils]: 2: Hoare triple {7347#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,569 INFO L290 TraceCheckUtils]: 1: Hoare triple {7347#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7347#true} is VALID [2022-04-07 22:03:06,569 INFO L272 TraceCheckUtils]: 0: Hoare triple {7347#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7347#true} is VALID [2022-04-07 22:03:06,569 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 19 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-07 22:03:06,569 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1251439425] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 22:03:06,569 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 22:03:06,569 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 18 [2022-04-07 22:03:06,569 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [279122511] [2022-04-07 22:03:06,569 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 22:03:06,570 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 44 [2022-04-07 22:03:06,570 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 22:03:06,570 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:03:06,626 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:03:06,626 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-04-07 22:03:06,626 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 22:03:06,626 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-04-07 22:03:06,626 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2022-04-07 22:03:06,627 INFO L87 Difference]: Start difference. First operand 99 states and 115 transitions. Second operand has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:03:08,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:08,157 INFO L93 Difference]: Finished difference Result 237 states and 284 transitions. [2022-04-07 22:03:08,157 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-07 22:03:08,157 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 44 [2022-04-07 22:03:08,157 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 22:03:08,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:03:08,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 126 transitions. [2022-04-07 22:03:08,158 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:03:08,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 126 transitions. [2022-04-07 22:03:08,159 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 126 transitions. [2022-04-07 22:03:08,272 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:03:08,274 INFO L225 Difference]: With dead ends: 237 [2022-04-07 22:03:08,274 INFO L226 Difference]: Without dead ends: 189 [2022-04-07 22:03:08,275 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 78 SyntacticMatches, 6 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=125, Invalid=525, Unknown=0, NotChecked=0, Total=650 [2022-04-07 22:03:08,275 INFO L913 BasicCegarLoop]: 41 mSDtfsCounter, 265 mSDsluCounter, 42 mSDsCounter, 0 mSdLazyCounter, 460 mSolverCounterSat, 46 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 265 SdHoareTripleChecker+Valid, 83 SdHoareTripleChecker+Invalid, 506 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 46 IncrementalHoareTripleChecker+Valid, 460 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-04-07 22:03:08,275 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [265 Valid, 83 Invalid, 506 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [46 Valid, 460 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-04-07 22:03:08,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2022-04-07 22:03:08,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 133. [2022-04-07 22:03:08,439 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 22:03:08,440 INFO L82 GeneralOperation]: Start isEquivalent. First operand 189 states. Second operand has 133 states, 123 states have (on average 1.1788617886178863) internal successors, (145), 124 states have internal predecessors, (145), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:08,440 INFO L74 IsIncluded]: Start isIncluded. First operand 189 states. Second operand has 133 states, 123 states have (on average 1.1788617886178863) internal successors, (145), 124 states have internal predecessors, (145), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:08,440 INFO L87 Difference]: Start difference. First operand 189 states. Second operand has 133 states, 123 states have (on average 1.1788617886178863) internal successors, (145), 124 states have internal predecessors, (145), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:08,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:08,443 INFO L93 Difference]: Finished difference Result 189 states and 223 transitions. [2022-04-07 22:03:08,443 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 223 transitions. [2022-04-07 22:03:08,443 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:03:08,443 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:03:08,443 INFO L74 IsIncluded]: Start isIncluded. First operand has 133 states, 123 states have (on average 1.1788617886178863) internal successors, (145), 124 states have internal predecessors, (145), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 189 states. [2022-04-07 22:03:08,443 INFO L87 Difference]: Start difference. First operand has 133 states, 123 states have (on average 1.1788617886178863) internal successors, (145), 124 states have internal predecessors, (145), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 189 states. [2022-04-07 22:03:08,446 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:08,446 INFO L93 Difference]: Finished difference Result 189 states and 223 transitions. [2022-04-07 22:03:08,446 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 223 transitions. [2022-04-07 22:03:08,446 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:03:08,446 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:03:08,446 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 22:03:08,446 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 22:03:08,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 133 states, 123 states have (on average 1.1788617886178863) internal successors, (145), 124 states have internal predecessors, (145), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:08,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 154 transitions. [2022-04-07 22:03:08,448 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 154 transitions. Word has length 44 [2022-04-07 22:03:08,448 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 22:03:08,448 INFO L478 AbstractCegarLoop]: Abstraction has 133 states and 154 transitions. [2022-04-07 22:03:08,448 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:03:08,448 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 154 transitions. [2022-04-07 22:03:08,449 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-04-07 22:03:08,449 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 22:03:08,449 INFO L499 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 22:03:08,473 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-04-07 22:03:08,665 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-04-07 22:03:08,665 INFO L403 AbstractCegarLoop]: === Iteration 15 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 22:03:08,665 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 22:03:08,665 INFO L85 PathProgramCache]: Analyzing trace with hash -1328658693, now seen corresponding path program 1 times [2022-04-07 22:03:08,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 22:03:08,666 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390413544] [2022-04-07 22:03:08,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:03:08,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 22:03:08,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:09,072 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 22:03:09,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:09,081 INFO L290 TraceCheckUtils]: 0: Hoare triple {8538#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8512#true} is VALID [2022-04-07 22:03:09,082 INFO L290 TraceCheckUtils]: 1: Hoare triple {8512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,082 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {8512#true} {8512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,082 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-04-07 22:03:09,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:09,085 INFO L290 TraceCheckUtils]: 0: Hoare triple {8512#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8512#true} is VALID [2022-04-07 22:03:09,085 INFO L290 TraceCheckUtils]: 1: Hoare triple {8512#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,085 INFO L290 TraceCheckUtils]: 2: Hoare triple {8512#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,086 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8512#true} {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:09,086 INFO L272 TraceCheckUtils]: 0: Hoare triple {8512#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8538#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 22:03:09,086 INFO L290 TraceCheckUtils]: 1: Hoare triple {8538#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8512#true} is VALID [2022-04-07 22:03:09,086 INFO L290 TraceCheckUtils]: 2: Hoare triple {8512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,087 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8512#true} {8512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,087 INFO L272 TraceCheckUtils]: 4: Hoare triple {8512#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,087 INFO L290 TraceCheckUtils]: 5: Hoare triple {8512#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {8517#(= main_~j~0 0)} is VALID [2022-04-07 22:03:09,087 INFO L290 TraceCheckUtils]: 6: Hoare triple {8517#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8517#(= main_~j~0 0)} is VALID [2022-04-07 22:03:09,088 INFO L290 TraceCheckUtils]: 7: Hoare triple {8517#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,088 INFO L290 TraceCheckUtils]: 8: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,089 INFO L290 TraceCheckUtils]: 9: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8519#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:09,089 INFO L290 TraceCheckUtils]: 10: Hoare triple {8519#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8519#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:09,089 INFO L290 TraceCheckUtils]: 11: Hoare triple {8519#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:09,090 INFO L290 TraceCheckUtils]: 12: Hoare triple {8512#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,090 INFO L290 TraceCheckUtils]: 13: Hoare triple {8512#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,090 INFO L290 TraceCheckUtils]: 14: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,091 INFO L290 TraceCheckUtils]: 15: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,091 INFO L290 TraceCheckUtils]: 16: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,092 INFO L290 TraceCheckUtils]: 17: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,092 INFO L290 TraceCheckUtils]: 18: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:09,092 INFO L290 TraceCheckUtils]: 19: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8520#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} is VALID [2022-04-07 22:03:09,093 INFO L290 TraceCheckUtils]: 20: Hoare triple {8520#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:09,094 INFO L290 TraceCheckUtils]: 21: Hoare triple {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:09,094 INFO L290 TraceCheckUtils]: 22: Hoare triple {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8522#(or (< main_~i~0 1) (and (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 4 (* main_~i~0 4))))} is VALID [2022-04-07 22:03:09,095 INFO L290 TraceCheckUtils]: 23: Hoare triple {8522#(or (< main_~i~0 1) (and (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 4 (* main_~i~0 4))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8523#(or (< main_~i~0 1) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4))))} is VALID [2022-04-07 22:03:09,096 INFO L290 TraceCheckUtils]: 24: Hoare triple {8523#(or (< main_~i~0 1) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {8524#(and (or (< main_~i~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))))) (<= main_~i~0 1))} is VALID [2022-04-07 22:03:09,097 INFO L290 TraceCheckUtils]: 25: Hoare triple {8524#(and (or (< main_~i~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))))) (<= main_~i~0 1))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {8525#(or (<= (+ main_~i~0 1) 0) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 22:03:09,097 INFO L290 TraceCheckUtils]: 26: Hoare triple {8525#(or (<= (+ main_~i~0 1) 0) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8526#(or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 22:03:09,098 INFO L290 TraceCheckUtils]: 27: Hoare triple {8526#(or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8527#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:09,098 INFO L290 TraceCheckUtils]: 28: Hoare triple {8527#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8527#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:09,099 INFO L290 TraceCheckUtils]: 29: Hoare triple {8527#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:09,100 INFO L290 TraceCheckUtils]: 30: Hoare triple {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:09,100 INFO L290 TraceCheckUtils]: 31: Hoare triple {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:09,100 INFO L290 TraceCheckUtils]: 32: Hoare triple {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:09,101 INFO L290 TraceCheckUtils]: 33: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:09,101 INFO L272 TraceCheckUtils]: 34: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8512#true} is VALID [2022-04-07 22:03:09,101 INFO L290 TraceCheckUtils]: 35: Hoare triple {8512#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8512#true} is VALID [2022-04-07 22:03:09,101 INFO L290 TraceCheckUtils]: 36: Hoare triple {8512#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,101 INFO L290 TraceCheckUtils]: 37: Hoare triple {8512#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:09,102 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {8512#true} {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:09,102 INFO L290 TraceCheckUtils]: 39: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:09,103 INFO L290 TraceCheckUtils]: 40: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {8534#(<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 22:03:09,103 INFO L290 TraceCheckUtils]: 41: Hoare triple {8534#(<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8535#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 22:03:09,104 INFO L272 TraceCheckUtils]: 42: Hoare triple {8535#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8536#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 22:03:09,104 INFO L290 TraceCheckUtils]: 43: Hoare triple {8536#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8537#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 22:03:09,105 INFO L290 TraceCheckUtils]: 44: Hoare triple {8537#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {8513#false} is VALID [2022-04-07 22:03:09,105 INFO L290 TraceCheckUtils]: 45: Hoare triple {8513#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8513#false} is VALID [2022-04-07 22:03:09,105 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 4 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 22:03:09,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 22:03:09,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [390413544] [2022-04-07 22:03:09,105 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [390413544] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 22:03:09,105 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [442163554] [2022-04-07 22:03:09,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:03:09,106 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:03:09,106 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 22:03:09,107 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 22:03:09,107 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-04-07 22:03:09,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:09,166 INFO L263 TraceCheckSpWp]: Trace formula consists of 170 conjuncts, 27 conjunts are in the unsatisfiable core [2022-04-07 22:03:09,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:09,181 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 22:03:09,480 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-07 22:03:09,480 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-07 22:03:10,222 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-07 22:03:10,222 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-07 22:03:20,605 INFO L356 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2022-04-07 22:03:20,606 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 12 [2022-04-07 22:03:20,692 INFO L272 TraceCheckUtils]: 0: Hoare triple {8512#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 1: Hoare triple {8512#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 2: Hoare triple {8512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8512#true} {8512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L272 TraceCheckUtils]: 4: Hoare triple {8512#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 5: Hoare triple {8512#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 6: Hoare triple {8512#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 7: Hoare triple {8512#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 8: Hoare triple {8512#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8512#true} is VALID [2022-04-07 22:03:20,692 INFO L290 TraceCheckUtils]: 9: Hoare triple {8512#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:20,693 INFO L290 TraceCheckUtils]: 10: Hoare triple {8512#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8512#true} is VALID [2022-04-07 22:03:20,693 INFO L290 TraceCheckUtils]: 11: Hoare triple {8512#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:20,693 INFO L290 TraceCheckUtils]: 12: Hoare triple {8512#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:20,693 INFO L290 TraceCheckUtils]: 13: Hoare triple {8512#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:20,693 INFO L290 TraceCheckUtils]: 14: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:20,694 INFO L290 TraceCheckUtils]: 15: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:20,694 INFO L290 TraceCheckUtils]: 16: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:20,694 INFO L290 TraceCheckUtils]: 17: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:20,695 INFO L290 TraceCheckUtils]: 18: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:20,695 INFO L290 TraceCheckUtils]: 19: Hoare triple {8518#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8519#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:03:20,696 INFO L290 TraceCheckUtils]: 20: Hoare triple {8519#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8602#(and (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-07 22:03:20,696 INFO L290 TraceCheckUtils]: 21: Hoare triple {8602#(and (<= main_~i~0 1) (<= 1 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8602#(and (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-07 22:03:20,697 INFO L290 TraceCheckUtils]: 22: Hoare triple {8602#(and (<= main_~i~0 1) (<= 1 main_~i~0))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8609#(and (<= main_~i~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 1 main_~i~0))} is VALID [2022-04-07 22:03:20,697 INFO L290 TraceCheckUtils]: 23: Hoare triple {8609#(and (<= main_~i~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 1 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8613#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-07 22:03:20,698 INFO L290 TraceCheckUtils]: 24: Hoare triple {8613#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {8617#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-07 22:03:20,699 INFO L290 TraceCheckUtils]: 25: Hoare triple {8617#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {8621#(exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1)))} is VALID [2022-04-07 22:03:20,702 INFO L290 TraceCheckUtils]: 26: Hoare triple {8621#(exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8625#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 22:03:20,705 INFO L290 TraceCheckUtils]: 27: Hoare triple {8625#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8629#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} is VALID [2022-04-07 22:03:20,707 INFO L290 TraceCheckUtils]: 28: Hoare triple {8629#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8629#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} is VALID [2022-04-07 22:03:20,709 INFO L290 TraceCheckUtils]: 29: Hoare triple {8629#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:20,709 INFO L290 TraceCheckUtils]: 30: Hoare triple {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:20,710 INFO L290 TraceCheckUtils]: 31: Hoare triple {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:20,710 INFO L290 TraceCheckUtils]: 32: Hoare triple {8528#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:20,711 INFO L290 TraceCheckUtils]: 33: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:20,712 INFO L272 TraceCheckUtils]: 34: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-07 22:03:20,712 INFO L290 TraceCheckUtils]: 35: Hoare triple {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-07 22:03:20,712 INFO L290 TraceCheckUtils]: 36: Hoare triple {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-07 22:03:20,713 INFO L290 TraceCheckUtils]: 37: Hoare triple {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-07 22:03:20,713 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {8651#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:20,714 INFO L290 TraceCheckUtils]: 39: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-07 22:03:20,714 INFO L290 TraceCheckUtils]: 40: Hoare triple {8529#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {8670#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 2) main_~k~0) 0))} is VALID [2022-04-07 22:03:20,715 INFO L290 TraceCheckUtils]: 41: Hoare triple {8670#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 2) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8535#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 22:03:20,715 INFO L272 TraceCheckUtils]: 42: Hoare triple {8535#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8677#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:03:20,716 INFO L290 TraceCheckUtils]: 43: Hoare triple {8677#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8681#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:03:20,716 INFO L290 TraceCheckUtils]: 44: Hoare triple {8681#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {8513#false} is VALID [2022-04-07 22:03:20,716 INFO L290 TraceCheckUtils]: 45: Hoare triple {8513#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8513#false} is VALID [2022-04-07 22:03:20,716 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 22:03:20,716 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 22:03:42,360 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 63 [2022-04-07 22:03:42,431 INFO L356 Elim1Store]: treesize reduction 31, result has 24.4 percent of original size [2022-04-07 22:03:42,432 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1679 treesize of output 1549 [2022-04-07 22:03:43,429 INFO L290 TraceCheckUtils]: 45: Hoare triple {8513#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8513#false} is VALID [2022-04-07 22:03:43,429 INFO L290 TraceCheckUtils]: 44: Hoare triple {8681#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {8513#false} is VALID [2022-04-07 22:03:43,430 INFO L290 TraceCheckUtils]: 43: Hoare triple {8677#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8681#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:03:43,430 INFO L272 TraceCheckUtils]: 42: Hoare triple {8697#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8677#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:03:43,431 INFO L290 TraceCheckUtils]: 41: Hoare triple {8701#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8697#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:03:43,432 INFO L290 TraceCheckUtils]: 40: Hoare triple {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {8701#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 22:03:43,432 INFO L290 TraceCheckUtils]: 39: Hoare triple {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:03:43,433 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {8512#true} {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:03:43,433 INFO L290 TraceCheckUtils]: 37: Hoare triple {8512#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,433 INFO L290 TraceCheckUtils]: 36: Hoare triple {8512#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,433 INFO L290 TraceCheckUtils]: 35: Hoare triple {8512#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8512#true} is VALID [2022-04-07 22:03:43,433 INFO L272 TraceCheckUtils]: 34: Hoare triple {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8512#true} is VALID [2022-04-07 22:03:43,433 INFO L290 TraceCheckUtils]: 33: Hoare triple {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:03:43,434 INFO L290 TraceCheckUtils]: 32: Hoare triple {8730#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {8705#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-07 22:03:43,434 INFO L290 TraceCheckUtils]: 31: Hoare triple {8730#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {8730#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:43,434 INFO L290 TraceCheckUtils]: 30: Hoare triple {8730#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8730#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:43,435 INFO L290 TraceCheckUtils]: 29: Hoare triple {8740#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8730#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-07 22:03:43,435 INFO L290 TraceCheckUtils]: 28: Hoare triple {8740#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8740#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} is VALID [2022-04-07 22:03:43,436 INFO L290 TraceCheckUtils]: 27: Hoare triple {8747#(or (not |main_#t~short10|) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8740#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} is VALID [2022-04-07 22:03:43,436 INFO L290 TraceCheckUtils]: 26: Hoare triple {8751#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8747#(or (not |main_#t~short10|) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} is VALID [2022-04-07 22:03:43,438 INFO L290 TraceCheckUtils]: 25: Hoare triple {8755#(forall ((v_main_~i~0_39 Int)) (or (not (<= 0 v_main_~i~0_39)) (forall ((v_ArrVal_286 Int)) (or (not (<= v_ArrVal_286 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))))) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {8751#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} is VALID [2022-04-07 22:03:43,439 INFO L290 TraceCheckUtils]: 24: Hoare triple {8759#(forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {8755#(forall ((v_main_~i~0_39 Int)) (or (not (<= 0 v_main_~i~0_39)) (forall ((v_ArrVal_286 Int)) (or (not (<= v_ArrVal_286 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))))) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} is VALID [2022-04-07 22:03:43,440 INFO L290 TraceCheckUtils]: 23: Hoare triple {8763#(or (forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0)))) (not |main_#t~short10|))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8759#(forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} is VALID [2022-04-07 22:03:43,441 INFO L290 TraceCheckUtils]: 22: Hoare triple {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8763#(or (forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0)))) (not |main_#t~short10|))} is VALID [2022-04-07 22:03:43,441 INFO L290 TraceCheckUtils]: 21: Hoare triple {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:43,442 INFO L290 TraceCheckUtils]: 20: Hoare triple {8520#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8521#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:43,443 INFO L290 TraceCheckUtils]: 19: Hoare triple {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8520#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} is VALID [2022-04-07 22:03:43,443 INFO L290 TraceCheckUtils]: 18: Hoare triple {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-07 22:03:43,443 INFO L290 TraceCheckUtils]: 17: Hoare triple {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-07 22:03:43,444 INFO L290 TraceCheckUtils]: 16: Hoare triple {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-07 22:03:43,448 INFO L290 TraceCheckUtils]: 15: Hoare triple {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-07 22:03:43,448 INFO L290 TraceCheckUtils]: 14: Hoare triple {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 13: Hoare triple {8512#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {8776#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 12: Hoare triple {8512#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 11: Hoare triple {8512#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 10: Hoare triple {8512#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 9: Hoare triple {8512#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 8: Hoare triple {8512#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 7: Hoare triple {8512#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 6: Hoare triple {8512#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L290 TraceCheckUtils]: 5: Hoare triple {8512#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {8512#true} is VALID [2022-04-07 22:03:43,449 INFO L272 TraceCheckUtils]: 4: Hoare triple {8512#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,450 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8512#true} {8512#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,450 INFO L290 TraceCheckUtils]: 2: Hoare triple {8512#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,450 INFO L290 TraceCheckUtils]: 1: Hoare triple {8512#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8512#true} is VALID [2022-04-07 22:03:43,450 INFO L272 TraceCheckUtils]: 0: Hoare triple {8512#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8512#true} is VALID [2022-04-07 22:03:43,450 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 16 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-07 22:03:43,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [442163554] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 22:03:43,450 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 22:03:43,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18, 17] total 42 [2022-04-07 22:03:43,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [876290721] [2022-04-07 22:03:43,450 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 22:03:43,451 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 46 [2022-04-07 22:03:43,452 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 22:03:43,452 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:43,550 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 97 edges. 97 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:03:43,550 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-04-07 22:03:43,550 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 22:03:43,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-04-07 22:03:43,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=1506, Unknown=17, NotChecked=0, Total=1722 [2022-04-07 22:03:43,551 INFO L87 Difference]: Start difference. First operand 133 states and 154 transitions. Second operand has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:55,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:55,154 INFO L93 Difference]: Finished difference Result 212 states and 247 transitions. [2022-04-07 22:03:55,154 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2022-04-07 22:03:55,154 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 46 [2022-04-07 22:03:55,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 22:03:55,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:55,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 147 transitions. [2022-04-07 22:03:55,156 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:55,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 147 transitions. [2022-04-07 22:03:55,157 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 44 states and 147 transitions. [2022-04-07 22:03:55,315 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 147 edges. 147 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-07 22:03:55,318 INFO L225 Difference]: With dead ends: 212 [2022-04-07 22:03:55,318 INFO L226 Difference]: Without dead ends: 210 [2022-04-07 22:03:55,320 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 161 GetRequests, 77 SyntacticMatches, 8 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1567 ImplicationChecksByTransitivity, 40.1s TimeCoverageRelationStatistics Valid=701, Invalid=5284, Unknown=21, NotChecked=0, Total=6006 [2022-04-07 22:03:55,320 INFO L913 BasicCegarLoop]: 43 mSDtfsCounter, 190 mSDsluCounter, 113 mSDsCounter, 0 mSdLazyCounter, 885 mSolverCounterSat, 115 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 191 SdHoareTripleChecker+Valid, 156 SdHoareTripleChecker+Invalid, 1483 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 115 IncrementalHoareTripleChecker+Valid, 885 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 483 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-04-07 22:03:55,320 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [191 Valid, 156 Invalid, 1483 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [115 Valid, 885 Invalid, 0 Unknown, 483 Unchecked, 1.0s Time] [2022-04-07 22:03:55,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2022-04-07 22:03:55,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 140. [2022-04-07 22:03:55,539 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 22:03:55,539 INFO L82 GeneralOperation]: Start isEquivalent. First operand 210 states. Second operand has 140 states, 130 states have (on average 1.1846153846153846) internal successors, (154), 131 states have internal predecessors, (154), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:55,540 INFO L74 IsIncluded]: Start isIncluded. First operand 210 states. Second operand has 140 states, 130 states have (on average 1.1846153846153846) internal successors, (154), 131 states have internal predecessors, (154), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:55,540 INFO L87 Difference]: Start difference. First operand 210 states. Second operand has 140 states, 130 states have (on average 1.1846153846153846) internal successors, (154), 131 states have internal predecessors, (154), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:55,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:55,543 INFO L93 Difference]: Finished difference Result 210 states and 245 transitions. [2022-04-07 22:03:55,543 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 245 transitions. [2022-04-07 22:03:55,543 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:03:55,543 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:03:55,543 INFO L74 IsIncluded]: Start isIncluded. First operand has 140 states, 130 states have (on average 1.1846153846153846) internal successors, (154), 131 states have internal predecessors, (154), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 210 states. [2022-04-07 22:03:55,544 INFO L87 Difference]: Start difference. First operand has 140 states, 130 states have (on average 1.1846153846153846) internal successors, (154), 131 states have internal predecessors, (154), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 210 states. [2022-04-07 22:03:55,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:03:55,547 INFO L93 Difference]: Finished difference Result 210 states and 245 transitions. [2022-04-07 22:03:55,547 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 245 transitions. [2022-04-07 22:03:55,548 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:03:55,548 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:03:55,548 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 22:03:55,548 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 22:03:55,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 130 states have (on average 1.1846153846153846) internal successors, (154), 131 states have internal predecessors, (154), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:03:55,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 163 transitions. [2022-04-07 22:03:55,550 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 163 transitions. Word has length 46 [2022-04-07 22:03:55,550 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 22:03:55,550 INFO L478 AbstractCegarLoop]: Abstraction has 140 states and 163 transitions. [2022-04-07 22:03:55,550 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-07 22:03:55,551 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 163 transitions. [2022-04-07 22:03:55,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-04-07 22:03:55,555 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 22:03:55,555 INFO L499 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 22:03:55,577 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2022-04-07 22:03:55,777 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2022-04-07 22:03:55,777 INFO L403 AbstractCegarLoop]: === Iteration 16 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 22:03:55,778 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 22:03:55,778 INFO L85 PathProgramCache]: Analyzing trace with hash -2059580614, now seen corresponding path program 2 times [2022-04-07 22:03:55,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 22:03:55,778 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [984413643] [2022-04-07 22:03:55,778 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:03:55,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 22:03:55,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:56,467 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 22:03:56,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:56,479 INFO L290 TraceCheckUtils]: 0: Hoare triple {9833#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {9809#true} is VALID [2022-04-07 22:03:56,479 INFO L290 TraceCheckUtils]: 1: Hoare triple {9809#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:56,479 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {9809#true} {9809#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:56,480 INFO L272 TraceCheckUtils]: 0: Hoare triple {9809#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9833#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 22:03:56,480 INFO L290 TraceCheckUtils]: 1: Hoare triple {9833#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {9809#true} is VALID [2022-04-07 22:03:56,480 INFO L290 TraceCheckUtils]: 2: Hoare triple {9809#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:56,480 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {9809#true} {9809#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:56,480 INFO L272 TraceCheckUtils]: 4: Hoare triple {9809#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:56,480 INFO L290 TraceCheckUtils]: 5: Hoare triple {9809#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {9814#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 22:03:56,481 INFO L290 TraceCheckUtils]: 6: Hoare triple {9814#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9814#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 22:03:56,481 INFO L290 TraceCheckUtils]: 7: Hoare triple {9814#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:56,482 INFO L290 TraceCheckUtils]: 8: Hoare triple {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:56,482 INFO L290 TraceCheckUtils]: 9: Hoare triple {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9816#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} is VALID [2022-04-07 22:03:56,483 INFO L290 TraceCheckUtils]: 10: Hoare triple {9816#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9816#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} is VALID [2022-04-07 22:03:56,483 INFO L290 TraceCheckUtils]: 11: Hoare triple {9816#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9817#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| (* main_~j~0 4)) 0)))} is VALID [2022-04-07 22:03:56,483 INFO L290 TraceCheckUtils]: 12: Hoare triple {9817#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| (* main_~j~0 4)) 0)))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:56,484 INFO L290 TraceCheckUtils]: 13: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:56,484 INFO L290 TraceCheckUtils]: 14: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:56,484 INFO L290 TraceCheckUtils]: 15: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:56,485 INFO L290 TraceCheckUtils]: 16: Hoare triple {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9819#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:03:56,486 INFO L290 TraceCheckUtils]: 17: Hoare triple {9819#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9820#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-07 22:03:56,486 INFO L290 TraceCheckUtils]: 18: Hoare triple {9820#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9821#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 22:03:56,487 INFO L290 TraceCheckUtils]: 19: Hoare triple {9821#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9822#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:03:56,488 INFO L290 TraceCheckUtils]: 20: Hoare triple {9822#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9823#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,488 INFO L290 TraceCheckUtils]: 21: Hoare triple {9823#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9824#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-07 22:03:56,489 INFO L290 TraceCheckUtils]: 22: Hoare triple {9824#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:56,489 INFO L290 TraceCheckUtils]: 23: Hoare triple {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:56,490 INFO L290 TraceCheckUtils]: 24: Hoare triple {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:56,490 INFO L290 TraceCheckUtils]: 25: Hoare triple {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:03:56,491 INFO L290 TraceCheckUtils]: 26: Hoare triple {9825#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,491 INFO L290 TraceCheckUtils]: 27: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,492 INFO L290 TraceCheckUtils]: 28: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,492 INFO L290 TraceCheckUtils]: 29: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,493 INFO L290 TraceCheckUtils]: 30: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,493 INFO L290 TraceCheckUtils]: 31: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,493 INFO L290 TraceCheckUtils]: 32: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {9827#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,494 INFO L290 TraceCheckUtils]: 33: Hoare triple {9827#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,494 INFO L290 TraceCheckUtils]: 34: Hoare triple {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,495 INFO L290 TraceCheckUtils]: 35: Hoare triple {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,495 INFO L290 TraceCheckUtils]: 36: Hoare triple {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,496 INFO L290 TraceCheckUtils]: 37: Hoare triple {9828#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,497 INFO L290 TraceCheckUtils]: 38: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,497 INFO L290 TraceCheckUtils]: 39: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:56,498 INFO L290 TraceCheckUtils]: 40: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {9829#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 22:03:56,498 INFO L290 TraceCheckUtils]: 41: Hoare triple {9829#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {9830#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:03:56,499 INFO L272 TraceCheckUtils]: 42: Hoare triple {9830#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {9831#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 22:03:56,499 INFO L290 TraceCheckUtils]: 43: Hoare triple {9831#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {9832#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 22:03:56,499 INFO L290 TraceCheckUtils]: 44: Hoare triple {9832#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {9810#false} is VALID [2022-04-07 22:03:56,499 INFO L290 TraceCheckUtils]: 45: Hoare triple {9810#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9810#false} is VALID [2022-04-07 22:03:56,500 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 3 proven. 41 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-07 22:03:56,500 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 22:03:56,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [984413643] [2022-04-07 22:03:56,500 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [984413643] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 22:03:56,500 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1834650284] [2022-04-07 22:03:56,500 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-07 22:03:56,500 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:03:56,500 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 22:03:56,501 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 22:03:56,502 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-04-07 22:03:56,562 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-07 22:03:56,562 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 22:03:56,563 INFO L263 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 27 conjunts are in the unsatisfiable core [2022-04-07 22:03:56,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:03:56,576 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 22:03:56,899 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:56,900 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-07 22:03:57,082 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:57,083 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:57,084 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:57,086 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 22:03:57,086 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 32 [2022-04-07 22:03:57,264 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:57,265 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:57,267 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-07 22:03:57,268 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 22:03:57,269 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 32 [2022-04-07 22:03:57,342 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-07 22:03:57,343 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-07 22:03:57,416 INFO L272 TraceCheckUtils]: 0: Hoare triple {9809#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:57,416 INFO L290 TraceCheckUtils]: 1: Hoare triple {9809#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {9809#true} is VALID [2022-04-07 22:03:57,416 INFO L290 TraceCheckUtils]: 2: Hoare triple {9809#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:57,416 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {9809#true} {9809#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:57,416 INFO L272 TraceCheckUtils]: 4: Hoare triple {9809#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:03:57,416 INFO L290 TraceCheckUtils]: 5: Hoare triple {9809#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,417 INFO L290 TraceCheckUtils]: 6: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,417 INFO L290 TraceCheckUtils]: 7: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,417 INFO L290 TraceCheckUtils]: 8: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,417 INFO L290 TraceCheckUtils]: 9: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,418 INFO L290 TraceCheckUtils]: 10: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,427 INFO L290 TraceCheckUtils]: 11: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,428 INFO L290 TraceCheckUtils]: 12: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,428 INFO L290 TraceCheckUtils]: 13: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,428 INFO L290 TraceCheckUtils]: 14: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {9818#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:03:57,428 INFO L290 TraceCheckUtils]: 15: Hoare triple {9818#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:57,429 INFO L290 TraceCheckUtils]: 16: Hoare triple {9815#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9885#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:57,429 INFO L290 TraceCheckUtils]: 17: Hoare triple {9885#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9885#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:03:57,430 INFO L290 TraceCheckUtils]: 18: Hoare triple {9885#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9821#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-07 22:03:57,431 INFO L290 TraceCheckUtils]: 19: Hoare triple {9821#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9822#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-07 22:03:57,432 INFO L290 TraceCheckUtils]: 20: Hoare triple {9822#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9823#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,432 INFO L290 TraceCheckUtils]: 21: Hoare triple {9823#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9901#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,433 INFO L290 TraceCheckUtils]: 22: Hoare triple {9901#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,433 INFO L290 TraceCheckUtils]: 23: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,434 INFO L290 TraceCheckUtils]: 24: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,434 INFO L290 TraceCheckUtils]: 25: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,435 INFO L290 TraceCheckUtils]: 26: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,435 INFO L290 TraceCheckUtils]: 27: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,436 INFO L290 TraceCheckUtils]: 28: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,436 INFO L290 TraceCheckUtils]: 29: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,436 INFO L290 TraceCheckUtils]: 30: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,437 INFO L290 TraceCheckUtils]: 31: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,437 INFO L290 TraceCheckUtils]: 32: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {9827#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,438 INFO L290 TraceCheckUtils]: 33: Hoare triple {9827#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,438 INFO L290 TraceCheckUtils]: 34: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,439 INFO L290 TraceCheckUtils]: 35: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,439 INFO L290 TraceCheckUtils]: 36: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,440 INFO L290 TraceCheckUtils]: 37: Hoare triple {9905#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,440 INFO L290 TraceCheckUtils]: 38: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,440 INFO L290 TraceCheckUtils]: 39: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:03:57,441 INFO L290 TraceCheckUtils]: 40: Hoare triple {9826#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {9829#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 22:03:57,441 INFO L290 TraceCheckUtils]: 41: Hoare triple {9829#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {9830#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:03:57,442 INFO L272 TraceCheckUtils]: 42: Hoare triple {9830#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {9966#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:03:57,442 INFO L290 TraceCheckUtils]: 43: Hoare triple {9966#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {9970#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:03:57,442 INFO L290 TraceCheckUtils]: 44: Hoare triple {9970#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {9810#false} is VALID [2022-04-07 22:03:57,442 INFO L290 TraceCheckUtils]: 45: Hoare triple {9810#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9810#false} is VALID [2022-04-07 22:03:57,443 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 3 proven. 21 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-04-07 22:03:57,443 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 22:04:05,818 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324))) (<= (select .cse0 |c_main_~#v~0.offset|) (select .cse0 (+ |c_main_~#v~0.offset| 4))))) (not (<= c_main_~i~0 (+ v_main_~i~0_43 1))))) is different from false [2022-04-07 22:04:36,406 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 51 [2022-04-07 22:04:36,487 INFO L356 Elim1Store]: treesize reduction 16, result has 56.8 percent of original size [2022-04-07 22:04:36,488 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1429 treesize of output 1347 [2022-04-07 22:04:47,192 INFO L290 TraceCheckUtils]: 45: Hoare triple {9810#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9810#false} is VALID [2022-04-07 22:04:47,192 INFO L290 TraceCheckUtils]: 44: Hoare triple {9970#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {9810#false} is VALID [2022-04-07 22:04:47,193 INFO L290 TraceCheckUtils]: 43: Hoare triple {9966#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {9970#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:04:47,193 INFO L272 TraceCheckUtils]: 42: Hoare triple {9830#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {9966#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:04:47,194 INFO L290 TraceCheckUtils]: 41: Hoare triple {9989#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {9830#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-07 22:04:47,194 INFO L290 TraceCheckUtils]: 40: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {9989#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-07 22:04:47,194 INFO L290 TraceCheckUtils]: 39: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,195 INFO L290 TraceCheckUtils]: 38: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,196 INFO L290 TraceCheckUtils]: 37: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,196 INFO L290 TraceCheckUtils]: 36: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,197 INFO L290 TraceCheckUtils]: 35: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,197 INFO L290 TraceCheckUtils]: 34: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,198 INFO L290 TraceCheckUtils]: 33: Hoare triple {10016#(forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))) (not (<= main_~i~0 (+ v_main_~i~0_43 1)))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,199 INFO L290 TraceCheckUtils]: 32: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {10016#(forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))) (not (<= main_~i~0 (+ v_main_~i~0_43 1)))))} is VALID [2022-04-07 22:04:47,200 INFO L290 TraceCheckUtils]: 31: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,200 INFO L290 TraceCheckUtils]: 30: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,200 INFO L290 TraceCheckUtils]: 29: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,201 INFO L290 TraceCheckUtils]: 28: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,201 INFO L290 TraceCheckUtils]: 27: Hoare triple {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,202 INFO L290 TraceCheckUtils]: 26: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9993#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-07 22:04:47,202 INFO L290 TraceCheckUtils]: 25: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,203 INFO L290 TraceCheckUtils]: 24: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,203 INFO L290 TraceCheckUtils]: 23: Hoare triple {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,205 INFO L290 TraceCheckUtils]: 22: Hoare triple {10050#(forall ((v_main_~i~0_45 Int)) (or (not (<= main_~j~0 (+ v_main_~i~0_45 1))) (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10003#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:04:47,998 WARN L290 TraceCheckUtils]: 21: Hoare triple {10054#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))) (< v_main_~i~0_45 main_~j~0)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10050#(forall ((v_main_~i~0_45 Int)) (or (not (<= main_~j~0 (+ v_main_~i~0_45 1))) (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} is UNKNOWN [2022-04-07 22:04:49,054 WARN L290 TraceCheckUtils]: 20: Hoare triple {10058#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10054#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))) (< v_main_~i~0_45 main_~j~0)))} is UNKNOWN [2022-04-07 22:04:49,055 INFO L290 TraceCheckUtils]: 19: Hoare triple {10062#(or |main_#t~short10| (forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10058#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-07 22:04:49,056 INFO L290 TraceCheckUtils]: 18: Hoare triple {10066#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10062#(or |main_#t~short10| (forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-07 22:04:49,057 INFO L290 TraceCheckUtils]: 17: Hoare triple {10066#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10066#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:04:49,057 INFO L290 TraceCheckUtils]: 16: Hoare triple {10073#(= (* main_~j~0 4) 4)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10066#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:04:49,057 INFO L290 TraceCheckUtils]: 15: Hoare triple {9809#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {10073#(= (* main_~j~0 4) 4)} is VALID [2022-04-07 22:04:49,057 INFO L290 TraceCheckUtils]: 14: Hoare triple {9809#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 13: Hoare triple {9809#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 12: Hoare triple {9809#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 11: Hoare triple {9809#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 10: Hoare triple {9809#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 9: Hoare triple {9809#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 8: Hoare triple {9809#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 7: Hoare triple {9809#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 6: Hoare triple {9809#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 5: Hoare triple {9809#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L272 TraceCheckUtils]: 4: Hoare triple {9809#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {9809#true} {9809#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 2: Hoare triple {9809#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L290 TraceCheckUtils]: 1: Hoare triple {9809#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {9809#true} is VALID [2022-04-07 22:04:49,058 INFO L272 TraceCheckUtils]: 0: Hoare triple {9809#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {9809#true} is VALID [2022-04-07 22:04:49,059 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 3 proven. 21 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-04-07 22:04:49,059 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1834650284] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-07 22:04:49,059 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-07 22:04:49,059 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 16, 15] total 37 [2022-04-07 22:04:49,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1662578001] [2022-04-07 22:04:49,059 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-07 22:04:49,060 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 46 [2022-04-07 22:04:49,060 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-07 22:04:49,060 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:04:52,821 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 88 edges. 85 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-07 22:04:52,821 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-04-07 22:04:52,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-07 22:04:52,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-04-07 22:04:52,822 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=168, Invalid=1075, Unknown=21, NotChecked=68, Total=1332 [2022-04-07 22:04:52,822 INFO L87 Difference]: Start difference. First operand 140 states and 163 transitions. Second operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:05:01,122 WARN L232 SmtUtils]: Spent 6.50s on a formula simplification. DAG size of input: 55 DAG size of output: 28 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 22:05:09,657 WARN L232 SmtUtils]: Spent 8.35s on a formula simplification. DAG size of input: 58 DAG size of output: 31 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 22:05:10,719 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (<= 2 c_main_~j~0) (<= 1 c_main_~i~0) (let ((.cse0 (select |c_#memory_int| |c_main_~#v~0.base|))) (<= (select .cse0 0) (select .cse0 (+ |c_main_~#v~0.offset| 4)))) (forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (let ((.cse1 (store (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ (* c_main_~i~0 4) |c_main_~#v~0.offset| 4) v_ArrVal_319) (+ |c_main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324))) (<= (select .cse1 |c_main_~#v~0.offset|) (select .cse1 (+ |c_main_~#v~0.offset| 4)))) (< v_main_~i~0_45 c_main_~j~0) (not (<= c_main_~key~0 v_ArrVal_319)))) (= |c_main_~#v~0.offset| 0) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-07 22:05:16,885 WARN L833 $PredicateComparison]: unable to prove that (and (let ((.cse0 (select |c_#memory_int| |c_main_~#v~0.base|)) (.cse1 (* 4 c_main_~k~0))) (<= (select .cse0 (+ |c_main_~#v~0.offset| (- 4) .cse1)) (select .cse0 (+ |c_main_~#v~0.offset| .cse1)))) (forall ((v_main_~i~0_45 Int)) (or (not (<= c_main_~j~0 (+ v_main_~i~0_45 1))) (forall ((v_ArrVal_324 Int)) (let ((.cse2 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324))) (<= (select .cse2 |c_main_~#v~0.offset|) (select .cse2 (+ |c_main_~#v~0.offset| 4)))))))) is different from false [2022-04-07 22:05:18,987 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (<= (+ 2 (div (* (- 1) |c_main_~#v~0.offset|) 4)) c_main_~i~0) (let ((.cse0 (select |c_#memory_int| |c_main_~#v~0.base|))) (<= (select .cse0 0) (select .cse0 (+ |c_main_~#v~0.offset| 4)))) (forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (let ((.cse1 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324))) (<= (select .cse1 |c_main_~#v~0.offset|) (select .cse1 (+ |c_main_~#v~0.offset| 4))))) (not (<= c_main_~i~0 (+ v_main_~i~0_43 1))))) (= |c_main_~#v~0.offset| 0) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-07 22:05:43,687 WARN L232 SmtUtils]: Spent 6.04s on a formula simplification that was a NOOP. DAG size: 31 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-07 22:05:48,681 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (let ((.cse0 (select |c_#memory_int| |c_main_~#v~0.base|))) (<= (select .cse0 |c_main_~#v~0.offset|) (select .cse0 (+ |c_main_~#v~0.offset| 4)))) (forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (let ((.cse1 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324))) (<= (select .cse1 |c_main_~#v~0.offset|) (select .cse1 (+ |c_main_~#v~0.offset| 4))))) (not (<= c_main_~i~0 (+ v_main_~i~0_43 1))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-07 22:05:49,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:05:49,096 INFO L93 Difference]: Finished difference Result 331 states and 398 transitions. [2022-04-07 22:05:49,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-07 22:05:49,096 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 46 [2022-04-07 22:05:49,096 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-07 22:05:49,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:05:49,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 196 transitions. [2022-04-07 22:05:49,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:05:49,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 196 transitions. [2022-04-07 22:05:49,103 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 196 transitions. [2022-04-07 22:05:52,289 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 196 edges. 194 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-07 22:05:52,294 INFO L225 Difference]: With dead ends: 331 [2022-04-07 22:05:52,295 INFO L226 Difference]: Without dead ends: 329 [2022-04-07 22:05:52,296 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 80 SyntacticMatches, 14 SemanticMatches, 72 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 1590 ImplicationChecksByTransitivity, 88.3s TimeCoverageRelationStatistics Valid=658, Invalid=4019, Unknown=35, NotChecked=690, Total=5402 [2022-04-07 22:05:52,296 INFO L913 BasicCegarLoop]: 15 mSDtfsCounter, 233 mSDsluCounter, 102 mSDsCounter, 0 mSdLazyCounter, 964 mSolverCounterSat, 133 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 235 SdHoareTripleChecker+Valid, 117 SdHoareTripleChecker+Invalid, 1617 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 133 IncrementalHoareTripleChecker+Valid, 964 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 520 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2022-04-07 22:05:52,297 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [235 Valid, 117 Invalid, 1617 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [133 Valid, 964 Invalid, 0 Unknown, 520 Unchecked, 1.3s Time] [2022-04-07 22:05:52,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states. [2022-04-07 22:05:52,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 172. [2022-04-07 22:05:52,556 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-07 22:05:52,556 INFO L82 GeneralOperation]: Start isEquivalent. First operand 329 states. Second operand has 172 states, 162 states have (on average 1.2160493827160495) internal successors, (197), 163 states have internal predecessors, (197), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:05:52,557 INFO L74 IsIncluded]: Start isIncluded. First operand 329 states. Second operand has 172 states, 162 states have (on average 1.2160493827160495) internal successors, (197), 163 states have internal predecessors, (197), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:05:52,557 INFO L87 Difference]: Start difference. First operand 329 states. Second operand has 172 states, 162 states have (on average 1.2160493827160495) internal successors, (197), 163 states have internal predecessors, (197), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:05:52,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:05:52,564 INFO L93 Difference]: Finished difference Result 329 states and 396 transitions. [2022-04-07 22:05:52,564 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 396 transitions. [2022-04-07 22:05:52,566 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:05:52,566 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:05:52,566 INFO L74 IsIncluded]: Start isIncluded. First operand has 172 states, 162 states have (on average 1.2160493827160495) internal successors, (197), 163 states have internal predecessors, (197), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 329 states. [2022-04-07 22:05:52,566 INFO L87 Difference]: Start difference. First operand has 172 states, 162 states have (on average 1.2160493827160495) internal successors, (197), 163 states have internal predecessors, (197), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) Second operand 329 states. [2022-04-07 22:05:52,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-07 22:05:52,572 INFO L93 Difference]: Finished difference Result 329 states and 396 transitions. [2022-04-07 22:05:52,572 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 396 transitions. [2022-04-07 22:05:52,573 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-07 22:05:52,573 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-07 22:05:52,573 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-07 22:05:52,573 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-07 22:05:52,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 172 states, 162 states have (on average 1.2160493827160495) internal successors, (197), 163 states have internal predecessors, (197), 5 states have call successors, (5), 5 states have call predecessors, (5), 4 states have return successors, (4), 3 states have call predecessors, (4), 4 states have call successors, (4) [2022-04-07 22:05:52,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 206 transitions. [2022-04-07 22:05:52,576 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 206 transitions. Word has length 46 [2022-04-07 22:05:52,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-07 22:05:52,576 INFO L478 AbstractCegarLoop]: Abstraction has 172 states and 206 transitions. [2022-04-07 22:05:52,577 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-07 22:05:52,577 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 206 transitions. [2022-04-07 22:05:52,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-04-07 22:05:52,578 INFO L491 BasicCegarLoop]: Found error trace [2022-04-07 22:05:52,578 INFO L499 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-07 22:05:52,607 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-04-07 22:05:52,792 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-04-07 22:05:52,793 INFO L403 AbstractCegarLoop]: === Iteration 17 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-07 22:05:52,793 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-07 22:05:52,793 INFO L85 PathProgramCache]: Analyzing trace with hash -1570483864, now seen corresponding path program 3 times [2022-04-07 22:05:52,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-07 22:05:52,793 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815532485] [2022-04-07 22:05:52,793 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-07 22:05:52,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-07 22:05:52,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:05:53,696 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-07 22:05:53,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:05:53,719 INFO L290 TraceCheckUtils]: 0: Hoare triple {11555#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {11527#true} is VALID [2022-04-07 22:05:53,720 INFO L290 TraceCheckUtils]: 1: Hoare triple {11527#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:53,720 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {11527#true} {11527#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:53,720 INFO L272 TraceCheckUtils]: 0: Hoare triple {11527#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11555#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-07 22:05:53,720 INFO L290 TraceCheckUtils]: 1: Hoare triple {11555#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {11527#true} is VALID [2022-04-07 22:05:53,721 INFO L290 TraceCheckUtils]: 2: Hoare triple {11527#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:53,721 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {11527#true} {11527#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:53,721 INFO L272 TraceCheckUtils]: 4: Hoare triple {11527#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:53,735 INFO L290 TraceCheckUtils]: 5: Hoare triple {11527#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {11532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 22:05:53,736 INFO L290 TraceCheckUtils]: 6: Hoare triple {11532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-07 22:05:53,736 INFO L290 TraceCheckUtils]: 7: Hoare triple {11532#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11533#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:05:53,737 INFO L290 TraceCheckUtils]: 8: Hoare triple {11533#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11533#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:05:53,737 INFO L290 TraceCheckUtils]: 9: Hoare triple {11533#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11534#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:05:53,738 INFO L290 TraceCheckUtils]: 10: Hoare triple {11534#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11534#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-07 22:05:53,738 INFO L290 TraceCheckUtils]: 11: Hoare triple {11534#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11535#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-07 22:05:53,739 INFO L290 TraceCheckUtils]: 12: Hoare triple {11535#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11535#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-07 22:05:53,739 INFO L290 TraceCheckUtils]: 13: Hoare triple {11535#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11536#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:05:53,739 INFO L290 TraceCheckUtils]: 14: Hoare triple {11536#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {11536#(= |main_~#v~0.offset| 0)} is VALID [2022-04-07 22:05:53,740 INFO L290 TraceCheckUtils]: 15: Hoare triple {11536#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {11533#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-07 22:05:53,741 INFO L290 TraceCheckUtils]: 16: Hoare triple {11533#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11537#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 22:05:53,741 INFO L290 TraceCheckUtils]: 17: Hoare triple {11537#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11538#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} is VALID [2022-04-07 22:05:53,742 INFO L290 TraceCheckUtils]: 18: Hoare triple {11538#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11539#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (<= 0 main_~i~0))} is VALID [2022-04-07 22:05:53,742 INFO L290 TraceCheckUtils]: 19: Hoare triple {11539#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (<= 0 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11540#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:05:53,743 INFO L290 TraceCheckUtils]: 20: Hoare triple {11540#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {11541#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-07 22:05:53,744 INFO L290 TraceCheckUtils]: 21: Hoare triple {11541#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {11542#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} is VALID [2022-04-07 22:05:53,744 INFO L290 TraceCheckUtils]: 22: Hoare triple {11542#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11543#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} is VALID [2022-04-07 22:05:53,745 INFO L290 TraceCheckUtils]: 23: Hoare triple {11543#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {11544#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,745 INFO L290 TraceCheckUtils]: 24: Hoare triple {11544#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11544#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,746 INFO L290 TraceCheckUtils]: 25: Hoare triple {11544#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11545#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,747 INFO L290 TraceCheckUtils]: 26: Hoare triple {11545#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11546#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-07 22:05:53,747 INFO L290 TraceCheckUtils]: 27: Hoare triple {11546#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:05:53,748 INFO L290 TraceCheckUtils]: 28: Hoare triple {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:05:53,748 INFO L290 TraceCheckUtils]: 29: Hoare triple {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:05:53,749 INFO L290 TraceCheckUtils]: 30: Hoare triple {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-07 22:05:53,750 INFO L290 TraceCheckUtils]: 31: Hoare triple {11547#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11546#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-07 22:05:53,750 INFO L290 TraceCheckUtils]: 32: Hoare triple {11546#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11548#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= main_~j~0 3))} is VALID [2022-04-07 22:05:53,751 INFO L290 TraceCheckUtils]: 33: Hoare triple {11548#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= main_~j~0 3))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,752 INFO L290 TraceCheckUtils]: 34: Hoare triple {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,752 INFO L290 TraceCheckUtils]: 35: Hoare triple {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,753 INFO L290 TraceCheckUtils]: 36: Hoare triple {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,754 INFO L290 TraceCheckUtils]: 37: Hoare triple {11549#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11550#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,754 INFO L290 TraceCheckUtils]: 38: Hoare triple {11550#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11550#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,755 INFO L290 TraceCheckUtils]: 39: Hoare triple {11550#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {11550#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-07 22:05:53,756 INFO L290 TraceCheckUtils]: 40: Hoare triple {11550#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {11551#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-07 22:05:53,756 INFO L290 TraceCheckUtils]: 41: Hoare triple {11551#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {11552#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 22:05:53,757 INFO L272 TraceCheckUtils]: 42: Hoare triple {11552#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {11553#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-07 22:05:53,757 INFO L290 TraceCheckUtils]: 43: Hoare triple {11553#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {11554#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-07 22:05:53,758 INFO L290 TraceCheckUtils]: 44: Hoare triple {11554#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {11528#false} is VALID [2022-04-07 22:05:53,758 INFO L290 TraceCheckUtils]: 45: Hoare triple {11528#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11528#false} is VALID [2022-04-07 22:05:53,758 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-07 22:05:53,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-07 22:05:53,758 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815532485] [2022-04-07 22:05:53,759 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815532485] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-07 22:05:53,759 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [372726883] [2022-04-07 22:05:53,759 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-07 22:05:53,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-07 22:05:53,759 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-07 22:05:53,761 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-07 22:05:53,762 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-04-07 22:05:53,876 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-04-07 22:05:53,876 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-07 22:05:53,877 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 33 conjunts are in the unsatisfiable core [2022-04-07 22:05:53,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-07 22:05:53,894 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-07 22:05:54,139 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-07 22:05:54,139 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-07 22:05:54,493 INFO L356 Elim1Store]: treesize reduction 109, result has 9.2 percent of original size [2022-04-07 22:05:54,493 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 30 [2022-04-07 22:05:55,113 INFO L356 Elim1Store]: treesize reduction 96, result has 20.7 percent of original size [2022-04-07 22:05:55,113 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 37 treesize of output 39 [2022-04-07 22:05:55,658 INFO L356 Elim1Store]: treesize reduction 88, result has 20.0 percent of original size [2022-04-07 22:05:55,658 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 37 [2022-04-07 22:05:56,064 INFO L356 Elim1Store]: treesize reduction 36, result has 7.7 percent of original size [2022-04-07 22:05:56,065 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2022-04-07 22:05:56,190 INFO L272 TraceCheckUtils]: 0: Hoare triple {11527#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 1: Hoare triple {11527#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 2: Hoare triple {11527#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {11527#true} {11527#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L272 TraceCheckUtils]: 4: Hoare triple {11527#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 5: Hoare triple {11527#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 6: Hoare triple {11527#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 7: Hoare triple {11527#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 8: Hoare triple {11527#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 9: Hoare triple {11527#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 10: Hoare triple {11527#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 11: Hoare triple {11527#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11527#true} is VALID [2022-04-07 22:05:56,191 INFO L290 TraceCheckUtils]: 12: Hoare triple {11527#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11527#true} is VALID [2022-04-07 22:05:56,192 INFO L290 TraceCheckUtils]: 13: Hoare triple {11527#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11527#true} is VALID [2022-04-07 22:05:56,192 INFO L290 TraceCheckUtils]: 14: Hoare triple {11527#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {11527#true} is VALID [2022-04-07 22:05:56,192 INFO L290 TraceCheckUtils]: 15: Hoare triple {11527#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {11604#(= main_~j~0 1)} is VALID [2022-04-07 22:05:56,192 INFO L290 TraceCheckUtils]: 16: Hoare triple {11604#(= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11608#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-07 22:05:56,193 INFO L290 TraceCheckUtils]: 17: Hoare triple {11608#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11608#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-07 22:05:56,193 INFO L290 TraceCheckUtils]: 18: Hoare triple {11608#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11615#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} is VALID [2022-04-07 22:05:56,194 INFO L290 TraceCheckUtils]: 19: Hoare triple {11615#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11619#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-07 22:05:56,194 INFO L290 TraceCheckUtils]: 20: Hoare triple {11619#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {11623#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-07 22:05:56,195 INFO L290 TraceCheckUtils]: 21: Hoare triple {11623#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {11627#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-07 22:05:56,196 INFO L290 TraceCheckUtils]: 22: Hoare triple {11627#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11631#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 22:05:56,196 INFO L290 TraceCheckUtils]: 23: Hoare triple {11631#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {11631#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-07 22:05:56,197 INFO L290 TraceCheckUtils]: 24: Hoare triple {11631#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11638#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-07 22:05:56,198 INFO L290 TraceCheckUtils]: 25: Hoare triple {11638#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 2)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11642#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} is VALID [2022-04-07 22:05:56,200 INFO L290 TraceCheckUtils]: 26: Hoare triple {11642#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11646#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-07 22:05:56,202 INFO L290 TraceCheckUtils]: 27: Hoare triple {11646#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-07 22:05:56,203 INFO L290 TraceCheckUtils]: 28: Hoare triple {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-07 22:05:56,205 INFO L290 TraceCheckUtils]: 29: Hoare triple {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-07 22:05:56,206 INFO L290 TraceCheckUtils]: 30: Hoare triple {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-07 22:05:56,209 INFO L290 TraceCheckUtils]: 31: Hoare triple {11650#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11646#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-07 22:05:56,209 INFO L290 TraceCheckUtils]: 32: Hoare triple {11646#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11666#(and (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))) (<= 3 main_~j~0))} is VALID [2022-04-07 22:05:56,212 INFO L290 TraceCheckUtils]: 33: Hoare triple {11666#(and (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))) (<= 3 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-07 22:05:56,213 INFO L290 TraceCheckUtils]: 34: Hoare triple {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-07 22:05:56,215 INFO L290 TraceCheckUtils]: 35: Hoare triple {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-07 22:05:56,217 INFO L290 TraceCheckUtils]: 36: Hoare triple {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-07 22:05:56,219 INFO L290 TraceCheckUtils]: 37: Hoare triple {11670#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11683#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} is VALID [2022-04-07 22:05:56,220 INFO L290 TraceCheckUtils]: 38: Hoare triple {11683#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11683#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} is VALID [2022-04-07 22:05:56,222 INFO L290 TraceCheckUtils]: 39: Hoare triple {11683#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {11683#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} is VALID [2022-04-07 22:05:56,223 INFO L290 TraceCheckUtils]: 40: Hoare triple {11683#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {11693#(and (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))) (= main_~k~0 1))} is VALID [2022-04-07 22:05:56,224 INFO L290 TraceCheckUtils]: 41: Hoare triple {11693#(and (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {11552#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-07 22:05:56,225 INFO L272 TraceCheckUtils]: 42: Hoare triple {11552#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {11700#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-07 22:05:56,225 INFO L290 TraceCheckUtils]: 43: Hoare triple {11700#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {11704#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-07 22:05:56,226 INFO L290 TraceCheckUtils]: 44: Hoare triple {11704#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {11528#false} is VALID [2022-04-07 22:05:56,226 INFO L290 TraceCheckUtils]: 45: Hoare triple {11528#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11528#false} is VALID [2022-04-07 22:05:56,226 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2022-04-07 22:05:56,226 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-07 22:07:44,555 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 93 [2022-04-07 22:07:44,809 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-07 22:07:44,810 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 2679803 treesize of output 2630649 [2022-04-07 22:09:54,862 WARN L232 SmtUtils]: Spent 2.17m on a formula simplification. DAG size of input: 927 DAG size of output: 851 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:10:15,358 WARN L232 SmtUtils]: Spent 16.09s on a formula simplification. DAG size of input: 836 DAG size of output: 836 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:10:37,318 WARN L232 SmtUtils]: Spent 10.12s on a formula simplification. DAG size of input: 704 DAG size of output: 704 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:11:04,475 WARN L232 SmtUtils]: Spent 8.92s on a formula simplification. DAG size of input: 681 DAG size of output: 681 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:11:19,239 WARN L232 SmtUtils]: Spent 7.80s on a formula simplification. DAG size of input: 670 DAG size of output: 670 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:11:40,255 WARN L232 SmtUtils]: Spent 6.76s on a formula simplification. DAG size of input: 640 DAG size of output: 640 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:11:52,672 WARN L232 SmtUtils]: Spent 6.62s on a formula simplification. DAG size of input: 638 DAG size of output: 638 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:12:03,517 WARN L232 SmtUtils]: Spent 6.69s on a formula simplification. DAG size of input: 636 DAG size of output: 636 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-07 22:12:22,488 WARN L232 SmtUtils]: Spent 6.52s on a formula simplification. DAG size of input: 519 DAG size of output: 519 (called from [L1067] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)