/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de52.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-e106359-m [2022-04-14 19:41:36,036 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-14 19:41:36,044 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-14 19:41:36,087 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-14 19:41:36,127 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-14 19:41:36,135 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-14 19:41:36,135 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-14 19:41:36,136 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-14 19:41:36,136 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-14 19:41:36,136 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-14 19:41:36,136 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-14 19:41:36,136 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-14 19:41:36,136 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-14 19:41:36,136 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-14 19:41:36,137 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-14 19:41:36,137 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-14 19:41:36,138 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-14 19:41:36,138 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-14 19:41:36,138 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-14 19:41:36,138 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-14 19:41:36,138 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-14 19:41:36,332 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-14 19:41:36,352 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-14 19:41:36,354 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-14 19:41:36,355 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-14 19:41:36,355 INFO L275 PluginConnector]: CDTParser initialized [2022-04-14 19:41:36,356 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de52.c [2022-04-14 19:41:36,408 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d062dd5fc/72369444f503471b9349aa9fadc95851/FLAG9f448cfb0 [2022-04-14 19:41:36,791 INFO L306 CDTParser]: Found 1 translation units. [2022-04-14 19:41:36,791 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de52.c [2022-04-14 19:41:36,795 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d062dd5fc/72369444f503471b9349aa9fadc95851/FLAG9f448cfb0 [2022-04-14 19:41:36,807 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/d062dd5fc/72369444f503471b9349aa9fadc95851 [2022-04-14 19:41:36,808 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-14 19:41:36,809 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-14 19:41:36,811 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-14 19:41:36,811 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-14 19:41:36,814 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-14 19:41:36,814 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.04 07:41:36" (1/1) ... [2022-04-14 19:41:36,815 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7672cff9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:36, skipping insertion in model container [2022-04-14 19:41:36,815 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 14.04 07:41:36" (1/1) ... [2022-04-14 19:41:36,820 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-14 19:41:36,829 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-14 19:41:36,940 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de52.c[368,381] [2022-04-14 19:41:36,950 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-14 19:41:36,956 INFO L203 MainTranslator]: Completed pre-run [2022-04-14 19:41:36,991 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de52.c[368,381] [2022-04-14 19:41:36,998 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-14 19:41:37,008 INFO L208 MainTranslator]: Completed translation [2022-04-14 19:41:37,009 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37 WrapperNode [2022-04-14 19:41:37,009 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-14 19:41:37,010 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-14 19:41:37,010 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-14 19:41:37,010 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-14 19:41:37,017 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,017 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,022 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,022 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,034 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,039 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,040 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,041 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-14 19:41:37,042 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-14 19:41:37,042 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-14 19:41:37,042 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-14 19:41:37,047 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,052 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-14 19:41:37,064 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:41:37,073 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-14 19:41:37,096 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-14 19:41:37,105 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-14 19:41:37,106 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-14 19:41:37,106 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-14 19:41:37,106 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-14 19:41:37,106 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-14 19:41:37,106 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-14 19:41:37,106 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-14 19:41:37,106 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-14 19:41:37,106 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-14 19:41:37,106 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-14 19:41:37,106 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-14 19:41:37,107 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-14 19:41:37,148 INFO L234 CfgBuilder]: Building ICFG [2022-04-14 19:41:37,149 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-14 19:41:37,291 INFO L275 CfgBuilder]: Performing block encoding [2022-04-14 19:41:37,296 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-14 19:41:37,296 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-04-14 19:41:37,297 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.04 07:41:37 BoogieIcfgContainer [2022-04-14 19:41:37,297 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-14 19:41:37,298 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-14 19:41:37,298 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-14 19:41:37,299 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-14 19:41:37,301 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.04 07:41:37" (1/1) ... [2022-04-14 19:41:37,303 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-14 19:41:37,901 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-14 19:41:37,901 INFO L91 elerationTransformer]: Accelerated Formula: (and (= (+ v_main_~x~0_3 1) v_main_~x~0_4) (= v_main_~y~0_5 (+ v_main_~y~0_6 1)) (< 0 (mod v_main_~x~0_4 4294967296))) InVars {main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_6} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-14 19:41:40,503 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-14 19:41:40,503 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_8 (+ v_main_~x~0_9 1)) (= v_main_~z~0_8 (+ v_main_~z~0_7 1)) (< 0 (mod v_main_~z~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_9, main_~z~0=v_main_~z~0_8} OutVars{main_~x~0=v_main_~x~0_8, main_~z~0=v_main_~z~0_7, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-14 19:41:40,836 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-14 19:41:40,836 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_4 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_4 (+ v_main_~y~0_3 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_3, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-14 19:41:41,104 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-14 19:41:41,105 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= (+ v_main_~y~0_8 1) v_main_~y~0_7)) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_8} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_7, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-14 19:41:41,381 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-14 19:41:41,382 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_10 (+ v_main_~z~0_9 1)) (< 0 (mod v_main_~z~0_10 4294967296)) (= v_main_~y~0_11 (+ v_main_~y~0_10 1))) InVars {main_~z~0=v_main_~z~0_10, main_~y~0=v_main_~y~0_11} OutVars{main_~z~0=v_main_~z~0_9, main_~y~0=v_main_~y~0_10, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] to Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] [2022-04-14 19:41:41,385 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 14.04 07:41:41 BasicIcfg [2022-04-14 19:41:41,385 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-14 19:41:41,386 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-14 19:41:41,386 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-14 19:41:41,388 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-14 19:41:41,388 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 14.04 07:41:36" (1/4) ... [2022-04-14 19:41:41,388 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5726adce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.04 07:41:41, skipping insertion in model container [2022-04-14 19:41:41,388 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 14.04 07:41:37" (2/4) ... [2022-04-14 19:41:41,389 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5726adce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 14.04 07:41:41, skipping insertion in model container [2022-04-14 19:41:41,389 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 14.04 07:41:37" (3/4) ... [2022-04-14 19:41:41,389 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5726adce and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 14.04 07:41:41, skipping insertion in model container [2022-04-14 19:41:41,389 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 14.04 07:41:41" (4/4) ... [2022-04-14 19:41:41,390 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de52.cJordan [2022-04-14 19:41:41,393 INFO L202 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-14 19:41:41,393 INFO L161 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-14 19:41:41,414 INFO L339 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-14 19:41:41,418 INFO L340 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP [2022-04-14 19:41:41,418 INFO L341 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-14 19:41:41,427 INFO L276 IsEmpty]: Start isEmpty. Operand has 24 states, 16 states have (on average 1.75) internal successors, (28), 17 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-14 19:41:41,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-14 19:41:41,431 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:41:41,431 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:41:41,431 INFO L403 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:41:41,434 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:41:41,434 INFO L85 PathProgramCache]: Analyzing trace with hash 702671213, now seen corresponding path program 1 times [2022-04-14 19:41:41,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:41:41,440 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1929440539] [2022-04-14 19:41:41,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:41:41,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:41:41,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:41,515 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:41:41,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:41,526 INFO L290 TraceCheckUtils]: 0: Hoare triple {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {27#true} is VALID [2022-04-14 19:41:41,526 INFO L290 TraceCheckUtils]: 1: Hoare triple {27#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-14 19:41:41,526 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {27#true} {27#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-14 19:41:41,527 INFO L272 TraceCheckUtils]: 0: Hoare triple {27#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:41:41,527 INFO L290 TraceCheckUtils]: 1: Hoare triple {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {27#true} is VALID [2022-04-14 19:41:41,528 INFO L290 TraceCheckUtils]: 2: Hoare triple {27#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-14 19:41:41,528 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {27#true} {27#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-14 19:41:41,528 INFO L272 TraceCheckUtils]: 4: Hoare triple {27#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-14 19:41:41,528 INFO L290 TraceCheckUtils]: 5: Hoare triple {27#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {27#true} is VALID [2022-04-14 19:41:41,528 INFO L290 TraceCheckUtils]: 6: Hoare triple {27#true} [92] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,529 INFO L290 TraceCheckUtils]: 7: Hoare triple {28#false} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {28#false} is VALID [2022-04-14 19:41:41,529 INFO L290 TraceCheckUtils]: 8: Hoare triple {28#false} [96] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,529 INFO L290 TraceCheckUtils]: 9: Hoare triple {28#false} [99] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,529 INFO L290 TraceCheckUtils]: 10: Hoare triple {28#false} [102] L35-1-->L41-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,529 INFO L290 TraceCheckUtils]: 11: Hoare triple {28#false} [105] L41-1-->L41-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,529 INFO L272 TraceCheckUtils]: 12: Hoare triple {28#false} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {28#false} is VALID [2022-04-14 19:41:41,530 INFO L290 TraceCheckUtils]: 13: Hoare triple {28#false} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {28#false} is VALID [2022-04-14 19:41:41,530 INFO L290 TraceCheckUtils]: 14: Hoare triple {28#false} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,530 INFO L290 TraceCheckUtils]: 15: Hoare triple {28#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-14 19:41:41,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:41,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:41:41,531 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1929440539] [2022-04-14 19:41:41,531 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1929440539] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-14 19:41:41,531 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-14 19:41:41,531 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-14 19:41:41,532 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1392358056] [2022-04-14 19:41:41,532 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-14 19:41:41,536 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-14 19:41:41,537 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:41:41,538 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,556 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:41:41,557 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-14 19:41:41,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:41:41,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-14 19:41:41,573 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-14 19:41:41,575 INFO L87 Difference]: Start difference. First operand has 24 states, 16 states have (on average 1.75) internal successors, (28), 17 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:41,654 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2022-04-14 19:41:41,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-14 19:41:41,654 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-14 19:41:41,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:41:41,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-14 19:41:41,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-14 19:41:41,662 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 34 transitions. [2022-04-14 19:41:41,691 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:41:41,696 INFO L225 Difference]: With dead ends: 24 [2022-04-14 19:41:41,696 INFO L226 Difference]: Without dead ends: 17 [2022-04-14 19:41:41,697 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-14 19:41:41,699 INFO L913 BasicCegarLoop]: 27 mSDtfsCounter, 19 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 30 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-14 19:41:41,700 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [20 Valid, 30 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-14 19:41:41,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2022-04-14 19:41:41,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-04-14 19:41:41,716 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:41:41,716 INFO L82 GeneralOperation]: Start isEquivalent. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,717 INFO L74 IsIncluded]: Start isIncluded. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,717 INFO L87 Difference]: Start difference. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:41,719 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2022-04-14 19:41:41,719 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-14 19:41:41,719 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:41:41,719 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:41:41,719 INFO L74 IsIncluded]: Start isIncluded. First operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 17 states. [2022-04-14 19:41:41,720 INFO L87 Difference]: Start difference. First operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 17 states. [2022-04-14 19:41:41,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:41,721 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2022-04-14 19:41:41,721 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-14 19:41:41,721 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:41:41,721 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:41:41,721 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:41:41,722 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:41:41,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2022-04-14 19:41:41,723 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 21 transitions. Word has length 16 [2022-04-14 19:41:41,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:41:41,723 INFO L478 AbstractCegarLoop]: Abstraction has 17 states and 21 transitions. [2022-04-14 19:41:41,724 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,724 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-14 19:41:41,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-14 19:41:41,724 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:41:41,724 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:41:41,724 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-14 19:41:41,725 INFO L403 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:41:41,725 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:41:41,725 INFO L85 PathProgramCache]: Analyzing trace with hash -1128942900, now seen corresponding path program 1 times [2022-04-14 19:41:41,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:41:41,725 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240502911] [2022-04-14 19:41:41,725 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:41:41,726 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:41:41,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:41,798 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:41:41,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:41,806 INFO L290 TraceCheckUtils]: 0: Hoare triple {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-14 19:41:41,807 INFO L290 TraceCheckUtils]: 1: Hoare triple {110#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,807 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {110#true} {110#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,807 INFO L272 TraceCheckUtils]: 0: Hoare triple {110#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:41:41,807 INFO L290 TraceCheckUtils]: 1: Hoare triple {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L290 TraceCheckUtils]: 2: Hoare triple {110#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {110#true} {110#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L272 TraceCheckUtils]: 4: Hoare triple {110#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L290 TraceCheckUtils]: 5: Hoare triple {110#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L290 TraceCheckUtils]: 6: Hoare triple {110#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L290 TraceCheckUtils]: 7: Hoare triple {110#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {110#true} is VALID [2022-04-14 19:41:41,808 INFO L290 TraceCheckUtils]: 8: Hoare triple {110#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-14 19:41:41,809 INFO L290 TraceCheckUtils]: 9: Hoare triple {110#true} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} is VALID [2022-04-14 19:41:41,810 INFO L290 TraceCheckUtils]: 10: Hoare triple {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} is VALID [2022-04-14 19:41:41,810 INFO L290 TraceCheckUtils]: 11: Hoare triple {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} is VALID [2022-04-14 19:41:41,811 INFO L272 TraceCheckUtils]: 12: Hoare triple {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {116#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:41:41,814 INFO L290 TraceCheckUtils]: 13: Hoare triple {116#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {117#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:41:41,814 INFO L290 TraceCheckUtils]: 14: Hoare triple {117#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-14 19:41:41,815 INFO L290 TraceCheckUtils]: 15: Hoare triple {111#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-14 19:41:41,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:41,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:41:41,815 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240502911] [2022-04-14 19:41:41,815 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240502911] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-14 19:41:41,815 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-14 19:41:41,815 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-14 19:41:41,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [22709824] [2022-04-14 19:41:41,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-14 19:41:41,817 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-14 19:41:41,817 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:41:41,817 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:41,831 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:41:41,833 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-14 19:41:41,833 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:41:41,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-14 19:41:41,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-04-14 19:41:41,834 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. Second operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:42,025 INFO L93 Difference]: Finished difference Result 28 states and 38 transitions. [2022-04-14 19:41:42,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-14 19:41:42,026 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-14 19:41:42,026 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:41:42,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 39 transitions. [2022-04-14 19:41:42,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 39 transitions. [2022-04-14 19:41:42,029 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 39 transitions. [2022-04-14 19:41:42,062 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:41:42,063 INFO L225 Difference]: With dead ends: 28 [2022-04-14 19:41:42,063 INFO L226 Difference]: Without dead ends: 25 [2022-04-14 19:41:42,063 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2022-04-14 19:41:42,064 INFO L913 BasicCegarLoop]: 14 mSDtfsCounter, 20 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 34 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 7 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-14 19:41:42,065 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [20 Valid, 34 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 33 Invalid, 0 Unknown, 7 Unchecked, 0.1s Time] [2022-04-14 19:41:42,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-04-14 19:41:42,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 19. [2022-04-14 19:41:42,066 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:41:42,066 INFO L82 GeneralOperation]: Start isEquivalent. First operand 25 states. Second operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,067 INFO L74 IsIncluded]: Start isIncluded. First operand 25 states. Second operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,067 INFO L87 Difference]: Start difference. First operand 25 states. Second operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:42,068 INFO L93 Difference]: Finished difference Result 25 states and 35 transitions. [2022-04-14 19:41:42,068 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-14 19:41:42,068 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:41:42,068 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:41:42,069 INFO L74 IsIncluded]: Start isIncluded. First operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-14 19:41:42,069 INFO L87 Difference]: Start difference. First operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-14 19:41:42,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:42,070 INFO L93 Difference]: Finished difference Result 25 states and 35 transitions. [2022-04-14 19:41:42,070 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-14 19:41:42,070 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:41:42,070 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:41:42,070 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:41:42,071 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:41:42,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 24 transitions. [2022-04-14 19:41:42,071 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 24 transitions. Word has length 16 [2022-04-14 19:41:42,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:41:42,072 INFO L478 AbstractCegarLoop]: Abstraction has 19 states and 24 transitions. [2022-04-14 19:41:42,072 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:42,072 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 24 transitions. [2022-04-14 19:41:42,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-14 19:41:42,072 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:41:42,072 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:41:42,072 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-14 19:41:42,073 INFO L403 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:41:42,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:41:42,073 INFO L85 PathProgramCache]: Analyzing trace with hash -610770875, now seen corresponding path program 1 times [2022-04-14 19:41:42,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:41:42,073 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2113027366] [2022-04-14 19:41:42,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:41:42,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:41:42,086 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:41:42,094 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:42,105 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:41:42,204 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:41:42,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:42,214 INFO L290 TraceCheckUtils]: 0: Hoare triple {235#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-14 19:41:42,214 INFO L290 TraceCheckUtils]: 1: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,214 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,215 INFO L272 TraceCheckUtils]: 0: Hoare triple {225#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {235#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:41:42,215 INFO L290 TraceCheckUtils]: 1: Hoare triple {235#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-14 19:41:42,215 INFO L290 TraceCheckUtils]: 2: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,215 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,216 INFO L272 TraceCheckUtils]: 4: Hoare triple {225#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,216 INFO L290 TraceCheckUtils]: 5: Hoare triple {225#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#(= main_~y~0 0)} is VALID [2022-04-14 19:41:42,216 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {230#(= main_~y~0 0)} is VALID [2022-04-14 19:41:42,217 INFO L290 TraceCheckUtils]: 7: Hoare triple {230#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {230#(= main_~y~0 0)} is VALID [2022-04-14 19:41:42,217 INFO L290 TraceCheckUtils]: 8: Hoare triple {230#(= main_~y~0 0)} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:41:42,218 INFO L290 TraceCheckUtils]: 9: Hoare triple {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:41:42,218 INFO L290 TraceCheckUtils]: 10: Hoare triple {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:41:42,220 INFO L290 TraceCheckUtils]: 11: Hoare triple {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:41:42,220 INFO L290 TraceCheckUtils]: 12: Hoare triple {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:41:42,221 INFO L272 TraceCheckUtils]: 13: Hoare triple {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {233#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:41:42,221 INFO L290 TraceCheckUtils]: 14: Hoare triple {233#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {234#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:41:42,222 INFO L290 TraceCheckUtils]: 15: Hoare triple {234#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-14 19:41:42,222 INFO L290 TraceCheckUtils]: 16: Hoare triple {226#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-14 19:41:42,222 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:42,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:41:42,222 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2113027366] [2022-04-14 19:41:42,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2113027366] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:41:42,223 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [205670975] [2022-04-14 19:41:42,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:41:42,223 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:41:42,223 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:41:42,224 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:41:42,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:42,265 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-14 19:41:42,265 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-14 19:41:42,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:42,319 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:41:42,918 INFO L272 TraceCheckUtils]: 0: Hoare triple {225#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,919 INFO L290 TraceCheckUtils]: 1: Hoare triple {225#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-14 19:41:42,919 INFO L290 TraceCheckUtils]: 2: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,919 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,919 INFO L272 TraceCheckUtils]: 4: Hoare triple {225#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,919 INFO L290 TraceCheckUtils]: 5: Hoare triple {225#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {225#true} is VALID [2022-04-14 19:41:42,919 INFO L290 TraceCheckUtils]: 6: Hoare triple {225#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:42,920 INFO L290 TraceCheckUtils]: 7: Hoare triple {225#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {225#true} is VALID [2022-04-14 19:41:42,920 INFO L290 TraceCheckUtils]: 8: Hoare triple {225#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {263#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-14 19:41:42,921 INFO L290 TraceCheckUtils]: 9: Hoare triple {263#(not (< 0 (mod main_~z~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-14 19:41:42,921 INFO L290 TraceCheckUtils]: 10: Hoare triple {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-14 19:41:42,922 INFO L290 TraceCheckUtils]: 11: Hoare triple {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:42,922 INFO L290 TraceCheckUtils]: 12: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:42,924 INFO L272 TraceCheckUtils]: 13: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {281#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:41:42,924 INFO L290 TraceCheckUtils]: 14: Hoare triple {281#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {285#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:41:42,924 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-14 19:41:42,925 INFO L290 TraceCheckUtils]: 16: Hoare triple {226#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-14 19:41:42,925 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:42,925 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:41:49,583 INFO L290 TraceCheckUtils]: 16: Hoare triple {226#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-14 19:41:49,583 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-14 19:41:49,584 INFO L290 TraceCheckUtils]: 14: Hoare triple {281#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {285#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:41:49,585 INFO L272 TraceCheckUtils]: 13: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {281#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:41:49,585 INFO L290 TraceCheckUtils]: 12: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:49,808 INFO L290 TraceCheckUtils]: 11: Hoare triple {307#(forall ((aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (<= aux_mod_v_main_~y~0_27_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_27_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_27_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:51,816 WARN L290 TraceCheckUtils]: 10: Hoare triple {307#(forall ((aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (<= aux_mod_v_main_~y~0_27_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_27_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_27_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))))))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {307#(forall ((aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (<= aux_mod_v_main_~y~0_27_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_27_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_27_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))))))))} is UNKNOWN [2022-04-14 19:41:51,819 INFO L290 TraceCheckUtils]: 9: Hoare triple {263#(not (< 0 (mod main_~z~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {307#(forall ((aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (<= aux_mod_v_main_~y~0_27_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_27_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_27_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))))))))} is VALID [2022-04-14 19:41:51,820 INFO L290 TraceCheckUtils]: 8: Hoare triple {225#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {263#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-14 19:41:51,820 INFO L290 TraceCheckUtils]: 7: Hoare triple {225#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {225#true} is VALID [2022-04-14 19:41:51,820 INFO L290 TraceCheckUtils]: 6: Hoare triple {225#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:51,820 INFO L290 TraceCheckUtils]: 5: Hoare triple {225#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {225#true} is VALID [2022-04-14 19:41:51,820 INFO L272 TraceCheckUtils]: 4: Hoare triple {225#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:51,820 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:51,821 INFO L290 TraceCheckUtils]: 2: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:51,821 INFO L290 TraceCheckUtils]: 1: Hoare triple {225#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-14 19:41:51,821 INFO L272 TraceCheckUtils]: 0: Hoare triple {225#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-14 19:41:51,821 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:51,821 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [205670975] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:41:51,821 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:41:51,822 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-14 19:41:51,822 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1193296568] [2022-04-14 19:41:51,822 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:41:51,822 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-14 19:41:51,823 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:41:51,823 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,362 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 33 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:41:52,362 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-14 19:41:52,362 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:41:52,362 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-14 19:41:52,363 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2022-04-14 19:41:52,363 INFO L87 Difference]: Start difference. First operand 19 states and 24 transitions. Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:52,913 INFO L93 Difference]: Finished difference Result 36 states and 50 transitions. [2022-04-14 19:41:52,913 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-14 19:41:52,913 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-14 19:41:52,914 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:41:52,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,915 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 51 transitions. [2022-04-14 19:41:52,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 51 transitions. [2022-04-14 19:41:52,917 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 51 transitions. [2022-04-14 19:41:52,973 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:41:52,975 INFO L225 Difference]: With dead ends: 36 [2022-04-14 19:41:52,975 INFO L226 Difference]: Without dead ends: 32 [2022-04-14 19:41:52,975 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=102, Invalid=360, Unknown=0, NotChecked=0, Total=462 [2022-04-14 19:41:52,976 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 27 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 62 SdHoareTripleChecker+Invalid, 114 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 19 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-14 19:41:52,976 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [27 Valid, 62 Invalid, 114 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 76 Invalid, 0 Unknown, 19 Unchecked, 0.1s Time] [2022-04-14 19:41:52,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-14 19:41:52,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 22. [2022-04-14 19:41:52,978 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:41:52,979 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,979 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,979 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:52,980 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-14 19:41:52,981 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-14 19:41:52,981 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:41:52,981 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:41:52,981 INFO L74 IsIncluded]: Start isIncluded. First operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-14 19:41:52,981 INFO L87 Difference]: Start difference. First operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-14 19:41:52,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:41:52,983 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-14 19:41:52,983 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-14 19:41:52,983 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:41:52,983 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:41:52,983 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:41:52,983 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:41:52,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,984 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 29 transitions. [2022-04-14 19:41:52,984 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 29 transitions. Word has length 17 [2022-04-14 19:41:52,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:41:52,984 INFO L478 AbstractCegarLoop]: Abstraction has 22 states and 29 transitions. [2022-04-14 19:41:52,985 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:41:52,985 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 29 transitions. [2022-04-14 19:41:52,985 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-14 19:41:52,985 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:41:52,985 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:41:53,010 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-14 19:41:53,211 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:41:53,211 INFO L403 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:41:53,212 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:41:53,212 INFO L85 PathProgramCache]: Analyzing trace with hash 162216202, now seen corresponding path program 1 times [2022-04-14 19:41:53,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:41:53,212 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296232177] [2022-04-14 19:41:53,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:41:53,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:41:53,235 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:41:53,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:53,264 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:41:53,450 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:41:53,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:53,463 INFO L290 TraceCheckUtils]: 0: Hoare triple {492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-14 19:41:53,463 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:53,464 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:53,468 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:41:53,469 INFO L290 TraceCheckUtils]: 1: Hoare triple {492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-14 19:41:53,469 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:53,469 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:53,469 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:53,469 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {487#(= main_~y~0 0)} is VALID [2022-04-14 19:41:53,470 INFO L290 TraceCheckUtils]: 6: Hoare triple {487#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:41:53,471 INFO L290 TraceCheckUtils]: 7: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:41:53,476 INFO L290 TraceCheckUtils]: 8: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:41:53,476 INFO L290 TraceCheckUtils]: 9: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:41:53,478 INFO L290 TraceCheckUtils]: 10: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:41:53,478 INFO L290 TraceCheckUtils]: 11: Hoare triple {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:41:53,479 INFO L290 TraceCheckUtils]: 12: Hoare triple {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:41:53,480 INFO L272 TraceCheckUtils]: 13: Hoare triple {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {490#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:41:53,480 INFO L290 TraceCheckUtils]: 14: Hoare triple {490#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {491#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:41:53,481 INFO L290 TraceCheckUtils]: 15: Hoare triple {491#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-14 19:41:53,481 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-14 19:41:53,481 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:53,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:41:53,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296232177] [2022-04-14 19:41:53,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296232177] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:41:53,482 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1266248821] [2022-04-14 19:41:53,482 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:41:53,482 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:41:53,482 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:41:53,483 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:41:53,491 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-14 19:41:53,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:53,530 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-14 19:41:53,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:41:53,542 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:41:54,052 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:54,052 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-14 19:41:54,052 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:54,052 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:54,053 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:41:54,053 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {482#true} is VALID [2022-04-14 19:41:54,053 INFO L290 TraceCheckUtils]: 6: Hoare triple {482#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:41:54,054 INFO L290 TraceCheckUtils]: 7: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:41:54,054 INFO L290 TraceCheckUtils]: 8: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:41:54,055 INFO L290 TraceCheckUtils]: 9: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {524#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:41:54,056 INFO L290 TraceCheckUtils]: 10: Hoare triple {524#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:54,056 INFO L290 TraceCheckUtils]: 11: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:54,057 INFO L290 TraceCheckUtils]: 12: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:41:54,057 INFO L272 TraceCheckUtils]: 13: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {538#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:41:54,058 INFO L290 TraceCheckUtils]: 14: Hoare triple {538#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {542#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:41:54,058 INFO L290 TraceCheckUtils]: 15: Hoare triple {542#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-14 19:41:54,059 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-14 19:41:54,059 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:41:54,059 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:42:00,107 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-14 19:42:00,107 INFO L290 TraceCheckUtils]: 15: Hoare triple {542#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-14 19:42:00,108 INFO L290 TraceCheckUtils]: 14: Hoare triple {538#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {542#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:42:00,108 INFO L272 TraceCheckUtils]: 13: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {538#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:42:00,109 INFO L290 TraceCheckUtils]: 12: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:42:00,109 INFO L290 TraceCheckUtils]: 11: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:42:00,240 INFO L290 TraceCheckUtils]: 10: Hoare triple {567#(forall ((aux_mod_v_main_~y~0_29_31 Int)) (or (<= aux_mod_v_main_~y~0_29_31 0) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_29_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296))))))) (or (forall ((aux_div_v_main_~y~0_29_31 Int)) (not (= (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296)) main_~y~0))) (< 0 (mod main_~x~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~y~0_29_31)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:42:00,241 INFO L290 TraceCheckUtils]: 9: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {567#(forall ((aux_mod_v_main_~y~0_29_31 Int)) (or (<= aux_mod_v_main_~y~0_29_31 0) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_29_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296))))))) (or (forall ((aux_div_v_main_~y~0_29_31 Int)) (not (= (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296)) main_~y~0))) (< 0 (mod main_~x~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~y~0_29_31)))} is VALID [2022-04-14 19:42:00,242 INFO L290 TraceCheckUtils]: 8: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:42:00,242 INFO L290 TraceCheckUtils]: 7: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:42:00,242 INFO L290 TraceCheckUtils]: 6: Hoare triple {482#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:42:00,242 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {482#true} is VALID [2022-04-14 19:42:00,242 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:42:00,243 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:42:00,243 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:42:00,243 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-14 19:42:00,243 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-14 19:42:00,243 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:42:00,246 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1266248821] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:42:00,246 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:42:00,246 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-14 19:42:00,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1004787919] [2022-04-14 19:42:00,246 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:42:00,248 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-14 19:42:00,249 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:42:00,249 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,313 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 31 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-14 19:42:02,313 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-14 19:42:02,313 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:42:02,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-14 19:42:02,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=142, Unknown=1, NotChecked=0, Total=182 [2022-04-14 19:42:02,314 INFO L87 Difference]: Start difference. First operand 22 states and 29 transitions. Second operand has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:42:02,883 INFO L93 Difference]: Finished difference Result 42 states and 60 transitions. [2022-04-14 19:42:02,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-14 19:42:02,883 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-14 19:42:02,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:42:02,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 57 transitions. [2022-04-14 19:42:02,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 57 transitions. [2022-04-14 19:42:02,886 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 57 transitions. [2022-04-14 19:42:02,937 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:42:02,938 INFO L225 Difference]: With dead ends: 42 [2022-04-14 19:42:02,938 INFO L226 Difference]: Without dead ends: 38 [2022-04-14 19:42:02,938 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 29 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=98, Invalid=363, Unknown=1, NotChecked=0, Total=462 [2022-04-14 19:42:02,939 INFO L913 BasicCegarLoop]: 16 mSDtfsCounter, 27 mSDsluCounter, 62 mSDsCounter, 0 mSdLazyCounter, 112 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 78 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 112 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-14 19:42:02,939 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [27 Valid, 78 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 112 Invalid, 0 Unknown, 24 Unchecked, 0.2s Time] [2022-04-14 19:42:02,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2022-04-14 19:42:02,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 25. [2022-04-14 19:42:02,941 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:42:02,941 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,942 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,942 INFO L87 Difference]: Start difference. First operand 38 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:42:02,943 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-14 19:42:02,943 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 55 transitions. [2022-04-14 19:42:02,944 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:42:02,944 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:42:02,944 INFO L74 IsIncluded]: Start isIncluded. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 38 states. [2022-04-14 19:42:02,944 INFO L87 Difference]: Start difference. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 38 states. [2022-04-14 19:42:02,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:42:02,945 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-14 19:42:02,945 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 55 transitions. [2022-04-14 19:42:02,946 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:42:02,946 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:42:02,946 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:42:02,946 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:42:02,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2022-04-14 19:42:02,947 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 35 transitions. Word has length 17 [2022-04-14 19:42:02,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:42:02,947 INFO L478 AbstractCegarLoop]: Abstraction has 25 states and 35 transitions. [2022-04-14 19:42:02,947 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:42:02,947 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-14 19:42:02,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-14 19:42:02,947 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:42:02,948 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:42:02,966 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-14 19:42:03,164 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-14 19:42:03,164 INFO L403 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:42:03,164 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:42:03,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1727307284, now seen corresponding path program 2 times [2022-04-14 19:42:03,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:42:03,165 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407152566] [2022-04-14 19:42:03,165 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:42:03,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:42:03,178 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:42:03,179 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_11 .cse0 (* (- 4294967296) (div (+ main_~z~0_11 .cse0) 4294967296)))) 0)) [2022-04-14 19:42:03,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:42:03,207 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:42:03,210 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_11 .cse0 (* (- 4294967296) (div (+ main_~z~0_11 .cse0) 4294967296)))) 0)) [2022-04-14 19:42:03,325 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:42:03,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:42:03,335 INFO L290 TraceCheckUtils]: 0: Hoare triple {772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-14 19:42:03,335 INFO L290 TraceCheckUtils]: 1: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,335 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,335 INFO L272 TraceCheckUtils]: 0: Hoare triple {762#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:42:03,336 INFO L290 TraceCheckUtils]: 1: Hoare triple {772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-14 19:42:03,336 INFO L290 TraceCheckUtils]: 2: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,336 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,336 INFO L272 TraceCheckUtils]: 4: Hoare triple {762#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,336 INFO L290 TraceCheckUtils]: 5: Hoare triple {762#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {767#(= main_~y~0 0)} is VALID [2022-04-14 19:42:03,337 INFO L290 TraceCheckUtils]: 6: Hoare triple {767#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {767#(= main_~y~0 0)} is VALID [2022-04-14 19:42:03,337 INFO L290 TraceCheckUtils]: 7: Hoare triple {767#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:42:03,337 INFO L290 TraceCheckUtils]: 8: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:42:03,338 INFO L290 TraceCheckUtils]: 9: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:42:03,338 INFO L290 TraceCheckUtils]: 10: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:42:03,339 INFO L290 TraceCheckUtils]: 11: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:42:03,340 INFO L290 TraceCheckUtils]: 12: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:42:03,340 INFO L290 TraceCheckUtils]: 13: Hoare triple {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:42:03,341 INFO L272 TraceCheckUtils]: 14: Hoare triple {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {770#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:42:03,342 INFO L290 TraceCheckUtils]: 15: Hoare triple {770#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {771#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:42:03,342 INFO L290 TraceCheckUtils]: 16: Hoare triple {771#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-14 19:42:03,342 INFO L290 TraceCheckUtils]: 17: Hoare triple {763#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-14 19:42:03,342 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:42:03,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:42:03,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407152566] [2022-04-14 19:42:03,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407152566] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:42:03,342 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1498952882] [2022-04-14 19:42:03,343 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-14 19:42:03,343 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:42:03,343 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:42:03,343 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:42:03,344 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-14 19:42:03,374 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-14 19:42:03,374 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-14 19:42:03,375 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-14 19:42:03,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:42:03,384 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:42:03,798 INFO L272 TraceCheckUtils]: 0: Hoare triple {762#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L290 TraceCheckUtils]: 1: Hoare triple {762#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L290 TraceCheckUtils]: 2: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L272 TraceCheckUtils]: 4: Hoare triple {762#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L290 TraceCheckUtils]: 5: Hoare triple {762#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L290 TraceCheckUtils]: 6: Hoare triple {762#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:42:03,799 INFO L290 TraceCheckUtils]: 7: Hoare triple {762#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {762#true} is VALID [2022-04-14 19:42:03,800 INFO L290 TraceCheckUtils]: 8: Hoare triple {762#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {800#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-14 19:42:03,800 INFO L290 TraceCheckUtils]: 9: Hoare triple {800#(not (< 0 (mod main_~z~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-14 19:42:03,800 INFO L290 TraceCheckUtils]: 10: Hoare triple {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-14 19:42:03,801 INFO L290 TraceCheckUtils]: 11: Hoare triple {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-14 19:42:03,802 INFO L290 TraceCheckUtils]: 12: Hoare triple {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:42:03,802 INFO L290 TraceCheckUtils]: 13: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:42:03,803 INFO L272 TraceCheckUtils]: 14: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {821#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:42:03,804 INFO L290 TraceCheckUtils]: 15: Hoare triple {821#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {825#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:42:03,805 INFO L290 TraceCheckUtils]: 16: Hoare triple {825#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-14 19:42:03,805 INFO L290 TraceCheckUtils]: 17: Hoare triple {763#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-14 19:42:03,805 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:42:03,805 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:43:40,911 INFO L290 TraceCheckUtils]: 17: Hoare triple {763#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-14 19:43:40,912 INFO L290 TraceCheckUtils]: 16: Hoare triple {825#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-14 19:43:40,912 INFO L290 TraceCheckUtils]: 15: Hoare triple {821#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {825#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:43:40,913 INFO L272 TraceCheckUtils]: 14: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {821#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:43:40,914 INFO L290 TraceCheckUtils]: 13: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:43:41,036 INFO L290 TraceCheckUtils]: 12: Hoare triple {847#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:43:43,192 WARN L290 TraceCheckUtils]: 11: Hoare triple {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {847#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))))))} is UNKNOWN [2022-04-14 19:43:45,277 WARN L290 TraceCheckUtils]: 10: Hoare triple {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} is UNKNOWN [2022-04-14 19:43:47,330 WARN L290 TraceCheckUtils]: 9: Hoare triple {858#(forall ((aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (< aux_mod_main_~y~0_26 0) (not (< 0 (mod main_~z~0 4294967296))) (< 0 aux_mod_main_~y~0_26) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295)) 4294967296)) (forall ((aux_div_main_~y~0_26 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_div_main_~y~0_26 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26)) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))))))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} is UNKNOWN [2022-04-14 19:43:47,332 INFO L290 TraceCheckUtils]: 8: Hoare triple {762#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {858#(forall ((aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (< aux_mod_main_~y~0_26 0) (not (< 0 (mod main_~z~0 4294967296))) (< 0 aux_mod_main_~y~0_26) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295)) 4294967296)) (forall ((aux_div_main_~y~0_26 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_div_main_~y~0_26 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26)) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))))))))} is VALID [2022-04-14 19:43:47,332 INFO L290 TraceCheckUtils]: 7: Hoare triple {762#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {762#true} is VALID [2022-04-14 19:43:47,332 INFO L290 TraceCheckUtils]: 6: Hoare triple {762#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:43:47,332 INFO L290 TraceCheckUtils]: 5: Hoare triple {762#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {762#true} is VALID [2022-04-14 19:43:47,332 INFO L272 TraceCheckUtils]: 4: Hoare triple {762#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:43:47,332 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:43:47,332 INFO L290 TraceCheckUtils]: 2: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:43:47,333 INFO L290 TraceCheckUtils]: 1: Hoare triple {762#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-14 19:43:47,333 INFO L272 TraceCheckUtils]: 0: Hoare triple {762#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-14 19:43:47,333 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:43:47,333 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1498952882] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:43:47,333 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:43:47,333 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 8] total 16 [2022-04-14 19:43:47,333 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1573052575] [2022-04-14 19:43:47,333 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:43:47,334 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:43:47,334 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:43:47,334 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:43:55,614 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 33 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-14 19:43:55,614 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-14 19:43:55,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:43:55,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-14 19:43:55,615 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=179, Unknown=13, NotChecked=0, Total=240 [2022-04-14 19:43:55,615 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:44:05,091 INFO L93 Difference]: Finished difference Result 42 states and 59 transitions. [2022-04-14 19:44:05,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-14 19:44:05,092 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:44:05,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:44:05,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 51 transitions. [2022-04-14 19:44:05,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 51 transitions. [2022-04-14 19:44:05,094 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 51 transitions. [2022-04-14 19:44:05,147 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:44:05,148 INFO L225 Difference]: With dead ends: 42 [2022-04-14 19:44:05,148 INFO L226 Difference]: Without dead ends: 32 [2022-04-14 19:44:05,149 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 31 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 35.2s TimeCoverageRelationStatistics Valid=104, Invalid=387, Unknown=15, NotChecked=0, Total=506 [2022-04-14 19:44:05,149 INFO L913 BasicCegarLoop]: 12 mSDtfsCounter, 37 mSDsluCounter, 65 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 37 SdHoareTripleChecker+Valid, 77 SdHoareTripleChecker+Invalid, 129 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 43 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-14 19:44:05,149 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [37 Valid, 77 Invalid, 129 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 72 Invalid, 0 Unknown, 43 Unchecked, 0.2s Time] [2022-04-14 19:44:05,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-14 19:44:05,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 24. [2022-04-14 19:44:05,151 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:44:05,151 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,151 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,151 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:44:05,152 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-14 19:44:05,152 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-14 19:44:05,153 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:44:05,153 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:44:05,153 INFO L74 IsIncluded]: Start isIncluded. First operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-14 19:44:05,153 INFO L87 Difference]: Start difference. First operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-14 19:44:05,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:44:05,156 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-14 19:44:05,157 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-14 19:44:05,157 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:44:05,157 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:44:05,157 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:44:05,157 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:44:05,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 32 transitions. [2022-04-14 19:44:05,158 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 32 transitions. Word has length 18 [2022-04-14 19:44:05,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:44:05,158 INFO L478 AbstractCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-04-14 19:44:05,158 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:05,158 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 32 transitions. [2022-04-14 19:44:05,159 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-14 19:44:05,159 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:44:05,159 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:44:05,195 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2022-04-14 19:44:05,382 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:44:05,383 INFO L403 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:44:05,383 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:44:05,383 INFO L85 PathProgramCache]: Analyzing trace with hash 760455623, now seen corresponding path program 1 times [2022-04-14 19:44:05,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:44:05,383 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816632273] [2022-04-14 19:44:05,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:44:05,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:44:05,394 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:44:05,395 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:44:05,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:05,415 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:44:05,417 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:44:05,658 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:44:05,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:05,663 INFO L290 TraceCheckUtils]: 0: Hoare triple {1046#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1034#true} is VALID [2022-04-14 19:44:05,663 INFO L290 TraceCheckUtils]: 1: Hoare triple {1034#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:05,663 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1034#true} {1034#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:05,664 INFO L272 TraceCheckUtils]: 0: Hoare triple {1034#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1046#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:44:05,664 INFO L290 TraceCheckUtils]: 1: Hoare triple {1046#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1034#true} is VALID [2022-04-14 19:44:05,664 INFO L290 TraceCheckUtils]: 2: Hoare triple {1034#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:05,664 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1034#true} {1034#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:05,664 INFO L272 TraceCheckUtils]: 4: Hoare triple {1034#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:05,665 INFO L290 TraceCheckUtils]: 5: Hoare triple {1034#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1039#(= main_~y~0 0)} is VALID [2022-04-14 19:44:05,665 INFO L290 TraceCheckUtils]: 6: Hoare triple {1039#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:05,666 INFO L290 TraceCheckUtils]: 7: Hoare triple {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:05,666 INFO L290 TraceCheckUtils]: 8: Hoare triple {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1041#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:44:05,667 INFO L290 TraceCheckUtils]: 9: Hoare triple {1041#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1041#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:44:05,668 INFO L290 TraceCheckUtils]: 10: Hoare triple {1041#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1042#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-14 19:44:05,669 INFO L290 TraceCheckUtils]: 11: Hoare triple {1042#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1042#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-14 19:44:05,670 INFO L290 TraceCheckUtils]: 12: Hoare triple {1042#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1043#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:44:05,670 INFO L290 TraceCheckUtils]: 13: Hoare triple {1043#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1043#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:44:05,671 INFO L272 TraceCheckUtils]: 14: Hoare triple {1043#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1044#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:44:05,672 INFO L290 TraceCheckUtils]: 15: Hoare triple {1044#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1045#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:44:05,672 INFO L290 TraceCheckUtils]: 16: Hoare triple {1045#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1035#false} is VALID [2022-04-14 19:44:05,672 INFO L290 TraceCheckUtils]: 17: Hoare triple {1035#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1035#false} is VALID [2022-04-14 19:44:05,672 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:44:05,672 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:44:05,672 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816632273] [2022-04-14 19:44:05,673 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816632273] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:44:05,673 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1858796916] [2022-04-14 19:44:05,673 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:44:05,673 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:44:05,673 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:44:05,674 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:44:05,674 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-14 19:44:05,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:05,706 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-14 19:44:05,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:05,715 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:44:06,696 INFO L272 TraceCheckUtils]: 0: Hoare triple {1034#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:06,696 INFO L290 TraceCheckUtils]: 1: Hoare triple {1034#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1034#true} is VALID [2022-04-14 19:44:06,696 INFO L290 TraceCheckUtils]: 2: Hoare triple {1034#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:06,696 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1034#true} {1034#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:06,696 INFO L272 TraceCheckUtils]: 4: Hoare triple {1034#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:06,697 INFO L290 TraceCheckUtils]: 5: Hoare triple {1034#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1034#true} is VALID [2022-04-14 19:44:06,697 INFO L290 TraceCheckUtils]: 6: Hoare triple {1034#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1068#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:06,697 INFO L290 TraceCheckUtils]: 7: Hoare triple {1068#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1068#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:06,698 INFO L290 TraceCheckUtils]: 8: Hoare triple {1068#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1075#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:44:06,698 INFO L290 TraceCheckUtils]: 9: Hoare triple {1075#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1079#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:44:06,699 INFO L290 TraceCheckUtils]: 10: Hoare triple {1079#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1083#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:44:06,700 INFO L290 TraceCheckUtils]: 11: Hoare triple {1083#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1083#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:44:06,700 INFO L290 TraceCheckUtils]: 12: Hoare triple {1083#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1090#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:44:06,701 INFO L290 TraceCheckUtils]: 13: Hoare triple {1090#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1090#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:44:06,701 INFO L272 TraceCheckUtils]: 14: Hoare triple {1090#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1097#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:44:06,702 INFO L290 TraceCheckUtils]: 15: Hoare triple {1097#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1101#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:44:06,702 INFO L290 TraceCheckUtils]: 16: Hoare triple {1101#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1035#false} is VALID [2022-04-14 19:44:06,702 INFO L290 TraceCheckUtils]: 17: Hoare triple {1035#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1035#false} is VALID [2022-04-14 19:44:06,702 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:44:06,703 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:44:21,881 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~y~0_36_31 Int) (v_main_~y~0_37 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (let ((.cse0 (< 0 (mod c_main_~z~0 4294967296)))) (and (or .cse0 (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31))))) (or (not .cse0) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37)))))))) (<= aux_mod_v_main_~y~0_36_31 0) (let ((.cse1 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (not (= v_main_~y~0_37 c_main_~y~0)) .cse1) (or (not .cse1) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 c_main_~y~0 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< c_main_~y~0 v_main_~y~0_37))))))) is different from false [2022-04-14 19:44:35,566 INFO L290 TraceCheckUtils]: 17: Hoare triple {1035#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1035#false} is VALID [2022-04-14 19:44:35,572 INFO L290 TraceCheckUtils]: 16: Hoare triple {1101#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1035#false} is VALID [2022-04-14 19:44:35,572 INFO L290 TraceCheckUtils]: 15: Hoare triple {1097#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1101#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:44:35,574 INFO L272 TraceCheckUtils]: 14: Hoare triple {1090#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1097#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:44:35,575 INFO L290 TraceCheckUtils]: 13: Hoare triple {1090#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1090#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:44:37,586 WARN L290 TraceCheckUtils]: 12: Hoare triple {1123#(forall ((aux_mod_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0)))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1090#(<= (mod main_~y~0 4294967296) 0)} is UNKNOWN [2022-04-14 19:44:39,596 WARN L290 TraceCheckUtils]: 11: Hoare triple {1123#(forall ((aux_mod_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0)))))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1123#(forall ((aux_mod_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0)))))))} is UNKNOWN [2022-04-14 19:44:41,617 WARN L290 TraceCheckUtils]: 10: Hoare triple {1130#(forall ((aux_mod_v_main_~y~0_36_31 Int) (v_main_~y~0_37 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (and (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 v_main_~y~0_37)) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (= v_main_~y~0_37 main_~y~0)) (< 0 (mod main_~x~0 4294967296)))) (<= aux_mod_v_main_~y~0_36_31 0)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1123#(forall ((aux_mod_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0)))))))} is UNKNOWN [2022-04-14 19:44:43,632 WARN L290 TraceCheckUtils]: 9: Hoare triple {1134#(forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_mod_main_~y~0_26 Int) (v_main_~y~0_37 Int)) (or (and (or (forall ((aux_div_main_~y~0_26 Int)) (not (= v_main_~y~0_37 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))))) (< 0 (mod main_~x~0 4294967296))) (or (forall ((aux_div_main_~y~0_26 Int)) (or (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_37)) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (not (< 0 (mod main_~x~0 4294967296))))) (< aux_mod_main_~y~0_26 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (< 0 aux_mod_main_~y~0_26) (<= aux_mod_v_main_~y~0_36_31 0)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1130#(forall ((aux_mod_v_main_~y~0_36_31 Int) (v_main_~y~0_37 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (and (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 v_main_~y~0_37)) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (= v_main_~y~0_37 main_~y~0)) (< 0 (mod main_~x~0 4294967296)))) (<= aux_mod_v_main_~y~0_36_31 0)))} is UNKNOWN [2022-04-14 19:44:43,638 INFO L290 TraceCheckUtils]: 8: Hoare triple {1068#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1134#(forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_mod_main_~y~0_26 Int) (v_main_~y~0_37 Int)) (or (and (or (forall ((aux_div_main_~y~0_26 Int)) (not (= v_main_~y~0_37 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))))) (< 0 (mod main_~x~0 4294967296))) (or (forall ((aux_div_main_~y~0_26 Int)) (or (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_37)) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (not (< 0 (mod main_~x~0 4294967296))))) (< aux_mod_main_~y~0_26 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (< 0 aux_mod_main_~y~0_26) (<= aux_mod_v_main_~y~0_36_31 0)))} is VALID [2022-04-14 19:44:43,639 INFO L290 TraceCheckUtils]: 7: Hoare triple {1068#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1068#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:43,640 INFO L290 TraceCheckUtils]: 6: Hoare triple {1034#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1068#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:43,640 INFO L290 TraceCheckUtils]: 5: Hoare triple {1034#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1034#true} is VALID [2022-04-14 19:44:43,640 INFO L272 TraceCheckUtils]: 4: Hoare triple {1034#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:43,640 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1034#true} {1034#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:43,640 INFO L290 TraceCheckUtils]: 2: Hoare triple {1034#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:43,640 INFO L290 TraceCheckUtils]: 1: Hoare triple {1034#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1034#true} is VALID [2022-04-14 19:44:43,641 INFO L272 TraceCheckUtils]: 0: Hoare triple {1034#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#true} is VALID [2022-04-14 19:44:43,641 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-14 19:44:43,641 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1858796916] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:44:43,641 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:44:43,641 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 20 [2022-04-14 19:44:43,641 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [658413064] [2022-04-14 19:44:43,641 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:44:43,642 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:44:43,642 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:44:43,642 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:49,273 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 35 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-14 19:44:49,273 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-04-14 19:44:49,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:44:49,274 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-04-14 19:44:49,274 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=269, Unknown=5, NotChecked=34, Total=380 [2022-04-14 19:44:49,274 INFO L87 Difference]: Start difference. First operand 24 states and 32 transitions. Second operand has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:52,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:44:52,959 INFO L93 Difference]: Finished difference Result 41 states and 56 transitions. [2022-04-14 19:44:52,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-04-14 19:44:52,959 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:44:52,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:44:52,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:52,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 56 transitions. [2022-04-14 19:44:52,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:52,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 56 transitions. [2022-04-14 19:44:52,968 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 19 states and 56 transitions. [2022-04-14 19:44:53,071 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:44:53,073 INFO L225 Difference]: With dead ends: 41 [2022-04-14 19:44:53,073 INFO L226 Difference]: Without dead ends: 37 [2022-04-14 19:44:53,073 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 26 SyntacticMatches, 6 SemanticMatches, 30 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 276 ImplicationChecksByTransitivity, 16.9s TimeCoverageRelationStatistics Valid=181, Invalid=748, Unknown=5, NotChecked=58, Total=992 [2022-04-14 19:44:53,074 INFO L913 BasicCegarLoop]: 15 mSDtfsCounter, 31 mSDsluCounter, 65 mSDsCounter, 0 mSdLazyCounter, 81 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 80 SdHoareTripleChecker+Invalid, 159 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 81 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 52 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-14 19:44:53,074 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [31 Valid, 80 Invalid, 159 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 81 Invalid, 0 Unknown, 52 Unchecked, 0.2s Time] [2022-04-14 19:44:53,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-14 19:44:53,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 26. [2022-04-14 19:44:53,076 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:44:53,077 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:53,077 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:53,077 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:53,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:44:53,078 INFO L93 Difference]: Finished difference Result 37 states and 51 transitions. [2022-04-14 19:44:53,078 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 51 transitions. [2022-04-14 19:44:53,079 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:44:53,079 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:44:53,079 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 37 states. [2022-04-14 19:44:53,079 INFO L87 Difference]: Start difference. First operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 37 states. [2022-04-14 19:44:53,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:44:53,080 INFO L93 Difference]: Finished difference Result 37 states and 51 transitions. [2022-04-14 19:44:53,081 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 51 transitions. [2022-04-14 19:44:53,081 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:44:53,081 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:44:53,081 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:44:53,081 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:44:53,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:53,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 35 transitions. [2022-04-14 19:44:53,082 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 35 transitions. Word has length 18 [2022-04-14 19:44:53,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:44:53,082 INFO L478 AbstractCegarLoop]: Abstraction has 26 states and 35 transitions. [2022-04-14 19:44:53,082 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:44:53,082 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 35 transitions. [2022-04-14 19:44:53,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-14 19:44:53,083 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:44:53,083 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:44:53,113 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-14 19:44:53,287 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:44:53,287 INFO L403 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:44:53,288 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:44:53,288 INFO L85 PathProgramCache]: Analyzing trace with hash 1533442700, now seen corresponding path program 2 times [2022-04-14 19:44:53,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:44:53,288 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105244701] [2022-04-14 19:44:53,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:44:53,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:44:53,297 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:44:53,299 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_10 (* (- 4294967296) (div (+ .cse0 main_~x~0_10) 4294967296)))) 0)) [2022-04-14 19:44:53,303 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:53,325 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:44:53,328 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_10 (* (- 4294967296) (div (+ .cse0 main_~x~0_10) 4294967296)))) 0)) [2022-04-14 19:44:53,571 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:44:53,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:53,580 INFO L290 TraceCheckUtils]: 0: Hoare triple {1343#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-14 19:44:53,580 INFO L290 TraceCheckUtils]: 1: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:53,580 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:53,581 INFO L272 TraceCheckUtils]: 0: Hoare triple {1333#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1343#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:44:53,581 INFO L290 TraceCheckUtils]: 1: Hoare triple {1343#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-14 19:44:53,581 INFO L290 TraceCheckUtils]: 2: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:53,581 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:53,581 INFO L272 TraceCheckUtils]: 4: Hoare triple {1333#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:53,582 INFO L290 TraceCheckUtils]: 5: Hoare triple {1333#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1338#(= main_~y~0 0)} is VALID [2022-04-14 19:44:53,582 INFO L290 TraceCheckUtils]: 6: Hoare triple {1338#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:53,583 INFO L290 TraceCheckUtils]: 7: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:53,583 INFO L290 TraceCheckUtils]: 8: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:53,584 INFO L290 TraceCheckUtils]: 9: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:53,585 INFO L290 TraceCheckUtils]: 10: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:44:53,587 INFO L290 TraceCheckUtils]: 11: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:44:53,587 INFO L290 TraceCheckUtils]: 12: Hoare triple {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:44:53,588 INFO L290 TraceCheckUtils]: 13: Hoare triple {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:44:53,588 INFO L272 TraceCheckUtils]: 14: Hoare triple {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1341#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:44:53,589 INFO L290 TraceCheckUtils]: 15: Hoare triple {1341#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1342#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:44:53,589 INFO L290 TraceCheckUtils]: 16: Hoare triple {1342#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-14 19:44:53,589 INFO L290 TraceCheckUtils]: 17: Hoare triple {1334#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-14 19:44:53,589 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:44:53,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:44:53,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [105244701] [2022-04-14 19:44:53,590 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [105244701] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:44:53,590 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [68887133] [2022-04-14 19:44:53,590 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-14 19:44:53,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:44:53,590 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:44:53,592 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:44:53,594 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-14 19:44:53,646 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-14 19:44:53,646 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-14 19:44:53,647 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-14 19:44:53,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:44:53,659 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:44:54,623 INFO L272 TraceCheckUtils]: 0: Hoare triple {1333#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:54,623 INFO L290 TraceCheckUtils]: 1: Hoare triple {1333#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-14 19:44:54,623 INFO L290 TraceCheckUtils]: 2: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:54,623 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:54,623 INFO L272 TraceCheckUtils]: 4: Hoare triple {1333#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:44:54,623 INFO L290 TraceCheckUtils]: 5: Hoare triple {1333#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1333#true} is VALID [2022-04-14 19:44:54,624 INFO L290 TraceCheckUtils]: 6: Hoare triple {1333#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1365#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:54,624 INFO L290 TraceCheckUtils]: 7: Hoare triple {1365#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1365#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:54,624 INFO L290 TraceCheckUtils]: 8: Hoare triple {1365#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1365#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:44:54,625 INFO L290 TraceCheckUtils]: 9: Hoare triple {1365#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:44:54,626 INFO L290 TraceCheckUtils]: 10: Hoare triple {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:44:54,627 INFO L290 TraceCheckUtils]: 11: Hoare triple {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:44:54,627 INFO L290 TraceCheckUtils]: 12: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:44:54,629 INFO L290 TraceCheckUtils]: 13: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:44:54,630 INFO L272 TraceCheckUtils]: 14: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:44:54,630 INFO L290 TraceCheckUtils]: 15: Hoare triple {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1396#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:44:54,631 INFO L290 TraceCheckUtils]: 16: Hoare triple {1396#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-14 19:44:54,631 INFO L290 TraceCheckUtils]: 17: Hoare triple {1334#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-14 19:44:54,631 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:44:54,631 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:46:37,221 INFO L290 TraceCheckUtils]: 17: Hoare triple {1334#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-14 19:46:37,224 INFO L290 TraceCheckUtils]: 16: Hoare triple {1396#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-14 19:46:37,225 INFO L290 TraceCheckUtils]: 15: Hoare triple {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1396#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:46:37,226 INFO L272 TraceCheckUtils]: 14: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:46:37,226 INFO L290 TraceCheckUtils]: 13: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:46:37,226 INFO L290 TraceCheckUtils]: 12: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:46:37,281 INFO L290 TraceCheckUtils]: 11: Hoare triple {1421#(forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)))) (or (forall ((aux_div_v_main_~y~0_40_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (not (< 0 (mod main_~x~0 4294967296))))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:46:39,293 WARN L290 TraceCheckUtils]: 10: Hoare triple {1425#(forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)))) (or (forall ((v_main_~y~0_41 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_41))) (not (< main_~y~0 v_main_~y~0_41)) (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (or (forall ((aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))))))) (not (< 0 (mod main_~x~0 4294967296)))))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1421#(forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)))) (or (forall ((aux_div_v_main_~y~0_40_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (not (< 0 (mod main_~x~0 4294967296))))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31)))} is UNKNOWN [2022-04-14 19:46:41,652 WARN L290 TraceCheckUtils]: 9: Hoare triple {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1425#(forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)))) (or (forall ((v_main_~y~0_41 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_41))) (not (< main_~y~0 v_main_~y~0_41)) (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (or (forall ((aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))))))) (not (< 0 (mod main_~x~0 4294967296)))))))} is UNKNOWN [2022-04-14 19:46:43,764 WARN L290 TraceCheckUtils]: 8: Hoare triple {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} is UNKNOWN [2022-04-14 19:46:45,790 WARN L290 TraceCheckUtils]: 7: Hoare triple {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} is UNKNOWN [2022-04-14 19:46:45,793 INFO L290 TraceCheckUtils]: 6: Hoare triple {1333#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} is VALID [2022-04-14 19:46:45,793 INFO L290 TraceCheckUtils]: 5: Hoare triple {1333#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1333#true} is VALID [2022-04-14 19:46:45,793 INFO L272 TraceCheckUtils]: 4: Hoare triple {1333#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:46:45,793 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:46:45,793 INFO L290 TraceCheckUtils]: 2: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:46:45,793 INFO L290 TraceCheckUtils]: 1: Hoare triple {1333#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-14 19:46:45,793 INFO L272 TraceCheckUtils]: 0: Hoare triple {1333#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-14 19:46:45,794 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:46:45,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [68887133] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:46:45,794 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:46:45,794 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 8] total 16 [2022-04-14 19:46:45,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1583991564] [2022-04-14 19:46:45,794 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:46:45,794 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:46:45,795 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:46:45,795 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:46:56,409 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 33 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-14 19:46:56,409 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-14 19:46:56,410 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:46:56,410 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-14 19:46:56,410 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=179, Unknown=13, NotChecked=0, Total=240 [2022-04-14 19:46:56,410 INFO L87 Difference]: Start difference. First operand 26 states and 35 transitions. Second operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:47:04,223 INFO L93 Difference]: Finished difference Result 43 states and 60 transitions. [2022-04-14 19:47:04,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-14 19:47:04,224 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:47:04,224 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:47:04,225 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 52 transitions. [2022-04-14 19:47:04,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 52 transitions. [2022-04-14 19:47:04,234 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 52 transitions. [2022-04-14 19:47:04,288 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:47:04,289 INFO L225 Difference]: With dead ends: 43 [2022-04-14 19:47:04,289 INFO L226 Difference]: Without dead ends: 39 [2022-04-14 19:47:04,289 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 29 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 39.5s TimeCoverageRelationStatistics Valid=104, Invalid=388, Unknown=14, NotChecked=0, Total=506 [2022-04-14 19:47:04,289 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 34 mSDsluCounter, 63 mSDsCounter, 0 mSdLazyCounter, 79 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 34 SdHoareTripleChecker+Valid, 76 SdHoareTripleChecker+Invalid, 131 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 79 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 38 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-14 19:47:04,290 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [34 Valid, 76 Invalid, 131 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 79 Invalid, 0 Unknown, 38 Unchecked, 0.3s Time] [2022-04-14 19:47:04,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2022-04-14 19:47:04,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 27. [2022-04-14 19:47:04,293 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:47:04,293 INFO L82 GeneralOperation]: Start isEquivalent. First operand 39 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,294 INFO L74 IsIncluded]: Start isIncluded. First operand 39 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,294 INFO L87 Difference]: Start difference. First operand 39 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:47:04,295 INFO L93 Difference]: Finished difference Result 39 states and 55 transitions. [2022-04-14 19:47:04,295 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 55 transitions. [2022-04-14 19:47:04,295 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:47:04,295 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:47:04,295 INFO L74 IsIncluded]: Start isIncluded. First operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 39 states. [2022-04-14 19:47:04,295 INFO L87 Difference]: Start difference. First operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 39 states. [2022-04-14 19:47:04,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:47:04,297 INFO L93 Difference]: Finished difference Result 39 states and 55 transitions. [2022-04-14 19:47:04,297 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 55 transitions. [2022-04-14 19:47:04,297 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:47:04,297 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:47:04,297 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:47:04,297 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:47:04,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,298 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-04-14 19:47:04,298 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 37 transitions. Word has length 18 [2022-04-14 19:47:04,298 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:47:04,298 INFO L478 AbstractCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-04-14 19:47:04,298 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:04,298 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 37 transitions. [2022-04-14 19:47:04,298 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-14 19:47:04,298 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:47:04,299 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:47:04,330 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-14 19:47:04,514 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:47:04,515 INFO L403 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:47:04,515 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:47:04,515 INFO L85 PathProgramCache]: Analyzing trace with hash 571694412, now seen corresponding path program 1 times [2022-04-14 19:47:04,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:47:04,515 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619864306] [2022-04-14 19:47:04,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:47:04,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:47:04,524 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-14 19:47:04,525 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-14 19:47:04,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:47:04,535 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-14 19:47:04,539 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-14 19:47:04,839 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:47:04,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:47:04,846 INFO L290 TraceCheckUtils]: 0: Hoare triple {1632#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-14 19:47:04,846 INFO L290 TraceCheckUtils]: 1: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:04,846 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:04,846 INFO L272 TraceCheckUtils]: 0: Hoare triple {1622#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1632#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:47:04,847 INFO L290 TraceCheckUtils]: 1: Hoare triple {1632#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-14 19:47:04,847 INFO L290 TraceCheckUtils]: 2: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:04,847 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:04,847 INFO L272 TraceCheckUtils]: 4: Hoare triple {1622#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:04,847 INFO L290 TraceCheckUtils]: 5: Hoare triple {1622#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1627#(= main_~y~0 0)} is VALID [2022-04-14 19:47:04,847 INFO L290 TraceCheckUtils]: 6: Hoare triple {1627#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1627#(= main_~y~0 0)} is VALID [2022-04-14 19:47:04,848 INFO L290 TraceCheckUtils]: 7: Hoare triple {1627#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:04,848 INFO L290 TraceCheckUtils]: 8: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:04,849 INFO L290 TraceCheckUtils]: 9: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:04,849 INFO L290 TraceCheckUtils]: 10: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:04,850 INFO L290 TraceCheckUtils]: 11: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:04,851 INFO L290 TraceCheckUtils]: 12: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:47:04,851 INFO L290 TraceCheckUtils]: 13: Hoare triple {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:47:04,852 INFO L272 TraceCheckUtils]: 14: Hoare triple {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1630#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:47:04,852 INFO L290 TraceCheckUtils]: 15: Hoare triple {1630#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1631#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:47:04,853 INFO L290 TraceCheckUtils]: 16: Hoare triple {1631#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-14 19:47:04,853 INFO L290 TraceCheckUtils]: 17: Hoare triple {1623#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-14 19:47:04,853 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:47:04,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:47:04,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619864306] [2022-04-14 19:47:04,853 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619864306] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:47:04,853 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [622587671] [2022-04-14 19:47:04,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:47:04,853 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:47:04,854 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:47:04,854 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:47:04,855 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-14 19:47:04,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:47:04,887 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 10 conjunts are in the unsatisfiable core [2022-04-14 19:47:04,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:47:04,897 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:47:05,150 INFO L272 TraceCheckUtils]: 0: Hoare triple {1622#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:05,150 INFO L290 TraceCheckUtils]: 1: Hoare triple {1622#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-14 19:47:05,150 INFO L290 TraceCheckUtils]: 2: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:05,151 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:05,151 INFO L272 TraceCheckUtils]: 4: Hoare triple {1622#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:05,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {1622#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1627#(= main_~y~0 0)} is VALID [2022-04-14 19:47:05,151 INFO L290 TraceCheckUtils]: 6: Hoare triple {1627#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1627#(= main_~y~0 0)} is VALID [2022-04-14 19:47:05,152 INFO L290 TraceCheckUtils]: 7: Hoare triple {1627#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:05,152 INFO L290 TraceCheckUtils]: 8: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:05,153 INFO L290 TraceCheckUtils]: 9: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:05,153 INFO L290 TraceCheckUtils]: 10: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:05,154 INFO L290 TraceCheckUtils]: 11: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-14 19:47:05,154 INFO L290 TraceCheckUtils]: 12: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1627#(= main_~y~0 0)} is VALID [2022-04-14 19:47:05,154 INFO L290 TraceCheckUtils]: 13: Hoare triple {1627#(= main_~y~0 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1627#(= main_~y~0 0)} is VALID [2022-04-14 19:47:05,155 INFO L272 TraceCheckUtils]: 14: Hoare triple {1627#(= main_~y~0 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:47:05,156 INFO L290 TraceCheckUtils]: 15: Hoare triple {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1682#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:47:05,156 INFO L290 TraceCheckUtils]: 16: Hoare triple {1682#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-14 19:47:05,156 INFO L290 TraceCheckUtils]: 17: Hoare triple {1623#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-14 19:47:05,157 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:47:05,157 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:47:34,073 WARN L855 $PredicateComparison]: unable to prove that (or (not (< 0 (mod c_main_~y~0 4294967296))) (forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (and (or (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) c_main_~y~0)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) c_main_~y~0) (<= 1 v_it_3))))) (< 0 (mod (+ (* 4294967295 aux_mod_v_main_~y~0_44_31) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (let ((.cse0 (* 4294967296 aux_div_v_main_~z~0_34_31))) (or (<= 4294967296 aux_mod_v_main_~z~0_34_31) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ c_main_~y~0 c_main_~z~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= (+ .cse0 aux_mod_v_main_~z~0_34_31) c_main_~z~0) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)))) (<= (+ c_main_~y~0 c_main_~z~0) (+ .cse0 aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))))) (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31))) (< 0 (mod c_main_~z~0 4294967296))) is different from true [2022-04-14 19:47:34,118 INFO L290 TraceCheckUtils]: 17: Hoare triple {1623#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-14 19:47:34,119 INFO L290 TraceCheckUtils]: 16: Hoare triple {1682#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-14 19:47:34,119 INFO L290 TraceCheckUtils]: 15: Hoare triple {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1682#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:47:34,120 INFO L272 TraceCheckUtils]: 14: Hoare triple {1698#(= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:47:34,120 INFO L290 TraceCheckUtils]: 13: Hoare triple {1698#(= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1698#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:47:34,162 INFO L290 TraceCheckUtils]: 12: Hoare triple {1705#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1698#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:47:34,163 INFO L290 TraceCheckUtils]: 11: Hoare triple {1705#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1705#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} is VALID [2022-04-14 19:47:34,164 INFO L290 TraceCheckUtils]: 10: Hoare triple {1705#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1705#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} is VALID [2022-04-14 19:47:36,176 WARN L290 TraceCheckUtils]: 9: Hoare triple {1715#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296)))))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))) (< 0 (mod main_~y~0 4294967296)))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1705#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} is UNKNOWN [2022-04-14 19:47:38,202 WARN L290 TraceCheckUtils]: 8: Hoare triple {1719#(or (not (< 0 (mod main_~y~0 4294967296))) (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1715#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296)))))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))) (< 0 (mod main_~y~0 4294967296)))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} is UNKNOWN [2022-04-14 19:47:38,204 INFO L290 TraceCheckUtils]: 7: Hoare triple {1622#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1719#(or (not (< 0 (mod main_~y~0 4294967296))) (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31))))} is VALID [2022-04-14 19:47:38,204 INFO L290 TraceCheckUtils]: 6: Hoare triple {1622#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:38,204 INFO L290 TraceCheckUtils]: 5: Hoare triple {1622#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1622#true} is VALID [2022-04-14 19:47:38,204 INFO L272 TraceCheckUtils]: 4: Hoare triple {1622#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:38,204 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:38,205 INFO L290 TraceCheckUtils]: 2: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:38,205 INFO L290 TraceCheckUtils]: 1: Hoare triple {1622#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-14 19:47:38,205 INFO L272 TraceCheckUtils]: 0: Hoare triple {1622#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-14 19:47:38,205 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:47:38,205 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [622587671] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:47:38,205 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:47:38,205 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 8] total 14 [2022-04-14 19:47:38,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1926047418] [2022-04-14 19:47:38,205 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:47:38,206 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:47:38,206 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:47:38,206 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:47:48,436 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 30 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-14 19:47:48,436 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-14 19:47:48,436 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:47:48,437 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-14 19:47:48,437 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=119, Unknown=6, NotChecked=22, Total=182 [2022-04-14 19:47:48,437 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:05,360 WARN L232 SmtUtils]: Spent 10.30s on a formula simplification that was a NOOP. DAG size: 76 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-14 19:48:30,134 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:48:30,134 INFO L93 Difference]: Finished difference Result 45 states and 63 transitions. [2022-04-14 19:48:30,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-14 19:48:30,134 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:48:30,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:48:30,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:30,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 54 transitions. [2022-04-14 19:48:30,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:30,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 54 transitions. [2022-04-14 19:48:30,137 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 54 transitions. [2022-04-14 19:48:36,511 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 51 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-14 19:48:36,512 INFO L225 Difference]: With dead ends: 45 [2022-04-14 19:48:36,512 INFO L226 Difference]: Without dead ends: 41 [2022-04-14 19:48:36,512 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 32 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 73 ImplicationChecksByTransitivity, 54.1s TimeCoverageRelationStatistics Valid=91, Invalid=317, Unknown=16, NotChecked=38, Total=462 [2022-04-14 19:48:36,512 INFO L913 BasicCegarLoop]: 14 mSDtfsCounter, 32 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 60 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 75 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-14 19:48:36,513 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [32 Valid, 60 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 61 Invalid, 0 Unknown, 75 Unchecked, 0.2s Time] [2022-04-14 19:48:36,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2022-04-14 19:48:36,514 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 34. [2022-04-14 19:48:36,514 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:48:36,515 INFO L82 GeneralOperation]: Start isEquivalent. First operand 41 states. Second operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:36,516 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:36,517 INFO L87 Difference]: Start difference. First operand 41 states. Second operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:36,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:48:36,518 INFO L93 Difference]: Finished difference Result 41 states and 58 transitions. [2022-04-14 19:48:36,518 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 58 transitions. [2022-04-14 19:48:36,518 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:48:36,518 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:48:36,518 INFO L74 IsIncluded]: Start isIncluded. First operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 41 states. [2022-04-14 19:48:36,518 INFO L87 Difference]: Start difference. First operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 41 states. [2022-04-14 19:48:36,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:48:36,519 INFO L93 Difference]: Finished difference Result 41 states and 58 transitions. [2022-04-14 19:48:36,519 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 58 transitions. [2022-04-14 19:48:36,520 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:48:36,520 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:48:36,520 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:48:36,520 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:48:36,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:36,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 50 transitions. [2022-04-14 19:48:36,521 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 50 transitions. Word has length 18 [2022-04-14 19:48:36,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:48:36,521 INFO L478 AbstractCegarLoop]: Abstraction has 34 states and 50 transitions. [2022-04-14 19:48:36,521 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:36,521 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 50 transitions. [2022-04-14 19:48:36,521 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-14 19:48:36,521 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:48:36,521 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:48:36,539 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-14 19:48:36,722 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:48:36,722 INFO L403 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:48:36,722 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:48:36,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1344681489, now seen corresponding path program 1 times [2022-04-14 19:48:36,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:48:36,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369008083] [2022-04-14 19:48:36,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:48:36,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:48:36,731 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-14 19:48:36,733 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:48:36,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:36,742 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-14 19:48:36,745 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:48:37,048 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:48:37,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:37,052 INFO L290 TraceCheckUtils]: 0: Hoare triple {1935#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-14 19:48:37,052 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:37,052 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:37,053 INFO L272 TraceCheckUtils]: 0: Hoare triple {1925#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1935#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:48:37,053 INFO L290 TraceCheckUtils]: 1: Hoare triple {1935#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-14 19:48:37,053 INFO L290 TraceCheckUtils]: 2: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:37,053 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:37,053 INFO L272 TraceCheckUtils]: 4: Hoare triple {1925#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:37,054 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1930#(= main_~y~0 0)} is VALID [2022-04-14 19:48:37,054 INFO L290 TraceCheckUtils]: 6: Hoare triple {1930#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:37,055 INFO L290 TraceCheckUtils]: 7: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:37,055 INFO L290 TraceCheckUtils]: 8: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:37,056 INFO L290 TraceCheckUtils]: 9: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:37,056 INFO L290 TraceCheckUtils]: 10: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:37,058 INFO L290 TraceCheckUtils]: 11: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:48:37,058 INFO L290 TraceCheckUtils]: 12: Hoare triple {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:48:37,059 INFO L290 TraceCheckUtils]: 13: Hoare triple {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:48:37,060 INFO L272 TraceCheckUtils]: 14: Hoare triple {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1933#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:48:37,060 INFO L290 TraceCheckUtils]: 15: Hoare triple {1933#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1934#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:48:37,060 INFO L290 TraceCheckUtils]: 16: Hoare triple {1934#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-14 19:48:37,060 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-14 19:48:37,061 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:48:37,061 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:48:37,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369008083] [2022-04-14 19:48:37,061 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369008083] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:48:37,061 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1985442857] [2022-04-14 19:48:37,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:48:37,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:48:37,061 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:48:37,062 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:48:37,063 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-14 19:48:37,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:37,111 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-14 19:48:37,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:37,118 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:48:38,148 INFO L272 TraceCheckUtils]: 0: Hoare triple {1925#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:38,148 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-14 19:48:38,149 INFO L290 TraceCheckUtils]: 2: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:38,149 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:38,149 INFO L272 TraceCheckUtils]: 4: Hoare triple {1925#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:38,149 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1925#true} is VALID [2022-04-14 19:48:38,149 INFO L290 TraceCheckUtils]: 6: Hoare triple {1925#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:38,149 INFO L290 TraceCheckUtils]: 7: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:38,150 INFO L290 TraceCheckUtils]: 8: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:38,150 INFO L290 TraceCheckUtils]: 9: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:38,151 INFO L290 TraceCheckUtils]: 10: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1970#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:48:38,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {1970#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:48:38,152 INFO L290 TraceCheckUtils]: 12: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:48:38,152 INFO L290 TraceCheckUtils]: 13: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:48:38,153 INFO L272 TraceCheckUtils]: 14: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:48:38,153 INFO L290 TraceCheckUtils]: 15: Hoare triple {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1988#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:48:38,154 INFO L290 TraceCheckUtils]: 16: Hoare triple {1988#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-14 19:48:38,154 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-14 19:48:38,154 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:48:38,154 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:48:47,034 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-14 19:48:47,034 INFO L290 TraceCheckUtils]: 16: Hoare triple {1988#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-14 19:48:47,035 INFO L290 TraceCheckUtils]: 15: Hoare triple {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1988#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:48:47,035 INFO L272 TraceCheckUtils]: 14: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:48:47,036 INFO L290 TraceCheckUtils]: 13: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:48:47,036 INFO L290 TraceCheckUtils]: 12: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:48:49,041 WARN L290 TraceCheckUtils]: 11: Hoare triple {2013#(forall ((aux_mod_v_main_~y~0_47_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_47_31) (<= aux_mod_v_main_~y~0_47_31 0) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (< 0 (mod main_~x~0 4294967296))))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1974#(<= (mod main_~y~0 4294967296) 0)} is UNKNOWN [2022-04-14 19:48:49,044 INFO L290 TraceCheckUtils]: 10: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2013#(forall ((aux_mod_v_main_~y~0_47_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_47_31) (<= aux_mod_v_main_~y~0_47_31 0) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (< 0 (mod main_~x~0 4294967296))))))} is VALID [2022-04-14 19:48:49,044 INFO L290 TraceCheckUtils]: 9: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:49,045 INFO L290 TraceCheckUtils]: 8: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:49,045 INFO L290 TraceCheckUtils]: 7: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:49,045 INFO L290 TraceCheckUtils]: 6: Hoare triple {1925#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:48:49,045 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1925#true} is VALID [2022-04-14 19:48:49,045 INFO L272 TraceCheckUtils]: 4: Hoare triple {1925#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:49,046 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:49,046 INFO L290 TraceCheckUtils]: 2: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:49,046 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-14 19:48:49,046 INFO L272 TraceCheckUtils]: 0: Hoare triple {1925#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-14 19:48:49,046 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:48:49,046 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1985442857] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:48:49,046 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:48:49,046 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-14 19:48:49,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1869136968] [2022-04-14 19:48:49,046 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:48:49,047 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:48:49,047 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:48:49,047 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:51,112 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 33 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-14 19:48:51,112 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-14 19:48:51,112 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:48:51,113 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-14 19:48:51,113 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=140, Unknown=3, NotChecked=0, Total=182 [2022-04-14 19:48:51,113 INFO L87 Difference]: Start difference. First operand 34 states and 50 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:48:52,272 INFO L93 Difference]: Finished difference Result 53 states and 77 transitions. [2022-04-14 19:48:52,272 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-04-14 19:48:52,272 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:48:52,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:48:52,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 60 transitions. [2022-04-14 19:48:52,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 60 transitions. [2022-04-14 19:48:52,274 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 15 states and 60 transitions. [2022-04-14 19:48:52,345 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:48:52,346 INFO L225 Difference]: With dead ends: 53 [2022-04-14 19:48:52,347 INFO L226 Difference]: Without dead ends: 49 [2022-04-14 19:48:52,347 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 32 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=98, Invalid=361, Unknown=3, NotChecked=0, Total=462 [2022-04-14 19:48:52,347 INFO L913 BasicCegarLoop]: 17 mSDtfsCounter, 40 mSDsluCounter, 41 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 58 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-14 19:48:52,348 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [40 Valid, 58 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 70 Invalid, 0 Unknown, 23 Unchecked, 0.3s Time] [2022-04-14 19:48:52,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-04-14 19:48:52,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 36. [2022-04-14 19:48:52,350 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:48:52,351 INFO L82 GeneralOperation]: Start isEquivalent. First operand 49 states. Second operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,351 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,351 INFO L87 Difference]: Start difference. First operand 49 states. Second operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:48:52,353 INFO L93 Difference]: Finished difference Result 49 states and 72 transitions. [2022-04-14 19:48:52,353 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 72 transitions. [2022-04-14 19:48:52,353 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:48:52,353 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:48:52,354 INFO L74 IsIncluded]: Start isIncluded. First operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 49 states. [2022-04-14 19:48:52,354 INFO L87 Difference]: Start difference. First operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 49 states. [2022-04-14 19:48:52,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:48:52,367 INFO L93 Difference]: Finished difference Result 49 states and 72 transitions. [2022-04-14 19:48:52,367 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 72 transitions. [2022-04-14 19:48:52,367 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:48:52,367 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:48:52,368 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:48:52,368 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:48:52,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 54 transitions. [2022-04-14 19:48:52,374 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 54 transitions. Word has length 18 [2022-04-14 19:48:52,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:48:52,374 INFO L478 AbstractCegarLoop]: Abstraction has 36 states and 54 transitions. [2022-04-14 19:48:52,375 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:48:52,375 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 54 transitions. [2022-04-14 19:48:52,375 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-14 19:48:52,375 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:48:52,375 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:48:52,403 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-14 19:48:52,583 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:48:52,585 INFO L403 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:48:52,586 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:48:52,586 INFO L85 PathProgramCache]: Analyzing trace with hash -211948756, now seen corresponding path program 1 times [2022-04-14 19:48:52,586 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:48:52,586 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1234510759] [2022-04-14 19:48:52,586 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:48:52,586 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:48:52,595 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:48:52,596 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-14 19:48:52,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:52,613 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:48:52,617 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-14 19:48:53,051 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:48:53,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:53,055 INFO L290 TraceCheckUtils]: 0: Hoare triple {2266#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-14 19:48:53,055 INFO L290 TraceCheckUtils]: 1: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:53,055 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:53,056 INFO L272 TraceCheckUtils]: 0: Hoare triple {2255#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2266#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:48:53,056 INFO L290 TraceCheckUtils]: 1: Hoare triple {2266#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-14 19:48:53,056 INFO L290 TraceCheckUtils]: 2: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:53,056 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:53,056 INFO L272 TraceCheckUtils]: 4: Hoare triple {2255#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:53,057 INFO L290 TraceCheckUtils]: 5: Hoare triple {2255#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2260#(= main_~y~0 0)} is VALID [2022-04-14 19:48:53,057 INFO L290 TraceCheckUtils]: 6: Hoare triple {2260#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:53,058 INFO L290 TraceCheckUtils]: 7: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:53,059 INFO L290 TraceCheckUtils]: 8: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:53,059 INFO L290 TraceCheckUtils]: 9: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:53,060 INFO L290 TraceCheckUtils]: 10: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:53,061 INFO L290 TraceCheckUtils]: 11: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:48:53,062 INFO L290 TraceCheckUtils]: 12: Hoare triple {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:48:53,062 INFO L290 TraceCheckUtils]: 13: Hoare triple {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:48:53,069 INFO L272 TraceCheckUtils]: 14: Hoare triple {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2264#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:48:53,070 INFO L290 TraceCheckUtils]: 15: Hoare triple {2264#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2265#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:48:53,070 INFO L290 TraceCheckUtils]: 16: Hoare triple {2265#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-14 19:48:53,070 INFO L290 TraceCheckUtils]: 17: Hoare triple {2256#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-14 19:48:53,070 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:48:53,070 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:48:53,070 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1234510759] [2022-04-14 19:48:53,071 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1234510759] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:48:53,071 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2010484715] [2022-04-14 19:48:53,071 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:48:53,071 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:48:53,071 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:48:53,072 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:48:53,073 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-14 19:48:53,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:53,110 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-14 19:48:53,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:48:53,123 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:48:54,013 INFO L272 TraceCheckUtils]: 0: Hoare triple {2255#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:54,013 INFO L290 TraceCheckUtils]: 1: Hoare triple {2255#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-14 19:48:54,013 INFO L290 TraceCheckUtils]: 2: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:54,013 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:54,013 INFO L272 TraceCheckUtils]: 4: Hoare triple {2255#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:48:54,014 INFO L290 TraceCheckUtils]: 5: Hoare triple {2255#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2260#(= main_~y~0 0)} is VALID [2022-04-14 19:48:54,015 INFO L290 TraceCheckUtils]: 6: Hoare triple {2260#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:54,015 INFO L290 TraceCheckUtils]: 7: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:54,016 INFO L290 TraceCheckUtils]: 8: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:54,017 INFO L290 TraceCheckUtils]: 9: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:54,017 INFO L290 TraceCheckUtils]: 10: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:48:54,018 INFO L290 TraceCheckUtils]: 11: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2260#(= main_~y~0 0)} is VALID [2022-04-14 19:48:54,018 INFO L290 TraceCheckUtils]: 12: Hoare triple {2260#(= main_~y~0 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2260#(= main_~y~0 0)} is VALID [2022-04-14 19:48:54,019 INFO L290 TraceCheckUtils]: 13: Hoare triple {2260#(= main_~y~0 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2260#(= main_~y~0 0)} is VALID [2022-04-14 19:48:54,019 INFO L272 TraceCheckUtils]: 14: Hoare triple {2260#(= main_~y~0 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:48:54,020 INFO L290 TraceCheckUtils]: 15: Hoare triple {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2316#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:48:54,020 INFO L290 TraceCheckUtils]: 16: Hoare triple {2316#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-14 19:48:54,020 INFO L290 TraceCheckUtils]: 17: Hoare triple {2256#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-14 19:48:54,020 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:48:54,020 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:49:03,832 INFO L290 TraceCheckUtils]: 17: Hoare triple {2256#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-14 19:49:03,833 INFO L290 TraceCheckUtils]: 16: Hoare triple {2316#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-14 19:49:03,833 INFO L290 TraceCheckUtils]: 15: Hoare triple {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2316#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:49:03,834 INFO L272 TraceCheckUtils]: 14: Hoare triple {2332#(= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:49:03,834 INFO L290 TraceCheckUtils]: 13: Hoare triple {2332#(= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2332#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:49:03,834 INFO L290 TraceCheckUtils]: 12: Hoare triple {2332#(= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2332#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:49:04,050 INFO L290 TraceCheckUtils]: 11: Hoare triple {2342#(forall ((aux_mod_v_main_~y~0_50_31 Int)) (or (and (or (forall ((aux_div_v_main_~y~0_50_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_50_31 Int)) (not (= (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)) main_~y~0))))) (> 0 aux_mod_v_main_~y~0_50_31) (= aux_mod_v_main_~y~0_50_31 0) (>= aux_mod_v_main_~y~0_50_31 4294967296)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2332#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:49:06,065 WARN L290 TraceCheckUtils]: 10: Hoare triple {2346#(or (forall ((aux_mod_v_main_~y~0_50_31 Int)) (or (forall ((aux_div_v_main_~y~0_50_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)))))) (> 0 aux_mod_v_main_~y~0_50_31) (= aux_mod_v_main_~y~0_50_31 0) (not (< 0 (mod main_~x~0 4294967296))) (>= aux_mod_v_main_~y~0_50_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2342#(forall ((aux_mod_v_main_~y~0_50_31 Int)) (or (and (or (forall ((aux_div_v_main_~y~0_50_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_50_31 Int)) (not (= (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)) main_~y~0))))) (> 0 aux_mod_v_main_~y~0_50_31) (= aux_mod_v_main_~y~0_50_31 0) (>= aux_mod_v_main_~y~0_50_31 4294967296)))} is UNKNOWN [2022-04-14 19:49:06,066 INFO L290 TraceCheckUtils]: 9: Hoare triple {2350#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2346#(or (forall ((aux_mod_v_main_~y~0_50_31 Int)) (or (forall ((aux_div_v_main_~y~0_50_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)))))) (> 0 aux_mod_v_main_~y~0_50_31) (= aux_mod_v_main_~y~0_50_31 0) (not (< 0 (mod main_~x~0 4294967296))) (>= aux_mod_v_main_~y~0_50_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-14 19:49:06,092 INFO L290 TraceCheckUtils]: 8: Hoare triple {2354#(or (forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))) (<= 1 v_it_2))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31))) (< 0 (mod main_~y~0 4294967296)))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2350#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-14 19:49:06,094 INFO L290 TraceCheckUtils]: 7: Hoare triple {2350#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2354#(or (forall ((aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (forall ((aux_div_v_main_~x~0_32_31 Int)) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))) (<= 1 v_it_2))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_32_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-14 19:49:06,094 INFO L290 TraceCheckUtils]: 6: Hoare triple {2255#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2350#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-14 19:49:06,094 INFO L290 TraceCheckUtils]: 5: Hoare triple {2255#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2255#true} is VALID [2022-04-14 19:49:06,094 INFO L272 TraceCheckUtils]: 4: Hoare triple {2255#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:49:06,094 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:49:06,094 INFO L290 TraceCheckUtils]: 2: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:49:06,095 INFO L290 TraceCheckUtils]: 1: Hoare triple {2255#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-14 19:49:06,095 INFO L272 TraceCheckUtils]: 0: Hoare triple {2255#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-14 19:49:06,095 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:49:06,095 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2010484715] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:49:06,095 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:49:06,095 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 9] total 16 [2022-04-14 19:49:06,095 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572385743] [2022-04-14 19:49:06,095 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:49:06,096 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:49:06,096 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:49:06,096 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:08,980 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 38 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-14 19:49:08,981 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-14 19:49:08,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:49:08,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-14 19:49:08,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=188, Unknown=1, NotChecked=0, Total=240 [2022-04-14 19:49:08,981 INFO L87 Difference]: Start difference. First operand 36 states and 54 transitions. Second operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:15,785 WARN L232 SmtUtils]: Spent 6.17s on a formula simplification that was a NOOP. DAG size: 53 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-14 19:49:19,117 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:49:19,117 INFO L93 Difference]: Finished difference Result 58 states and 86 transitions. [2022-04-14 19:49:19,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-04-14 19:49:19,118 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-14 19:49:19,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:49:19,118 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 57 transitions. [2022-04-14 19:49:19,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 57 transitions. [2022-04-14 19:49:19,120 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 17 states and 57 transitions. [2022-04-14 19:49:19,397 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:49:19,397 INFO L225 Difference]: With dead ends: 58 [2022-04-14 19:49:19,398 INFO L226 Difference]: Without dead ends: 54 [2022-04-14 19:49:19,398 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 30 SyntacticMatches, 7 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 167 ImplicationChecksByTransitivity, 16.4s TimeCoverageRelationStatistics Valid=141, Invalid=508, Unknown=1, NotChecked=0, Total=650 [2022-04-14 19:49:19,398 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 44 mSDsluCounter, 41 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 44 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 119 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 34 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-14 19:49:19,398 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [44 Valid, 54 Invalid, 119 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 68 Invalid, 0 Unknown, 34 Unchecked, 0.3s Time] [2022-04-14 19:49:19,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2022-04-14 19:49:19,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 40. [2022-04-14 19:49:19,401 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:49:19,401 INFO L82 GeneralOperation]: Start isEquivalent. First operand 54 states. Second operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,401 INFO L74 IsIncluded]: Start isIncluded. First operand 54 states. Second operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,401 INFO L87 Difference]: Start difference. First operand 54 states. Second operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:49:19,402 INFO L93 Difference]: Finished difference Result 54 states and 81 transitions. [2022-04-14 19:49:19,402 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 81 transitions. [2022-04-14 19:49:19,402 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:49:19,402 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:49:19,402 INFO L74 IsIncluded]: Start isIncluded. First operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 54 states. [2022-04-14 19:49:19,402 INFO L87 Difference]: Start difference. First operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 54 states. [2022-04-14 19:49:19,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:49:19,403 INFO L93 Difference]: Finished difference Result 54 states and 81 transitions. [2022-04-14 19:49:19,404 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 81 transitions. [2022-04-14 19:49:19,404 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:49:19,404 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:49:19,404 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:49:19,404 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:49:19,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 61 transitions. [2022-04-14 19:49:19,405 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 61 transitions. Word has length 18 [2022-04-14 19:49:19,405 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:49:19,405 INFO L478 AbstractCegarLoop]: Abstraction has 40 states and 61 transitions. [2022-04-14 19:49:19,405 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:49:19,405 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 61 transitions. [2022-04-14 19:49:19,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-14 19:49:19,405 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:49:19,405 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:49:19,437 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-14 19:49:19,621 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-04-14 19:49:19,621 INFO L403 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:49:19,622 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:49:19,622 INFO L85 PathProgramCache]: Analyzing trace with hash 2126008490, now seen corresponding path program 2 times [2022-04-14 19:49:19,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:49:19,622 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901839218] [2022-04-14 19:49:19,622 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:49:19,622 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:49:19,631 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:49:19,632 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:49:19,633 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_12 .cse0 (* (- 4294967296) (div (+ main_~z~0_12 .cse0) 4294967296)))) 0)) [2022-04-14 19:49:19,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:49:19,651 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:49:19,653 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.4))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:49:19,655 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_12 .cse0 (* (- 4294967296) (div (+ main_~z~0_12 .cse0) 4294967296)))) 0)) [2022-04-14 19:49:20,164 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:49:20,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:49:20,168 INFO L290 TraceCheckUtils]: 0: Hoare triple {2623#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2611#true} is VALID [2022-04-14 19:49:20,168 INFO L290 TraceCheckUtils]: 1: Hoare triple {2611#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:20,168 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2611#true} {2611#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:20,168 INFO L272 TraceCheckUtils]: 0: Hoare triple {2611#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2623#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:49:20,168 INFO L290 TraceCheckUtils]: 1: Hoare triple {2623#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2611#true} is VALID [2022-04-14 19:49:20,168 INFO L290 TraceCheckUtils]: 2: Hoare triple {2611#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:20,169 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2611#true} {2611#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:20,169 INFO L272 TraceCheckUtils]: 4: Hoare triple {2611#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:20,169 INFO L290 TraceCheckUtils]: 5: Hoare triple {2611#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2616#(= main_~y~0 0)} is VALID [2022-04-14 19:49:20,170 INFO L290 TraceCheckUtils]: 6: Hoare triple {2616#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2617#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:49:20,170 INFO L290 TraceCheckUtils]: 7: Hoare triple {2617#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2618#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:49:20,170 INFO L290 TraceCheckUtils]: 8: Hoare triple {2618#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2618#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:49:20,171 INFO L290 TraceCheckUtils]: 9: Hoare triple {2618#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2618#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:49:20,172 INFO L290 TraceCheckUtils]: 10: Hoare triple {2618#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2619#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} is VALID [2022-04-14 19:49:20,173 INFO L290 TraceCheckUtils]: 11: Hoare triple {2619#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2619#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} is VALID [2022-04-14 19:49:20,173 INFO L290 TraceCheckUtils]: 12: Hoare triple {2619#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2619#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} is VALID [2022-04-14 19:49:20,175 INFO L290 TraceCheckUtils]: 13: Hoare triple {2619#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2620#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:49:20,175 INFO L290 TraceCheckUtils]: 14: Hoare triple {2620#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2620#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:49:20,176 INFO L272 TraceCheckUtils]: 15: Hoare triple {2620#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2621#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:49:20,176 INFO L290 TraceCheckUtils]: 16: Hoare triple {2621#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2622#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:49:20,177 INFO L290 TraceCheckUtils]: 17: Hoare triple {2622#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2612#false} is VALID [2022-04-14 19:49:20,177 INFO L290 TraceCheckUtils]: 18: Hoare triple {2612#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2612#false} is VALID [2022-04-14 19:49:20,177 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:49:20,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:49:20,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901839218] [2022-04-14 19:49:20,177 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901839218] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:49:20,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [435333114] [2022-04-14 19:49:20,177 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-14 19:49:20,177 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:49:20,177 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:49:20,178 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:49:20,179 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-14 19:49:20,211 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-14 19:49:20,211 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-14 19:49:20,211 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-14 19:49:20,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:49:20,224 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:49:22,005 INFO L272 TraceCheckUtils]: 0: Hoare triple {2611#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:22,006 INFO L290 TraceCheckUtils]: 1: Hoare triple {2611#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2611#true} is VALID [2022-04-14 19:49:22,006 INFO L290 TraceCheckUtils]: 2: Hoare triple {2611#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:22,006 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2611#true} {2611#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:22,006 INFO L272 TraceCheckUtils]: 4: Hoare triple {2611#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:49:22,006 INFO L290 TraceCheckUtils]: 5: Hoare triple {2611#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2611#true} is VALID [2022-04-14 19:49:22,006 INFO L290 TraceCheckUtils]: 6: Hoare triple {2611#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2645#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:49:22,018 INFO L290 TraceCheckUtils]: 7: Hoare triple {2645#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2645#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:49:22,019 INFO L290 TraceCheckUtils]: 8: Hoare triple {2645#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2652#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:49:22,019 INFO L290 TraceCheckUtils]: 9: Hoare triple {2652#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2656#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:49:22,021 INFO L290 TraceCheckUtils]: 10: Hoare triple {2656#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2660#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:49:22,021 INFO L290 TraceCheckUtils]: 11: Hoare triple {2660#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2660#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:49:22,022 INFO L290 TraceCheckUtils]: 12: Hoare triple {2660#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2660#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:49:22,023 INFO L290 TraceCheckUtils]: 13: Hoare triple {2660#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2670#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:49:22,024 INFO L290 TraceCheckUtils]: 14: Hoare triple {2670#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2670#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:49:22,024 INFO L272 TraceCheckUtils]: 15: Hoare triple {2670#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:49:22,025 INFO L290 TraceCheckUtils]: 16: Hoare triple {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2681#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:49:22,025 INFO L290 TraceCheckUtils]: 17: Hoare triple {2681#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2612#false} is VALID [2022-04-14 19:49:22,025 INFO L290 TraceCheckUtils]: 18: Hoare triple {2612#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2612#false} is VALID [2022-04-14 19:49:22,025 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:49:22,025 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-14 19:54:15,765 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~y~0_56 Int) (aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (let ((.cse0 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (not .cse0) (forall ((aux_div_main_~y~0_26 Int)) (or (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_56)) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_56) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (or .cse0 (forall ((aux_div_main_~y~0_26 Int)) (not (= v_main_~y~0_56 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))))))) (let ((.cse1 (< 0 (mod c_main_~z~0 4294967296)))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) .cse1) (or (not .cse1) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (let ((.cse2 (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70))) (or (<= (+ (* v_main_~y~0_56 4294967296) c_main_~z~0) .cse2) (exists ((v_it_5 Int)) (and (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 aux_mod_v_main_~y~0_54_31 c_main_~z~0 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_55_70 0) (<= .cse2 (+ (* v_main_~y~0_56 4294967295) aux_mod_v_main_~y~0_54_31 c_main_~z~0 (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* v_main_~y~0_56 4294967296) c_main_~z~0)) (<= 1 v_it_5))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))) (or (< 0 (mod (+ (* v_main_~y~0_56 4294967295) aux_mod_v_main_~y~0_54_31 c_main_~z~0) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))) (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31))) is different from false [2022-04-14 19:54:17,526 INFO L290 TraceCheckUtils]: 18: Hoare triple {2612#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2612#false} is VALID [2022-04-14 19:54:17,527 INFO L290 TraceCheckUtils]: 17: Hoare triple {2681#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2612#false} is VALID [2022-04-14 19:54:17,527 INFO L290 TraceCheckUtils]: 16: Hoare triple {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2681#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:54:17,528 INFO L272 TraceCheckUtils]: 15: Hoare triple {2670#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2677#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:54:17,528 INFO L290 TraceCheckUtils]: 14: Hoare triple {2670#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2670#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:54:18,456 INFO L290 TraceCheckUtils]: 13: Hoare triple {2703#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))) (not (< 0 (mod main_~z~0 4294967296))))) (<= aux_mod_v_main_~y~0_54_31 0) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2670#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:54:20,475 WARN L290 TraceCheckUtils]: 12: Hoare triple {2707#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2703#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))) (not (< 0 (mod main_~z~0 4294967296))))) (<= aux_mod_v_main_~y~0_54_31 0) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-14 19:54:22,545 WARN L290 TraceCheckUtils]: 11: Hoare triple {2707#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2707#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-14 19:54:24,565 WARN L290 TraceCheckUtils]: 10: Hoare triple {2714#(forall ((v_main_~y~0_56 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (and (or (not (< main_~y~0 v_main_~y~0_56)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_56) (<= 1 v_it_4)))) (or (not (= v_main_~y~0_56 main_~y~0)) (< 0 (mod main_~x~0 4294967296)))) (<= aux_mod_v_main_~y~0_54_31 0) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2707#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-14 19:54:26,668 WARN L290 TraceCheckUtils]: 9: Hoare triple {2718#(forall ((v_main_~y~0_56 Int) (aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (forall ((aux_div_main_~y~0_26 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_56) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_56)))) (not (< 0 (mod main_~x~0 4294967296)))) (or (forall ((aux_div_main_~y~0_26 Int)) (not (= v_main_~y~0_56 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))))) (< 0 (mod main_~x~0 4294967296)))) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2714#(forall ((v_main_~y~0_56 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (and (or (not (< main_~y~0 v_main_~y~0_56)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_56) (<= 1 v_it_4)))) (or (not (= v_main_~y~0_56 main_~y~0)) (< 0 (mod main_~x~0 4294967296)))) (<= aux_mod_v_main_~y~0_54_31 0) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-14 19:54:26,703 INFO L290 TraceCheckUtils]: 8: Hoare triple {2645#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2718#(forall ((v_main_~y~0_56 Int) (aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (forall ((aux_div_main_~y~0_26 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_56) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_56)))) (not (< 0 (mod main_~x~0 4294967296)))) (or (forall ((aux_div_main_~y~0_26 Int)) (not (= v_main_~y~0_56 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))))) (< 0 (mod main_~x~0 4294967296)))) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is VALID [2022-04-14 19:54:26,703 INFO L290 TraceCheckUtils]: 7: Hoare triple {2645#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2645#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:54:26,703 INFO L290 TraceCheckUtils]: 6: Hoare triple {2611#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2645#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:54:26,703 INFO L290 TraceCheckUtils]: 5: Hoare triple {2611#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2611#true} is VALID [2022-04-14 19:54:26,704 INFO L272 TraceCheckUtils]: 4: Hoare triple {2611#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:54:26,704 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2611#true} {2611#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:54:26,704 INFO L290 TraceCheckUtils]: 2: Hoare triple {2611#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:54:26,704 INFO L290 TraceCheckUtils]: 1: Hoare triple {2611#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2611#true} is VALID [2022-04-14 19:54:26,704 INFO L272 TraceCheckUtils]: 0: Hoare triple {2611#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2611#true} is VALID [2022-04-14 19:54:26,704 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-14 19:54:26,704 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [435333114] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-14 19:54:26,704 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-14 19:54:26,705 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 10] total 21 [2022-04-14 19:54:26,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804841289] [2022-04-14 19:54:26,705 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-14 19:54:26,705 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-14 19:54:26,705 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-14 19:54:26,705 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:36,304 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 36 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-14 19:54:36,304 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2022-04-14 19:54:36,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-14 19:54:36,305 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2022-04-14 19:54:36,305 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=291, Unknown=16, NotChecked=36, Total=420 [2022-04-14 19:54:36,305 INFO L87 Difference]: Start difference. First operand 40 states and 61 transitions. Second operand has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:54:59,843 INFO L93 Difference]: Finished difference Result 57 states and 82 transitions. [2022-04-14 19:54:59,843 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-04-14 19:54:59,843 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-14 19:54:59,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-14 19:54:59,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 56 transitions. [2022-04-14 19:54:59,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 56 transitions. [2022-04-14 19:54:59,846 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 18 states and 56 transitions. [2022-04-14 19:54:59,942 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-14 19:54:59,942 INFO L225 Difference]: With dead ends: 57 [2022-04-14 19:54:59,942 INFO L226 Difference]: Without dead ends: 47 [2022-04-14 19:54:59,943 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 28 SyntacticMatches, 5 SemanticMatches, 32 ConstructedPredicates, 1 IntricatePredicates, 1 DeprecatedPredicates, 284 ImplicationChecksByTransitivity, 70.6s TimeCoverageRelationStatistics Valid=202, Invalid=835, Unknown=23, NotChecked=62, Total=1122 [2022-04-14 19:54:59,943 INFO L913 BasicCegarLoop]: 14 mSDtfsCounter, 31 mSDsluCounter, 86 mSDsCounter, 0 mSdLazyCounter, 121 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 100 SdHoareTripleChecker+Invalid, 202 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 121 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 61 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-04-14 19:54:59,943 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [31 Valid, 100 Invalid, 202 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 121 Invalid, 0 Unknown, 61 Unchecked, 0.5s Time] [2022-04-14 19:54:59,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2022-04-14 19:54:59,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 40. [2022-04-14 19:54:59,946 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-14 19:54:59,947 INFO L82 GeneralOperation]: Start isEquivalent. First operand 47 states. Second operand has 40 states, 35 states have (on average 1.6) internal successors, (56), 35 states have internal predecessors, (56), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,947 INFO L74 IsIncluded]: Start isIncluded. First operand 47 states. Second operand has 40 states, 35 states have (on average 1.6) internal successors, (56), 35 states have internal predecessors, (56), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,947 INFO L87 Difference]: Start difference. First operand 47 states. Second operand has 40 states, 35 states have (on average 1.6) internal successors, (56), 35 states have internal predecessors, (56), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:54:59,948 INFO L93 Difference]: Finished difference Result 47 states and 69 transitions. [2022-04-14 19:54:59,948 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 69 transitions. [2022-04-14 19:54:59,948 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:54:59,948 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:54:59,948 INFO L74 IsIncluded]: Start isIncluded. First operand has 40 states, 35 states have (on average 1.6) internal successors, (56), 35 states have internal predecessors, (56), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 47 states. [2022-04-14 19:54:59,948 INFO L87 Difference]: Start difference. First operand has 40 states, 35 states have (on average 1.6) internal successors, (56), 35 states have internal predecessors, (56), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 47 states. [2022-04-14 19:54:59,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-14 19:54:59,949 INFO L93 Difference]: Finished difference Result 47 states and 69 transitions. [2022-04-14 19:54:59,949 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 69 transitions. [2022-04-14 19:54:59,949 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-14 19:54:59,950 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-14 19:54:59,950 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-14 19:54:59,950 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-14 19:54:59,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 35 states have (on average 1.6) internal successors, (56), 35 states have internal predecessors, (56), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 60 transitions. [2022-04-14 19:54:59,950 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 60 transitions. Word has length 19 [2022-04-14 19:54:59,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-14 19:54:59,951 INFO L478 AbstractCegarLoop]: Abstraction has 40 states and 60 transitions. [2022-04-14 19:54:59,951 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-14 19:54:59,951 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 60 transitions. [2022-04-14 19:54:59,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-14 19:54:59,951 INFO L491 BasicCegarLoop]: Found error trace [2022-04-14 19:54:59,951 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-14 19:54:59,969 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-04-14 19:55:00,151 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:55:00,152 INFO L403 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-14 19:55:00,152 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-14 19:55:00,152 INFO L85 PathProgramCache]: Analyzing trace with hash 318804101, now seen corresponding path program 3 times [2022-04-14 19:55:00,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-14 19:55:00,152 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652244736] [2022-04-14 19:55:00,152 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-14 19:55:00,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-14 19:55:00,161 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:55:00,162 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_10 (* (- 4294967296) (div (+ .cse0 main_~x~0_10) 4294967296)))) 0)) [2022-04-14 19:55:00,163 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:55:00,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:55:00,173 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-14 19:55:00,176 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.4))) (+ .cse0 main_~x~0_10 (* (- 4294967296) (div (+ .cse0 main_~x~0_10) 4294967296)))) 0)) [2022-04-14 19:55:00,177 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-14 19:55:00,772 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-14 19:55:00,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:55:00,776 INFO L290 TraceCheckUtils]: 0: Hoare triple {2979#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2967#true} is VALID [2022-04-14 19:55:00,776 INFO L290 TraceCheckUtils]: 1: Hoare triple {2967#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:00,776 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2967#true} {2967#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:00,776 INFO L272 TraceCheckUtils]: 0: Hoare triple {2967#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2979#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-14 19:55:00,776 INFO L290 TraceCheckUtils]: 1: Hoare triple {2979#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2967#true} is VALID [2022-04-14 19:55:00,776 INFO L290 TraceCheckUtils]: 2: Hoare triple {2967#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:00,777 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2967#true} {2967#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:00,777 INFO L272 TraceCheckUtils]: 4: Hoare triple {2967#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:00,777 INFO L290 TraceCheckUtils]: 5: Hoare triple {2967#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2972#(= main_~y~0 0)} is VALID [2022-04-14 19:55:00,778 INFO L290 TraceCheckUtils]: 6: Hoare triple {2972#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2973#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:55:00,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {2973#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2973#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-14 19:55:00,779 INFO L290 TraceCheckUtils]: 8: Hoare triple {2973#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2974#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:55:00,779 INFO L290 TraceCheckUtils]: 9: Hoare triple {2974#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2974#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:55:00,781 INFO L290 TraceCheckUtils]: 10: Hoare triple {2974#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2974#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-14 19:55:00,783 INFO L290 TraceCheckUtils]: 11: Hoare triple {2974#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2975#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-14 19:55:00,783 INFO L290 TraceCheckUtils]: 12: Hoare triple {2975#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2975#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-14 19:55:00,785 INFO L290 TraceCheckUtils]: 13: Hoare triple {2975#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2976#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:55:00,785 INFO L290 TraceCheckUtils]: 14: Hoare triple {2976#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2976#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-14 19:55:00,786 INFO L272 TraceCheckUtils]: 15: Hoare triple {2976#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2977#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-14 19:55:00,787 INFO L290 TraceCheckUtils]: 16: Hoare triple {2977#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2978#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-14 19:55:00,787 INFO L290 TraceCheckUtils]: 17: Hoare triple {2978#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2968#false} is VALID [2022-04-14 19:55:00,787 INFO L290 TraceCheckUtils]: 18: Hoare triple {2968#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2968#false} is VALID [2022-04-14 19:55:00,787 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:55:00,787 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-14 19:55:00,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652244736] [2022-04-14 19:55:00,787 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652244736] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-14 19:55:00,787 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1829184285] [2022-04-14 19:55:00,787 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-14 19:55:00,788 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-14 19:55:00,788 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-14 19:55:00,788 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-14 19:55:00,789 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-04-14 19:55:00,838 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2022-04-14 19:55:00,838 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-14 19:55:00,838 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-14 19:55:00,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-14 19:55:00,850 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-14 19:55:02,597 INFO L272 TraceCheckUtils]: 0: Hoare triple {2967#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:02,598 INFO L290 TraceCheckUtils]: 1: Hoare triple {2967#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2967#true} is VALID [2022-04-14 19:55:02,598 INFO L290 TraceCheckUtils]: 2: Hoare triple {2967#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:02,598 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2967#true} {2967#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:02,598 INFO L272 TraceCheckUtils]: 4: Hoare triple {2967#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2967#true} is VALID [2022-04-14 19:55:02,598 INFO L290 TraceCheckUtils]: 5: Hoare triple {2967#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2967#true} is VALID [2022-04-14 19:55:02,598 INFO L290 TraceCheckUtils]: 6: Hoare triple {2967#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {3001#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:55:02,599 INFO L290 TraceCheckUtils]: 7: Hoare triple {3001#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3001#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-14 19:55:02,599 INFO L290 TraceCheckUtils]: 8: Hoare triple {3001#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3008#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:55:02,599 INFO L290 TraceCheckUtils]: 9: Hoare triple {3008#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3012#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:55:02,601 INFO L290 TraceCheckUtils]: 10: Hoare triple {3012#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {3012#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-14 19:55:02,602 INFO L290 TraceCheckUtils]: 11: Hoare triple {3012#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {3019#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:55:02,603 INFO L290 TraceCheckUtils]: 12: Hoare triple {3019#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3019#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-14 19:55:02,604 INFO L290 TraceCheckUtils]: 13: Hoare triple {3019#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {3026#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:55:02,604 INFO L290 TraceCheckUtils]: 14: Hoare triple {3026#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3026#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-14 19:55:02,605 INFO L272 TraceCheckUtils]: 15: Hoare triple {3026#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {3033#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-14 19:55:02,605 INFO L290 TraceCheckUtils]: 16: Hoare triple {3033#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3037#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-14 19:55:02,605 INFO L290 TraceCheckUtils]: 17: Hoare triple {3037#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2968#false} is VALID [2022-04-14 19:55:02,605 INFO L290 TraceCheckUtils]: 18: Hoare triple {2968#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2968#false} is VALID [2022-04-14 19:55:02,605 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-14 19:55:02,605 INFO L328 TraceCheckSpWp]: Computing backward predicates...