/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-e106359-m [2022-04-15 01:30:06,343 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-15 01:30:06,367 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-15 01:30:06,394 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-15 01:30:06,412 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-15 01:30:06,413 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-15 01:30:06,414 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-15 01:30:06,415 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-15 01:30:06,415 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-15 01:30:06,416 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-15 01:30:06,419 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-15 01:30:06,423 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-15 01:30:06,424 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-15 01:30:06,425 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-15 01:30:06,425 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-15 01:30:06,426 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-15 01:30:06,427 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-15 01:30:06,432 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-15 01:30:06,437 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-15 01:30:06,438 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-15 01:30:06,439 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-15 01:30:06,440 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-15 01:30:06,460 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-15 01:30:06,460 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-15 01:30:06,461 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-15 01:30:06,461 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-15 01:30:06,462 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-15 01:30:06,462 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-15 01:30:06,462 INFO L138 SettingsManager]: * Use SBE=true [2022-04-15 01:30:06,462 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-15 01:30:06,462 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-15 01:30:06,463 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-15 01:30:06,463 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-15 01:30:06,464 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-15 01:30:06,464 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-15 01:30:06,465 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-15 01:30:06,465 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-15 01:30:06,466 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-15 01:30:06,466 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-15 01:30:06,646 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-15 01:30:06,670 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-15 01:30:06,672 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-15 01:30:06,673 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-15 01:30:06,687 INFO L275 PluginConnector]: CDTParser initialized [2022-04-15 01:30:06,688 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c [2022-04-15 01:30:06,730 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ebc4a022e/7fb90a686a82458582e969c317420861/FLAG578c1b78c [2022-04-15 01:30:07,079 INFO L306 CDTParser]: Found 1 translation units. [2022-04-15 01:30:07,079 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c [2022-04-15 01:30:07,089 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ebc4a022e/7fb90a686a82458582e969c317420861/FLAG578c1b78c [2022-04-15 01:30:07,101 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ebc4a022e/7fb90a686a82458582e969c317420861 [2022-04-15 01:30:07,103 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-15 01:30:07,104 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-15 01:30:07,106 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-15 01:30:07,106 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-15 01:30:07,109 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-15 01:30:07,112 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,113 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@755c2339 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07, skipping insertion in model container [2022-04-15 01:30:07,114 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,118 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-15 01:30:07,127 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-15 01:30:07,276 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c[557,570] [2022-04-15 01:30:07,285 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c[613,626] [2022-04-15 01:30:07,292 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-15 01:30:07,309 INFO L203 MainTranslator]: Completed pre-run [2022-04-15 01:30:07,321 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c[557,570] [2022-04-15 01:30:07,323 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-invariants/linear-inequality-inv-a.c[613,626] [2022-04-15 01:30:07,323 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-15 01:30:07,339 INFO L208 MainTranslator]: Completed translation [2022-04-15 01:30:07,339 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07 WrapperNode [2022-04-15 01:30:07,339 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-15 01:30:07,340 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-15 01:30:07,340 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-15 01:30:07,340 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-15 01:30:07,349 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,349 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,354 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,354 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,359 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,363 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,367 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,373 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-15 01:30:07,374 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-15 01:30:07,374 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-15 01:30:07,374 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-15 01:30:07,375 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-15 01:30:07,388 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:07,403 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-15 01:30:07,418 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-15 01:30:07,429 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-15 01:30:07,430 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-15 01:30:07,430 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-15 01:30:07,430 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-15 01:30:07,430 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-15 01:30:07,431 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uchar [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-15 01:30:07,432 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-15 01:30:07,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-15 01:30:07,479 INFO L234 CfgBuilder]: Building ICFG [2022-04-15 01:30:07,480 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-15 01:30:07,569 INFO L275 CfgBuilder]: Performing block encoding [2022-04-15 01:30:07,575 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-15 01:30:07,575 INFO L299 CfgBuilder]: Removed 1 assume(true) statements. [2022-04-15 01:30:07,576 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.04 01:30:07 BoogieIcfgContainer [2022-04-15 01:30:07,576 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-15 01:30:07,577 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-15 01:30:07,577 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-15 01:30:07,578 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-15 01:30:07,580 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.04 01:30:07" (1/1) ... [2022-04-15 01:30:07,581 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-15 01:30:07,601 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 15.04 01:30:07 BasicIcfg [2022-04-15 01:30:07,602 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-15 01:30:07,603 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-15 01:30:07,603 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-15 01:30:07,606 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-15 01:30:07,606 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 15.04 01:30:07" (1/4) ... [2022-04-15 01:30:07,607 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20c43c61 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.04 01:30:07, skipping insertion in model container [2022-04-15 01:30:07,607 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 15.04 01:30:07" (2/4) ... [2022-04-15 01:30:07,607 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20c43c61 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 15.04 01:30:07, skipping insertion in model container [2022-04-15 01:30:07,607 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 15.04 01:30:07" (3/4) ... [2022-04-15 01:30:07,608 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@20c43c61 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 15.04 01:30:07, skipping insertion in model container [2022-04-15 01:30:07,608 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 15.04 01:30:07" (4/4) ... [2022-04-15 01:30:07,609 INFO L111 eAbstractionObserver]: Analyzing ICFG linear-inequality-inv-a.cqvasr [2022-04-15 01:30:07,613 INFO L202 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-15 01:30:07,613 INFO L161 ceAbstractionStarter]: Applying trace abstraction to program that has 2 error locations. [2022-04-15 01:30:07,649 INFO L339 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-15 01:30:07,657 INFO L340 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP [2022-04-15 01:30:07,657 INFO L341 AbstractCegarLoop]: Starting to check reachability of 2 error locations. [2022-04-15 01:30:07,672 INFO L276 IsEmpty]: Start isEmpty. Operand has 18 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 13 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-15 01:30:07,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2022-04-15 01:30:07,674 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:07,675 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:07,675 INFO L403 AbstractCegarLoop]: === Iteration 1 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:07,679 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:07,679 INFO L85 PathProgramCache]: Analyzing trace with hash 733275225, now seen corresponding path program 1 times [2022-04-15 01:30:07,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:07,686 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [499368107] [2022-04-15 01:30:07,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:07,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:07,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:07,842 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:07,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:07,870 INFO L290 TraceCheckUtils]: 0: Hoare triple {26#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {21#true} is VALID [2022-04-15 01:30:07,870 INFO L290 TraceCheckUtils]: 1: Hoare triple {21#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-15 01:30:07,870 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21#true} {21#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-15 01:30:07,872 INFO L272 TraceCheckUtils]: 0: Hoare triple {21#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:07,872 INFO L290 TraceCheckUtils]: 1: Hoare triple {26#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {21#true} is VALID [2022-04-15 01:30:07,872 INFO L290 TraceCheckUtils]: 2: Hoare triple {21#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-15 01:30:07,872 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21#true} {21#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-15 01:30:07,872 INFO L272 TraceCheckUtils]: 4: Hoare triple {21#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-15 01:30:07,873 INFO L290 TraceCheckUtils]: 5: Hoare triple {21#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {21#true} is VALID [2022-04-15 01:30:07,873 INFO L290 TraceCheckUtils]: 6: Hoare triple {21#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {21#true} is VALID [2022-04-15 01:30:07,873 INFO L290 TraceCheckUtils]: 7: Hoare triple {21#true} [50] L12-2-->L12-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {22#false} is VALID [2022-04-15 01:30:07,874 INFO L290 TraceCheckUtils]: 8: Hoare triple {22#false} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {22#false} is VALID [2022-04-15 01:30:07,874 INFO L290 TraceCheckUtils]: 9: Hoare triple {22#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#false} is VALID [2022-04-15 01:30:07,874 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:07,874 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:07,875 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [499368107] [2022-04-15 01:30:07,875 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [499368107] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-15 01:30:07,875 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-15 01:30:07,875 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-15 01:30:07,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679399560] [2022-04-15 01:30:07,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-15 01:30:07,891 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 10 [2022-04-15 01:30:07,892 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:07,895 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:07,921 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 10 edges. 10 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:07,921 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-15 01:30:07,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:07,936 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-15 01:30:07,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-15 01:30:07,939 INFO L87 Difference]: Start difference. First operand has 18 states, 11 states have (on average 1.6363636363636365) internal successors, (18), 13 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:07,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:07,986 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-15 01:30:07,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-15 01:30:07,986 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 10 [2022-04-15 01:30:07,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:07,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:07,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 33 transitions. [2022-04-15 01:30:07,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 33 transitions. [2022-04-15 01:30:08,004 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 33 transitions. [2022-04-15 01:30:08,058 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 33 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:08,065 INFO L225 Difference]: With dead ends: 28 [2022-04-15 01:30:08,066 INFO L226 Difference]: Without dead ends: 14 [2022-04-15 01:30:08,069 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-15 01:30:08,073 INFO L913 BasicCegarLoop]: 19 mSDtfsCounter, 12 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 2 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 12 SdHoareTripleChecker+Valid, 22 SdHoareTripleChecker+Invalid, 3 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 2 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:08,075 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [12 Valid, 22 Invalid, 3 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 2 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-15 01:30:08,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2022-04-15 01:30:08,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2022-04-15 01:30:08,095 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:08,096 INFO L82 GeneralOperation]: Start isEquivalent. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 10 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,097 INFO L74 IsIncluded]: Start isIncluded. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 10 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,098 INFO L87 Difference]: Start difference. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 10 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:08,100 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2022-04-15 01:30:08,100 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-15 01:30:08,100 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:08,100 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:08,101 INFO L74 IsIncluded]: Start isIncluded. First operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 10 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 14 states. [2022-04-15 01:30:08,101 INFO L87 Difference]: Start difference. First operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 10 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 14 states. [2022-04-15 01:30:08,102 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:08,102 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2022-04-15 01:30:08,102 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-15 01:30:08,102 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:08,105 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:08,105 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:08,105 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:08,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 10 states have internal predecessors, (11), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2022-04-15 01:30:08,109 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 10 [2022-04-15 01:30:08,110 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:08,110 INFO L478 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2022-04-15 01:30:08,110 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,110 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-15 01:30:08,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2022-04-15 01:30:08,110 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:08,110 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:08,111 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-15 01:30:08,111 INFO L403 AbstractCegarLoop]: === Iteration 2 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:08,111 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:08,111 INFO L85 PathProgramCache]: Analyzing trace with hash 733276186, now seen corresponding path program 1 times [2022-04-15 01:30:08,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:08,112 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076898637] [2022-04-15 01:30:08,112 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:08,112 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:08,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:08,196 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:08,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:08,203 INFO L290 TraceCheckUtils]: 0: Hoare triple {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {109#true} is VALID [2022-04-15 01:30:08,203 INFO L290 TraceCheckUtils]: 1: Hoare triple {109#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {109#true} is VALID [2022-04-15 01:30:08,203 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {109#true} {109#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {109#true} is VALID [2022-04-15 01:30:08,204 INFO L272 TraceCheckUtils]: 0: Hoare triple {109#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:08,204 INFO L290 TraceCheckUtils]: 1: Hoare triple {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {109#true} is VALID [2022-04-15 01:30:08,204 INFO L290 TraceCheckUtils]: 2: Hoare triple {109#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {109#true} is VALID [2022-04-15 01:30:08,204 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {109#true} {109#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {109#true} is VALID [2022-04-15 01:30:08,205 INFO L272 TraceCheckUtils]: 4: Hoare triple {109#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {109#true} is VALID [2022-04-15 01:30:08,205 INFO L290 TraceCheckUtils]: 5: Hoare triple {109#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {109#true} is VALID [2022-04-15 01:30:08,206 INFO L290 TraceCheckUtils]: 6: Hoare triple {109#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {114#(and (= main_~i~0 0) (not (<= main_~n~0 (* 256 (div main_~n~0 256)))))} is VALID [2022-04-15 01:30:08,206 INFO L290 TraceCheckUtils]: 7: Hoare triple {114#(and (= main_~i~0 0) (not (<= main_~n~0 (* 256 (div main_~n~0 256)))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {110#false} is VALID [2022-04-15 01:30:08,206 INFO L290 TraceCheckUtils]: 8: Hoare triple {110#false} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {110#false} is VALID [2022-04-15 01:30:08,207 INFO L290 TraceCheckUtils]: 9: Hoare triple {110#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#false} is VALID [2022-04-15 01:30:08,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:08,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:08,207 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076898637] [2022-04-15 01:30:08,207 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076898637] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-15 01:30:08,207 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-15 01:30:08,207 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-15 01:30:08,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2044365754] [2022-04-15 01:30:08,208 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-15 01:30:08,208 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 10 [2022-04-15 01:30:08,208 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:08,209 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,217 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 10 edges. 10 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:08,217 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-15 01:30:08,217 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:08,217 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-15 01:30:08,218 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-15 01:30:08,218 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:08,280 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-15 01:30:08,280 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-15 01:30:08,281 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 10 [2022-04-15 01:30:08,281 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:08,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 21 transitions. [2022-04-15 01:30:08,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,291 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 21 transitions. [2022-04-15 01:30:08,292 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 21 transitions. [2022-04-15 01:30:08,319 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 21 edges. 21 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:08,320 INFO L225 Difference]: With dead ends: 21 [2022-04-15 01:30:08,320 INFO L226 Difference]: Without dead ends: 15 [2022-04-15 01:30:08,320 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-15 01:30:08,321 INFO L913 BasicCegarLoop]: 13 mSDtfsCounter, 9 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 10 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 20 SdHoareTripleChecker+Invalid, 12 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 10 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:08,321 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [9 Valid, 20 Invalid, 12 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 10 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-15 01:30:08,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2022-04-15 01:30:08,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2022-04-15 01:30:08,338 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:08,338 INFO L82 GeneralOperation]: Start isEquivalent. First operand 15 states. Second operand has 15 states, 10 states have (on average 1.2) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,338 INFO L74 IsIncluded]: Start isIncluded. First operand 15 states. Second operand has 15 states, 10 states have (on average 1.2) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,339 INFO L87 Difference]: Start difference. First operand 15 states. Second operand has 15 states, 10 states have (on average 1.2) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:08,339 INFO L93 Difference]: Finished difference Result 15 states and 15 transitions. [2022-04-15 01:30:08,340 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2022-04-15 01:30:08,340 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:08,340 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:08,340 INFO L74 IsIncluded]: Start isIncluded. First operand has 15 states, 10 states have (on average 1.2) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 15 states. [2022-04-15 01:30:08,340 INFO L87 Difference]: Start difference. First operand has 15 states, 10 states have (on average 1.2) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 15 states. [2022-04-15 01:30:08,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:08,341 INFO L93 Difference]: Finished difference Result 15 states and 15 transitions. [2022-04-15 01:30:08,341 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2022-04-15 01:30:08,342 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:08,342 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:08,342 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:08,342 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:08,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 10 states have (on average 1.2) internal successors, (12), 11 states have internal predecessors, (12), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2022-04-15 01:30:08,343 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 10 [2022-04-15 01:30:08,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:08,343 INFO L478 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2022-04-15 01:30:08,343 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 1 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:08,344 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2022-04-15 01:30:08,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-15 01:30:08,344 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:08,344 INFO L499 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:08,344 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-15 01:30:08,344 INFO L403 AbstractCegarLoop]: === Iteration 3 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:08,345 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:08,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1256753148, now seen corresponding path program 1 times [2022-04-15 01:30:08,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:08,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550848874] [2022-04-15 01:30:08,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:08,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:08,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:08,424 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:08,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:08,431 INFO L290 TraceCheckUtils]: 0: Hoare triple {205#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {198#true} is VALID [2022-04-15 01:30:08,431 INFO L290 TraceCheckUtils]: 1: Hoare triple {198#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,431 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {198#true} {198#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,432 INFO L272 TraceCheckUtils]: 0: Hoare triple {198#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {205#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:08,432 INFO L290 TraceCheckUtils]: 1: Hoare triple {205#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {198#true} is VALID [2022-04-15 01:30:08,432 INFO L290 TraceCheckUtils]: 2: Hoare triple {198#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,432 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {198#true} {198#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,433 INFO L272 TraceCheckUtils]: 4: Hoare triple {198#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,433 INFO L290 TraceCheckUtils]: 5: Hoare triple {198#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {198#true} is VALID [2022-04-15 01:30:08,433 INFO L290 TraceCheckUtils]: 6: Hoare triple {198#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {203#(= main_~s~0 0)} is VALID [2022-04-15 01:30:08,434 INFO L290 TraceCheckUtils]: 7: Hoare triple {203#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {204#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:30:08,435 INFO L290 TraceCheckUtils]: 8: Hoare triple {204#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {204#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:30:08,435 INFO L290 TraceCheckUtils]: 9: Hoare triple {204#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {199#false} is VALID [2022-04-15 01:30:08,436 INFO L290 TraceCheckUtils]: 10: Hoare triple {199#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#false} is VALID [2022-04-15 01:30:08,436 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:08,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:08,436 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550848874] [2022-04-15 01:30:08,436 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550848874] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:30:08,437 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [846968273] [2022-04-15 01:30:08,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:08,437 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:08,437 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:08,568 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:30:08,569 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-15 01:30:08,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:08,610 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-15 01:30:08,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:08,619 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:30:08,681 INFO L272 TraceCheckUtils]: 0: Hoare triple {198#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,681 INFO L290 TraceCheckUtils]: 1: Hoare triple {198#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {198#true} is VALID [2022-04-15 01:30:08,682 INFO L290 TraceCheckUtils]: 2: Hoare triple {198#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,682 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {198#true} {198#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,682 INFO L272 TraceCheckUtils]: 4: Hoare triple {198#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:08,682 INFO L290 TraceCheckUtils]: 5: Hoare triple {198#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {198#true} is VALID [2022-04-15 01:30:08,683 INFO L290 TraceCheckUtils]: 6: Hoare triple {198#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {203#(= main_~s~0 0)} is VALID [2022-04-15 01:30:08,683 INFO L290 TraceCheckUtils]: 7: Hoare triple {203#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {230#(= (+ main_~s~0 (* (- 1) (mod main_~v~0 256))) 0)} is VALID [2022-04-15 01:30:08,684 INFO L290 TraceCheckUtils]: 8: Hoare triple {230#(= (+ main_~s~0 (* (- 1) (mod main_~v~0 256))) 0)} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {230#(= (+ main_~s~0 (* (- 1) (mod main_~v~0 256))) 0)} is VALID [2022-04-15 01:30:08,685 INFO L290 TraceCheckUtils]: 9: Hoare triple {230#(= (+ main_~s~0 (* (- 1) (mod main_~v~0 256))) 0)} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {199#false} is VALID [2022-04-15 01:30:08,685 INFO L290 TraceCheckUtils]: 10: Hoare triple {199#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#false} is VALID [2022-04-15 01:30:08,685 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:08,685 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:30:09,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {199#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#false} is VALID [2022-04-15 01:30:09,153 INFO L290 TraceCheckUtils]: 9: Hoare triple {243#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {199#false} is VALID [2022-04-15 01:30:09,154 INFO L290 TraceCheckUtils]: 8: Hoare triple {243#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {243#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:30:09,166 INFO L290 TraceCheckUtils]: 7: Hoare triple {250#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {243#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:30:09,166 INFO L290 TraceCheckUtils]: 6: Hoare triple {198#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {250#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} is VALID [2022-04-15 01:30:09,167 INFO L290 TraceCheckUtils]: 5: Hoare triple {198#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {198#true} is VALID [2022-04-15 01:30:09,167 INFO L272 TraceCheckUtils]: 4: Hoare triple {198#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:09,167 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {198#true} {198#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:09,167 INFO L290 TraceCheckUtils]: 2: Hoare triple {198#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:09,168 INFO L290 TraceCheckUtils]: 1: Hoare triple {198#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {198#true} is VALID [2022-04-15 01:30:09,168 INFO L272 TraceCheckUtils]: 0: Hoare triple {198#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {198#true} is VALID [2022-04-15 01:30:09,168 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:09,169 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [846968273] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:30:09,169 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:30:09,169 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-15 01:30:09,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2142683806] [2022-04-15 01:30:09,169 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:30:09,170 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-15 01:30:09,170 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:09,170 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,191 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 20 edges. 20 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:09,191 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-15 01:30:09,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:09,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-15 01:30:09,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2022-04-15 01:30:09,193 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:09,403 INFO L93 Difference]: Finished difference Result 32 states and 34 transitions. [2022-04-15 01:30:09,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-15 01:30:09,403 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-15 01:30:09,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:09,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 34 transitions. [2022-04-15 01:30:09,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 34 transitions. [2022-04-15 01:30:09,406 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 34 transitions. [2022-04-15 01:30:09,450 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:09,451 INFO L225 Difference]: With dead ends: 32 [2022-04-15 01:30:09,451 INFO L226 Difference]: Without dead ends: 26 [2022-04-15 01:30:09,451 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 21 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=65, Invalid=117, Unknown=0, NotChecked=0, Total=182 [2022-04-15 01:30:09,452 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 42 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 42 SdHoareTripleChecker+Valid, 23 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:09,452 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [42 Valid, 23 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 30 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-15 01:30:09,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-04-15 01:30:09,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 19. [2022-04-15 01:30:09,460 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:09,460 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand has 19 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,460 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand has 19 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,461 INFO L87 Difference]: Start difference. First operand 26 states. Second operand has 19 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:09,462 INFO L93 Difference]: Finished difference Result 26 states and 26 transitions. [2022-04-15 01:30:09,462 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2022-04-15 01:30:09,462 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:09,462 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:09,462 INFO L74 IsIncluded]: Start isIncluded. First operand has 19 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 26 states. [2022-04-15 01:30:09,463 INFO L87 Difference]: Start difference. First operand has 19 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 26 states. [2022-04-15 01:30:09,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:09,464 INFO L93 Difference]: Finished difference Result 26 states and 26 transitions. [2022-04-15 01:30:09,464 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2022-04-15 01:30:09,464 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:09,464 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:09,464 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:09,464 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:09,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 15 states have internal predecessors, (18), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 21 transitions. [2022-04-15 01:30:09,465 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 21 transitions. Word has length 11 [2022-04-15 01:30:09,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:09,465 INFO L478 AbstractCegarLoop]: Abstraction has 19 states and 21 transitions. [2022-04-15 01:30:09,466 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:09,466 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 21 transitions. [2022-04-15 01:30:09,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-04-15 01:30:09,466 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:09,466 INFO L499 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:09,483 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-15 01:30:09,679 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:09,679 INFO L403 AbstractCegarLoop]: === Iteration 4 === Targeting mainErr1ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:09,680 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:09,680 INFO L85 PathProgramCache]: Analyzing trace with hash 854829856, now seen corresponding path program 1 times [2022-04-15 01:30:09,680 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:09,680 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [693306345] [2022-04-15 01:30:09,680 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:09,681 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:09,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:09,764 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:09,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:09,775 INFO L290 TraceCheckUtils]: 0: Hoare triple {415#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {407#true} is VALID [2022-04-15 01:30:09,775 INFO L290 TraceCheckUtils]: 1: Hoare triple {407#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:09,775 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {407#true} {407#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:09,776 INFO L272 TraceCheckUtils]: 0: Hoare triple {407#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {415#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:09,776 INFO L290 TraceCheckUtils]: 1: Hoare triple {415#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {407#true} is VALID [2022-04-15 01:30:09,776 INFO L290 TraceCheckUtils]: 2: Hoare triple {407#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:09,776 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {407#true} {407#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:09,776 INFO L272 TraceCheckUtils]: 4: Hoare triple {407#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:09,777 INFO L290 TraceCheckUtils]: 5: Hoare triple {407#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {407#true} is VALID [2022-04-15 01:30:09,777 INFO L290 TraceCheckUtils]: 6: Hoare triple {407#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {412#(= main_~s~0 0)} is VALID [2022-04-15 01:30:09,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {412#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {413#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:09,778 INFO L290 TraceCheckUtils]: 8: Hoare triple {413#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:09,779 INFO L290 TraceCheckUtils]: 9: Hoare triple {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:09,779 INFO L290 TraceCheckUtils]: 10: Hoare triple {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:09,780 INFO L290 TraceCheckUtils]: 11: Hoare triple {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {408#false} is VALID [2022-04-15 01:30:09,780 INFO L290 TraceCheckUtils]: 12: Hoare triple {408#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {408#false} is VALID [2022-04-15 01:30:09,780 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:09,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:09,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [693306345] [2022-04-15 01:30:09,781 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [693306345] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:30:09,781 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1625237091] [2022-04-15 01:30:09,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:09,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:09,781 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:09,782 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:30:09,783 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-15 01:30:09,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:09,822 INFO L263 TraceCheckSpWp]: Trace formula consists of 66 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-15 01:30:09,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:09,834 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:30:10,223 INFO L272 TraceCheckUtils]: 0: Hoare triple {407#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:10,224 INFO L290 TraceCheckUtils]: 1: Hoare triple {407#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {407#true} is VALID [2022-04-15 01:30:10,227 INFO L290 TraceCheckUtils]: 2: Hoare triple {407#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:10,227 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {407#true} {407#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:10,227 INFO L272 TraceCheckUtils]: 4: Hoare triple {407#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:10,227 INFO L290 TraceCheckUtils]: 5: Hoare triple {407#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {407#true} is VALID [2022-04-15 01:30:10,230 INFO L290 TraceCheckUtils]: 6: Hoare triple {407#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {412#(= main_~s~0 0)} is VALID [2022-04-15 01:30:10,231 INFO L290 TraceCheckUtils]: 7: Hoare triple {412#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {413#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:10,232 INFO L290 TraceCheckUtils]: 8: Hoare triple {413#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:10,232 INFO L290 TraceCheckUtils]: 9: Hoare triple {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:10,234 INFO L290 TraceCheckUtils]: 10: Hoare triple {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:10,235 INFO L290 TraceCheckUtils]: 11: Hoare triple {414#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {408#false} is VALID [2022-04-15 01:30:10,235 INFO L290 TraceCheckUtils]: 12: Hoare triple {408#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {408#false} is VALID [2022-04-15 01:30:10,235 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:10,235 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:30:11,577 INFO L290 TraceCheckUtils]: 12: Hoare triple {408#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {408#false} is VALID [2022-04-15 01:30:11,577 INFO L290 TraceCheckUtils]: 11: Hoare triple {458#(not (< 65025 (mod main_~s~0 4294967296)))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {408#false} is VALID [2022-04-15 01:30:11,577 INFO L290 TraceCheckUtils]: 10: Hoare triple {458#(not (< 65025 (mod main_~s~0 4294967296)))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {458#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:30:11,578 INFO L290 TraceCheckUtils]: 9: Hoare triple {458#(not (< 65025 (mod main_~s~0 4294967296)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {458#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:30:11,581 INFO L290 TraceCheckUtils]: 8: Hoare triple {468#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {458#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:30:11,591 INFO L290 TraceCheckUtils]: 7: Hoare triple {472#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {468#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} is VALID [2022-04-15 01:30:11,591 INFO L290 TraceCheckUtils]: 6: Hoare triple {407#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {472#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} is VALID [2022-04-15 01:30:11,592 INFO L290 TraceCheckUtils]: 5: Hoare triple {407#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {407#true} is VALID [2022-04-15 01:30:11,592 INFO L272 TraceCheckUtils]: 4: Hoare triple {407#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:11,592 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {407#true} {407#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:11,592 INFO L290 TraceCheckUtils]: 2: Hoare triple {407#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:11,592 INFO L290 TraceCheckUtils]: 1: Hoare triple {407#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {407#true} is VALID [2022-04-15 01:30:11,592 INFO L272 TraceCheckUtils]: 0: Hoare triple {407#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {407#true} is VALID [2022-04-15 01:30:11,593 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:11,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1625237091] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:30:11,593 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:30:11,593 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 9 [2022-04-15 01:30:11,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154373652] [2022-04-15 01:30:11,593 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:30:11,594 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 13 [2022-04-15 01:30:11,594 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:11,594 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,619 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 21 edges. 21 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:11,620 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 9 states [2022-04-15 01:30:11,620 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:11,620 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2022-04-15 01:30:11,620 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2022-04-15 01:30:11,621 INFO L87 Difference]: Start difference. First operand 19 states and 21 transitions. Second operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:11,816 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-15 01:30:11,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-15 01:30:11,817 INFO L78 Accepts]: Start accepts. Automaton has has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 13 [2022-04-15 01:30:11,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:11,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 35 transitions. [2022-04-15 01:30:11,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 35 transitions. [2022-04-15 01:30:11,819 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 35 transitions. [2022-04-15 01:30:11,860 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:11,864 INFO L225 Difference]: With dead ends: 30 [2022-04-15 01:30:11,864 INFO L226 Difference]: Without dead ends: 22 [2022-04-15 01:30:11,864 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 23 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2022-04-15 01:30:11,865 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 29 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 27 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 29 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 44 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 27 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:11,865 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [29 Valid, 18 Invalid, 44 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 27 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-15 01:30:11,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2022-04-15 01:30:11,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2022-04-15 01:30:11,890 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:11,892 INFO L82 GeneralOperation]: Start isEquivalent. First operand 22 states. Second operand has 21 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,892 INFO L74 IsIncluded]: Start isIncluded. First operand 22 states. Second operand has 21 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,892 INFO L87 Difference]: Start difference. First operand 22 states. Second operand has 21 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:11,895 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2022-04-15 01:30:11,895 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 24 transitions. [2022-04-15 01:30:11,895 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:11,896 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:11,896 INFO L74 IsIncluded]: Start isIncluded. First operand has 21 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-15 01:30:11,896 INFO L87 Difference]: Start difference. First operand has 21 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-15 01:30:11,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:11,897 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2022-04-15 01:30:11,897 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 24 transitions. [2022-04-15 01:30:11,897 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:11,897 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:11,897 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:11,897 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:11,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 16 states have (on average 1.25) internal successors, (20), 17 states have internal predecessors, (20), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 23 transitions. [2022-04-15 01:30:11,898 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 23 transitions. Word has length 13 [2022-04-15 01:30:11,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:11,899 INFO L478 AbstractCegarLoop]: Abstraction has 21 states and 23 transitions. [2022-04-15 01:30:11,899 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 9 states, 9 states have (on average 1.8888888888888888) internal successors, (17), 8 states have internal predecessors, (17), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:11,899 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 23 transitions. [2022-04-15 01:30:11,899 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-04-15 01:30:11,899 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:11,899 INFO L499 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:11,919 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-15 01:30:12,119 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-15 01:30:12,120 INFO L403 AbstractCegarLoop]: === Iteration 5 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:12,120 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:12,120 INFO L85 PathProgramCache]: Analyzing trace with hash 730779802, now seen corresponding path program 2 times [2022-04-15 01:30:12,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:12,120 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1997864833] [2022-04-15 01:30:12,120 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:12,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:12,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:12,222 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:12,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:12,227 INFO L290 TraceCheckUtils]: 0: Hoare triple {635#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {625#true} is VALID [2022-04-15 01:30:12,228 INFO L290 TraceCheckUtils]: 1: Hoare triple {625#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:12,228 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {625#true} {625#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:12,228 INFO L272 TraceCheckUtils]: 0: Hoare triple {625#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {635#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:12,228 INFO L290 TraceCheckUtils]: 1: Hoare triple {635#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {625#true} is VALID [2022-04-15 01:30:12,229 INFO L290 TraceCheckUtils]: 2: Hoare triple {625#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:12,229 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {625#true} {625#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:12,229 INFO L272 TraceCheckUtils]: 4: Hoare triple {625#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:12,229 INFO L290 TraceCheckUtils]: 5: Hoare triple {625#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {625#true} is VALID [2022-04-15 01:30:12,229 INFO L290 TraceCheckUtils]: 6: Hoare triple {625#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {630#(= main_~s~0 0)} is VALID [2022-04-15 01:30:12,230 INFO L290 TraceCheckUtils]: 7: Hoare triple {630#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {631#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:12,231 INFO L290 TraceCheckUtils]: 8: Hoare triple {631#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {632#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:12,232 INFO L290 TraceCheckUtils]: 9: Hoare triple {632#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {633#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:12,232 INFO L290 TraceCheckUtils]: 10: Hoare triple {633#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {634#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:30:12,233 INFO L290 TraceCheckUtils]: 11: Hoare triple {634#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {634#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:30:12,233 INFO L290 TraceCheckUtils]: 12: Hoare triple {634#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {626#false} is VALID [2022-04-15 01:30:12,234 INFO L290 TraceCheckUtils]: 13: Hoare triple {626#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {626#false} is VALID [2022-04-15 01:30:12,234 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:12,234 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:12,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1997864833] [2022-04-15 01:30:12,234 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1997864833] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:30:12,234 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [944887572] [2022-04-15 01:30:12,235 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-15 01:30:12,235 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:12,235 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:12,243 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:30:12,244 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-15 01:30:12,296 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-15 01:30:12,297 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-15 01:30:12,297 INFO L263 TraceCheckSpWp]: Trace formula consists of 79 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-15 01:30:12,304 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:12,305 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:30:13,438 INFO L272 TraceCheckUtils]: 0: Hoare triple {625#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:13,438 INFO L290 TraceCheckUtils]: 1: Hoare triple {625#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {625#true} is VALID [2022-04-15 01:30:13,438 INFO L290 TraceCheckUtils]: 2: Hoare triple {625#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:13,438 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {625#true} {625#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:13,438 INFO L272 TraceCheckUtils]: 4: Hoare triple {625#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:13,439 INFO L290 TraceCheckUtils]: 5: Hoare triple {625#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {625#true} is VALID [2022-04-15 01:30:13,440 INFO L290 TraceCheckUtils]: 6: Hoare triple {625#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {630#(= main_~s~0 0)} is VALID [2022-04-15 01:30:13,441 INFO L290 TraceCheckUtils]: 7: Hoare triple {630#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {631#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:13,441 INFO L290 TraceCheckUtils]: 8: Hoare triple {631#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {632#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:13,442 INFO L290 TraceCheckUtils]: 9: Hoare triple {632#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {633#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:13,443 INFO L290 TraceCheckUtils]: 10: Hoare triple {633#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {669#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 765 (mod main_~v~0 256))))} is VALID [2022-04-15 01:30:13,443 INFO L290 TraceCheckUtils]: 11: Hoare triple {669#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 765 (mod main_~v~0 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {669#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 765 (mod main_~v~0 256))))} is VALID [2022-04-15 01:30:13,444 INFO L290 TraceCheckUtils]: 12: Hoare triple {669#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 765 (mod main_~v~0 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {626#false} is VALID [2022-04-15 01:30:13,444 INFO L290 TraceCheckUtils]: 13: Hoare triple {626#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {626#false} is VALID [2022-04-15 01:30:13,444 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:13,444 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:30:17,296 INFO L290 TraceCheckUtils]: 13: Hoare triple {626#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {626#false} is VALID [2022-04-15 01:30:17,296 INFO L290 TraceCheckUtils]: 12: Hoare triple {682#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {626#false} is VALID [2022-04-15 01:30:17,297 INFO L290 TraceCheckUtils]: 11: Hoare triple {682#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {682#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:30:17,298 INFO L290 TraceCheckUtils]: 10: Hoare triple {689#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {682#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:30:17,303 INFO L290 TraceCheckUtils]: 9: Hoare triple {693#(<= (div (+ (- 4294967807) (* (- 1) main_~s~0)) (- 4294967296)) (+ 3 (div (+ main_~s~0 (- 4294967296)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {689#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} is VALID [2022-04-15 01:30:17,310 INFO L290 TraceCheckUtils]: 8: Hoare triple {697#(<= (div (+ (- 8589935358) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ (- 8589934592) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {693#(<= (div (+ (- 4294967807) (* (- 1) main_~s~0)) (- 4294967296)) (+ 3 (div (+ main_~s~0 (- 4294967296)) 4294967296)))} is VALID [2022-04-15 01:30:17,312 INFO L290 TraceCheckUtils]: 7: Hoare triple {701#(<= (div (+ (- 12884902909) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {697#(<= (div (+ (- 8589935358) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ (- 8589934592) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:30:17,313 INFO L290 TraceCheckUtils]: 6: Hoare triple {625#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {701#(<= (div (+ (- 12884902909) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} is VALID [2022-04-15 01:30:17,313 INFO L290 TraceCheckUtils]: 5: Hoare triple {625#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {625#true} is VALID [2022-04-15 01:30:17,313 INFO L272 TraceCheckUtils]: 4: Hoare triple {625#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:17,313 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {625#true} {625#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:17,313 INFO L290 TraceCheckUtils]: 2: Hoare triple {625#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:17,314 INFO L290 TraceCheckUtils]: 1: Hoare triple {625#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {625#true} is VALID [2022-04-15 01:30:17,314 INFO L272 TraceCheckUtils]: 0: Hoare triple {625#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {625#true} is VALID [2022-04-15 01:30:17,314 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:17,314 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [944887572] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:30:17,314 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:30:17,314 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-15 01:30:17,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1759935063] [2022-04-15 01:30:17,314 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:30:17,315 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-15 01:30:17,315 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:17,315 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:17,346 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:17,347 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-15 01:30:17,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:17,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-15 01:30:17,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2022-04-15 01:30:17,348 INFO L87 Difference]: Start difference. First operand 21 states and 23 transitions. Second operand has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:17,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:17,958 INFO L93 Difference]: Finished difference Result 44 states and 49 transitions. [2022-04-15 01:30:17,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-04-15 01:30:17,959 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-15 01:30:17,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:17,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:17,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 49 transitions. [2022-04-15 01:30:17,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:17,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 49 transitions. [2022-04-15 01:30:17,962 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 15 states and 49 transitions. [2022-04-15 01:30:18,062 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:18,064 INFO L225 Difference]: With dead ends: 44 [2022-04-15 01:30:18,064 INFO L226 Difference]: Without dead ends: 40 [2022-04-15 01:30:18,064 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 21 SyntacticMatches, 3 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=227, Invalid=423, Unknown=0, NotChecked=0, Total=650 [2022-04-15 01:30:18,065 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 80 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 28 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 80 SdHoareTripleChecker+Valid, 33 SdHoareTripleChecker+Invalid, 78 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 28 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:18,065 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [80 Valid, 33 Invalid, 78 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [28 Valid, 50 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-15 01:30:18,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2022-04-15 01:30:18,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 25. [2022-04-15 01:30:18,088 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:18,088 INFO L82 GeneralOperation]: Start isEquivalent. First operand 40 states. Second operand has 25 states, 20 states have (on average 1.3) internal successors, (26), 21 states have internal predecessors, (26), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:18,088 INFO L74 IsIncluded]: Start isIncluded. First operand 40 states. Second operand has 25 states, 20 states have (on average 1.3) internal successors, (26), 21 states have internal predecessors, (26), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:18,088 INFO L87 Difference]: Start difference. First operand 40 states. Second operand has 25 states, 20 states have (on average 1.3) internal successors, (26), 21 states have internal predecessors, (26), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:18,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:18,090 INFO L93 Difference]: Finished difference Result 40 states and 40 transitions. [2022-04-15 01:30:18,090 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 40 transitions. [2022-04-15 01:30:18,091 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:18,091 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:18,091 INFO L74 IsIncluded]: Start isIncluded. First operand has 25 states, 20 states have (on average 1.3) internal successors, (26), 21 states have internal predecessors, (26), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 40 states. [2022-04-15 01:30:18,091 INFO L87 Difference]: Start difference. First operand has 25 states, 20 states have (on average 1.3) internal successors, (26), 21 states have internal predecessors, (26), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 40 states. [2022-04-15 01:30:18,093 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:18,093 INFO L93 Difference]: Finished difference Result 40 states and 40 transitions. [2022-04-15 01:30:18,093 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 40 transitions. [2022-04-15 01:30:18,093 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:18,093 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:18,093 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:18,093 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:18,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 20 states have (on average 1.3) internal successors, (26), 21 states have internal predecessors, (26), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:18,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 29 transitions. [2022-04-15 01:30:18,095 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 29 transitions. Word has length 14 [2022-04-15 01:30:18,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:18,095 INFO L478 AbstractCegarLoop]: Abstraction has 25 states and 29 transitions. [2022-04-15 01:30:18,095 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.5714285714285714) internal successors, (22), 13 states have internal predecessors, (22), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:18,095 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 29 transitions. [2022-04-15 01:30:18,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-15 01:30:18,095 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:18,096 INFO L499 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:18,121 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-15 01:30:18,311 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:18,312 INFO L403 AbstractCegarLoop]: === Iteration 6 === Targeting mainErr1ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:18,312 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:18,312 INFO L85 PathProgramCache]: Analyzing trace with hash -500501856, now seen corresponding path program 2 times [2022-04-15 01:30:18,312 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:18,312 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [369291020] [2022-04-15 01:30:18,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:18,313 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:18,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:18,491 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:18,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:18,497 INFO L290 TraceCheckUtils]: 0: Hoare triple {940#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {928#true} is VALID [2022-04-15 01:30:18,497 INFO L290 TraceCheckUtils]: 1: Hoare triple {928#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:18,498 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {928#true} {928#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:18,498 INFO L272 TraceCheckUtils]: 0: Hoare triple {928#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {940#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:18,498 INFO L290 TraceCheckUtils]: 1: Hoare triple {940#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {928#true} is VALID [2022-04-15 01:30:18,498 INFO L290 TraceCheckUtils]: 2: Hoare triple {928#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:18,499 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {928#true} {928#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:18,499 INFO L272 TraceCheckUtils]: 4: Hoare triple {928#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:18,499 INFO L290 TraceCheckUtils]: 5: Hoare triple {928#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {928#true} is VALID [2022-04-15 01:30:18,499 INFO L290 TraceCheckUtils]: 6: Hoare triple {928#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {933#(= main_~s~0 0)} is VALID [2022-04-15 01:30:18,500 INFO L290 TraceCheckUtils]: 7: Hoare triple {933#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {934#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:18,501 INFO L290 TraceCheckUtils]: 8: Hoare triple {934#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {935#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:18,501 INFO L290 TraceCheckUtils]: 9: Hoare triple {935#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {936#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:18,502 INFO L290 TraceCheckUtils]: 10: Hoare triple {936#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {937#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:30:18,503 INFO L290 TraceCheckUtils]: 11: Hoare triple {937#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {938#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:30:18,504 INFO L290 TraceCheckUtils]: 12: Hoare triple {938#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:18,504 INFO L290 TraceCheckUtils]: 13: Hoare triple {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:18,504 INFO L290 TraceCheckUtils]: 14: Hoare triple {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:18,505 INFO L290 TraceCheckUtils]: 15: Hoare triple {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {929#false} is VALID [2022-04-15 01:30:18,505 INFO L290 TraceCheckUtils]: 16: Hoare triple {929#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {929#false} is VALID [2022-04-15 01:30:18,506 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:18,506 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:18,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [369291020] [2022-04-15 01:30:18,506 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [369291020] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:30:18,506 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1310959723] [2022-04-15 01:30:18,506 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-15 01:30:18,506 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:18,506 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:18,507 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:30:18,508 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-15 01:30:18,557 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-15 01:30:18,557 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-15 01:30:18,559 INFO L263 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 15 conjunts are in the unsatisfiable core [2022-04-15 01:30:18,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:18,571 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:30:19,569 INFO L272 TraceCheckUtils]: 0: Hoare triple {928#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:19,570 INFO L290 TraceCheckUtils]: 1: Hoare triple {928#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {928#true} is VALID [2022-04-15 01:30:19,570 INFO L290 TraceCheckUtils]: 2: Hoare triple {928#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:19,570 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {928#true} {928#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:19,570 INFO L272 TraceCheckUtils]: 4: Hoare triple {928#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:19,570 INFO L290 TraceCheckUtils]: 5: Hoare triple {928#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {928#true} is VALID [2022-04-15 01:30:19,579 INFO L290 TraceCheckUtils]: 6: Hoare triple {928#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {933#(= main_~s~0 0)} is VALID [2022-04-15 01:30:19,581 INFO L290 TraceCheckUtils]: 7: Hoare triple {933#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {934#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:19,582 INFO L290 TraceCheckUtils]: 8: Hoare triple {934#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {935#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:19,582 INFO L290 TraceCheckUtils]: 9: Hoare triple {935#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {936#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:19,583 INFO L290 TraceCheckUtils]: 10: Hoare triple {936#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {937#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:30:19,584 INFO L290 TraceCheckUtils]: 11: Hoare triple {937#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {938#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:30:19,585 INFO L290 TraceCheckUtils]: 12: Hoare triple {938#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:19,585 INFO L290 TraceCheckUtils]: 13: Hoare triple {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:19,586 INFO L290 TraceCheckUtils]: 14: Hoare triple {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:19,587 INFO L290 TraceCheckUtils]: 15: Hoare triple {939#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {929#false} is VALID [2022-04-15 01:30:19,587 INFO L290 TraceCheckUtils]: 16: Hoare triple {929#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {929#false} is VALID [2022-04-15 01:30:19,587 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:19,587 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:30:30,113 INFO L290 TraceCheckUtils]: 16: Hoare triple {929#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {929#false} is VALID [2022-04-15 01:30:30,113 INFO L290 TraceCheckUtils]: 15: Hoare triple {995#(not (< 65025 (mod main_~s~0 4294967296)))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {929#false} is VALID [2022-04-15 01:30:30,114 INFO L290 TraceCheckUtils]: 14: Hoare triple {995#(not (< 65025 (mod main_~s~0 4294967296)))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {995#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:30:30,114 INFO L290 TraceCheckUtils]: 13: Hoare triple {995#(not (< 65025 (mod main_~s~0 4294967296)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {995#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:30:30,115 INFO L290 TraceCheckUtils]: 12: Hoare triple {1005#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {995#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:30:30,124 INFO L290 TraceCheckUtils]: 11: Hoare triple {1009#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1005#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} is VALID [2022-04-15 01:30:30,126 INFO L290 TraceCheckUtils]: 10: Hoare triple {1013#(<= (div (+ (- 8589870332) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1009#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} is VALID [2022-04-15 01:30:30,137 INFO L290 TraceCheckUtils]: 9: Hoare triple {1017#(<= (div (+ (- 12884837883) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ (- 17179869184) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1013#(<= (div (+ (- 8589870332) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} is VALID [2022-04-15 01:30:30,138 INFO L290 TraceCheckUtils]: 8: Hoare triple {1021#(<= (div (+ (* (- 1) main_~s~0) (- 17179805434)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 9))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1017#(<= (div (+ (- 12884837883) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ (- 17179869184) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:30:30,142 INFO L290 TraceCheckUtils]: 7: Hoare triple {1025#(<= (div (+ (- 21474772985) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 11))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1021#(<= (div (+ (* (- 1) main_~s~0) (- 17179805434)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 9))} is VALID [2022-04-15 01:30:30,142 INFO L290 TraceCheckUtils]: 6: Hoare triple {928#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1025#(<= (div (+ (- 21474772985) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 11))} is VALID [2022-04-15 01:30:30,142 INFO L290 TraceCheckUtils]: 5: Hoare triple {928#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {928#true} is VALID [2022-04-15 01:30:30,142 INFO L272 TraceCheckUtils]: 4: Hoare triple {928#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:30,143 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {928#true} {928#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:30,143 INFO L290 TraceCheckUtils]: 2: Hoare triple {928#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:30,143 INFO L290 TraceCheckUtils]: 1: Hoare triple {928#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {928#true} is VALID [2022-04-15 01:30:30,143 INFO L272 TraceCheckUtils]: 0: Hoare triple {928#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {928#true} is VALID [2022-04-15 01:30:30,143 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:30,143 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1310959723] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:30:30,143 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:30:30,143 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 17 [2022-04-15 01:30:30,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [972687856] [2022-04-15 01:30:30,144 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:30:30,144 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-15 01:30:30,144 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:30,144 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:30,190 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:30,190 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-15 01:30:30,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:30,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-15 01:30:30,191 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2022-04-15 01:30:30,191 INFO L87 Difference]: Start difference. First operand 25 states and 29 transitions. Second operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:30,729 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:30,729 INFO L93 Difference]: Finished difference Result 46 states and 57 transitions. [2022-04-15 01:30:30,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-04-15 01:30:30,729 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-15 01:30:30,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:30,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:30,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 57 transitions. [2022-04-15 01:30:30,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:30,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 57 transitions. [2022-04-15 01:30:30,735 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 17 states and 57 transitions. [2022-04-15 01:30:30,984 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:30,985 INFO L225 Difference]: With dead ends: 46 [2022-04-15 01:30:30,985 INFO L226 Difference]: Without dead ends: 32 [2022-04-15 01:30:30,986 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 23 SyntacticMatches, 7 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 127 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=360, Invalid=570, Unknown=0, NotChecked=0, Total=930 [2022-04-15 01:30:30,986 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 61 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 47 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 61 SdHoareTripleChecker+Valid, 28 SdHoareTripleChecker+Invalid, 84 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 47 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:30,987 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [61 Valid, 28 Invalid, 84 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 47 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-15 01:30:30,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-15 01:30:31,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 29. [2022-04-15 01:30:31,013 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:31,013 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:31,013 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:31,013 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:31,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:31,014 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2022-04-15 01:30:31,014 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2022-04-15 01:30:31,014 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:31,014 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:31,015 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-15 01:30:31,015 INFO L87 Difference]: Start difference. First operand has 29 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-15 01:30:31,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:31,016 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2022-04-15 01:30:31,016 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2022-04-15 01:30:31,016 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:31,016 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:31,016 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:31,016 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:31,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 24 states have (on average 1.25) internal successors, (30), 25 states have internal predecessors, (30), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:31,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 33 transitions. [2022-04-15 01:30:31,017 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 33 transitions. Word has length 17 [2022-04-15 01:30:31,017 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:31,017 INFO L478 AbstractCegarLoop]: Abstraction has 29 states and 33 transitions. [2022-04-15 01:30:31,017 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 16 states have internal predecessors, (25), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:31,017 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 33 transitions. [2022-04-15 01:30:31,018 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-15 01:30:31,018 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:31,018 INFO L499 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:31,045 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-15 01:30:31,220 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:31,220 INFO L403 AbstractCegarLoop]: === Iteration 7 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:31,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:31,221 INFO L85 PathProgramCache]: Analyzing trace with hash -1793837734, now seen corresponding path program 3 times [2022-04-15 01:30:31,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:31,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [744868316] [2022-04-15 01:30:31,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:31,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:31,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:31,425 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:31,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:31,434 INFO L290 TraceCheckUtils]: 0: Hoare triple {1270#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-15 01:30:31,434 INFO L290 TraceCheckUtils]: 1: Hoare triple {1254#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:31,434 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1254#true} {1254#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:31,435 INFO L272 TraceCheckUtils]: 0: Hoare triple {1254#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1270#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:31,435 INFO L290 TraceCheckUtils]: 1: Hoare triple {1270#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-15 01:30:31,435 INFO L290 TraceCheckUtils]: 2: Hoare triple {1254#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:31,435 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1254#true} {1254#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:31,435 INFO L272 TraceCheckUtils]: 4: Hoare triple {1254#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:31,435 INFO L290 TraceCheckUtils]: 5: Hoare triple {1254#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {1254#true} is VALID [2022-04-15 01:30:31,436 INFO L290 TraceCheckUtils]: 6: Hoare triple {1254#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1259#(= main_~s~0 0)} is VALID [2022-04-15 01:30:31,437 INFO L290 TraceCheckUtils]: 7: Hoare triple {1259#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1260#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:31,438 INFO L290 TraceCheckUtils]: 8: Hoare triple {1260#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1261#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:31,439 INFO L290 TraceCheckUtils]: 9: Hoare triple {1261#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1262#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:31,439 INFO L290 TraceCheckUtils]: 10: Hoare triple {1262#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1263#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:30:31,440 INFO L290 TraceCheckUtils]: 11: Hoare triple {1263#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1264#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:30:31,441 INFO L290 TraceCheckUtils]: 12: Hoare triple {1264#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1265#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:31,441 INFO L290 TraceCheckUtils]: 13: Hoare triple {1265#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1266#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:30:31,442 INFO L290 TraceCheckUtils]: 14: Hoare triple {1266#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1267#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:31,442 INFO L290 TraceCheckUtils]: 15: Hoare triple {1267#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1268#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:30:31,443 INFO L290 TraceCheckUtils]: 16: Hoare triple {1268#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1269#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:30:31,444 INFO L290 TraceCheckUtils]: 17: Hoare triple {1269#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {1269#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:30:31,444 INFO L290 TraceCheckUtils]: 18: Hoare triple {1269#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-15 01:30:31,444 INFO L290 TraceCheckUtils]: 19: Hoare triple {1255#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-15 01:30:31,445 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:31,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:31,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [744868316] [2022-04-15 01:30:31,445 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [744868316] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:30:31,445 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [47075735] [2022-04-15 01:30:31,445 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-15 01:30:31,445 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:31,445 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:31,446 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:30:31,447 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-15 01:30:31,529 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-04-15 01:30:31,529 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-15 01:30:31,530 INFO L263 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-15 01:30:31,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:31,538 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:30:33,564 INFO L272 TraceCheckUtils]: 0: Hoare triple {1254#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:33,565 INFO L290 TraceCheckUtils]: 1: Hoare triple {1254#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-15 01:30:33,565 INFO L290 TraceCheckUtils]: 2: Hoare triple {1254#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:33,565 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1254#true} {1254#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:33,565 INFO L272 TraceCheckUtils]: 4: Hoare triple {1254#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:33,565 INFO L290 TraceCheckUtils]: 5: Hoare triple {1254#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {1254#true} is VALID [2022-04-15 01:30:33,566 INFO L290 TraceCheckUtils]: 6: Hoare triple {1254#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1259#(= main_~s~0 0)} is VALID [2022-04-15 01:30:33,566 INFO L290 TraceCheckUtils]: 7: Hoare triple {1259#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1260#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:33,567 INFO L290 TraceCheckUtils]: 8: Hoare triple {1260#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1261#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:33,567 INFO L290 TraceCheckUtils]: 9: Hoare triple {1261#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1262#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:33,568 INFO L290 TraceCheckUtils]: 10: Hoare triple {1262#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1263#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:30:33,569 INFO L290 TraceCheckUtils]: 11: Hoare triple {1263#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1264#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:30:33,569 INFO L290 TraceCheckUtils]: 12: Hoare triple {1264#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1265#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:33,570 INFO L290 TraceCheckUtils]: 13: Hoare triple {1265#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1266#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:30:33,570 INFO L290 TraceCheckUtils]: 14: Hoare triple {1266#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1267#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:33,571 INFO L290 TraceCheckUtils]: 15: Hoare triple {1267#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1268#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:30:33,572 INFO L290 TraceCheckUtils]: 16: Hoare triple {1268#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1322#(and (<= main_~s~0 (+ 2295 (mod main_~v~0 256))) (<= (mod main_~v~0 256) main_~s~0))} is VALID [2022-04-15 01:30:33,572 INFO L290 TraceCheckUtils]: 17: Hoare triple {1322#(and (<= main_~s~0 (+ 2295 (mod main_~v~0 256))) (<= (mod main_~v~0 256) main_~s~0))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {1322#(and (<= main_~s~0 (+ 2295 (mod main_~v~0 256))) (<= (mod main_~v~0 256) main_~s~0))} is VALID [2022-04-15 01:30:33,573 INFO L290 TraceCheckUtils]: 18: Hoare triple {1322#(and (<= main_~s~0 (+ 2295 (mod main_~v~0 256))) (<= (mod main_~v~0 256) main_~s~0))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-15 01:30:33,573 INFO L290 TraceCheckUtils]: 19: Hoare triple {1255#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-15 01:30:33,573 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:33,573 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:30:46,556 INFO L290 TraceCheckUtils]: 19: Hoare triple {1255#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-15 01:30:46,557 INFO L290 TraceCheckUtils]: 18: Hoare triple {1335#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {1255#false} is VALID [2022-04-15 01:30:46,559 INFO L290 TraceCheckUtils]: 17: Hoare triple {1335#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {1335#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:30:46,567 INFO L290 TraceCheckUtils]: 16: Hoare triple {1342#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1335#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:30:46,573 INFO L290 TraceCheckUtils]: 15: Hoare triple {1346#(<= (div (+ (- 4294967807) (* (- 1) main_~s~0)) (- 4294967296)) (+ 3 (div (+ main_~s~0 (- 4294967296)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1342#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} is VALID [2022-04-15 01:30:46,576 INFO L290 TraceCheckUtils]: 14: Hoare triple {1350#(<= (div (+ (- 8589935358) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ (- 8589934592) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1346#(<= (div (+ (- 4294967807) (* (- 1) main_~s~0)) (- 4294967296)) (+ 3 (div (+ main_~s~0 (- 4294967296)) 4294967296)))} is VALID [2022-04-15 01:30:46,579 INFO L290 TraceCheckUtils]: 13: Hoare triple {1354#(<= (div (+ (- 12884902909) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1350#(<= (div (+ (- 8589935358) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ (- 8589934592) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:30:46,583 INFO L290 TraceCheckUtils]: 12: Hoare triple {1358#(<= (div (+ (* (- 1) main_~s~0) (- 17179870460)) (- 4294967296)) (+ (div (+ (- 17179869184) main_~s~0) 4294967296) 9))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1354#(<= (div (+ (- 12884902909) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} is VALID [2022-04-15 01:30:46,585 INFO L290 TraceCheckUtils]: 11: Hoare triple {1362#(<= (div (+ (* (- 1) main_~s~0) (- 21474838011)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 11))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1358#(<= (div (+ (* (- 1) main_~s~0) (- 17179870460)) (- 4294967296)) (+ (div (+ (- 17179869184) main_~s~0) 4294967296) 9))} is VALID [2022-04-15 01:30:46,592 INFO L290 TraceCheckUtils]: 10: Hoare triple {1366#(<= (div (+ (* (- 1) main_~s~0) (- 25769805562)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 13))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1362#(<= (div (+ (* (- 1) main_~s~0) (- 21474838011)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 11))} is VALID [2022-04-15 01:30:46,599 INFO L290 TraceCheckUtils]: 9: Hoare triple {1370#(<= (div (+ (* (- 1) main_~s~0) (- 30064773113)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 15))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1366#(<= (div (+ (* (- 1) main_~s~0) (- 25769805562)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 13))} is VALID [2022-04-15 01:30:46,600 INFO L290 TraceCheckUtils]: 8: Hoare triple {1374#(<= (div (+ (- 34359740664) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 34359738368)) 4294967296) 17))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1370#(<= (div (+ (* (- 1) main_~s~0) (- 30064773113)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 15))} is VALID [2022-04-15 01:30:46,740 INFO L290 TraceCheckUtils]: 7: Hoare triple {1378#(<= (div (+ (- 38654708215) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ main_~s~0 (- 38654705664)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1374#(<= (div (+ (- 34359740664) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 34359738368)) 4294967296) 17))} is VALID [2022-04-15 01:30:46,741 INFO L290 TraceCheckUtils]: 6: Hoare triple {1254#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1378#(<= (div (+ (- 38654708215) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ main_~s~0 (- 38654705664)) 4294967296)))} is VALID [2022-04-15 01:30:46,741 INFO L290 TraceCheckUtils]: 5: Hoare triple {1254#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {1254#true} is VALID [2022-04-15 01:30:46,741 INFO L272 TraceCheckUtils]: 4: Hoare triple {1254#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:46,741 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1254#true} {1254#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:46,741 INFO L290 TraceCheckUtils]: 2: Hoare triple {1254#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:46,741 INFO L290 TraceCheckUtils]: 1: Hoare triple {1254#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1254#true} is VALID [2022-04-15 01:30:46,742 INFO L272 TraceCheckUtils]: 0: Hoare triple {1254#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1254#true} is VALID [2022-04-15 01:30:46,742 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:46,742 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [47075735] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:30:46,742 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:30:46,742 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2022-04-15 01:30:46,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1150415472] [2022-04-15 01:30:46,742 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:30:46,743 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-15 01:30:46,743 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:30:46,743 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:46,817 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:46,817 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-04-15 01:30:46,817 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:30:46,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-04-15 01:30:46,818 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=252, Invalid=398, Unknown=0, NotChecked=0, Total=650 [2022-04-15 01:30:46,818 INFO L87 Difference]: Start difference. First operand 29 states and 33 transitions. Second operand has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:48,159 INFO L93 Difference]: Finished difference Result 74 states and 85 transitions. [2022-04-15 01:30:48,159 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-04-15 01:30:48,159 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-15 01:30:48,160 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:30:48,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 85 transitions. [2022-04-15 01:30:48,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 85 transitions. [2022-04-15 01:30:48,162 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 27 states and 85 transitions. [2022-04-15 01:30:48,325 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 85 edges. 85 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:30:48,326 INFO L225 Difference]: With dead ends: 74 [2022-04-15 01:30:48,326 INFO L226 Difference]: Without dead ends: 68 [2022-04-15 01:30:48,326 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 21 SyntacticMatches, 9 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 426 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=875, Invalid=1575, Unknown=0, NotChecked=0, Total=2450 [2022-04-15 01:30:48,327 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 142 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 95 mSolverCounterSat, 55 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 43 SdHoareTripleChecker+Invalid, 150 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 55 IncrementalHoareTripleChecker+Valid, 95 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-15 01:30:48,327 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [142 Valid, 43 Invalid, 150 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [55 Valid, 95 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-15 01:30:48,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68 states. [2022-04-15 01:30:48,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68 to 37. [2022-04-15 01:30:48,371 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:30:48,372 INFO L82 GeneralOperation]: Start isEquivalent. First operand 68 states. Second operand has 37 states, 32 states have (on average 1.3125) internal successors, (42), 33 states have internal predecessors, (42), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,372 INFO L74 IsIncluded]: Start isIncluded. First operand 68 states. Second operand has 37 states, 32 states have (on average 1.3125) internal successors, (42), 33 states have internal predecessors, (42), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,372 INFO L87 Difference]: Start difference. First operand 68 states. Second operand has 37 states, 32 states have (on average 1.3125) internal successors, (42), 33 states have internal predecessors, (42), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:48,373 INFO L93 Difference]: Finished difference Result 68 states and 68 transitions. [2022-04-15 01:30:48,373 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 68 transitions. [2022-04-15 01:30:48,374 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:48,374 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:48,374 INFO L74 IsIncluded]: Start isIncluded. First operand has 37 states, 32 states have (on average 1.3125) internal successors, (42), 33 states have internal predecessors, (42), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 68 states. [2022-04-15 01:30:48,374 INFO L87 Difference]: Start difference. First operand has 37 states, 32 states have (on average 1.3125) internal successors, (42), 33 states have internal predecessors, (42), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 68 states. [2022-04-15 01:30:48,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:30:48,375 INFO L93 Difference]: Finished difference Result 68 states and 68 transitions. [2022-04-15 01:30:48,375 INFO L276 IsEmpty]: Start isEmpty. Operand 68 states and 68 transitions. [2022-04-15 01:30:48,376 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:30:48,376 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:30:48,376 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:30:48,376 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:30:48,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 32 states have (on average 1.3125) internal successors, (42), 33 states have internal predecessors, (42), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,377 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 45 transitions. [2022-04-15 01:30:48,377 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 45 transitions. Word has length 20 [2022-04-15 01:30:48,377 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:30:48,377 INFO L478 AbstractCegarLoop]: Abstraction has 37 states and 45 transitions. [2022-04-15 01:30:48,377 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 1.3076923076923077) internal successors, (34), 25 states have internal predecessors, (34), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:30:48,377 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-15 01:30:48,378 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-15 01:30:48,378 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:30:48,378 INFO L499 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:30:48,394 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-15 01:30:48,591 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:48,593 INFO L403 AbstractCegarLoop]: === Iteration 8 === Targeting mainErr1ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:30:48,593 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:30:48,593 INFO L85 PathProgramCache]: Analyzing trace with hash -1297464928, now seen corresponding path program 3 times [2022-04-15 01:30:48,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:30:48,593 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1587254086] [2022-04-15 01:30:48,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:30:48,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:30:48,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:48,887 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:30:48,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:48,893 INFO L290 TraceCheckUtils]: 0: Hoare triple {1771#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1751#true} is VALID [2022-04-15 01:30:48,894 INFO L290 TraceCheckUtils]: 1: Hoare triple {1751#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:48,894 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1751#true} {1751#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:48,894 INFO L272 TraceCheckUtils]: 0: Hoare triple {1751#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1771#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:30:48,894 INFO L290 TraceCheckUtils]: 1: Hoare triple {1771#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1751#true} is VALID [2022-04-15 01:30:48,894 INFO L290 TraceCheckUtils]: 2: Hoare triple {1751#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:48,895 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1751#true} {1751#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:48,895 INFO L272 TraceCheckUtils]: 4: Hoare triple {1751#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:48,895 INFO L290 TraceCheckUtils]: 5: Hoare triple {1751#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {1751#true} is VALID [2022-04-15 01:30:48,895 INFO L290 TraceCheckUtils]: 6: Hoare triple {1751#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1756#(= main_~s~0 0)} is VALID [2022-04-15 01:30:48,896 INFO L290 TraceCheckUtils]: 7: Hoare triple {1756#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1757#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:48,896 INFO L290 TraceCheckUtils]: 8: Hoare triple {1757#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1758#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,897 INFO L290 TraceCheckUtils]: 9: Hoare triple {1758#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1759#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,898 INFO L290 TraceCheckUtils]: 10: Hoare triple {1759#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1760#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:30:48,898 INFO L290 TraceCheckUtils]: 11: Hoare triple {1760#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1761#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:30:48,899 INFO L290 TraceCheckUtils]: 12: Hoare triple {1761#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1762#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:48,900 INFO L290 TraceCheckUtils]: 13: Hoare triple {1762#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1763#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:30:48,901 INFO L290 TraceCheckUtils]: 14: Hoare triple {1763#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1764#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,902 INFO L290 TraceCheckUtils]: 15: Hoare triple {1764#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1765#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:30:48,902 INFO L290 TraceCheckUtils]: 16: Hoare triple {1765#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1766#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,903 INFO L290 TraceCheckUtils]: 17: Hoare triple {1766#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1767#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:30:48,904 INFO L290 TraceCheckUtils]: 18: Hoare triple {1767#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1768#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,904 INFO L290 TraceCheckUtils]: 19: Hoare triple {1768#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1769#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,905 INFO L290 TraceCheckUtils]: 20: Hoare triple {1769#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,905 INFO L290 TraceCheckUtils]: 21: Hoare triple {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,906 INFO L290 TraceCheckUtils]: 22: Hoare triple {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:48,906 INFO L290 TraceCheckUtils]: 23: Hoare triple {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {1752#false} is VALID [2022-04-15 01:30:48,906 INFO L290 TraceCheckUtils]: 24: Hoare triple {1752#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1752#false} is VALID [2022-04-15 01:30:48,907 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:48,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:30:48,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1587254086] [2022-04-15 01:30:48,907 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1587254086] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:30:48,907 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1810793483] [2022-04-15 01:30:48,907 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-15 01:30:48,907 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:30:48,907 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:30:48,908 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:30:48,909 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-15 01:30:49,077 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2022-04-15 01:30:49,077 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-15 01:30:49,078 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 31 conjunts are in the unsatisfiable core [2022-04-15 01:30:49,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:30:49,088 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:30:51,123 INFO L272 TraceCheckUtils]: 0: Hoare triple {1751#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:51,123 INFO L290 TraceCheckUtils]: 1: Hoare triple {1751#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1751#true} is VALID [2022-04-15 01:30:51,123 INFO L290 TraceCheckUtils]: 2: Hoare triple {1751#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:51,123 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1751#true} {1751#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:51,123 INFO L272 TraceCheckUtils]: 4: Hoare triple {1751#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:30:51,123 INFO L290 TraceCheckUtils]: 5: Hoare triple {1751#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {1751#true} is VALID [2022-04-15 01:30:51,125 INFO L290 TraceCheckUtils]: 6: Hoare triple {1751#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1756#(= main_~s~0 0)} is VALID [2022-04-15 01:30:51,126 INFO L290 TraceCheckUtils]: 7: Hoare triple {1756#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1757#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:30:51,126 INFO L290 TraceCheckUtils]: 8: Hoare triple {1757#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1758#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,128 INFO L290 TraceCheckUtils]: 9: Hoare triple {1758#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1759#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,129 INFO L290 TraceCheckUtils]: 10: Hoare triple {1759#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1760#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:30:51,129 INFO L290 TraceCheckUtils]: 11: Hoare triple {1760#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1761#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:30:51,130 INFO L290 TraceCheckUtils]: 12: Hoare triple {1761#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1762#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:30:51,131 INFO L290 TraceCheckUtils]: 13: Hoare triple {1762#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1763#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:30:51,131 INFO L290 TraceCheckUtils]: 14: Hoare triple {1763#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1764#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,132 INFO L290 TraceCheckUtils]: 15: Hoare triple {1764#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1765#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:30:51,133 INFO L290 TraceCheckUtils]: 16: Hoare triple {1765#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1766#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,133 INFO L290 TraceCheckUtils]: 17: Hoare triple {1766#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1767#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:30:51,134 INFO L290 TraceCheckUtils]: 18: Hoare triple {1767#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1768#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,134 INFO L290 TraceCheckUtils]: 19: Hoare triple {1768#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1769#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,135 INFO L290 TraceCheckUtils]: 20: Hoare triple {1769#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,135 INFO L290 TraceCheckUtils]: 21: Hoare triple {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,136 INFO L290 TraceCheckUtils]: 22: Hoare triple {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:30:51,136 INFO L290 TraceCheckUtils]: 23: Hoare triple {1770#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {1752#false} is VALID [2022-04-15 01:30:51,136 INFO L290 TraceCheckUtils]: 24: Hoare triple {1752#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1752#false} is VALID [2022-04-15 01:30:51,137 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:30:51,137 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:31:15,009 INFO L290 TraceCheckUtils]: 24: Hoare triple {1752#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1752#false} is VALID [2022-04-15 01:31:15,010 INFO L290 TraceCheckUtils]: 23: Hoare triple {1850#(not (< 65025 (mod main_~s~0 4294967296)))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {1752#false} is VALID [2022-04-15 01:31:15,010 INFO L290 TraceCheckUtils]: 22: Hoare triple {1850#(not (< 65025 (mod main_~s~0 4294967296)))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {1850#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:31:15,015 INFO L290 TraceCheckUtils]: 21: Hoare triple {1850#(not (< 65025 (mod main_~s~0 4294967296)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {1850#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:31:15,019 INFO L290 TraceCheckUtils]: 20: Hoare triple {1860#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1850#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:31:15,021 INFO L290 TraceCheckUtils]: 19: Hoare triple {1864#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1860#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} is VALID [2022-04-15 01:31:15,022 INFO L290 TraceCheckUtils]: 18: Hoare triple {1868#(<= (div (+ (- 8589870332) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1864#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} is VALID [2022-04-15 01:31:15,029 INFO L290 TraceCheckUtils]: 17: Hoare triple {1872#(<= (div (+ (- 12884837883) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ (- 17179869184) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1868#(<= (div (+ (- 8589870332) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} is VALID [2022-04-15 01:31:15,049 INFO L290 TraceCheckUtils]: 16: Hoare triple {1876#(<= (div (+ (* (- 1) main_~s~0) (- 17179805434)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 9))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1872#(<= (div (+ (- 12884837883) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ (- 17179869184) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:15,050 INFO L290 TraceCheckUtils]: 15: Hoare triple {1880#(<= (div (+ (- 21474772985) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 11))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1876#(<= (div (+ (* (- 1) main_~s~0) (- 17179805434)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 9))} is VALID [2022-04-15 01:31:15,052 INFO L290 TraceCheckUtils]: 14: Hoare triple {1884#(<= (div (+ (- 25769740536) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 13))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1880#(<= (div (+ (- 21474772985) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 11))} is VALID [2022-04-15 01:31:15,065 INFO L290 TraceCheckUtils]: 13: Hoare triple {1888#(<= (div (+ (- 30064708087) (* (- 1) main_~s~0)) (- 4294967296)) (+ 15 (div (+ main_~s~0 (- 34359738368)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1884#(<= (div (+ (- 25769740536) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 13))} is VALID [2022-04-15 01:31:15,159 INFO L290 TraceCheckUtils]: 12: Hoare triple {1892#(<= (div (+ (- 34359675638) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 38654705664)) 4294967296) 17))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1888#(<= (div (+ (- 30064708087) (* (- 1) main_~s~0)) (- 4294967296)) (+ 15 (div (+ main_~s~0 (- 34359738368)) 4294967296)))} is VALID [2022-04-15 01:31:15,160 INFO L290 TraceCheckUtils]: 11: Hoare triple {1896#(<= (div (+ (- 38654643189) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ (- 42949672960) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1892#(<= (div (+ (- 34359675638) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 38654705664)) 4294967296) 17))} is VALID [2022-04-15 01:31:15,163 INFO L290 TraceCheckUtils]: 10: Hoare triple {1900#(<= (div (+ (* (- 1) main_~s~0) (- 42949610740)) (- 4294967296)) (+ (div (+ main_~s~0 (- 47244640256)) 4294967296) 21))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1896#(<= (div (+ (- 38654643189) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ (- 42949672960) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:15,164 INFO L290 TraceCheckUtils]: 9: Hoare triple {1904#(<= (div (+ (* (- 1) main_~s~0) (- 47244578291)) (- 4294967296)) (+ 23 (div (+ (- 51539607552) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1900#(<= (div (+ (* (- 1) main_~s~0) (- 42949610740)) (- 4294967296)) (+ (div (+ main_~s~0 (- 47244640256)) 4294967296) 21))} is VALID [2022-04-15 01:31:15,263 INFO L290 TraceCheckUtils]: 8: Hoare triple {1908#(<= (div (+ (- 51539545842) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 55834574848) main_~s~0) 4294967296) 25))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1904#(<= (div (+ (* (- 1) main_~s~0) (- 47244578291)) (- 4294967296)) (+ 23 (div (+ (- 51539607552) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:15,265 INFO L290 TraceCheckUtils]: 7: Hoare triple {1912#(<= (div (+ (- 55834513393) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 60129542144)) 4294967296) 27))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {1908#(<= (div (+ (- 51539545842) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 55834574848) main_~s~0) 4294967296) 25))} is VALID [2022-04-15 01:31:15,265 INFO L290 TraceCheckUtils]: 6: Hoare triple {1751#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {1912#(<= (div (+ (- 55834513393) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 60129542144)) 4294967296) 27))} is VALID [2022-04-15 01:31:15,265 INFO L290 TraceCheckUtils]: 5: Hoare triple {1751#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {1751#true} is VALID [2022-04-15 01:31:15,265 INFO L272 TraceCheckUtils]: 4: Hoare triple {1751#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:31:15,265 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1751#true} {1751#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:31:15,265 INFO L290 TraceCheckUtils]: 2: Hoare triple {1751#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:31:15,266 INFO L290 TraceCheckUtils]: 1: Hoare triple {1751#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1751#true} is VALID [2022-04-15 01:31:15,266 INFO L272 TraceCheckUtils]: 0: Hoare triple {1751#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1751#true} is VALID [2022-04-15 01:31:15,266 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:31:15,266 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1810793483] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:31:15,266 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:31:15,266 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 33 [2022-04-15 01:31:15,266 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781371807] [2022-04-15 01:31:15,266 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:31:15,267 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-15 01:31:15,267 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:31:15,267 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:15,358 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:31:15,358 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 33 states [2022-04-15 01:31:15,358 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:31:15,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2022-04-15 01:31:15,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=558, Unknown=0, NotChecked=0, Total=1056 [2022-04-15 01:31:15,359 INFO L87 Difference]: Start difference. First operand 37 states and 45 transitions. Second operand has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:31:17,693 INFO L93 Difference]: Finished difference Result 78 states and 101 transitions. [2022-04-15 01:31:17,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2022-04-15 01:31:17,693 INFO L78 Accepts]: Start accepts. Automaton has has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-15 01:31:17,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:31:17,693 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 101 transitions. [2022-04-15 01:31:17,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 101 transitions. [2022-04-15 01:31:17,699 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 33 states and 101 transitions. [2022-04-15 01:31:17,898 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 101 edges. 101 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:31:17,899 INFO L225 Difference]: With dead ends: 78 [2022-04-15 01:31:17,899 INFO L226 Difference]: Without dead ends: 52 [2022-04-15 01:31:17,900 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 23 SyntacticMatches, 15 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 631 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1488, Invalid=2418, Unknown=0, NotChecked=0, Total=3906 [2022-04-15 01:31:17,903 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 127 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 93 mSolverCounterSat, 87 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 127 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 180 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 87 IncrementalHoareTripleChecker+Valid, 93 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-04-15 01:31:17,903 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [127 Valid, 38 Invalid, 180 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [87 Valid, 93 Invalid, 0 Unknown, 0 Unchecked, 1.0s Time] [2022-04-15 01:31:17,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2022-04-15 01:31:17,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 45. [2022-04-15 01:31:17,965 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:31:17,965 INFO L82 GeneralOperation]: Start isEquivalent. First operand 52 states. Second operand has 45 states, 40 states have (on average 1.25) internal successors, (50), 41 states have internal predecessors, (50), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,965 INFO L74 IsIncluded]: Start isIncluded. First operand 52 states. Second operand has 45 states, 40 states have (on average 1.25) internal successors, (50), 41 states have internal predecessors, (50), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,965 INFO L87 Difference]: Start difference. First operand 52 states. Second operand has 45 states, 40 states have (on average 1.25) internal successors, (50), 41 states have internal predecessors, (50), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:31:17,966 INFO L93 Difference]: Finished difference Result 52 states and 60 transitions. [2022-04-15 01:31:17,966 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 60 transitions. [2022-04-15 01:31:17,967 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:31:17,967 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:31:17,967 INFO L74 IsIncluded]: Start isIncluded. First operand has 45 states, 40 states have (on average 1.25) internal successors, (50), 41 states have internal predecessors, (50), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 52 states. [2022-04-15 01:31:17,967 INFO L87 Difference]: Start difference. First operand has 45 states, 40 states have (on average 1.25) internal successors, (50), 41 states have internal predecessors, (50), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 52 states. [2022-04-15 01:31:17,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:31:17,968 INFO L93 Difference]: Finished difference Result 52 states and 60 transitions. [2022-04-15 01:31:17,968 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 60 transitions. [2022-04-15 01:31:17,968 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:31:17,968 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:31:17,968 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:31:17,968 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:31:17,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 40 states have (on average 1.25) internal successors, (50), 41 states have internal predecessors, (50), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2022-04-15 01:31:17,970 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 53 transitions. Word has length 25 [2022-04-15 01:31:17,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:31:17,970 INFO L478 AbstractCegarLoop]: Abstraction has 45 states and 53 transitions. [2022-04-15 01:31:17,970 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:17,970 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 53 transitions. [2022-04-15 01:31:17,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-04-15 01:31:17,970 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:31:17,970 INFO L499 BasicCegarLoop]: trace histogram [22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:31:17,980 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2022-04-15 01:31:18,175 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:31:18,176 INFO L403 AbstractCegarLoop]: === Iteration 9 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:31:18,176 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:31:18,176 INFO L85 PathProgramCache]: Analyzing trace with hash -41988390, now seen corresponding path program 4 times [2022-04-15 01:31:18,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:31:18,177 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700907161] [2022-04-15 01:31:18,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:31:18,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:31:18,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:31:18,598 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:31:18,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:31:18,618 INFO L290 TraceCheckUtils]: 0: Hoare triple {2321#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2293#true} is VALID [2022-04-15 01:31:18,618 INFO L290 TraceCheckUtils]: 1: Hoare triple {2293#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:18,619 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2293#true} {2293#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:18,619 INFO L272 TraceCheckUtils]: 0: Hoare triple {2293#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2321#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:31:18,619 INFO L290 TraceCheckUtils]: 1: Hoare triple {2321#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2293#true} is VALID [2022-04-15 01:31:18,619 INFO L290 TraceCheckUtils]: 2: Hoare triple {2293#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:18,619 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2293#true} {2293#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:18,619 INFO L272 TraceCheckUtils]: 4: Hoare triple {2293#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:18,619 INFO L290 TraceCheckUtils]: 5: Hoare triple {2293#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {2293#true} is VALID [2022-04-15 01:31:18,620 INFO L290 TraceCheckUtils]: 6: Hoare triple {2293#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {2298#(= main_~s~0 0)} is VALID [2022-04-15 01:31:18,621 INFO L290 TraceCheckUtils]: 7: Hoare triple {2298#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2299#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:31:18,621 INFO L290 TraceCheckUtils]: 8: Hoare triple {2299#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2300#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,622 INFO L290 TraceCheckUtils]: 9: Hoare triple {2300#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2301#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,622 INFO L290 TraceCheckUtils]: 10: Hoare triple {2301#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2302#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:31:18,623 INFO L290 TraceCheckUtils]: 11: Hoare triple {2302#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2303#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:31:18,624 INFO L290 TraceCheckUtils]: 12: Hoare triple {2303#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2304#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:31:18,624 INFO L290 TraceCheckUtils]: 13: Hoare triple {2304#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2305#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:31:18,625 INFO L290 TraceCheckUtils]: 14: Hoare triple {2305#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2306#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,625 INFO L290 TraceCheckUtils]: 15: Hoare triple {2306#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2307#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:31:18,626 INFO L290 TraceCheckUtils]: 16: Hoare triple {2307#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2308#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,626 INFO L290 TraceCheckUtils]: 17: Hoare triple {2308#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2309#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:31:18,627 INFO L290 TraceCheckUtils]: 18: Hoare triple {2309#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2310#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,628 INFO L290 TraceCheckUtils]: 19: Hoare triple {2310#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2311#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,628 INFO L290 TraceCheckUtils]: 20: Hoare triple {2311#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2312#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,629 INFO L290 TraceCheckUtils]: 21: Hoare triple {2312#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2313#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} is VALID [2022-04-15 01:31:18,629 INFO L290 TraceCheckUtils]: 22: Hoare triple {2313#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2314#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} is VALID [2022-04-15 01:31:18,630 INFO L290 TraceCheckUtils]: 23: Hoare triple {2314#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2315#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} is VALID [2022-04-15 01:31:18,631 INFO L290 TraceCheckUtils]: 24: Hoare triple {2315#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2316#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:18,631 INFO L290 TraceCheckUtils]: 25: Hoare triple {2316#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2317#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} is VALID [2022-04-15 01:31:18,632 INFO L290 TraceCheckUtils]: 26: Hoare triple {2317#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2318#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} is VALID [2022-04-15 01:31:18,633 INFO L290 TraceCheckUtils]: 27: Hoare triple {2318#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2319#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} is VALID [2022-04-15 01:31:18,634 INFO L290 TraceCheckUtils]: 28: Hoare triple {2319#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2320#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:31:18,634 INFO L290 TraceCheckUtils]: 29: Hoare triple {2320#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {2320#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:31:18,635 INFO L290 TraceCheckUtils]: 30: Hoare triple {2320#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {2294#false} is VALID [2022-04-15 01:31:18,635 INFO L290 TraceCheckUtils]: 31: Hoare triple {2294#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2294#false} is VALID [2022-04-15 01:31:18,635 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:31:18,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:31:18,635 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700907161] [2022-04-15 01:31:18,635 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700907161] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:31:18,636 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [382013978] [2022-04-15 01:31:18,636 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-15 01:31:18,636 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:31:18,636 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:31:18,637 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:31:18,637 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-15 01:31:18,726 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-15 01:31:18,727 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-15 01:31:18,728 INFO L263 TraceCheckSpWp]: Trace formula consists of 205 conjuncts, 47 conjunts are in the unsatisfiable core [2022-04-15 01:31:18,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:31:18,742 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:31:22,515 INFO L272 TraceCheckUtils]: 0: Hoare triple {2293#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:22,516 INFO L290 TraceCheckUtils]: 1: Hoare triple {2293#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2293#true} is VALID [2022-04-15 01:31:22,516 INFO L290 TraceCheckUtils]: 2: Hoare triple {2293#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:22,516 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2293#true} {2293#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:22,516 INFO L272 TraceCheckUtils]: 4: Hoare triple {2293#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:22,516 INFO L290 TraceCheckUtils]: 5: Hoare triple {2293#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {2293#true} is VALID [2022-04-15 01:31:22,523 INFO L290 TraceCheckUtils]: 6: Hoare triple {2293#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {2298#(= main_~s~0 0)} is VALID [2022-04-15 01:31:22,524 INFO L290 TraceCheckUtils]: 7: Hoare triple {2298#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2299#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:31:22,525 INFO L290 TraceCheckUtils]: 8: Hoare triple {2299#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2300#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,525 INFO L290 TraceCheckUtils]: 9: Hoare triple {2300#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2301#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,526 INFO L290 TraceCheckUtils]: 10: Hoare triple {2301#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2302#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:31:22,526 INFO L290 TraceCheckUtils]: 11: Hoare triple {2302#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2303#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:31:22,527 INFO L290 TraceCheckUtils]: 12: Hoare triple {2303#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2304#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:31:22,527 INFO L290 TraceCheckUtils]: 13: Hoare triple {2304#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2305#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:31:22,528 INFO L290 TraceCheckUtils]: 14: Hoare triple {2305#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2306#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,529 INFO L290 TraceCheckUtils]: 15: Hoare triple {2306#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2307#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:31:22,529 INFO L290 TraceCheckUtils]: 16: Hoare triple {2307#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2308#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,530 INFO L290 TraceCheckUtils]: 17: Hoare triple {2308#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2309#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:31:22,530 INFO L290 TraceCheckUtils]: 18: Hoare triple {2309#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2310#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,531 INFO L290 TraceCheckUtils]: 19: Hoare triple {2310#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2311#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,532 INFO L290 TraceCheckUtils]: 20: Hoare triple {2311#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2312#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,532 INFO L290 TraceCheckUtils]: 21: Hoare triple {2312#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2313#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} is VALID [2022-04-15 01:31:22,533 INFO L290 TraceCheckUtils]: 22: Hoare triple {2313#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2314#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} is VALID [2022-04-15 01:31:22,533 INFO L290 TraceCheckUtils]: 23: Hoare triple {2314#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2315#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} is VALID [2022-04-15 01:31:22,534 INFO L290 TraceCheckUtils]: 24: Hoare triple {2315#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2316#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:22,535 INFO L290 TraceCheckUtils]: 25: Hoare triple {2316#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2317#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} is VALID [2022-04-15 01:31:22,535 INFO L290 TraceCheckUtils]: 26: Hoare triple {2317#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2318#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} is VALID [2022-04-15 01:31:22,536 INFO L290 TraceCheckUtils]: 27: Hoare triple {2318#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2319#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} is VALID [2022-04-15 01:31:22,536 INFO L290 TraceCheckUtils]: 28: Hoare triple {2319#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2409#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 5355 (mod main_~v~0 256))))} is VALID [2022-04-15 01:31:22,537 INFO L290 TraceCheckUtils]: 29: Hoare triple {2409#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 5355 (mod main_~v~0 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {2409#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 5355 (mod main_~v~0 256))))} is VALID [2022-04-15 01:31:22,537 INFO L290 TraceCheckUtils]: 30: Hoare triple {2409#(and (<= (mod main_~v~0 256) main_~s~0) (<= main_~s~0 (+ 5355 (mod main_~v~0 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {2294#false} is VALID [2022-04-15 01:31:22,538 INFO L290 TraceCheckUtils]: 31: Hoare triple {2294#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2294#false} is VALID [2022-04-15 01:31:22,538 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:31:22,538 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:31:50,550 INFO L290 TraceCheckUtils]: 31: Hoare triple {2294#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2294#false} is VALID [2022-04-15 01:31:50,551 INFO L290 TraceCheckUtils]: 30: Hoare triple {2422#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {2294#false} is VALID [2022-04-15 01:31:50,551 INFO L290 TraceCheckUtils]: 29: Hoare triple {2422#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {2422#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:31:50,555 INFO L290 TraceCheckUtils]: 28: Hoare triple {2429#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2422#(not (< (mod main_~s~0 4294967296) (mod main_~v~0 256)))} is VALID [2022-04-15 01:31:50,556 INFO L290 TraceCheckUtils]: 27: Hoare triple {2433#(<= (div (+ (- 4294967807) (* (- 1) main_~s~0)) (- 4294967296)) (+ 3 (div (+ main_~s~0 (- 4294967296)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2429#(<= (div (+ (- 256) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div main_~s~0 4294967296) 1))} is VALID [2022-04-15 01:31:50,557 INFO L290 TraceCheckUtils]: 26: Hoare triple {2437#(<= (div (+ (- 8589935358) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ (- 8589934592) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2433#(<= (div (+ (- 4294967807) (* (- 1) main_~s~0)) (- 4294967296)) (+ 3 (div (+ main_~s~0 (- 4294967296)) 4294967296)))} is VALID [2022-04-15 01:31:50,561 INFO L290 TraceCheckUtils]: 25: Hoare triple {2441#(<= (div (+ (- 12884902909) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2437#(<= (div (+ (- 8589935358) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ (- 8589934592) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:50,562 INFO L290 TraceCheckUtils]: 24: Hoare triple {2445#(<= (div (+ (* (- 1) main_~s~0) (- 17179870460)) (- 4294967296)) (+ (div (+ (- 17179869184) main_~s~0) 4294967296) 9))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2441#(<= (div (+ (- 12884902909) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} is VALID [2022-04-15 01:31:50,587 INFO L290 TraceCheckUtils]: 23: Hoare triple {2449#(<= (div (+ (* (- 1) main_~s~0) (- 21474838011)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 11))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2445#(<= (div (+ (* (- 1) main_~s~0) (- 17179870460)) (- 4294967296)) (+ (div (+ (- 17179869184) main_~s~0) 4294967296) 9))} is VALID [2022-04-15 01:31:50,589 INFO L290 TraceCheckUtils]: 22: Hoare triple {2453#(<= (div (+ (* (- 1) main_~s~0) (- 25769805562)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 13))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2449#(<= (div (+ (* (- 1) main_~s~0) (- 21474838011)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 11))} is VALID [2022-04-15 01:31:50,595 INFO L290 TraceCheckUtils]: 21: Hoare triple {2457#(<= (div (+ (* (- 1) main_~s~0) (- 30064773113)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 15))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2453#(<= (div (+ (* (- 1) main_~s~0) (- 25769805562)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 13))} is VALID [2022-04-15 01:31:50,601 INFO L290 TraceCheckUtils]: 20: Hoare triple {2461#(<= (div (+ (- 34359740664) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 34359738368)) 4294967296) 17))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2457#(<= (div (+ (* (- 1) main_~s~0) (- 30064773113)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 15))} is VALID [2022-04-15 01:31:50,606 INFO L290 TraceCheckUtils]: 19: Hoare triple {2465#(<= (div (+ (- 38654708215) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ main_~s~0 (- 38654705664)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2461#(<= (div (+ (- 34359740664) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 34359738368)) 4294967296) 17))} is VALID [2022-04-15 01:31:50,616 INFO L290 TraceCheckUtils]: 18: Hoare triple {2469#(<= (div (+ (- 42949675766) (* (- 1) main_~s~0)) (- 4294967296)) (+ 21 (div (+ (- 42949672960) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2465#(<= (div (+ (- 38654708215) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ main_~s~0 (- 38654705664)) 4294967296)))} is VALID [2022-04-15 01:31:50,617 INFO L290 TraceCheckUtils]: 17: Hoare triple {2473#(<= (div (+ (* (- 1) main_~s~0) (- 47244643317)) (- 4294967296)) (+ 23 (div (+ main_~s~0 (- 47244640256)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2469#(<= (div (+ (- 42949675766) (* (- 1) main_~s~0)) (- 4294967296)) (+ 21 (div (+ (- 42949672960) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:50,619 INFO L290 TraceCheckUtils]: 16: Hoare triple {2477#(<= (div (+ (- 51539610868) (* (- 1) main_~s~0)) (- 4294967296)) (+ 25 (div (+ (- 51539607552) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2473#(<= (div (+ (* (- 1) main_~s~0) (- 47244643317)) (- 4294967296)) (+ 23 (div (+ main_~s~0 (- 47244640256)) 4294967296)))} is VALID [2022-04-15 01:31:50,621 INFO L290 TraceCheckUtils]: 15: Hoare triple {2481#(<= (div (+ (- 55834578419) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 55834574848) main_~s~0) 4294967296) 27))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2477#(<= (div (+ (- 51539610868) (* (- 1) main_~s~0)) (- 4294967296)) (+ 25 (div (+ (- 51539607552) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:50,625 INFO L290 TraceCheckUtils]: 14: Hoare triple {2485#(<= (div (+ (- 60129545970) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 60129542144)) 4294967296) 29))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2481#(<= (div (+ (- 55834578419) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 55834574848) main_~s~0) 4294967296) 27))} is VALID [2022-04-15 01:31:50,628 INFO L290 TraceCheckUtils]: 13: Hoare triple {2489#(<= (div (+ (- 64424513521) (* (- 1) main_~s~0)) (- 4294967296)) (+ 31 (div (+ (- 64424509440) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2485#(<= (div (+ (- 60129545970) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 60129542144)) 4294967296) 29))} is VALID [2022-04-15 01:31:50,631 INFO L290 TraceCheckUtils]: 12: Hoare triple {2493#(<= (div (+ (- 68719481072) (* (- 1) main_~s~0)) (- 4294967296)) (+ 33 (div (+ main_~s~0 (- 68719476736)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2489#(<= (div (+ (- 64424513521) (* (- 1) main_~s~0)) (- 4294967296)) (+ 31 (div (+ (- 64424509440) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:31:50,636 INFO L290 TraceCheckUtils]: 11: Hoare triple {2497#(<= (div (+ (* (- 1) main_~s~0) (- 73014448623)) (- 4294967296)) (+ (div (+ (- 73014444032) main_~s~0) 4294967296) 35))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2493#(<= (div (+ (- 68719481072) (* (- 1) main_~s~0)) (- 4294967296)) (+ 33 (div (+ main_~s~0 (- 68719476736)) 4294967296)))} is VALID [2022-04-15 01:31:50,685 INFO L290 TraceCheckUtils]: 10: Hoare triple {2501#(<= (div (+ (* (- 1) main_~s~0) (- 77309416174)) (- 4294967296)) (+ (div (+ (- 77309411328) main_~s~0) 4294967296) 37))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2497#(<= (div (+ (* (- 1) main_~s~0) (- 73014448623)) (- 4294967296)) (+ (div (+ (- 73014444032) main_~s~0) 4294967296) 35))} is VALID [2022-04-15 01:31:50,688 INFO L290 TraceCheckUtils]: 9: Hoare triple {2505#(<= (div (+ (- 81604383725) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 81604378624) main_~s~0) 4294967296) 39))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2501#(<= (div (+ (* (- 1) main_~s~0) (- 77309416174)) (- 4294967296)) (+ (div (+ (- 77309411328) main_~s~0) 4294967296) 37))} is VALID [2022-04-15 01:31:50,690 INFO L290 TraceCheckUtils]: 8: Hoare triple {2509#(<= (div (+ (* (- 1) main_~s~0) (- 85899351276)) (- 4294967296)) (+ 41 (div (+ main_~s~0 (- 85899345920)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2505#(<= (div (+ (- 81604383725) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 81604378624) main_~s~0) 4294967296) 39))} is VALID [2022-04-15 01:31:50,691 INFO L290 TraceCheckUtils]: 7: Hoare triple {2513#(<= (div (+ (- 90194318827) (* (- 1) main_~s~0)) (- 4294967296)) (+ 43 (div (+ main_~s~0 (- 90194313216)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {2509#(<= (div (+ (* (- 1) main_~s~0) (- 85899351276)) (- 4294967296)) (+ 41 (div (+ main_~s~0 (- 85899345920)) 4294967296)))} is VALID [2022-04-15 01:31:50,691 INFO L290 TraceCheckUtils]: 6: Hoare triple {2293#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {2513#(<= (div (+ (- 90194318827) (* (- 1) main_~s~0)) (- 4294967296)) (+ 43 (div (+ main_~s~0 (- 90194313216)) 4294967296)))} is VALID [2022-04-15 01:31:50,691 INFO L290 TraceCheckUtils]: 5: Hoare triple {2293#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {2293#true} is VALID [2022-04-15 01:31:50,692 INFO L272 TraceCheckUtils]: 4: Hoare triple {2293#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:50,692 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2293#true} {2293#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:50,692 INFO L290 TraceCheckUtils]: 2: Hoare triple {2293#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:50,692 INFO L290 TraceCheckUtils]: 1: Hoare triple {2293#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2293#true} is VALID [2022-04-15 01:31:50,692 INFO L272 TraceCheckUtils]: 0: Hoare triple {2293#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2293#true} is VALID [2022-04-15 01:31:50,692 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:31:50,692 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [382013978] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:31:50,693 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:31:50,693 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 50 [2022-04-15 01:31:50,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020407719] [2022-04-15 01:31:50,693 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:31:50,693 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 32 [2022-04-15 01:31:50,694 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:31:50,694 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:50,792 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:31:50,792 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-04-15 01:31:50,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:31:50,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-04-15 01:31:50,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1068, Invalid=1382, Unknown=0, NotChecked=0, Total=2450 [2022-04-15 01:31:50,794 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. Second operand has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:54,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:31:54,717 INFO L93 Difference]: Finished difference Result 134 states and 157 transitions. [2022-04-15 01:31:54,717 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2022-04-15 01:31:54,718 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 32 [2022-04-15 01:31:54,718 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:31:54,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:54,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 157 transitions. [2022-04-15 01:31:54,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:54,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 157 transitions. [2022-04-15 01:31:54,723 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 51 states and 157 transitions. [2022-04-15 01:31:55,027 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 157 edges. 157 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:31:55,029 INFO L225 Difference]: With dead ends: 134 [2022-04-15 01:31:55,030 INFO L226 Difference]: Without dead ends: 124 [2022-04-15 01:31:55,032 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 21 SyntacticMatches, 21 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1722 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=3467, Invalid=6039, Unknown=0, NotChecked=0, Total=9506 [2022-04-15 01:31:55,033 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 386 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 152 mSolverCounterSat, 102 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 386 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 254 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 102 IncrementalHoareTripleChecker+Valid, 152 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-04-15 01:31:55,033 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [386 Valid, 38 Invalid, 254 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [102 Valid, 152 Invalid, 0 Unknown, 0 Unchecked, 0.4s Time] [2022-04-15 01:31:55,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2022-04-15 01:31:55,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 61. [2022-04-15 01:31:55,145 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:31:55,145 INFO L82 GeneralOperation]: Start isEquivalent. First operand 124 states. Second operand has 61 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 57 states have internal predecessors, (74), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:55,145 INFO L74 IsIncluded]: Start isIncluded. First operand 124 states. Second operand has 61 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 57 states have internal predecessors, (74), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:55,146 INFO L87 Difference]: Start difference. First operand 124 states. Second operand has 61 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 57 states have internal predecessors, (74), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:55,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:31:55,148 INFO L93 Difference]: Finished difference Result 124 states and 124 transitions. [2022-04-15 01:31:55,148 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 124 transitions. [2022-04-15 01:31:55,148 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:31:55,148 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:31:55,148 INFO L74 IsIncluded]: Start isIncluded. First operand has 61 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 57 states have internal predecessors, (74), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 124 states. [2022-04-15 01:31:55,149 INFO L87 Difference]: Start difference. First operand has 61 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 57 states have internal predecessors, (74), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 124 states. [2022-04-15 01:31:55,151 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:31:55,151 INFO L93 Difference]: Finished difference Result 124 states and 124 transitions. [2022-04-15 01:31:55,151 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 124 transitions. [2022-04-15 01:31:55,151 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:31:55,151 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:31:55,151 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:31:55,151 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:31:55,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 61 states, 56 states have (on average 1.3214285714285714) internal successors, (74), 57 states have internal predecessors, (74), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:55,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 77 transitions. [2022-04-15 01:31:55,152 INFO L78 Accepts]: Start accepts. Automaton has 61 states and 77 transitions. Word has length 32 [2022-04-15 01:31:55,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:31:55,153 INFO L478 AbstractCegarLoop]: Abstraction has 61 states and 77 transitions. [2022-04-15 01:31:55,153 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 1.16) internal successors, (58), 49 states have internal predecessors, (58), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:31:55,153 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 77 transitions. [2022-04-15 01:31:55,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2022-04-15 01:31:55,153 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:31:55,153 INFO L499 BasicCegarLoop]: trace histogram [30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:31:55,172 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-15 01:31:55,359 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:31:55,359 INFO L403 AbstractCegarLoop]: === Iteration 10 === Targeting mainErr1ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:31:55,360 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:31:55,360 INFO L85 PathProgramCache]: Analyzing trace with hash 275505056, now seen corresponding path program 4 times [2022-04-15 01:31:55,360 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:31:55,360 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1876451494] [2022-04-15 01:31:55,360 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:31:55,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:31:55,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:31:56,048 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:31:56,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:31:56,052 INFO L290 TraceCheckUtils]: 0: Hoare triple {3214#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3178#true} is VALID [2022-04-15 01:31:56,052 INFO L290 TraceCheckUtils]: 1: Hoare triple {3178#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:31:56,052 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3178#true} {3178#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:31:56,053 INFO L272 TraceCheckUtils]: 0: Hoare triple {3178#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3214#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:31:56,053 INFO L290 TraceCheckUtils]: 1: Hoare triple {3214#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3178#true} is VALID [2022-04-15 01:31:56,053 INFO L290 TraceCheckUtils]: 2: Hoare triple {3178#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:31:56,053 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3178#true} {3178#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:31:56,053 INFO L272 TraceCheckUtils]: 4: Hoare triple {3178#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:31:56,053 INFO L290 TraceCheckUtils]: 5: Hoare triple {3178#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {3178#true} is VALID [2022-04-15 01:31:56,054 INFO L290 TraceCheckUtils]: 6: Hoare triple {3178#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {3183#(= main_~s~0 0)} is VALID [2022-04-15 01:31:56,054 INFO L290 TraceCheckUtils]: 7: Hoare triple {3183#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3184#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:31:56,055 INFO L290 TraceCheckUtils]: 8: Hoare triple {3184#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3185#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,056 INFO L290 TraceCheckUtils]: 9: Hoare triple {3185#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3186#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,056 INFO L290 TraceCheckUtils]: 10: Hoare triple {3186#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3187#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:31:56,057 INFO L290 TraceCheckUtils]: 11: Hoare triple {3187#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3188#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:31:56,057 INFO L290 TraceCheckUtils]: 12: Hoare triple {3188#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3189#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:31:56,058 INFO L290 TraceCheckUtils]: 13: Hoare triple {3189#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3190#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:31:56,059 INFO L290 TraceCheckUtils]: 14: Hoare triple {3190#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3191#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,059 INFO L290 TraceCheckUtils]: 15: Hoare triple {3191#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3192#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:31:56,060 INFO L290 TraceCheckUtils]: 16: Hoare triple {3192#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3193#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,061 INFO L290 TraceCheckUtils]: 17: Hoare triple {3193#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3194#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:31:56,061 INFO L290 TraceCheckUtils]: 18: Hoare triple {3194#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3195#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,062 INFO L290 TraceCheckUtils]: 19: Hoare triple {3195#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3196#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,062 INFO L290 TraceCheckUtils]: 20: Hoare triple {3196#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3197#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,063 INFO L290 TraceCheckUtils]: 21: Hoare triple {3197#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3198#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} is VALID [2022-04-15 01:31:56,064 INFO L290 TraceCheckUtils]: 22: Hoare triple {3198#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3199#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} is VALID [2022-04-15 01:31:56,064 INFO L290 TraceCheckUtils]: 23: Hoare triple {3199#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3200#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} is VALID [2022-04-15 01:31:56,065 INFO L290 TraceCheckUtils]: 24: Hoare triple {3200#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3201#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,065 INFO L290 TraceCheckUtils]: 25: Hoare triple {3201#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3202#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} is VALID [2022-04-15 01:31:56,066 INFO L290 TraceCheckUtils]: 26: Hoare triple {3202#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3203#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} is VALID [2022-04-15 01:31:56,067 INFO L290 TraceCheckUtils]: 27: Hoare triple {3203#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3204#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} is VALID [2022-04-15 01:31:56,067 INFO L290 TraceCheckUtils]: 28: Hoare triple {3204#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3205#(and (<= main_~s~0 5610) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,068 INFO L290 TraceCheckUtils]: 29: Hoare triple {3205#(and (<= main_~s~0 5610) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3206#(and (<= main_~s~0 5865) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,068 INFO L290 TraceCheckUtils]: 30: Hoare triple {3206#(and (<= main_~s~0 5865) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3207#(and (<= 0 main_~s~0) (<= main_~s~0 6120))} is VALID [2022-04-15 01:31:56,069 INFO L290 TraceCheckUtils]: 31: Hoare triple {3207#(and (<= 0 main_~s~0) (<= main_~s~0 6120))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3208#(and (<= main_~s~0 6375) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,070 INFO L290 TraceCheckUtils]: 32: Hoare triple {3208#(and (<= main_~s~0 6375) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3209#(and (<= main_~s~0 6630) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,070 INFO L290 TraceCheckUtils]: 33: Hoare triple {3209#(and (<= main_~s~0 6630) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3210#(and (<= main_~s~0 6885) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,071 INFO L290 TraceCheckUtils]: 34: Hoare triple {3210#(and (<= main_~s~0 6885) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3211#(and (<= main_~s~0 7140) (<= 0 main_~s~0))} is VALID [2022-04-15 01:31:56,072 INFO L290 TraceCheckUtils]: 35: Hoare triple {3211#(and (<= main_~s~0 7140) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3212#(and (<= 0 main_~s~0) (<= main_~s~0 7395))} is VALID [2022-04-15 01:31:56,072 INFO L290 TraceCheckUtils]: 36: Hoare triple {3212#(and (<= 0 main_~s~0) (<= main_~s~0 7395))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:31:56,073 INFO L290 TraceCheckUtils]: 37: Hoare triple {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:31:56,073 INFO L290 TraceCheckUtils]: 38: Hoare triple {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:31:56,073 INFO L290 TraceCheckUtils]: 39: Hoare triple {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {3179#false} is VALID [2022-04-15 01:31:56,074 INFO L290 TraceCheckUtils]: 40: Hoare triple {3179#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3179#false} is VALID [2022-04-15 01:31:56,074 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:31:56,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:31:56,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1876451494] [2022-04-15 01:31:56,074 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1876451494] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:31:56,074 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1538355585] [2022-04-15 01:31:56,075 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-15 01:31:56,075 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:31:56,075 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:31:56,079 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:31:56,083 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-15 01:31:56,247 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-15 01:31:56,247 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-15 01:31:56,249 INFO L263 TraceCheckSpWp]: Trace formula consists of 262 conjuncts, 63 conjunts are in the unsatisfiable core [2022-04-15 01:31:56,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:31:56,260 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-15 01:32:00,918 INFO L272 TraceCheckUtils]: 0: Hoare triple {3178#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:32:00,918 INFO L290 TraceCheckUtils]: 1: Hoare triple {3178#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3178#true} is VALID [2022-04-15 01:32:00,919 INFO L290 TraceCheckUtils]: 2: Hoare triple {3178#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:32:00,919 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3178#true} {3178#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:32:00,919 INFO L272 TraceCheckUtils]: 4: Hoare triple {3178#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:32:00,919 INFO L290 TraceCheckUtils]: 5: Hoare triple {3178#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {3178#true} is VALID [2022-04-15 01:32:00,919 INFO L290 TraceCheckUtils]: 6: Hoare triple {3178#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {3183#(= main_~s~0 0)} is VALID [2022-04-15 01:32:00,920 INFO L290 TraceCheckUtils]: 7: Hoare triple {3183#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3184#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:32:00,921 INFO L290 TraceCheckUtils]: 8: Hoare triple {3184#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3185#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,921 INFO L290 TraceCheckUtils]: 9: Hoare triple {3185#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3186#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,922 INFO L290 TraceCheckUtils]: 10: Hoare triple {3186#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3187#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:32:00,923 INFO L290 TraceCheckUtils]: 11: Hoare triple {3187#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3188#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:32:00,923 INFO L290 TraceCheckUtils]: 12: Hoare triple {3188#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3189#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:32:00,924 INFO L290 TraceCheckUtils]: 13: Hoare triple {3189#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3190#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:32:00,924 INFO L290 TraceCheckUtils]: 14: Hoare triple {3190#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3191#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,925 INFO L290 TraceCheckUtils]: 15: Hoare triple {3191#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3192#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:32:00,926 INFO L290 TraceCheckUtils]: 16: Hoare triple {3192#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3193#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,926 INFO L290 TraceCheckUtils]: 17: Hoare triple {3193#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3194#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:32:00,927 INFO L290 TraceCheckUtils]: 18: Hoare triple {3194#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3195#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,928 INFO L290 TraceCheckUtils]: 19: Hoare triple {3195#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3196#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,928 INFO L290 TraceCheckUtils]: 20: Hoare triple {3196#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3197#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,929 INFO L290 TraceCheckUtils]: 21: Hoare triple {3197#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3198#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} is VALID [2022-04-15 01:32:00,929 INFO L290 TraceCheckUtils]: 22: Hoare triple {3198#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3199#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} is VALID [2022-04-15 01:32:00,933 INFO L290 TraceCheckUtils]: 23: Hoare triple {3199#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3200#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} is VALID [2022-04-15 01:32:00,933 INFO L290 TraceCheckUtils]: 24: Hoare triple {3200#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3201#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,934 INFO L290 TraceCheckUtils]: 25: Hoare triple {3201#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3202#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} is VALID [2022-04-15 01:32:00,934 INFO L290 TraceCheckUtils]: 26: Hoare triple {3202#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3203#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} is VALID [2022-04-15 01:32:00,935 INFO L290 TraceCheckUtils]: 27: Hoare triple {3203#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3204#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} is VALID [2022-04-15 01:32:00,936 INFO L290 TraceCheckUtils]: 28: Hoare triple {3204#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3205#(and (<= main_~s~0 5610) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,936 INFO L290 TraceCheckUtils]: 29: Hoare triple {3205#(and (<= main_~s~0 5610) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3206#(and (<= main_~s~0 5865) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,937 INFO L290 TraceCheckUtils]: 30: Hoare triple {3206#(and (<= main_~s~0 5865) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3207#(and (<= 0 main_~s~0) (<= main_~s~0 6120))} is VALID [2022-04-15 01:32:00,937 INFO L290 TraceCheckUtils]: 31: Hoare triple {3207#(and (<= 0 main_~s~0) (<= main_~s~0 6120))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3208#(and (<= main_~s~0 6375) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,938 INFO L290 TraceCheckUtils]: 32: Hoare triple {3208#(and (<= main_~s~0 6375) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3209#(and (<= main_~s~0 6630) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,938 INFO L290 TraceCheckUtils]: 33: Hoare triple {3209#(and (<= main_~s~0 6630) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3210#(and (<= main_~s~0 6885) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,939 INFO L290 TraceCheckUtils]: 34: Hoare triple {3210#(and (<= main_~s~0 6885) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3211#(and (<= main_~s~0 7140) (<= 0 main_~s~0))} is VALID [2022-04-15 01:32:00,940 INFO L290 TraceCheckUtils]: 35: Hoare triple {3211#(and (<= main_~s~0 7140) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3212#(and (<= 0 main_~s~0) (<= main_~s~0 7395))} is VALID [2022-04-15 01:32:00,940 INFO L290 TraceCheckUtils]: 36: Hoare triple {3212#(and (<= 0 main_~s~0) (<= main_~s~0 7395))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:32:00,941 INFO L290 TraceCheckUtils]: 37: Hoare triple {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:32:00,941 INFO L290 TraceCheckUtils]: 38: Hoare triple {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:32:00,942 INFO L290 TraceCheckUtils]: 39: Hoare triple {3213#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {3179#false} is VALID [2022-04-15 01:32:00,942 INFO L290 TraceCheckUtils]: 40: Hoare triple {3179#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3179#false} is VALID [2022-04-15 01:32:00,942 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:32:00,942 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-15 01:33:00,185 INFO L290 TraceCheckUtils]: 40: Hoare triple {3179#false} [59] L22-->mainErr1ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3179#false} is VALID [2022-04-15 01:33:00,186 INFO L290 TraceCheckUtils]: 39: Hoare triple {3341#(not (< 65025 (mod main_~s~0 4294967296)))} [57] L21-->L22: Formula: (< 65025 (mod v_main_~s~0_1 4294967296)) InVars {main_~s~0=v_main_~s~0_1} OutVars{main_~s~0=v_main_~s~0_1} AuxVars[] AssignedVars[] {3179#false} is VALID [2022-04-15 01:33:00,186 INFO L290 TraceCheckUtils]: 38: Hoare triple {3341#(not (< 65025 (mod main_~s~0 4294967296)))} [54] L12-3-->L21: Formula: (not (< (mod v_main_~s~0_7 4294967296) (mod v_main_~v~0_4 256))) InVars {main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} OutVars{main_~v~0=v_main_~v~0_4, main_~s~0=v_main_~s~0_7} AuxVars[] AssignedVars[] {3341#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:33:00,187 INFO L290 TraceCheckUtils]: 37: Hoare triple {3341#(not (< 65025 (mod main_~s~0 4294967296)))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {3341#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:33:00,188 INFO L290 TraceCheckUtils]: 36: Hoare triple {3351#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3341#(not (< 65025 (mod main_~s~0 4294967296)))} is VALID [2022-04-15 01:33:00,191 INFO L290 TraceCheckUtils]: 35: Hoare triple {3355#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3351#(<= (div (+ (* (- 1) main_~s~0) 64770) (- 4294967296)) (+ (div (+ main_~s~0 (- 4294967296)) 4294967296) 1))} is VALID [2022-04-15 01:33:00,193 INFO L290 TraceCheckUtils]: 34: Hoare triple {3359#(<= (div (+ (- 8589870332) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3355#(<= (div (+ (- 4294902781) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 8589934592) main_~s~0) 4294967296) 3))} is VALID [2022-04-15 01:33:00,195 INFO L290 TraceCheckUtils]: 33: Hoare triple {3363#(<= (div (+ (- 12884837883) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ (- 17179869184) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3359#(<= (div (+ (- 8589870332) (* (- 1) main_~s~0)) (- 4294967296)) (+ 5 (div (+ main_~s~0 (- 12884901888)) 4294967296)))} is VALID [2022-04-15 01:33:00,227 INFO L290 TraceCheckUtils]: 32: Hoare triple {3367#(<= (div (+ (* (- 1) main_~s~0) (- 17179805434)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 9))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3363#(<= (div (+ (- 12884837883) (* (- 1) main_~s~0)) (- 4294967296)) (+ 7 (div (+ (- 17179869184) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,233 INFO L290 TraceCheckUtils]: 31: Hoare triple {3371#(<= (div (+ (- 21474772985) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 11))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3367#(<= (div (+ (* (- 1) main_~s~0) (- 17179805434)) (- 4294967296)) (+ (div (+ main_~s~0 (- 21474836480)) 4294967296) 9))} is VALID [2022-04-15 01:33:00,244 INFO L290 TraceCheckUtils]: 30: Hoare triple {3375#(<= (div (+ (- 25769740536) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 13))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3371#(<= (div (+ (- 21474772985) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 25769803776)) 4294967296) 11))} is VALID [2022-04-15 01:33:00,245 INFO L290 TraceCheckUtils]: 29: Hoare triple {3379#(<= (div (+ (- 30064708087) (* (- 1) main_~s~0)) (- 4294967296)) (+ 15 (div (+ main_~s~0 (- 34359738368)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3375#(<= (div (+ (- 25769740536) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 30064771072)) 4294967296) 13))} is VALID [2022-04-15 01:33:00,307 INFO L290 TraceCheckUtils]: 28: Hoare triple {3383#(<= (div (+ (- 34359675638) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 38654705664)) 4294967296) 17))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3379#(<= (div (+ (- 30064708087) (* (- 1) main_~s~0)) (- 4294967296)) (+ 15 (div (+ main_~s~0 (- 34359738368)) 4294967296)))} is VALID [2022-04-15 01:33:00,309 INFO L290 TraceCheckUtils]: 27: Hoare triple {3387#(<= (div (+ (- 38654643189) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ (- 42949672960) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3383#(<= (div (+ (- 34359675638) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 38654705664)) 4294967296) 17))} is VALID [2022-04-15 01:33:00,311 INFO L290 TraceCheckUtils]: 26: Hoare triple {3391#(<= (div (+ (* (- 1) main_~s~0) (- 42949610740)) (- 4294967296)) (+ (div (+ main_~s~0 (- 47244640256)) 4294967296) 21))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3387#(<= (div (+ (- 38654643189) (* (- 1) main_~s~0)) (- 4294967296)) (+ 19 (div (+ (- 42949672960) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,314 INFO L290 TraceCheckUtils]: 25: Hoare triple {3395#(<= (div (+ (* (- 1) main_~s~0) (- 47244578291)) (- 4294967296)) (+ 23 (div (+ (- 51539607552) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3391#(<= (div (+ (* (- 1) main_~s~0) (- 42949610740)) (- 4294967296)) (+ (div (+ main_~s~0 (- 47244640256)) 4294967296) 21))} is VALID [2022-04-15 01:33:00,319 INFO L290 TraceCheckUtils]: 24: Hoare triple {3399#(<= (div (+ (- 51539545842) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 55834574848) main_~s~0) 4294967296) 25))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3395#(<= (div (+ (* (- 1) main_~s~0) (- 47244578291)) (- 4294967296)) (+ 23 (div (+ (- 51539607552) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,321 INFO L290 TraceCheckUtils]: 23: Hoare triple {3403#(<= (div (+ (- 55834513393) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 60129542144)) 4294967296) 27))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3399#(<= (div (+ (- 51539545842) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 55834574848) main_~s~0) 4294967296) 25))} is VALID [2022-04-15 01:33:00,323 INFO L290 TraceCheckUtils]: 22: Hoare triple {3407#(<= (div (+ (- 60129480944) (* (- 1) main_~s~0)) (- 4294967296)) (+ 29 (div (+ (- 64424509440) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3403#(<= (div (+ (- 55834513393) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 60129542144)) 4294967296) 27))} is VALID [2022-04-15 01:33:00,324 INFO L290 TraceCheckUtils]: 21: Hoare triple {3411#(<= (div (+ (* (- 1) main_~s~0) (- 64424448495)) (- 4294967296)) (+ 31 (div (+ main_~s~0 (- 68719476736)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3407#(<= (div (+ (- 60129480944) (* (- 1) main_~s~0)) (- 4294967296)) (+ 29 (div (+ (- 64424509440) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,328 INFO L290 TraceCheckUtils]: 20: Hoare triple {3415#(<= (div (+ (- 68719416046) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 73014444032) main_~s~0) 4294967296) 33))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3411#(<= (div (+ (* (- 1) main_~s~0) (- 64424448495)) (- 4294967296)) (+ 31 (div (+ main_~s~0 (- 68719476736)) 4294967296)))} is VALID [2022-04-15 01:33:00,330 INFO L290 TraceCheckUtils]: 19: Hoare triple {3419#(<= (div (+ (- 73014383597) (* (- 1) main_~s~0)) (- 4294967296)) (+ 35 (div (+ (- 77309411328) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3415#(<= (div (+ (- 68719416046) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 73014444032) main_~s~0) 4294967296) 33))} is VALID [2022-04-15 01:33:00,333 INFO L290 TraceCheckUtils]: 18: Hoare triple {3423#(<= (div (+ (- 77309351148) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 81604378624) main_~s~0) 4294967296) 37))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3419#(<= (div (+ (- 73014383597) (* (- 1) main_~s~0)) (- 4294967296)) (+ 35 (div (+ (- 77309411328) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,338 INFO L290 TraceCheckUtils]: 17: Hoare triple {3427#(<= (div (+ (- 81604318699) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 85899345920)) 4294967296) 39))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3423#(<= (div (+ (- 77309351148) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ (- 81604378624) main_~s~0) 4294967296) 37))} is VALID [2022-04-15 01:33:00,340 INFO L290 TraceCheckUtils]: 16: Hoare triple {3431#(<= (div (+ (* (- 1) main_~s~0) (- 85899286250)) (- 4294967296)) (+ 41 (div (+ main_~s~0 (- 90194313216)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3427#(<= (div (+ (- 81604318699) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 85899345920)) 4294967296) 39))} is VALID [2022-04-15 01:33:00,342 INFO L290 TraceCheckUtils]: 15: Hoare triple {3435#(<= (div (+ (* (- 1) main_~s~0) (- 90194253801)) (- 4294967296)) (+ 43 (div (+ (- 94489280512) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3431#(<= (div (+ (* (- 1) main_~s~0) (- 85899286250)) (- 4294967296)) (+ 41 (div (+ main_~s~0 (- 90194313216)) 4294967296)))} is VALID [2022-04-15 01:33:00,343 INFO L290 TraceCheckUtils]: 14: Hoare triple {3439#(<= (div (+ (* (- 1) main_~s~0) (- 94489221352)) (- 4294967296)) (+ (div (+ main_~s~0 (- 98784247808)) 4294967296) 45))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3435#(<= (div (+ (* (- 1) main_~s~0) (- 90194253801)) (- 4294967296)) (+ 43 (div (+ (- 94489280512) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,344 INFO L290 TraceCheckUtils]: 13: Hoare triple {3443#(<= (div (+ (- 98784188903) (* (- 1) main_~s~0)) (- 4294967296)) (+ 47 (div (+ (- 103079215104) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3439#(<= (div (+ (* (- 1) main_~s~0) (- 94489221352)) (- 4294967296)) (+ (div (+ main_~s~0 (- 98784247808)) 4294967296) 45))} is VALID [2022-04-15 01:33:00,348 INFO L290 TraceCheckUtils]: 12: Hoare triple {3447#(<= (div (+ (- 103079156454) (* (- 1) main_~s~0)) (- 4294967296)) (+ 49 (div (+ (- 107374182400) main_~s~0) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3443#(<= (div (+ (- 98784188903) (* (- 1) main_~s~0)) (- 4294967296)) (+ 47 (div (+ (- 103079215104) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,351 INFO L290 TraceCheckUtils]: 11: Hoare triple {3451#(<= (div (+ (- 107374124005) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 111669149696)) 4294967296) 51))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3447#(<= (div (+ (- 103079156454) (* (- 1) main_~s~0)) (- 4294967296)) (+ 49 (div (+ (- 107374182400) main_~s~0) 4294967296)))} is VALID [2022-04-15 01:33:00,355 INFO L290 TraceCheckUtils]: 10: Hoare triple {3455#(<= (div (+ (* (- 1) main_~s~0) (- 111669091556)) (- 4294967296)) (+ 53 (div (+ main_~s~0 (- 115964116992)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3451#(<= (div (+ (- 107374124005) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 111669149696)) 4294967296) 51))} is VALID [2022-04-15 01:33:00,390 INFO L290 TraceCheckUtils]: 9: Hoare triple {3459#(<= (div (+ (- 115964059107) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 120259084288)) 4294967296) 55))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3455#(<= (div (+ (* (- 1) main_~s~0) (- 111669091556)) (- 4294967296)) (+ 53 (div (+ main_~s~0 (- 115964116992)) 4294967296)))} is VALID [2022-04-15 01:33:00,406 INFO L290 TraceCheckUtils]: 8: Hoare triple {3463#(<= (div (+ (* (- 1) main_~s~0) (- 120259026658)) (- 4294967296)) (+ (div (+ main_~s~0 (- 124554051584)) 4294967296) 57))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3459#(<= (div (+ (- 115964059107) (* (- 1) main_~s~0)) (- 4294967296)) (+ (div (+ main_~s~0 (- 120259084288)) 4294967296) 55))} is VALID [2022-04-15 01:33:00,412 INFO L290 TraceCheckUtils]: 7: Hoare triple {3467#(<= (div (+ (- 124553994209) (* (- 1) main_~s~0)) (- 4294967296)) (+ 59 (div (+ main_~s~0 (- 128849018880)) 4294967296)))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {3463#(<= (div (+ (* (- 1) main_~s~0) (- 120259026658)) (- 4294967296)) (+ (div (+ main_~s~0 (- 124554051584)) 4294967296) 57))} is VALID [2022-04-15 01:33:00,413 INFO L290 TraceCheckUtils]: 6: Hoare triple {3178#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {3467#(<= (div (+ (- 124553994209) (* (- 1) main_~s~0)) (- 4294967296)) (+ 59 (div (+ main_~s~0 (- 128849018880)) 4294967296)))} is VALID [2022-04-15 01:33:00,413 INFO L290 TraceCheckUtils]: 5: Hoare triple {3178#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {3178#true} is VALID [2022-04-15 01:33:00,413 INFO L272 TraceCheckUtils]: 4: Hoare triple {3178#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:33:00,413 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3178#true} {3178#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:33:00,413 INFO L290 TraceCheckUtils]: 2: Hoare triple {3178#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:33:00,413 INFO L290 TraceCheckUtils]: 1: Hoare triple {3178#true} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3178#true} is VALID [2022-04-15 01:33:00,413 INFO L272 TraceCheckUtils]: 0: Hoare triple {3178#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3178#true} is VALID [2022-04-15 01:33:00,414 INFO L134 CoverageAnalysis]: Checked inductivity of 465 backedges. 0 proven. 465 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:33:00,414 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1538355585] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-15 01:33:00,414 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-15 01:33:00,414 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33, 33] total 65 [2022-04-15 01:33:00,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489515102] [2022-04-15 01:33:00,414 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-15 01:33:00,415 INFO L78 Accepts]: Start accepts. Automaton has has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 41 [2022-04-15 01:33:00,415 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-15 01:33:00,415 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:00,704 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 77 edges. 77 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:33:00,704 INFO L554 AbstractCegarLoop]: INTERPOLANT automaton has 65 states [2022-04-15 01:33:00,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-15 01:33:00,705 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2022-04-15 01:33:00,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2018, Invalid=2142, Unknown=0, NotChecked=0, Total=4160 [2022-04-15 01:33:00,706 INFO L87 Difference]: Start difference. First operand 61 states and 77 transitions. Second operand has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:05,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:33:05,781 INFO L93 Difference]: Finished difference Result 142 states and 189 transitions. [2022-04-15 01:33:05,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-04-15 01:33:05,781 INFO L78 Accepts]: Start accepts. Automaton has has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 41 [2022-04-15 01:33:05,781 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-15 01:33:05,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:05,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 189 transitions. [2022-04-15 01:33:05,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:05,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 189 transitions. [2022-04-15 01:33:05,792 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 65 states and 189 transitions. [2022-04-15 01:33:07,012 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 189 edges. 189 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-15 01:33:07,013 INFO L225 Difference]: With dead ends: 142 [2022-04-15 01:33:07,013 INFO L226 Difference]: Without dead ends: 92 [2022-04-15 01:33:07,017 INFO L912 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 23 SyntacticMatches, 31 SemanticMatches, 125 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2791 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=6048, Invalid=9954, Unknown=0, NotChecked=0, Total=16002 [2022-04-15 01:33:07,017 INFO L913 BasicCegarLoop]: 11 mSDtfsCounter, 265 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 171 mSolverCounterSat, 166 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 265 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 337 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 166 IncrementalHoareTripleChecker+Valid, 171 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-04-15 01:33:07,017 INFO L914 BasicCegarLoop]: SdHoareTripleChecker [265 Valid, 38 Invalid, 337 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [166 Valid, 171 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-04-15 01:33:07,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 92 states. [2022-04-15 01:33:07,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 92 to 77. [2022-04-15 01:33:07,144 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-15 01:33:07,144 INFO L82 GeneralOperation]: Start isEquivalent. First operand 92 states. Second operand has 77 states, 72 states have (on average 1.25) internal successors, (90), 73 states have internal predecessors, (90), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:07,145 INFO L74 IsIncluded]: Start isIncluded. First operand 92 states. Second operand has 77 states, 72 states have (on average 1.25) internal successors, (90), 73 states have internal predecessors, (90), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:07,145 INFO L87 Difference]: Start difference. First operand 92 states. Second operand has 77 states, 72 states have (on average 1.25) internal successors, (90), 73 states have internal predecessors, (90), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:07,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:33:07,146 INFO L93 Difference]: Finished difference Result 92 states and 108 transitions. [2022-04-15 01:33:07,146 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 108 transitions. [2022-04-15 01:33:07,146 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:33:07,146 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:33:07,147 INFO L74 IsIncluded]: Start isIncluded. First operand has 77 states, 72 states have (on average 1.25) internal successors, (90), 73 states have internal predecessors, (90), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 92 states. [2022-04-15 01:33:07,147 INFO L87 Difference]: Start difference. First operand has 77 states, 72 states have (on average 1.25) internal successors, (90), 73 states have internal predecessors, (90), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 92 states. [2022-04-15 01:33:07,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-15 01:33:07,148 INFO L93 Difference]: Finished difference Result 92 states and 108 transitions. [2022-04-15 01:33:07,148 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 108 transitions. [2022-04-15 01:33:07,148 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-15 01:33:07,148 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-15 01:33:07,148 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-15 01:33:07,148 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-15 01:33:07,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 72 states have (on average 1.25) internal successors, (90), 73 states have internal predecessors, (90), 2 states have call successors, (2), 2 states have call predecessors, (2), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:07,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 93 transitions. [2022-04-15 01:33:07,149 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 93 transitions. Word has length 41 [2022-04-15 01:33:07,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-15 01:33:07,150 INFO L478 AbstractCegarLoop]: Abstraction has 77 states and 93 transitions. [2022-04-15 01:33:07,150 INFO L479 AbstractCegarLoop]: INTERPOLANT automaton has has 65 states, 65 states have (on average 1.123076923076923) internal successors, (73), 64 states have internal predecessors, (73), 1 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-15 01:33:07,150 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 93 transitions. [2022-04-15 01:33:07,150 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2022-04-15 01:33:07,151 INFO L491 BasicCegarLoop]: Found error trace [2022-04-15 01:33:07,151 INFO L499 BasicCegarLoop]: trace histogram [46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-15 01:33:07,179 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-15 01:33:07,363 WARN L460 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-04-15 01:33:07,363 INFO L403 AbstractCegarLoop]: === Iteration 11 === Targeting mainErr0ASSERT_VIOLATIONERROR_FUNCTION === [mainErr0ASSERT_VIOLATIONERROR_FUNCTION, mainErr1ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-15 01:33:07,363 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-15 01:33:07,364 INFO L85 PathProgramCache]: Analyzing trace with hash -1851342374, now seen corresponding path program 5 times [2022-04-15 01:33:07,364 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-15 01:33:07,364 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1869809277] [2022-04-15 01:33:07,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-15 01:33:07,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-15 01:33:07,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:33:08,587 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-15 01:33:08,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-15 01:33:08,600 INFO L290 TraceCheckUtils]: 0: Hoare triple {4204#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4152#true} is VALID [2022-04-15 01:33:08,600 INFO L290 TraceCheckUtils]: 1: Hoare triple {4152#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4152#true} is VALID [2022-04-15 01:33:08,600 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4152#true} {4152#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4152#true} is VALID [2022-04-15 01:33:08,601 INFO L272 TraceCheckUtils]: 0: Hoare triple {4152#true} [41] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4204#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-15 01:33:08,601 INFO L290 TraceCheckUtils]: 1: Hoare triple {4204#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [43] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (= (select |v_#length_1| 2) 26) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4152#true} is VALID [2022-04-15 01:33:08,601 INFO L290 TraceCheckUtils]: 2: Hoare triple {4152#true} [46] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4152#true} is VALID [2022-04-15 01:33:08,601 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4152#true} {4152#true} [61] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4152#true} is VALID [2022-04-15 01:33:08,601 INFO L272 TraceCheckUtils]: 4: Hoare triple {4152#true} [42] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4152#true} is VALID [2022-04-15 01:33:08,602 INFO L290 TraceCheckUtils]: 5: Hoare triple {4152#true} [45] mainENTRY-->L6: Formula: (= v_main_~n~0_1 |v_main_#t~nondet4_2|) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~n~0=v_main_~n~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~n~0] {4152#true} is VALID [2022-04-15 01:33:08,602 INFO L290 TraceCheckUtils]: 6: Hoare triple {4152#true} [48] L6-->L12-2: Formula: (and (= v_main_~i~0_1 0) (= v_main_~s~0_3 0) (= v_main_~v~0_1 0) (not (= (mod v_main_~n~0_3 256) 0))) InVars {main_~n~0=v_main_~n~0_3} OutVars{main_~i~0=v_main_~i~0_1, main_~v~0=v_main_~v~0_1, main_~n~0=v_main_~n~0_3, main_~s~0=v_main_~s~0_3} AuxVars[] AssignedVars[main_~v~0, main_~i~0, main_~s~0] {4157#(= main_~s~0 0)} is VALID [2022-04-15 01:33:08,603 INFO L290 TraceCheckUtils]: 7: Hoare triple {4157#(= main_~s~0 0)} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4158#(and (<= 0 main_~s~0) (<= main_~s~0 255))} is VALID [2022-04-15 01:33:08,604 INFO L290 TraceCheckUtils]: 8: Hoare triple {4158#(and (<= 0 main_~s~0) (<= main_~s~0 255))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4159#(and (<= main_~s~0 510) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,604 INFO L290 TraceCheckUtils]: 9: Hoare triple {4159#(and (<= main_~s~0 510) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4160#(and (<= main_~s~0 765) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,605 INFO L290 TraceCheckUtils]: 10: Hoare triple {4160#(and (<= main_~s~0 765) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4161#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} is VALID [2022-04-15 01:33:08,606 INFO L290 TraceCheckUtils]: 11: Hoare triple {4161#(and (<= 0 main_~s~0) (<= main_~s~0 1020))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4162#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} is VALID [2022-04-15 01:33:08,606 INFO L290 TraceCheckUtils]: 12: Hoare triple {4162#(and (<= 0 main_~s~0) (<= main_~s~0 1275))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4163#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} is VALID [2022-04-15 01:33:08,607 INFO L290 TraceCheckUtils]: 13: Hoare triple {4163#(and (<= 0 main_~s~0) (<= main_~s~0 1530))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4164#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} is VALID [2022-04-15 01:33:08,608 INFO L290 TraceCheckUtils]: 14: Hoare triple {4164#(and (<= 0 main_~s~0) (<= main_~s~0 1785))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4165#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,609 INFO L290 TraceCheckUtils]: 15: Hoare triple {4165#(and (<= main_~s~0 2040) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4166#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} is VALID [2022-04-15 01:33:08,609 INFO L290 TraceCheckUtils]: 16: Hoare triple {4166#(and (<= 0 main_~s~0) (<= main_~s~0 2295))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4167#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,610 INFO L290 TraceCheckUtils]: 17: Hoare triple {4167#(and (<= main_~s~0 2550) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4168#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} is VALID [2022-04-15 01:33:08,610 INFO L290 TraceCheckUtils]: 18: Hoare triple {4168#(and (<= 0 main_~s~0) (<= main_~s~0 2805))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4169#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,611 INFO L290 TraceCheckUtils]: 19: Hoare triple {4169#(and (<= main_~s~0 3060) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4170#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,612 INFO L290 TraceCheckUtils]: 20: Hoare triple {4170#(and (<= main_~s~0 3315) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4171#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,613 INFO L290 TraceCheckUtils]: 21: Hoare triple {4171#(and (<= main_~s~0 3570) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4172#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} is VALID [2022-04-15 01:33:08,614 INFO L290 TraceCheckUtils]: 22: Hoare triple {4172#(and (<= 0 main_~s~0) (<= main_~s~0 3825))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4173#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} is VALID [2022-04-15 01:33:08,614 INFO L290 TraceCheckUtils]: 23: Hoare triple {4173#(and (<= 0 main_~s~0) (<= main_~s~0 4080))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4174#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} is VALID [2022-04-15 01:33:08,615 INFO L290 TraceCheckUtils]: 24: Hoare triple {4174#(and (<= 0 main_~s~0) (<= main_~s~0 4335))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4175#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,616 INFO L290 TraceCheckUtils]: 25: Hoare triple {4175#(and (<= main_~s~0 4590) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4176#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} is VALID [2022-04-15 01:33:08,617 INFO L290 TraceCheckUtils]: 26: Hoare triple {4176#(and (<= 0 main_~s~0) (<= main_~s~0 4845))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4177#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} is VALID [2022-04-15 01:33:08,618 INFO L290 TraceCheckUtils]: 27: Hoare triple {4177#(and (<= 0 main_~s~0) (<= main_~s~0 5100))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4178#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} is VALID [2022-04-15 01:33:08,618 INFO L290 TraceCheckUtils]: 28: Hoare triple {4178#(and (<= 0 main_~s~0) (<= main_~s~0 5355))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4179#(and (<= main_~s~0 5610) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,619 INFO L290 TraceCheckUtils]: 29: Hoare triple {4179#(and (<= main_~s~0 5610) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4180#(and (<= main_~s~0 5865) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,620 INFO L290 TraceCheckUtils]: 30: Hoare triple {4180#(and (<= main_~s~0 5865) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4181#(and (<= 0 main_~s~0) (<= main_~s~0 6120))} is VALID [2022-04-15 01:33:08,621 INFO L290 TraceCheckUtils]: 31: Hoare triple {4181#(and (<= 0 main_~s~0) (<= main_~s~0 6120))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4182#(and (<= main_~s~0 6375) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,622 INFO L290 TraceCheckUtils]: 32: Hoare triple {4182#(and (<= main_~s~0 6375) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4183#(and (<= main_~s~0 6630) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,622 INFO L290 TraceCheckUtils]: 33: Hoare triple {4183#(and (<= main_~s~0 6630) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4184#(and (<= main_~s~0 6885) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,623 INFO L290 TraceCheckUtils]: 34: Hoare triple {4184#(and (<= main_~s~0 6885) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4185#(and (<= main_~s~0 7140) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,624 INFO L290 TraceCheckUtils]: 35: Hoare triple {4185#(and (<= main_~s~0 7140) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4186#(and (<= 0 main_~s~0) (<= main_~s~0 7395))} is VALID [2022-04-15 01:33:08,625 INFO L290 TraceCheckUtils]: 36: Hoare triple {4186#(and (<= 0 main_~s~0) (<= main_~s~0 7395))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4187#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} is VALID [2022-04-15 01:33:08,625 INFO L290 TraceCheckUtils]: 37: Hoare triple {4187#(and (<= 0 main_~s~0) (<= main_~s~0 7650))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4188#(and (<= main_~s~0 7905) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,626 INFO L290 TraceCheckUtils]: 38: Hoare triple {4188#(and (<= main_~s~0 7905) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4189#(and (<= main_~s~0 8160) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,627 INFO L290 TraceCheckUtils]: 39: Hoare triple {4189#(and (<= main_~s~0 8160) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4190#(and (<= main_~s~0 8415) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,627 INFO L290 TraceCheckUtils]: 40: Hoare triple {4190#(and (<= main_~s~0 8415) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4191#(and (<= 0 main_~s~0) (<= main_~s~0 8670))} is VALID [2022-04-15 01:33:08,628 INFO L290 TraceCheckUtils]: 41: Hoare triple {4191#(and (<= 0 main_~s~0) (<= main_~s~0 8670))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4192#(and (<= main_~s~0 8925) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,629 INFO L290 TraceCheckUtils]: 42: Hoare triple {4192#(and (<= main_~s~0 8925) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4193#(and (<= 0 main_~s~0) (<= main_~s~0 9180))} is VALID [2022-04-15 01:33:08,629 INFO L290 TraceCheckUtils]: 43: Hoare triple {4193#(and (<= 0 main_~s~0) (<= main_~s~0 9180))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4194#(and (<= main_~s~0 9435) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,630 INFO L290 TraceCheckUtils]: 44: Hoare triple {4194#(and (<= main_~s~0 9435) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4195#(and (<= main_~s~0 9690) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,631 INFO L290 TraceCheckUtils]: 45: Hoare triple {4195#(and (<= main_~s~0 9690) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4196#(and (<= 0 main_~s~0) (<= main_~s~0 9945))} is VALID [2022-04-15 01:33:08,631 INFO L290 TraceCheckUtils]: 46: Hoare triple {4196#(and (<= 0 main_~s~0) (<= main_~s~0 9945))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4197#(and (<= 0 main_~s~0) (<= main_~s~0 10200))} is VALID [2022-04-15 01:33:08,632 INFO L290 TraceCheckUtils]: 47: Hoare triple {4197#(and (<= 0 main_~s~0) (<= main_~s~0 10200))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4198#(and (<= 0 main_~s~0) (<= main_~s~0 10455))} is VALID [2022-04-15 01:33:08,633 INFO L290 TraceCheckUtils]: 48: Hoare triple {4198#(and (<= 0 main_~s~0) (<= main_~s~0 10455))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4199#(and (<= 0 main_~s~0) (<= main_~s~0 10710))} is VALID [2022-04-15 01:33:08,633 INFO L290 TraceCheckUtils]: 49: Hoare triple {4199#(and (<= 0 main_~s~0) (<= main_~s~0 10710))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4200#(and (<= main_~s~0 10965) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,634 INFO L290 TraceCheckUtils]: 50: Hoare triple {4200#(and (<= main_~s~0 10965) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4201#(and (<= main_~s~0 11220) (<= 0 main_~s~0))} is VALID [2022-04-15 01:33:08,635 INFO L290 TraceCheckUtils]: 51: Hoare triple {4201#(and (<= main_~s~0 11220) (<= 0 main_~s~0))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4202#(and (<= 0 main_~s~0) (<= main_~s~0 11475))} is VALID [2022-04-15 01:33:08,636 INFO L290 TraceCheckUtils]: 52: Hoare triple {4202#(and (<= 0 main_~s~0) (<= main_~s~0 11475))} [52] L12-2-->L12-2: Formula: (and (= v_main_~s~0_4 (+ v_main_~s~0_5 (mod v_main_~v~0_2 256))) (= v_main_~i~0_3 (+ v_main_~i~0_4 1)) (< (mod v_main_~i~0_4 4294967296) (mod v_main_~n~0_5 256)) (= v_main_~v~0_2 |v_main_#t~nondet5_2|)) InVars {main_#t~nondet5=|v_main_#t~nondet5_2|, main_~i~0=v_main_~i~0_4, main_~n~0=v_main_~n~0_5, main_~s~0=v_main_~s~0_5} OutVars{main_~i~0=v_main_~i~0_3, main_~v~0=v_main_~v~0_2, main_~n~0=v_main_~n~0_5, main_#t~pre6=|v_main_#t~pre6_1|, main_~s~0=v_main_~s~0_4} AuxVars[] AssignedVars[main_#t~nondet5, main_~v~0, main_~i~0, main_#t~pre6, main_~s~0] {4203#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:33:08,636 INFO L290 TraceCheckUtils]: 53: Hoare triple {4203#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [51] L12-2-->L12-3: Formula: (not (< (mod v_main_~i~0_2 4294967296) (mod v_main_~n~0_4 256))) InVars {main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} OutVars{main_~i~0=v_main_~i~0_2, main_~n~0=v_main_~n~0_4} AuxVars[] AssignedVars[] {4203#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} is VALID [2022-04-15 01:33:08,636 INFO L290 TraceCheckUtils]: 54: Hoare triple {4203#(and (<= (div main_~s~0 4294967296) 0) (<= main_~v~0 (+ main_~s~0 (* (div main_~v~0 256) 256))))} [53] L12-3-->L18: Formula: (< (mod v_main_~s~0_6 4294967296) (mod v_main_~v~0_3 256)) InVars {main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} OutVars{main_~v~0=v_main_~v~0_3, main_~s~0=v_main_~s~0_6} AuxVars[] AssignedVars[] {4153#false} is VALID [2022-04-15 01:33:08,637 INFO L290 TraceCheckUtils]: 55: Hoare triple {4153#false} [55] L18-->mainErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4153#false} is VALID [2022-04-15 01:33:08,637 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-15 01:33:08,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-15 01:33:08,637 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1869809277] [2022-04-15 01:33:08,638 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1869809277] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-15 01:33:08,638 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [834763366] [2022-04-15 01:33:08,638 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-15 01:33:08,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-15 01:33:08,638 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-15 01:33:08,639 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-15 01:33:08,639 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process