/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array_1-1.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 16:00:02,973 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 16:00:02,974 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 16:00:03,027 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 16:00:03,027 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 16:00:03,028 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 16:00:03,029 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 16:00:03,030 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 16:00:03,036 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 16:00:03,051 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 16:00:03,052 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 16:00:03,053 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 16:00:03,053 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 16:00:03,053 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 16:00:03,054 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 16:00:03,054 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 16:00:03,055 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 16:00:03,055 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 16:00:03,056 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 16:00:03,057 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 16:00:03,058 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 16:00:03,062 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 16:00:03,062 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 16:00:03,063 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 16:00:03,063 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 16:00:03,065 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 16:00:03,069 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 16:00:03,069 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 16:00:03,073 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 16:00:03,074 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 16:00:03,085 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 16:00:03,085 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 16:00:03,086 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 16:00:03,086 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 16:00:03,086 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 16:00:03,086 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 16:00:03,087 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 16:00:03,087 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 16:00:03,087 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 16:00:03,087 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 16:00:03,087 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 16:00:03,088 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 16:00:03,088 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:00:03,088 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 16:00:03,089 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 16:00:03,089 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 16:00:03,089 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 16:00:03,283 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 16:00:03,299 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 16:00:03,301 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 16:00:03,301 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 16:00:03,302 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 16:00:03,302 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array_1-1.c [2022-04-27 16:00:03,350 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e2d37ad65/9d793cb39fd7481b89383217717cabd3/FLAGc3682eb54 [2022-04-27 16:00:03,697 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 16:00:03,697 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_1-1.c [2022-04-27 16:00:03,701 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e2d37ad65/9d793cb39fd7481b89383217717cabd3/FLAGc3682eb54 [2022-04-27 16:00:03,711 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/e2d37ad65/9d793cb39fd7481b89383217717cabd3 [2022-04-27 16:00:03,713 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 16:00:03,714 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 16:00:03,715 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 16:00:03,715 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 16:00:03,718 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 16:00:03,719 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,720 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@206a4175 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03, skipping insertion in model container [2022-04-27 16:00:03,720 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,724 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 16:00:03,733 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 16:00:03,840 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_1-1.c[321,334] [2022-04-27 16:00:03,852 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:00:03,858 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 16:00:03,865 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_1-1.c[321,334] [2022-04-27 16:00:03,867 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:00:03,879 INFO L208 MainTranslator]: Completed translation [2022-04-27 16:00:03,880 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03 WrapperNode [2022-04-27 16:00:03,880 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 16:00:03,880 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 16:00:03,881 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 16:00:03,881 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 16:00:03,887 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,887 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,891 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,891 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,895 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,897 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,898 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,898 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 16:00:03,899 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 16:00:03,899 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 16:00:03,899 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 16:00:03,900 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (1/1) ... [2022-04-27 16:00:03,904 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:00:03,911 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:03,920 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 16:00:03,925 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 16:00:03,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 16:00:03,947 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 16:00:03,947 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 16:00:03,947 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 16:00:03,948 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 16:00:03,948 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-27 16:00:03,949 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 16:00:03,949 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 16:00:03,949 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 16:00:03,951 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 16:00:03,951 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 16:00:03,951 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 16:00:03,990 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 16:00:03,991 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 16:00:04,068 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 16:00:04,072 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 16:00:04,072 INFO L299 CfgBuilder]: Removed 1 assume(true) statements. [2022-04-27 16:00:04,074 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:00:04 BoogieIcfgContainer [2022-04-27 16:00:04,074 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 16:00:04,074 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 16:00:04,074 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 16:00:04,081 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 16:00:04,084 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:00:04" (1/1) ... [2022-04-27 16:00:04,086 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 16:00:04,100 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:00:04 BasicIcfg [2022-04-27 16:00:04,100 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 16:00:04,101 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 16:00:04,102 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 16:00:04,103 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 16:00:04,111 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 04:00:03" (1/4) ... [2022-04-27 16:00:04,111 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b1a455c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:00:04, skipping insertion in model container [2022-04-27 16:00:04,112 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:00:03" (2/4) ... [2022-04-27 16:00:04,112 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b1a455c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:00:04, skipping insertion in model container [2022-04-27 16:00:04,112 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:00:04" (3/4) ... [2022-04-27 16:00:04,112 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4b1a455c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 04:00:04, skipping insertion in model container [2022-04-27 16:00:04,112 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:00:04" (4/4) ... [2022-04-27 16:00:04,113 INFO L111 eAbstractionObserver]: Analyzing ICFG array_1-1.cJordan [2022-04-27 16:00:04,122 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 16:00:04,126 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 16:00:04,181 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 16:00:04,199 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@591191ad, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@312e838e [2022-04-27 16:00:04,200 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 16:00:04,208 INFO L276 IsEmpty]: Start isEmpty. Operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 16:00:04,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-04-27 16:00:04,212 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:04,212 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:04,213 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:04,216 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:04,216 INFO L85 PathProgramCache]: Analyzing trace with hash -737742564, now seen corresponding path program 1 times [2022-04-27 16:00:04,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:04,222 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [238412673] [2022-04-27 16:00:04,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:04,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:04,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,331 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:04,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,348 INFO L290 TraceCheckUtils]: 0: Hoare triple {29#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {24#true} is VALID [2022-04-27 16:00:04,349 INFO L290 TraceCheckUtils]: 1: Hoare triple {24#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 16:00:04,349 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {24#true} {24#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 16:00:04,356 INFO L272 TraceCheckUtils]: 0: Hoare triple {24#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {29#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:04,356 INFO L290 TraceCheckUtils]: 1: Hoare triple {29#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {24#true} is VALID [2022-04-27 16:00:04,356 INFO L290 TraceCheckUtils]: 2: Hoare triple {24#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 16:00:04,356 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {24#true} {24#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 16:00:04,357 INFO L272 TraceCheckUtils]: 4: Hoare triple {24#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 16:00:04,357 INFO L290 TraceCheckUtils]: 5: Hoare triple {24#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {24#true} is VALID [2022-04-27 16:00:04,362 INFO L290 TraceCheckUtils]: 6: Hoare triple {24#true} [48] L16-3-->L16-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {25#false} is VALID [2022-04-27 16:00:04,363 INFO L290 TraceCheckUtils]: 7: Hoare triple {25#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {25#false} is VALID [2022-04-27 16:00:04,363 INFO L272 TraceCheckUtils]: 8: Hoare triple {25#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {25#false} is VALID [2022-04-27 16:00:04,363 INFO L290 TraceCheckUtils]: 9: Hoare triple {25#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {25#false} is VALID [2022-04-27 16:00:04,363 INFO L290 TraceCheckUtils]: 10: Hoare triple {25#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {25#false} is VALID [2022-04-27 16:00:04,364 INFO L290 TraceCheckUtils]: 11: Hoare triple {25#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {25#false} is VALID [2022-04-27 16:00:04,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:04,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:04,364 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [238412673] [2022-04-27 16:00:04,365 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [238412673] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:00:04,365 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:00:04,365 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 16:00:04,366 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808620463] [2022-04-27 16:00:04,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:00:04,370 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 16:00:04,371 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:04,373 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,392 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 12 edges. 12 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:04,393 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 16:00:04,393 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:04,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 16:00:04,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:00:04,414 INFO L87 Difference]: Start difference. First operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:04,475 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-27 16:00:04,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 16:00:04,476 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 16:00:04,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:04,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,489 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 23 transitions. [2022-04-27 16:00:04,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 23 transitions. [2022-04-27 16:00:04,493 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 23 transitions. [2022-04-27 16:00:04,522 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:04,529 INFO L225 Difference]: With dead ends: 21 [2022-04-27 16:00:04,529 INFO L226 Difference]: Without dead ends: 14 [2022-04-27 16:00:04,530 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:00:04,535 INFO L413 NwaCegarLoop]: 20 mSDtfsCounter, 12 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 23 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:04,536 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 23 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:00:04,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2022-04-27 16:00:04,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2022-04-27 16:00:04,554 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:04,554 INFO L82 GeneralOperation]: Start isEquivalent. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,555 INFO L74 IsIncluded]: Start isIncluded. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,555 INFO L87 Difference]: Start difference. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:04,559 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2022-04-27 16:00:04,559 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-27 16:00:04,560 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:04,560 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:04,560 INFO L74 IsIncluded]: Start isIncluded. First operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 14 states. [2022-04-27 16:00:04,561 INFO L87 Difference]: Start difference. First operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 14 states. [2022-04-27 16:00:04,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:04,565 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2022-04-27 16:00:04,565 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-27 16:00:04,565 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:04,565 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:04,566 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:04,566 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:04,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,567 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2022-04-27 16:00:04,568 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 12 [2022-04-27 16:00:04,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:04,568 INFO L495 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2022-04-27 16:00:04,568 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,568 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-27 16:00:04,569 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-04-27 16:00:04,569 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:04,570 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:04,570 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 16:00:04,573 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:04,581 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:04,581 INFO L85 PathProgramCache]: Analyzing trace with hash -709113413, now seen corresponding path program 1 times [2022-04-27 16:00:04,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:04,581 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700336430] [2022-04-27 16:00:04,582 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:04,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:04,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,628 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:04,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,650 INFO L290 TraceCheckUtils]: 0: Hoare triple {101#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {95#true} is VALID [2022-04-27 16:00:04,650 INFO L290 TraceCheckUtils]: 1: Hoare triple {95#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {95#true} is VALID [2022-04-27 16:00:04,650 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {95#true} {95#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {95#true} is VALID [2022-04-27 16:00:04,652 INFO L272 TraceCheckUtils]: 0: Hoare triple {95#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {101#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:04,652 INFO L290 TraceCheckUtils]: 1: Hoare triple {101#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {95#true} is VALID [2022-04-27 16:00:04,652 INFO L290 TraceCheckUtils]: 2: Hoare triple {95#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {95#true} is VALID [2022-04-27 16:00:04,652 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {95#true} {95#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {95#true} is VALID [2022-04-27 16:00:04,652 INFO L272 TraceCheckUtils]: 4: Hoare triple {95#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {95#true} is VALID [2022-04-27 16:00:04,653 INFO L290 TraceCheckUtils]: 5: Hoare triple {95#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {100#(= main_~i~0 0)} is VALID [2022-04-27 16:00:04,653 INFO L290 TraceCheckUtils]: 6: Hoare triple {100#(= main_~i~0 0)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {96#false} is VALID [2022-04-27 16:00:04,653 INFO L290 TraceCheckUtils]: 7: Hoare triple {96#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {96#false} is VALID [2022-04-27 16:00:04,654 INFO L272 TraceCheckUtils]: 8: Hoare triple {96#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {96#false} is VALID [2022-04-27 16:00:04,654 INFO L290 TraceCheckUtils]: 9: Hoare triple {96#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {96#false} is VALID [2022-04-27 16:00:04,654 INFO L290 TraceCheckUtils]: 10: Hoare triple {96#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {96#false} is VALID [2022-04-27 16:00:04,654 INFO L290 TraceCheckUtils]: 11: Hoare triple {96#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {96#false} is VALID [2022-04-27 16:00:04,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:04,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:04,655 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700336430] [2022-04-27 16:00:04,655 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700336430] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:00:04,655 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:00:04,655 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 16:00:04,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [719993363] [2022-04-27 16:00:04,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:00:04,656 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 16:00:04,657 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:04,657 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,671 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 12 edges. 12 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:04,671 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 16:00:04,671 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:04,672 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 16:00:04,672 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 16:00:04,673 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:04,724 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 16:00:04,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 16:00:04,725 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 16:00:04,725 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:04,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,727 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 17 transitions. [2022-04-27 16:00:04,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 17 transitions. [2022-04-27 16:00:04,728 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 17 transitions. [2022-04-27 16:00:04,749 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:04,751 INFO L225 Difference]: With dead ends: 16 [2022-04-27 16:00:04,751 INFO L226 Difference]: Without dead ends: 16 [2022-04-27 16:00:04,752 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 16:00:04,754 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 10 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 19 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:04,754 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 19 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:00:04,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2022-04-27 16:00:04,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2022-04-27 16:00:04,758 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:04,758 INFO L82 GeneralOperation]: Start isEquivalent. First operand 16 states. Second operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,758 INFO L74 IsIncluded]: Start isIncluded. First operand 16 states. Second operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,758 INFO L87 Difference]: Start difference. First operand 16 states. Second operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:04,765 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 16:00:04,765 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 16:00:04,765 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:04,765 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:04,766 INFO L74 IsIncluded]: Start isIncluded. First operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 16:00:04,766 INFO L87 Difference]: Start difference. First operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 16:00:04,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:04,767 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 16:00:04,767 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 16:00:04,768 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:04,768 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:04,768 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:04,768 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:04,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2022-04-27 16:00:04,769 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 12 [2022-04-27 16:00:04,769 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:04,769 INFO L495 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2022-04-27 16:00:04,769 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:04,769 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2022-04-27 16:00:04,769 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-04-27 16:00:04,770 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:04,770 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:04,770 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 16:00:04,770 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:04,770 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:04,770 INFO L85 PathProgramCache]: Analyzing trace with hash -341174979, now seen corresponding path program 1 times [2022-04-27 16:00:04,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:04,771 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556015636] [2022-04-27 16:00:04,771 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:04,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:04,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,816 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:04,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,823 INFO L290 TraceCheckUtils]: 0: Hoare triple {176#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {169#true} is VALID [2022-04-27 16:00:04,823 INFO L290 TraceCheckUtils]: 1: Hoare triple {169#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,823 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {169#true} {169#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,824 INFO L272 TraceCheckUtils]: 0: Hoare triple {169#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {176#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:04,824 INFO L290 TraceCheckUtils]: 1: Hoare triple {176#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {169#true} is VALID [2022-04-27 16:00:04,824 INFO L290 TraceCheckUtils]: 2: Hoare triple {169#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,824 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {169#true} {169#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,824 INFO L272 TraceCheckUtils]: 4: Hoare triple {169#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,825 INFO L290 TraceCheckUtils]: 5: Hoare triple {169#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {174#(= main_~i~0 0)} is VALID [2022-04-27 16:00:04,825 INFO L290 TraceCheckUtils]: 6: Hoare triple {174#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {174#(= main_~i~0 0)} is VALID [2022-04-27 16:00:04,826 INFO L290 TraceCheckUtils]: 7: Hoare triple {174#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {175#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:04,826 INFO L290 TraceCheckUtils]: 8: Hoare triple {175#(<= main_~i~0 1)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:04,826 INFO L290 TraceCheckUtils]: 9: Hoare triple {170#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {170#false} is VALID [2022-04-27 16:00:04,826 INFO L272 TraceCheckUtils]: 10: Hoare triple {170#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {170#false} is VALID [2022-04-27 16:00:04,826 INFO L290 TraceCheckUtils]: 11: Hoare triple {170#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {170#false} is VALID [2022-04-27 16:00:04,827 INFO L290 TraceCheckUtils]: 12: Hoare triple {170#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:04,827 INFO L290 TraceCheckUtils]: 13: Hoare triple {170#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:04,827 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:04,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:04,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [556015636] [2022-04-27 16:00:04,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [556015636] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:00:04,827 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1115867126] [2022-04-27 16:00:04,827 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:04,828 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:04,828 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:04,830 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:00:04,830 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 16:00:04,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,883 INFO L263 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 3 conjunts are in the unsatisfiable core [2022-04-27 16:00:04,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:04,904 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:00:04,982 INFO L272 TraceCheckUtils]: 0: Hoare triple {169#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,983 INFO L290 TraceCheckUtils]: 1: Hoare triple {169#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {169#true} is VALID [2022-04-27 16:00:04,987 INFO L290 TraceCheckUtils]: 2: Hoare triple {169#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,987 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {169#true} {169#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,987 INFO L272 TraceCheckUtils]: 4: Hoare triple {169#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:04,988 INFO L290 TraceCheckUtils]: 5: Hoare triple {169#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {195#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:04,988 INFO L290 TraceCheckUtils]: 6: Hoare triple {195#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {195#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:04,989 INFO L290 TraceCheckUtils]: 7: Hoare triple {195#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {175#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:04,991 INFO L290 TraceCheckUtils]: 8: Hoare triple {175#(<= main_~i~0 1)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:04,991 INFO L290 TraceCheckUtils]: 9: Hoare triple {170#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {170#false} is VALID [2022-04-27 16:00:04,991 INFO L272 TraceCheckUtils]: 10: Hoare triple {170#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {170#false} is VALID [2022-04-27 16:00:04,991 INFO L290 TraceCheckUtils]: 11: Hoare triple {170#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {170#false} is VALID [2022-04-27 16:00:04,992 INFO L290 TraceCheckUtils]: 12: Hoare triple {170#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:04,992 INFO L290 TraceCheckUtils]: 13: Hoare triple {170#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:04,992 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:04,992 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:00:05,071 INFO L290 TraceCheckUtils]: 13: Hoare triple {170#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:05,072 INFO L290 TraceCheckUtils]: 12: Hoare triple {170#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:05,072 INFO L290 TraceCheckUtils]: 11: Hoare triple {170#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {170#false} is VALID [2022-04-27 16:00:05,072 INFO L272 TraceCheckUtils]: 10: Hoare triple {170#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {170#false} is VALID [2022-04-27 16:00:05,072 INFO L290 TraceCheckUtils]: 9: Hoare triple {170#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {170#false} is VALID [2022-04-27 16:00:05,072 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {170#false} is VALID [2022-04-27 16:00:05,073 INFO L290 TraceCheckUtils]: 7: Hoare triple {239#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {235#(< main_~i~0 1024)} is VALID [2022-04-27 16:00:05,074 INFO L290 TraceCheckUtils]: 6: Hoare triple {239#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {239#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:05,074 INFO L290 TraceCheckUtils]: 5: Hoare triple {169#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {239#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:05,074 INFO L272 TraceCheckUtils]: 4: Hoare triple {169#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:05,074 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {169#true} {169#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:05,074 INFO L290 TraceCheckUtils]: 2: Hoare triple {169#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:05,075 INFO L290 TraceCheckUtils]: 1: Hoare triple {169#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {169#true} is VALID [2022-04-27 16:00:05,075 INFO L272 TraceCheckUtils]: 0: Hoare triple {169#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {169#true} is VALID [2022-04-27 16:00:05,075 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:05,075 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1115867126] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:00:05,075 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:00:05,075 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-27 16:00:05,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1815987946] [2022-04-27 16:00:05,075 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:00:05,076 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-27 16:00:05,076 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:05,076 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,092 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:05,092 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:00:05,092 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:05,093 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:00:05,093 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2022-04-27 16:00:05,093 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:05,184 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-27 16:00:05,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 16:00:05,184 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-27 16:00:05,184 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:05,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,186 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 24 transitions. [2022-04-27 16:00:05,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 24 transitions. [2022-04-27 16:00:05,188 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 24 transitions. [2022-04-27 16:00:05,216 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 24 edges. 24 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:05,217 INFO L225 Difference]: With dead ends: 21 [2022-04-27 16:00:05,217 INFO L226 Difference]: Without dead ends: 21 [2022-04-27 16:00:05,217 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=80, Unknown=0, NotChecked=0, Total=132 [2022-04-27 16:00:05,220 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 17 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 16 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 17 SdHoareTripleChecker+Valid, 19 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 16 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:05,221 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [17 Valid, 19 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 16 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:00:05,221 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2022-04-27 16:00:05,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-04-27 16:00:05,224 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:05,224 INFO L82 GeneralOperation]: Start isEquivalent. First operand 21 states. Second operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,226 INFO L74 IsIncluded]: Start isIncluded. First operand 21 states. Second operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,226 INFO L87 Difference]: Start difference. First operand 21 states. Second operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:05,227 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-27 16:00:05,227 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-04-27 16:00:05,228 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:05,228 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:05,228 INFO L74 IsIncluded]: Start isIncluded. First operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 21 states. [2022-04-27 16:00:05,228 INFO L87 Difference]: Start difference. First operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 21 states. [2022-04-27 16:00:05,230 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:05,230 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-27 16:00:05,230 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-04-27 16:00:05,230 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:05,230 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:05,230 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:05,230 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:05,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2022-04-27 16:00:05,232 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 14 [2022-04-27 16:00:05,232 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:05,232 INFO L495 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2022-04-27 16:00:05,233 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,233 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-04-27 16:00:05,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:00:05,233 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:05,233 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:05,266 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-04-27 16:00:05,451 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:05,452 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:05,452 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:05,452 INFO L85 PathProgramCache]: Analyzing trace with hash -1847565117, now seen corresponding path program 2 times [2022-04-27 16:00:05,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:05,452 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139816575] [2022-04-27 16:00:05,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:05,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:05,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:05,534 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:05,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:05,546 INFO L290 TraceCheckUtils]: 0: Hoare triple {365#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {355#true} is VALID [2022-04-27 16:00:05,546 INFO L290 TraceCheckUtils]: 1: Hoare triple {355#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,546 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {355#true} {355#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,546 INFO L272 TraceCheckUtils]: 0: Hoare triple {355#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {365#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:05,547 INFO L290 TraceCheckUtils]: 1: Hoare triple {365#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {355#true} is VALID [2022-04-27 16:00:05,547 INFO L290 TraceCheckUtils]: 2: Hoare triple {355#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,547 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {355#true} {355#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,547 INFO L272 TraceCheckUtils]: 4: Hoare triple {355#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,551 INFO L290 TraceCheckUtils]: 5: Hoare triple {355#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {360#(= main_~i~0 0)} is VALID [2022-04-27 16:00:05,551 INFO L290 TraceCheckUtils]: 6: Hoare triple {360#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {360#(= main_~i~0 0)} is VALID [2022-04-27 16:00:05,552 INFO L290 TraceCheckUtils]: 7: Hoare triple {360#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {361#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:05,552 INFO L290 TraceCheckUtils]: 8: Hoare triple {361#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {361#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:05,553 INFO L290 TraceCheckUtils]: 9: Hoare triple {361#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {362#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:05,553 INFO L290 TraceCheckUtils]: 10: Hoare triple {362#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {362#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:05,554 INFO L290 TraceCheckUtils]: 11: Hoare triple {362#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {363#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:05,554 INFO L290 TraceCheckUtils]: 12: Hoare triple {363#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {363#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:05,555 INFO L290 TraceCheckUtils]: 13: Hoare triple {363#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {364#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:05,555 INFO L290 TraceCheckUtils]: 14: Hoare triple {364#(<= main_~i~0 4)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,555 INFO L290 TraceCheckUtils]: 15: Hoare triple {356#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {356#false} is VALID [2022-04-27 16:00:05,555 INFO L272 TraceCheckUtils]: 16: Hoare triple {356#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {356#false} is VALID [2022-04-27 16:00:05,555 INFO L290 TraceCheckUtils]: 17: Hoare triple {356#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {356#false} is VALID [2022-04-27 16:00:05,556 INFO L290 TraceCheckUtils]: 18: Hoare triple {356#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,556 INFO L290 TraceCheckUtils]: 19: Hoare triple {356#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,556 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:05,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:05,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2139816575] [2022-04-27 16:00:05,556 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2139816575] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:00:05,556 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [288939129] [2022-04-27 16:00:05,556 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:00:05,557 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:05,557 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:05,557 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:00:05,558 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 16:00:05,612 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:00:05,612 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:00:05,613 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:00:05,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:05,622 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:00:05,724 INFO L272 TraceCheckUtils]: 0: Hoare triple {355#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,724 INFO L290 TraceCheckUtils]: 1: Hoare triple {355#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {355#true} is VALID [2022-04-27 16:00:05,725 INFO L290 TraceCheckUtils]: 2: Hoare triple {355#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,725 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {355#true} {355#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,725 INFO L272 TraceCheckUtils]: 4: Hoare triple {355#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,727 INFO L290 TraceCheckUtils]: 5: Hoare triple {355#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {384#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:05,728 INFO L290 TraceCheckUtils]: 6: Hoare triple {384#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {384#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:05,728 INFO L290 TraceCheckUtils]: 7: Hoare triple {384#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {361#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:05,729 INFO L290 TraceCheckUtils]: 8: Hoare triple {361#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {361#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:05,729 INFO L290 TraceCheckUtils]: 9: Hoare triple {361#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {362#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:05,730 INFO L290 TraceCheckUtils]: 10: Hoare triple {362#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {362#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:05,730 INFO L290 TraceCheckUtils]: 11: Hoare triple {362#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {363#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:05,731 INFO L290 TraceCheckUtils]: 12: Hoare triple {363#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {363#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:05,732 INFO L290 TraceCheckUtils]: 13: Hoare triple {363#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {364#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:05,732 INFO L290 TraceCheckUtils]: 14: Hoare triple {364#(<= main_~i~0 4)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,733 INFO L290 TraceCheckUtils]: 15: Hoare triple {356#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {356#false} is VALID [2022-04-27 16:00:05,734 INFO L272 TraceCheckUtils]: 16: Hoare triple {356#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {356#false} is VALID [2022-04-27 16:00:05,734 INFO L290 TraceCheckUtils]: 17: Hoare triple {356#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {356#false} is VALID [2022-04-27 16:00:05,734 INFO L290 TraceCheckUtils]: 18: Hoare triple {356#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,735 INFO L290 TraceCheckUtils]: 19: Hoare triple {356#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,735 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:05,735 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:00:05,877 INFO L290 TraceCheckUtils]: 19: Hoare triple {356#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,878 INFO L290 TraceCheckUtils]: 18: Hoare triple {356#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,878 INFO L290 TraceCheckUtils]: 17: Hoare triple {356#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {356#false} is VALID [2022-04-27 16:00:05,878 INFO L272 TraceCheckUtils]: 16: Hoare triple {356#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {356#false} is VALID [2022-04-27 16:00:05,878 INFO L290 TraceCheckUtils]: 15: Hoare triple {356#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {356#false} is VALID [2022-04-27 16:00:05,890 INFO L290 TraceCheckUtils]: 14: Hoare triple {442#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {356#false} is VALID [2022-04-27 16:00:05,891 INFO L290 TraceCheckUtils]: 13: Hoare triple {446#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {442#(< main_~i~0 1024)} is VALID [2022-04-27 16:00:05,892 INFO L290 TraceCheckUtils]: 12: Hoare triple {446#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {446#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:05,892 INFO L290 TraceCheckUtils]: 11: Hoare triple {453#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {446#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:05,892 INFO L290 TraceCheckUtils]: 10: Hoare triple {453#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {453#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:05,893 INFO L290 TraceCheckUtils]: 9: Hoare triple {460#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {453#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:05,893 INFO L290 TraceCheckUtils]: 8: Hoare triple {460#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {460#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:05,894 INFO L290 TraceCheckUtils]: 7: Hoare triple {467#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {460#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:05,894 INFO L290 TraceCheckUtils]: 6: Hoare triple {467#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {467#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:05,895 INFO L290 TraceCheckUtils]: 5: Hoare triple {355#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {467#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:05,895 INFO L272 TraceCheckUtils]: 4: Hoare triple {355#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,895 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {355#true} {355#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,895 INFO L290 TraceCheckUtils]: 2: Hoare triple {355#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,895 INFO L290 TraceCheckUtils]: 1: Hoare triple {355#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {355#true} is VALID [2022-04-27 16:00:05,895 INFO L272 TraceCheckUtils]: 0: Hoare triple {355#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {355#true} is VALID [2022-04-27 16:00:05,895 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:05,896 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [288939129] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:00:05,896 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:00:05,896 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 16:00:05,896 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [588884732] [2022-04-27 16:00:05,896 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:00:05,896 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:00:05,897 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:05,897 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:05,924 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:05,924 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:00:05,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:05,925 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:00:05,925 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2022-04-27 16:00:05,925 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:06,127 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2022-04-27 16:00:06,128 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:00:06,128 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:00:06,128 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:06,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 39 transitions. [2022-04-27 16:00:06,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 39 transitions. [2022-04-27 16:00:06,130 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 39 transitions. [2022-04-27 16:00:06,164 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:06,165 INFO L225 Difference]: With dead ends: 33 [2022-04-27 16:00:06,165 INFO L226 Difference]: Without dead ends: 33 [2022-04-27 16:00:06,165 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=211, Invalid=341, Unknown=0, NotChecked=0, Total=552 [2022-04-27 16:00:06,166 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 32 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 36 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 24 SdHoareTripleChecker+Invalid, 56 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 36 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:06,166 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 24 Invalid, 56 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 36 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:00:06,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-27 16:00:06,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2022-04-27 16:00:06,168 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:06,168 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,168 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,168 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:06,169 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2022-04-27 16:00:06,169 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2022-04-27 16:00:06,170 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:06,170 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:06,170 INFO L74 IsIncluded]: Start isIncluded. First operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 33 states. [2022-04-27 16:00:06,170 INFO L87 Difference]: Start difference. First operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 33 states. [2022-04-27 16:00:06,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:06,171 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2022-04-27 16:00:06,171 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2022-04-27 16:00:06,171 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:06,171 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:06,171 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:06,171 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:06,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,183 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2022-04-27 16:00:06,183 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 20 [2022-04-27 16:00:06,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:06,183 INFO L495 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2022-04-27 16:00:06,184 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:06,184 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2022-04-27 16:00:06,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-04-27 16:00:06,184 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:06,184 INFO L195 NwaCegarLoop]: trace histogram [10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:06,199 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 16:00:06,384 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 16:00:06,385 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:06,385 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:06,385 INFO L85 PathProgramCache]: Analyzing trace with hash 1093643855, now seen corresponding path program 3 times [2022-04-27 16:00:06,385 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:06,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2047800574] [2022-04-27 16:00:06,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:06,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:06,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:06,550 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:06,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:06,561 INFO L290 TraceCheckUtils]: 0: Hoare triple {659#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {643#true} is VALID [2022-04-27 16:00:06,561 INFO L290 TraceCheckUtils]: 1: Hoare triple {643#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,561 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {643#true} {643#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,562 INFO L272 TraceCheckUtils]: 0: Hoare triple {643#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {659#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:06,562 INFO L290 TraceCheckUtils]: 1: Hoare triple {659#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {643#true} is VALID [2022-04-27 16:00:06,563 INFO L290 TraceCheckUtils]: 2: Hoare triple {643#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,563 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {643#true} {643#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,563 INFO L272 TraceCheckUtils]: 4: Hoare triple {643#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,563 INFO L290 TraceCheckUtils]: 5: Hoare triple {643#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {648#(= main_~i~0 0)} is VALID [2022-04-27 16:00:06,563 INFO L290 TraceCheckUtils]: 6: Hoare triple {648#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {648#(= main_~i~0 0)} is VALID [2022-04-27 16:00:06,564 INFO L290 TraceCheckUtils]: 7: Hoare triple {648#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {649#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:06,564 INFO L290 TraceCheckUtils]: 8: Hoare triple {649#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {649#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:06,564 INFO L290 TraceCheckUtils]: 9: Hoare triple {649#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {650#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:06,565 INFO L290 TraceCheckUtils]: 10: Hoare triple {650#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {650#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:06,565 INFO L290 TraceCheckUtils]: 11: Hoare triple {650#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {651#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:06,565 INFO L290 TraceCheckUtils]: 12: Hoare triple {651#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {651#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:06,566 INFO L290 TraceCheckUtils]: 13: Hoare triple {651#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {652#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:06,566 INFO L290 TraceCheckUtils]: 14: Hoare triple {652#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {652#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:06,567 INFO L290 TraceCheckUtils]: 15: Hoare triple {652#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {653#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:06,567 INFO L290 TraceCheckUtils]: 16: Hoare triple {653#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {653#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:06,567 INFO L290 TraceCheckUtils]: 17: Hoare triple {653#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {654#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:06,568 INFO L290 TraceCheckUtils]: 18: Hoare triple {654#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {654#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:06,568 INFO L290 TraceCheckUtils]: 19: Hoare triple {654#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {655#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:06,569 INFO L290 TraceCheckUtils]: 20: Hoare triple {655#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {655#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:06,569 INFO L290 TraceCheckUtils]: 21: Hoare triple {655#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {656#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:06,569 INFO L290 TraceCheckUtils]: 22: Hoare triple {656#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {656#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:06,570 INFO L290 TraceCheckUtils]: 23: Hoare triple {656#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {657#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:06,570 INFO L290 TraceCheckUtils]: 24: Hoare triple {657#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {657#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:06,571 INFO L290 TraceCheckUtils]: 25: Hoare triple {657#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {658#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:06,571 INFO L290 TraceCheckUtils]: 26: Hoare triple {658#(<= main_~i~0 10)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:06,571 INFO L290 TraceCheckUtils]: 27: Hoare triple {644#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {644#false} is VALID [2022-04-27 16:00:06,571 INFO L272 TraceCheckUtils]: 28: Hoare triple {644#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {644#false} is VALID [2022-04-27 16:00:06,571 INFO L290 TraceCheckUtils]: 29: Hoare triple {644#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {644#false} is VALID [2022-04-27 16:00:06,571 INFO L290 TraceCheckUtils]: 30: Hoare triple {644#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:06,571 INFO L290 TraceCheckUtils]: 31: Hoare triple {644#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:06,572 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:06,572 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:06,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2047800574] [2022-04-27 16:00:06,572 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2047800574] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:00:06,572 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1366452894] [2022-04-27 16:00:06,572 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 16:00:06,572 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:06,572 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:06,573 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:00:06,574 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 16:00:06,658 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-04-27 16:00:06,658 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:00:06,660 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 16:00:06,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:06,681 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:00:06,833 INFO L272 TraceCheckUtils]: 0: Hoare triple {643#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,833 INFO L290 TraceCheckUtils]: 1: Hoare triple {643#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {643#true} is VALID [2022-04-27 16:00:06,833 INFO L290 TraceCheckUtils]: 2: Hoare triple {643#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,833 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {643#true} {643#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,833 INFO L272 TraceCheckUtils]: 4: Hoare triple {643#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:06,834 INFO L290 TraceCheckUtils]: 5: Hoare triple {643#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {678#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:06,835 INFO L290 TraceCheckUtils]: 6: Hoare triple {678#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {678#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:06,835 INFO L290 TraceCheckUtils]: 7: Hoare triple {678#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {649#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:06,835 INFO L290 TraceCheckUtils]: 8: Hoare triple {649#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {649#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:06,836 INFO L290 TraceCheckUtils]: 9: Hoare triple {649#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {650#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:06,836 INFO L290 TraceCheckUtils]: 10: Hoare triple {650#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {650#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:06,836 INFO L290 TraceCheckUtils]: 11: Hoare triple {650#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {651#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:06,837 INFO L290 TraceCheckUtils]: 12: Hoare triple {651#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {651#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:06,837 INFO L290 TraceCheckUtils]: 13: Hoare triple {651#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {652#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:06,837 INFO L290 TraceCheckUtils]: 14: Hoare triple {652#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {652#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:06,838 INFO L290 TraceCheckUtils]: 15: Hoare triple {652#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {653#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:06,838 INFO L290 TraceCheckUtils]: 16: Hoare triple {653#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {653#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:06,838 INFO L290 TraceCheckUtils]: 17: Hoare triple {653#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {654#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:06,839 INFO L290 TraceCheckUtils]: 18: Hoare triple {654#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {654#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:06,839 INFO L290 TraceCheckUtils]: 19: Hoare triple {654#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {655#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:06,839 INFO L290 TraceCheckUtils]: 20: Hoare triple {655#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {655#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:06,840 INFO L290 TraceCheckUtils]: 21: Hoare triple {655#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {656#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:06,840 INFO L290 TraceCheckUtils]: 22: Hoare triple {656#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {656#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:06,841 INFO L290 TraceCheckUtils]: 23: Hoare triple {656#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {657#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:06,841 INFO L290 TraceCheckUtils]: 24: Hoare triple {657#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {657#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:06,841 INFO L290 TraceCheckUtils]: 25: Hoare triple {657#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {658#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:06,842 INFO L290 TraceCheckUtils]: 26: Hoare triple {658#(<= main_~i~0 10)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:06,842 INFO L290 TraceCheckUtils]: 27: Hoare triple {644#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {644#false} is VALID [2022-04-27 16:00:06,842 INFO L272 TraceCheckUtils]: 28: Hoare triple {644#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {644#false} is VALID [2022-04-27 16:00:06,842 INFO L290 TraceCheckUtils]: 29: Hoare triple {644#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {644#false} is VALID [2022-04-27 16:00:06,842 INFO L290 TraceCheckUtils]: 30: Hoare triple {644#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:06,842 INFO L290 TraceCheckUtils]: 31: Hoare triple {644#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:06,842 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:06,842 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:00:07,139 INFO L290 TraceCheckUtils]: 31: Hoare triple {644#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:07,139 INFO L290 TraceCheckUtils]: 30: Hoare triple {644#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:07,139 INFO L290 TraceCheckUtils]: 29: Hoare triple {644#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {644#false} is VALID [2022-04-27 16:00:07,139 INFO L272 TraceCheckUtils]: 28: Hoare triple {644#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {644#false} is VALID [2022-04-27 16:00:07,139 INFO L290 TraceCheckUtils]: 27: Hoare triple {644#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {644#false} is VALID [2022-04-27 16:00:07,139 INFO L290 TraceCheckUtils]: 26: Hoare triple {772#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {644#false} is VALID [2022-04-27 16:00:07,140 INFO L290 TraceCheckUtils]: 25: Hoare triple {776#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {772#(< main_~i~0 1024)} is VALID [2022-04-27 16:00:07,140 INFO L290 TraceCheckUtils]: 24: Hoare triple {776#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {776#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:07,141 INFO L290 TraceCheckUtils]: 23: Hoare triple {783#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {776#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:07,141 INFO L290 TraceCheckUtils]: 22: Hoare triple {783#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {783#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:07,141 INFO L290 TraceCheckUtils]: 21: Hoare triple {790#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {783#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:07,142 INFO L290 TraceCheckUtils]: 20: Hoare triple {790#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {790#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:07,142 INFO L290 TraceCheckUtils]: 19: Hoare triple {797#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {790#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:07,144 INFO L290 TraceCheckUtils]: 18: Hoare triple {797#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {797#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:07,144 INFO L290 TraceCheckUtils]: 17: Hoare triple {804#(< main_~i~0 1019)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {797#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:07,144 INFO L290 TraceCheckUtils]: 16: Hoare triple {804#(< main_~i~0 1019)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {804#(< main_~i~0 1019)} is VALID [2022-04-27 16:00:07,145 INFO L290 TraceCheckUtils]: 15: Hoare triple {811#(< main_~i~0 1018)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {804#(< main_~i~0 1019)} is VALID [2022-04-27 16:00:07,145 INFO L290 TraceCheckUtils]: 14: Hoare triple {811#(< main_~i~0 1018)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {811#(< main_~i~0 1018)} is VALID [2022-04-27 16:00:07,146 INFO L290 TraceCheckUtils]: 13: Hoare triple {818#(< main_~i~0 1017)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {811#(< main_~i~0 1018)} is VALID [2022-04-27 16:00:07,146 INFO L290 TraceCheckUtils]: 12: Hoare triple {818#(< main_~i~0 1017)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {818#(< main_~i~0 1017)} is VALID [2022-04-27 16:00:07,146 INFO L290 TraceCheckUtils]: 11: Hoare triple {825#(< main_~i~0 1016)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {818#(< main_~i~0 1017)} is VALID [2022-04-27 16:00:07,146 INFO L290 TraceCheckUtils]: 10: Hoare triple {825#(< main_~i~0 1016)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {825#(< main_~i~0 1016)} is VALID [2022-04-27 16:00:07,147 INFO L290 TraceCheckUtils]: 9: Hoare triple {832#(< main_~i~0 1015)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {825#(< main_~i~0 1016)} is VALID [2022-04-27 16:00:07,148 INFO L290 TraceCheckUtils]: 8: Hoare triple {832#(< main_~i~0 1015)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {832#(< main_~i~0 1015)} is VALID [2022-04-27 16:00:07,148 INFO L290 TraceCheckUtils]: 7: Hoare triple {839#(< main_~i~0 1014)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {832#(< main_~i~0 1015)} is VALID [2022-04-27 16:00:07,148 INFO L290 TraceCheckUtils]: 6: Hoare triple {839#(< main_~i~0 1014)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {839#(< main_~i~0 1014)} is VALID [2022-04-27 16:00:07,149 INFO L290 TraceCheckUtils]: 5: Hoare triple {643#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {839#(< main_~i~0 1014)} is VALID [2022-04-27 16:00:07,149 INFO L272 TraceCheckUtils]: 4: Hoare triple {643#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:07,149 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {643#true} {643#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:07,149 INFO L290 TraceCheckUtils]: 2: Hoare triple {643#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:07,149 INFO L290 TraceCheckUtils]: 1: Hoare triple {643#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {643#true} is VALID [2022-04-27 16:00:07,149 INFO L272 TraceCheckUtils]: 0: Hoare triple {643#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {643#true} is VALID [2022-04-27 16:00:07,149 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:07,150 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1366452894] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:00:07,150 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:00:07,150 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2022-04-27 16:00:07,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [773257457] [2022-04-27 16:00:07,150 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:00:07,150 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 32 [2022-04-27 16:00:07,151 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:07,151 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,190 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 59 edges. 59 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:07,191 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-04-27 16:00:07,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:07,191 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-04-27 16:00:07,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=302, Invalid=348, Unknown=0, NotChecked=0, Total=650 [2022-04-27 16:00:07,192 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:07,677 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2022-04-27 16:00:07,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-04-27 16:00:07,678 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 32 [2022-04-27 16:00:07,678 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:07,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 69 transitions. [2022-04-27 16:00:07,680 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 69 transitions. [2022-04-27 16:00:07,681 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 25 states and 69 transitions. [2022-04-27 16:00:07,733 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 69 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:07,734 INFO L225 Difference]: With dead ends: 57 [2022-04-27 16:00:07,734 INFO L226 Difference]: Without dead ends: 57 [2022-04-27 16:00:07,735 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 346 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=853, Invalid=1403, Unknown=0, NotChecked=0, Total=2256 [2022-04-27 16:00:07,735 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 51 mSDsluCounter, 42 mSDsCounter, 0 mSdLazyCounter, 94 mSolverCounterSat, 37 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 51 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 131 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 37 IncrementalHoareTripleChecker+Valid, 94 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:07,735 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [51 Valid, 54 Invalid, 131 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [37 Valid, 94 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 16:00:07,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2022-04-27 16:00:07,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2022-04-27 16:00:07,738 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:07,738 INFO L82 GeneralOperation]: Start isEquivalent. First operand 57 states. Second operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,738 INFO L74 IsIncluded]: Start isIncluded. First operand 57 states. Second operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,738 INFO L87 Difference]: Start difference. First operand 57 states. Second operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:07,739 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2022-04-27 16:00:07,740 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2022-04-27 16:00:07,740 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:07,740 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:07,740 INFO L74 IsIncluded]: Start isIncluded. First operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-27 16:00:07,740 INFO L87 Difference]: Start difference. First operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-27 16:00:07,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:07,742 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2022-04-27 16:00:07,742 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2022-04-27 16:00:07,742 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:07,742 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:07,742 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:07,742 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:07,742 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2022-04-27 16:00:07,743 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 32 [2022-04-27 16:00:07,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:07,743 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2022-04-27 16:00:07,744 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:07,744 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2022-04-27 16:00:07,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2022-04-27 16:00:07,744 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:07,744 INFO L195 NwaCegarLoop]: trace histogram [22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:07,763 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 16:00:07,959 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:07,959 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:07,960 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:07,960 INFO L85 PathProgramCache]: Analyzing trace with hash -1053856921, now seen corresponding path program 4 times [2022-04-27 16:00:07,960 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:07,960 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887177844] [2022-04-27 16:00:07,960 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:07,960 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:08,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:08,303 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:08,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:08,311 INFO L290 TraceCheckUtils]: 0: Hoare triple {1163#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1135#true} is VALID [2022-04-27 16:00:08,311 INFO L290 TraceCheckUtils]: 1: Hoare triple {1135#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,311 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1135#true} {1135#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,313 INFO L272 TraceCheckUtils]: 0: Hoare triple {1135#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1163#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:08,313 INFO L290 TraceCheckUtils]: 1: Hoare triple {1163#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1135#true} is VALID [2022-04-27 16:00:08,314 INFO L290 TraceCheckUtils]: 2: Hoare triple {1135#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,314 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1135#true} {1135#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,314 INFO L272 TraceCheckUtils]: 4: Hoare triple {1135#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,319 INFO L290 TraceCheckUtils]: 5: Hoare triple {1135#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {1140#(= main_~i~0 0)} is VALID [2022-04-27 16:00:08,320 INFO L290 TraceCheckUtils]: 6: Hoare triple {1140#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1140#(= main_~i~0 0)} is VALID [2022-04-27 16:00:08,321 INFO L290 TraceCheckUtils]: 7: Hoare triple {1140#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1141#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:08,321 INFO L290 TraceCheckUtils]: 8: Hoare triple {1141#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1141#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:08,322 INFO L290 TraceCheckUtils]: 9: Hoare triple {1141#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1142#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:08,322 INFO L290 TraceCheckUtils]: 10: Hoare triple {1142#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1142#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:08,322 INFO L290 TraceCheckUtils]: 11: Hoare triple {1142#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1143#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:08,323 INFO L290 TraceCheckUtils]: 12: Hoare triple {1143#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1143#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:08,323 INFO L290 TraceCheckUtils]: 13: Hoare triple {1143#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1144#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:08,323 INFO L290 TraceCheckUtils]: 14: Hoare triple {1144#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1144#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:08,324 INFO L290 TraceCheckUtils]: 15: Hoare triple {1144#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1145#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:08,324 INFO L290 TraceCheckUtils]: 16: Hoare triple {1145#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1145#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:08,327 INFO L290 TraceCheckUtils]: 17: Hoare triple {1145#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1146#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:08,328 INFO L290 TraceCheckUtils]: 18: Hoare triple {1146#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1146#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:08,328 INFO L290 TraceCheckUtils]: 19: Hoare triple {1146#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1147#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:08,329 INFO L290 TraceCheckUtils]: 20: Hoare triple {1147#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1147#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:08,329 INFO L290 TraceCheckUtils]: 21: Hoare triple {1147#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1148#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:08,330 INFO L290 TraceCheckUtils]: 22: Hoare triple {1148#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1148#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:08,330 INFO L290 TraceCheckUtils]: 23: Hoare triple {1148#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1149#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:08,330 INFO L290 TraceCheckUtils]: 24: Hoare triple {1149#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1149#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:08,331 INFO L290 TraceCheckUtils]: 25: Hoare triple {1149#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1150#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:08,331 INFO L290 TraceCheckUtils]: 26: Hoare triple {1150#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1150#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:08,332 INFO L290 TraceCheckUtils]: 27: Hoare triple {1150#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1151#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:08,332 INFO L290 TraceCheckUtils]: 28: Hoare triple {1151#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1151#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:08,333 INFO L290 TraceCheckUtils]: 29: Hoare triple {1151#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1152#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:08,333 INFO L290 TraceCheckUtils]: 30: Hoare triple {1152#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1152#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:08,334 INFO L290 TraceCheckUtils]: 31: Hoare triple {1152#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1153#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:08,334 INFO L290 TraceCheckUtils]: 32: Hoare triple {1153#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1153#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:08,335 INFO L290 TraceCheckUtils]: 33: Hoare triple {1153#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1154#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:08,335 INFO L290 TraceCheckUtils]: 34: Hoare triple {1154#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1154#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:08,336 INFO L290 TraceCheckUtils]: 35: Hoare triple {1154#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1155#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:08,336 INFO L290 TraceCheckUtils]: 36: Hoare triple {1155#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1155#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:08,336 INFO L290 TraceCheckUtils]: 37: Hoare triple {1155#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1156#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:08,337 INFO L290 TraceCheckUtils]: 38: Hoare triple {1156#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1156#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:08,337 INFO L290 TraceCheckUtils]: 39: Hoare triple {1156#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1157#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:08,338 INFO L290 TraceCheckUtils]: 40: Hoare triple {1157#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1157#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:08,338 INFO L290 TraceCheckUtils]: 41: Hoare triple {1157#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1158#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:08,339 INFO L290 TraceCheckUtils]: 42: Hoare triple {1158#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1158#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:08,339 INFO L290 TraceCheckUtils]: 43: Hoare triple {1158#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1159#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:08,339 INFO L290 TraceCheckUtils]: 44: Hoare triple {1159#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1159#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:08,340 INFO L290 TraceCheckUtils]: 45: Hoare triple {1159#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1160#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:08,341 INFO L290 TraceCheckUtils]: 46: Hoare triple {1160#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1160#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:08,341 INFO L290 TraceCheckUtils]: 47: Hoare triple {1160#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1161#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:08,341 INFO L290 TraceCheckUtils]: 48: Hoare triple {1161#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1161#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:08,342 INFO L290 TraceCheckUtils]: 49: Hoare triple {1161#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1162#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:08,342 INFO L290 TraceCheckUtils]: 50: Hoare triple {1162#(<= main_~i~0 22)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:08,342 INFO L290 TraceCheckUtils]: 51: Hoare triple {1136#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {1136#false} is VALID [2022-04-27 16:00:08,343 INFO L272 TraceCheckUtils]: 52: Hoare triple {1136#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {1136#false} is VALID [2022-04-27 16:00:08,343 INFO L290 TraceCheckUtils]: 53: Hoare triple {1136#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1136#false} is VALID [2022-04-27 16:00:08,343 INFO L290 TraceCheckUtils]: 54: Hoare triple {1136#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:08,343 INFO L290 TraceCheckUtils]: 55: Hoare triple {1136#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:08,345 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:08,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:08,345 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1887177844] [2022-04-27 16:00:08,345 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1887177844] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:00:08,346 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1519851824] [2022-04-27 16:00:08,346 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 16:00:08,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:08,346 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:08,356 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:00:08,359 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 16:00:08,436 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 16:00:08,437 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:00:08,438 INFO L263 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 24 conjunts are in the unsatisfiable core [2022-04-27 16:00:08,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:08,456 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:00:08,813 INFO L272 TraceCheckUtils]: 0: Hoare triple {1135#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,813 INFO L290 TraceCheckUtils]: 1: Hoare triple {1135#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1135#true} is VALID [2022-04-27 16:00:08,813 INFO L290 TraceCheckUtils]: 2: Hoare triple {1135#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,813 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1135#true} {1135#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,814 INFO L272 TraceCheckUtils]: 4: Hoare triple {1135#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:08,814 INFO L290 TraceCheckUtils]: 5: Hoare triple {1135#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {1182#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:08,814 INFO L290 TraceCheckUtils]: 6: Hoare triple {1182#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1182#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:08,815 INFO L290 TraceCheckUtils]: 7: Hoare triple {1182#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1141#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:08,815 INFO L290 TraceCheckUtils]: 8: Hoare triple {1141#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1141#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:08,817 INFO L290 TraceCheckUtils]: 9: Hoare triple {1141#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1142#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:08,817 INFO L290 TraceCheckUtils]: 10: Hoare triple {1142#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1142#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:08,817 INFO L290 TraceCheckUtils]: 11: Hoare triple {1142#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1143#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:08,818 INFO L290 TraceCheckUtils]: 12: Hoare triple {1143#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1143#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:08,818 INFO L290 TraceCheckUtils]: 13: Hoare triple {1143#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1144#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:08,819 INFO L290 TraceCheckUtils]: 14: Hoare triple {1144#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1144#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:08,819 INFO L290 TraceCheckUtils]: 15: Hoare triple {1144#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1145#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:08,819 INFO L290 TraceCheckUtils]: 16: Hoare triple {1145#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1145#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:08,820 INFO L290 TraceCheckUtils]: 17: Hoare triple {1145#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1146#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:08,820 INFO L290 TraceCheckUtils]: 18: Hoare triple {1146#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1146#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:08,821 INFO L290 TraceCheckUtils]: 19: Hoare triple {1146#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1147#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:08,821 INFO L290 TraceCheckUtils]: 20: Hoare triple {1147#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1147#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:08,822 INFO L290 TraceCheckUtils]: 21: Hoare triple {1147#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1148#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:08,822 INFO L290 TraceCheckUtils]: 22: Hoare triple {1148#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1148#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:08,823 INFO L290 TraceCheckUtils]: 23: Hoare triple {1148#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1149#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:08,823 INFO L290 TraceCheckUtils]: 24: Hoare triple {1149#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1149#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:08,824 INFO L290 TraceCheckUtils]: 25: Hoare triple {1149#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1150#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:08,824 INFO L290 TraceCheckUtils]: 26: Hoare triple {1150#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1150#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:08,824 INFO L290 TraceCheckUtils]: 27: Hoare triple {1150#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1151#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:08,825 INFO L290 TraceCheckUtils]: 28: Hoare triple {1151#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1151#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:08,825 INFO L290 TraceCheckUtils]: 29: Hoare triple {1151#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1152#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:08,826 INFO L290 TraceCheckUtils]: 30: Hoare triple {1152#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1152#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:08,826 INFO L290 TraceCheckUtils]: 31: Hoare triple {1152#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1153#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:08,826 INFO L290 TraceCheckUtils]: 32: Hoare triple {1153#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1153#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:08,827 INFO L290 TraceCheckUtils]: 33: Hoare triple {1153#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1154#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:08,827 INFO L290 TraceCheckUtils]: 34: Hoare triple {1154#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1154#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:08,828 INFO L290 TraceCheckUtils]: 35: Hoare triple {1154#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1155#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:08,828 INFO L290 TraceCheckUtils]: 36: Hoare triple {1155#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1155#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:08,828 INFO L290 TraceCheckUtils]: 37: Hoare triple {1155#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1156#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:08,829 INFO L290 TraceCheckUtils]: 38: Hoare triple {1156#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1156#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:08,829 INFO L290 TraceCheckUtils]: 39: Hoare triple {1156#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1157#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:08,829 INFO L290 TraceCheckUtils]: 40: Hoare triple {1157#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1157#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:08,848 INFO L290 TraceCheckUtils]: 41: Hoare triple {1157#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1158#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:08,848 INFO L290 TraceCheckUtils]: 42: Hoare triple {1158#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1158#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:08,848 INFO L290 TraceCheckUtils]: 43: Hoare triple {1158#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1159#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:08,849 INFO L290 TraceCheckUtils]: 44: Hoare triple {1159#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1159#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:08,849 INFO L290 TraceCheckUtils]: 45: Hoare triple {1159#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1160#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:08,850 INFO L290 TraceCheckUtils]: 46: Hoare triple {1160#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1160#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:08,850 INFO L290 TraceCheckUtils]: 47: Hoare triple {1160#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1161#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:08,850 INFO L290 TraceCheckUtils]: 48: Hoare triple {1161#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1161#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:08,851 INFO L290 TraceCheckUtils]: 49: Hoare triple {1161#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1162#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:08,851 INFO L290 TraceCheckUtils]: 50: Hoare triple {1162#(<= main_~i~0 22)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:08,851 INFO L290 TraceCheckUtils]: 51: Hoare triple {1136#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {1136#false} is VALID [2022-04-27 16:00:08,852 INFO L272 TraceCheckUtils]: 52: Hoare triple {1136#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {1136#false} is VALID [2022-04-27 16:00:08,852 INFO L290 TraceCheckUtils]: 53: Hoare triple {1136#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1136#false} is VALID [2022-04-27 16:00:08,852 INFO L290 TraceCheckUtils]: 54: Hoare triple {1136#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:08,852 INFO L290 TraceCheckUtils]: 55: Hoare triple {1136#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:08,852 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:08,853 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:00:09,791 INFO L290 TraceCheckUtils]: 55: Hoare triple {1136#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:09,791 INFO L290 TraceCheckUtils]: 54: Hoare triple {1136#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:09,791 INFO L290 TraceCheckUtils]: 53: Hoare triple {1136#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1136#false} is VALID [2022-04-27 16:00:09,791 INFO L272 TraceCheckUtils]: 52: Hoare triple {1136#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {1136#false} is VALID [2022-04-27 16:00:09,792 INFO L290 TraceCheckUtils]: 51: Hoare triple {1136#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {1136#false} is VALID [2022-04-27 16:00:09,792 INFO L290 TraceCheckUtils]: 50: Hoare triple {1348#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {1136#false} is VALID [2022-04-27 16:00:09,792 INFO L290 TraceCheckUtils]: 49: Hoare triple {1352#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1348#(< main_~i~0 1024)} is VALID [2022-04-27 16:00:09,793 INFO L290 TraceCheckUtils]: 48: Hoare triple {1352#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1352#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:09,793 INFO L290 TraceCheckUtils]: 47: Hoare triple {1359#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1352#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:09,793 INFO L290 TraceCheckUtils]: 46: Hoare triple {1359#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1359#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:09,794 INFO L290 TraceCheckUtils]: 45: Hoare triple {1366#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1359#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:09,794 INFO L290 TraceCheckUtils]: 44: Hoare triple {1366#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1366#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:09,807 INFO L290 TraceCheckUtils]: 43: Hoare triple {1373#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1366#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:09,808 INFO L290 TraceCheckUtils]: 42: Hoare triple {1373#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1373#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:09,808 INFO L290 TraceCheckUtils]: 41: Hoare triple {1380#(< main_~i~0 1019)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1373#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:09,808 INFO L290 TraceCheckUtils]: 40: Hoare triple {1380#(< main_~i~0 1019)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1380#(< main_~i~0 1019)} is VALID [2022-04-27 16:00:09,809 INFO L290 TraceCheckUtils]: 39: Hoare triple {1387#(< main_~i~0 1018)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1380#(< main_~i~0 1019)} is VALID [2022-04-27 16:00:09,809 INFO L290 TraceCheckUtils]: 38: Hoare triple {1387#(< main_~i~0 1018)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1387#(< main_~i~0 1018)} is VALID [2022-04-27 16:00:09,810 INFO L290 TraceCheckUtils]: 37: Hoare triple {1394#(< main_~i~0 1017)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1387#(< main_~i~0 1018)} is VALID [2022-04-27 16:00:09,810 INFO L290 TraceCheckUtils]: 36: Hoare triple {1394#(< main_~i~0 1017)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1394#(< main_~i~0 1017)} is VALID [2022-04-27 16:00:09,810 INFO L290 TraceCheckUtils]: 35: Hoare triple {1401#(< main_~i~0 1016)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1394#(< main_~i~0 1017)} is VALID [2022-04-27 16:00:09,819 INFO L290 TraceCheckUtils]: 34: Hoare triple {1401#(< main_~i~0 1016)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1401#(< main_~i~0 1016)} is VALID [2022-04-27 16:00:09,819 INFO L290 TraceCheckUtils]: 33: Hoare triple {1408#(< main_~i~0 1015)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1401#(< main_~i~0 1016)} is VALID [2022-04-27 16:00:09,823 INFO L290 TraceCheckUtils]: 32: Hoare triple {1408#(< main_~i~0 1015)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1408#(< main_~i~0 1015)} is VALID [2022-04-27 16:00:09,824 INFO L290 TraceCheckUtils]: 31: Hoare triple {1415#(< main_~i~0 1014)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1408#(< main_~i~0 1015)} is VALID [2022-04-27 16:00:09,824 INFO L290 TraceCheckUtils]: 30: Hoare triple {1415#(< main_~i~0 1014)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1415#(< main_~i~0 1014)} is VALID [2022-04-27 16:00:09,824 INFO L290 TraceCheckUtils]: 29: Hoare triple {1422#(< main_~i~0 1013)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1415#(< main_~i~0 1014)} is VALID [2022-04-27 16:00:09,826 INFO L290 TraceCheckUtils]: 28: Hoare triple {1422#(< main_~i~0 1013)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1422#(< main_~i~0 1013)} is VALID [2022-04-27 16:00:09,827 INFO L290 TraceCheckUtils]: 27: Hoare triple {1429#(< main_~i~0 1012)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1422#(< main_~i~0 1013)} is VALID [2022-04-27 16:00:09,827 INFO L290 TraceCheckUtils]: 26: Hoare triple {1429#(< main_~i~0 1012)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1429#(< main_~i~0 1012)} is VALID [2022-04-27 16:00:09,827 INFO L290 TraceCheckUtils]: 25: Hoare triple {1436#(< main_~i~0 1011)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1429#(< main_~i~0 1012)} is VALID [2022-04-27 16:00:09,830 INFO L290 TraceCheckUtils]: 24: Hoare triple {1436#(< main_~i~0 1011)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1436#(< main_~i~0 1011)} is VALID [2022-04-27 16:00:09,830 INFO L290 TraceCheckUtils]: 23: Hoare triple {1443#(< main_~i~0 1010)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1436#(< main_~i~0 1011)} is VALID [2022-04-27 16:00:09,831 INFO L290 TraceCheckUtils]: 22: Hoare triple {1443#(< main_~i~0 1010)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1443#(< main_~i~0 1010)} is VALID [2022-04-27 16:00:09,832 INFO L290 TraceCheckUtils]: 21: Hoare triple {1450#(< main_~i~0 1009)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1443#(< main_~i~0 1010)} is VALID [2022-04-27 16:00:09,832 INFO L290 TraceCheckUtils]: 20: Hoare triple {1450#(< main_~i~0 1009)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1450#(< main_~i~0 1009)} is VALID [2022-04-27 16:00:09,833 INFO L290 TraceCheckUtils]: 19: Hoare triple {1457#(< main_~i~0 1008)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1450#(< main_~i~0 1009)} is VALID [2022-04-27 16:00:09,833 INFO L290 TraceCheckUtils]: 18: Hoare triple {1457#(< main_~i~0 1008)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1457#(< main_~i~0 1008)} is VALID [2022-04-27 16:00:09,833 INFO L290 TraceCheckUtils]: 17: Hoare triple {1464#(< main_~i~0 1007)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1457#(< main_~i~0 1008)} is VALID [2022-04-27 16:00:09,834 INFO L290 TraceCheckUtils]: 16: Hoare triple {1464#(< main_~i~0 1007)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1464#(< main_~i~0 1007)} is VALID [2022-04-27 16:00:09,834 INFO L290 TraceCheckUtils]: 15: Hoare triple {1471#(< main_~i~0 1006)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1464#(< main_~i~0 1007)} is VALID [2022-04-27 16:00:09,834 INFO L290 TraceCheckUtils]: 14: Hoare triple {1471#(< main_~i~0 1006)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1471#(< main_~i~0 1006)} is VALID [2022-04-27 16:00:09,835 INFO L290 TraceCheckUtils]: 13: Hoare triple {1478#(< main_~i~0 1005)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1471#(< main_~i~0 1006)} is VALID [2022-04-27 16:00:09,835 INFO L290 TraceCheckUtils]: 12: Hoare triple {1478#(< main_~i~0 1005)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1478#(< main_~i~0 1005)} is VALID [2022-04-27 16:00:09,835 INFO L290 TraceCheckUtils]: 11: Hoare triple {1485#(< main_~i~0 1004)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1478#(< main_~i~0 1005)} is VALID [2022-04-27 16:00:09,836 INFO L290 TraceCheckUtils]: 10: Hoare triple {1485#(< main_~i~0 1004)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1485#(< main_~i~0 1004)} is VALID [2022-04-27 16:00:09,836 INFO L290 TraceCheckUtils]: 9: Hoare triple {1492#(< main_~i~0 1003)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1485#(< main_~i~0 1004)} is VALID [2022-04-27 16:00:09,836 INFO L290 TraceCheckUtils]: 8: Hoare triple {1492#(< main_~i~0 1003)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1492#(< main_~i~0 1003)} is VALID [2022-04-27 16:00:09,837 INFO L290 TraceCheckUtils]: 7: Hoare triple {1499#(< main_~i~0 1002)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1492#(< main_~i~0 1003)} is VALID [2022-04-27 16:00:09,837 INFO L290 TraceCheckUtils]: 6: Hoare triple {1499#(< main_~i~0 1002)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1499#(< main_~i~0 1002)} is VALID [2022-04-27 16:00:09,837 INFO L290 TraceCheckUtils]: 5: Hoare triple {1135#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {1499#(< main_~i~0 1002)} is VALID [2022-04-27 16:00:09,838 INFO L272 TraceCheckUtils]: 4: Hoare triple {1135#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:09,838 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1135#true} {1135#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:09,838 INFO L290 TraceCheckUtils]: 2: Hoare triple {1135#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:09,838 INFO L290 TraceCheckUtils]: 1: Hoare triple {1135#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1135#true} is VALID [2022-04-27 16:00:09,838 INFO L272 TraceCheckUtils]: 0: Hoare triple {1135#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1135#true} is VALID [2022-04-27 16:00:09,838 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:09,839 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1519851824] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:00:09,839 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:00:09,839 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 50 [2022-04-27 16:00:09,839 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2055807178] [2022-04-27 16:00:09,839 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:00:09,839 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 56 [2022-04-27 16:00:09,840 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:09,840 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:09,914 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 107 edges. 107 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:09,914 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-04-27 16:00:09,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:09,915 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-04-27 16:00:09,917 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1178, Invalid=1272, Unknown=0, NotChecked=0, Total=2450 [2022-04-27 16:00:09,917 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:11,096 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2022-04-27 16:00:11,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-27 16:00:11,097 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 56 [2022-04-27 16:00:11,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:11,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 129 transitions. [2022-04-27 16:00:11,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 129 transitions. [2022-04-27 16:00:11,101 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 129 transitions. [2022-04-27 16:00:11,195 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 129 edges. 129 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:11,196 INFO L225 Difference]: With dead ends: 105 [2022-04-27 16:00:11,196 INFO L226 Difference]: Without dead ends: 105 [2022-04-27 16:00:11,199 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1420 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3433, Invalid=5687, Unknown=0, NotChecked=0, Total=9120 [2022-04-27 16:00:11,199 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 99 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 132 mSolverCounterSat, 74 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 99 SdHoareTripleChecker+Valid, 44 SdHoareTripleChecker+Invalid, 206 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 74 IncrementalHoareTripleChecker+Valid, 132 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:11,199 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [99 Valid, 44 Invalid, 206 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [74 Valid, 132 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 16:00:11,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2022-04-27 16:00:11,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2022-04-27 16:00:11,203 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:11,203 INFO L82 GeneralOperation]: Start isEquivalent. First operand 105 states. Second operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,203 INFO L74 IsIncluded]: Start isIncluded. First operand 105 states. Second operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,203 INFO L87 Difference]: Start difference. First operand 105 states. Second operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:11,206 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2022-04-27 16:00:11,206 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2022-04-27 16:00:11,206 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:11,206 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:11,206 INFO L74 IsIncluded]: Start isIncluded. First operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 105 states. [2022-04-27 16:00:11,206 INFO L87 Difference]: Start difference. First operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 105 states. [2022-04-27 16:00:11,208 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:11,208 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2022-04-27 16:00:11,208 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2022-04-27 16:00:11,209 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:11,209 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:11,209 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:11,209 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:11,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2022-04-27 16:00:11,211 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 56 [2022-04-27 16:00:11,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:11,211 INFO L495 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2022-04-27 16:00:11,211 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:11,211 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2022-04-27 16:00:11,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2022-04-27 16:00:11,213 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:11,213 INFO L195 NwaCegarLoop]: trace histogram [46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:11,239 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 16:00:11,427 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:11,427 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:11,428 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:11,428 INFO L85 PathProgramCache]: Analyzing trace with hash 1931971991, now seen corresponding path program 5 times [2022-04-27 16:00:11,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:11,428 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1373188636] [2022-04-27 16:00:11,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:11,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:11,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:12,387 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:12,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:12,395 INFO L290 TraceCheckUtils]: 0: Hoare triple {2087#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2035#true} is VALID [2022-04-27 16:00:12,395 INFO L290 TraceCheckUtils]: 1: Hoare triple {2035#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:12,395 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2035#true} {2035#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:12,396 INFO L272 TraceCheckUtils]: 0: Hoare triple {2035#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2087#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:12,396 INFO L290 TraceCheckUtils]: 1: Hoare triple {2087#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2035#true} is VALID [2022-04-27 16:00:12,396 INFO L290 TraceCheckUtils]: 2: Hoare triple {2035#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:12,396 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2035#true} {2035#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:12,396 INFO L272 TraceCheckUtils]: 4: Hoare triple {2035#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:12,397 INFO L290 TraceCheckUtils]: 5: Hoare triple {2035#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {2040#(= main_~i~0 0)} is VALID [2022-04-27 16:00:12,397 INFO L290 TraceCheckUtils]: 6: Hoare triple {2040#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2040#(= main_~i~0 0)} is VALID [2022-04-27 16:00:12,397 INFO L290 TraceCheckUtils]: 7: Hoare triple {2040#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2041#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:12,397 INFO L290 TraceCheckUtils]: 8: Hoare triple {2041#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2041#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:12,398 INFO L290 TraceCheckUtils]: 9: Hoare triple {2041#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2042#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:12,398 INFO L290 TraceCheckUtils]: 10: Hoare triple {2042#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2042#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:12,399 INFO L290 TraceCheckUtils]: 11: Hoare triple {2042#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2043#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:12,399 INFO L290 TraceCheckUtils]: 12: Hoare triple {2043#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2043#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:12,399 INFO L290 TraceCheckUtils]: 13: Hoare triple {2043#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2044#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:12,399 INFO L290 TraceCheckUtils]: 14: Hoare triple {2044#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2044#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:12,400 INFO L290 TraceCheckUtils]: 15: Hoare triple {2044#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2045#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:12,400 INFO L290 TraceCheckUtils]: 16: Hoare triple {2045#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2045#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:12,400 INFO L290 TraceCheckUtils]: 17: Hoare triple {2045#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2046#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:12,401 INFO L290 TraceCheckUtils]: 18: Hoare triple {2046#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2046#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:12,401 INFO L290 TraceCheckUtils]: 19: Hoare triple {2046#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2047#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:12,401 INFO L290 TraceCheckUtils]: 20: Hoare triple {2047#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2047#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:12,402 INFO L290 TraceCheckUtils]: 21: Hoare triple {2047#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2048#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:12,402 INFO L290 TraceCheckUtils]: 22: Hoare triple {2048#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2048#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:12,403 INFO L290 TraceCheckUtils]: 23: Hoare triple {2048#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2049#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:12,404 INFO L290 TraceCheckUtils]: 24: Hoare triple {2049#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2049#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:12,404 INFO L290 TraceCheckUtils]: 25: Hoare triple {2049#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2050#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:12,404 INFO L290 TraceCheckUtils]: 26: Hoare triple {2050#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2050#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:12,405 INFO L290 TraceCheckUtils]: 27: Hoare triple {2050#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2051#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:12,405 INFO L290 TraceCheckUtils]: 28: Hoare triple {2051#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2051#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:12,405 INFO L290 TraceCheckUtils]: 29: Hoare triple {2051#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2052#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:12,406 INFO L290 TraceCheckUtils]: 30: Hoare triple {2052#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2052#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:12,406 INFO L290 TraceCheckUtils]: 31: Hoare triple {2052#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2053#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:12,407 INFO L290 TraceCheckUtils]: 32: Hoare triple {2053#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2053#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:12,407 INFO L290 TraceCheckUtils]: 33: Hoare triple {2053#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2054#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:12,407 INFO L290 TraceCheckUtils]: 34: Hoare triple {2054#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2054#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:12,408 INFO L290 TraceCheckUtils]: 35: Hoare triple {2054#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2055#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:12,408 INFO L290 TraceCheckUtils]: 36: Hoare triple {2055#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2055#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:12,408 INFO L290 TraceCheckUtils]: 37: Hoare triple {2055#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2056#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:12,409 INFO L290 TraceCheckUtils]: 38: Hoare triple {2056#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2056#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:12,409 INFO L290 TraceCheckUtils]: 39: Hoare triple {2056#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2057#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:12,409 INFO L290 TraceCheckUtils]: 40: Hoare triple {2057#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2057#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:12,410 INFO L290 TraceCheckUtils]: 41: Hoare triple {2057#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2058#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:12,410 INFO L290 TraceCheckUtils]: 42: Hoare triple {2058#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2058#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:12,410 INFO L290 TraceCheckUtils]: 43: Hoare triple {2058#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2059#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:12,411 INFO L290 TraceCheckUtils]: 44: Hoare triple {2059#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2059#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:12,411 INFO L290 TraceCheckUtils]: 45: Hoare triple {2059#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2060#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:12,411 INFO L290 TraceCheckUtils]: 46: Hoare triple {2060#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2060#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:12,412 INFO L290 TraceCheckUtils]: 47: Hoare triple {2060#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2061#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:12,412 INFO L290 TraceCheckUtils]: 48: Hoare triple {2061#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2061#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:12,412 INFO L290 TraceCheckUtils]: 49: Hoare triple {2061#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2062#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:12,413 INFO L290 TraceCheckUtils]: 50: Hoare triple {2062#(<= main_~i~0 22)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2062#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:12,413 INFO L290 TraceCheckUtils]: 51: Hoare triple {2062#(<= main_~i~0 22)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2063#(<= main_~i~0 23)} is VALID [2022-04-27 16:00:12,413 INFO L290 TraceCheckUtils]: 52: Hoare triple {2063#(<= main_~i~0 23)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2063#(<= main_~i~0 23)} is VALID [2022-04-27 16:00:12,414 INFO L290 TraceCheckUtils]: 53: Hoare triple {2063#(<= main_~i~0 23)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2064#(<= main_~i~0 24)} is VALID [2022-04-27 16:00:12,414 INFO L290 TraceCheckUtils]: 54: Hoare triple {2064#(<= main_~i~0 24)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2064#(<= main_~i~0 24)} is VALID [2022-04-27 16:00:12,414 INFO L290 TraceCheckUtils]: 55: Hoare triple {2064#(<= main_~i~0 24)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2065#(<= main_~i~0 25)} is VALID [2022-04-27 16:00:12,414 INFO L290 TraceCheckUtils]: 56: Hoare triple {2065#(<= main_~i~0 25)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2065#(<= main_~i~0 25)} is VALID [2022-04-27 16:00:12,415 INFO L290 TraceCheckUtils]: 57: Hoare triple {2065#(<= main_~i~0 25)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2066#(<= main_~i~0 26)} is VALID [2022-04-27 16:00:12,415 INFO L290 TraceCheckUtils]: 58: Hoare triple {2066#(<= main_~i~0 26)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2066#(<= main_~i~0 26)} is VALID [2022-04-27 16:00:12,416 INFO L290 TraceCheckUtils]: 59: Hoare triple {2066#(<= main_~i~0 26)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2067#(<= main_~i~0 27)} is VALID [2022-04-27 16:00:12,416 INFO L290 TraceCheckUtils]: 60: Hoare triple {2067#(<= main_~i~0 27)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2067#(<= main_~i~0 27)} is VALID [2022-04-27 16:00:12,416 INFO L290 TraceCheckUtils]: 61: Hoare triple {2067#(<= main_~i~0 27)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2068#(<= main_~i~0 28)} is VALID [2022-04-27 16:00:12,416 INFO L290 TraceCheckUtils]: 62: Hoare triple {2068#(<= main_~i~0 28)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2068#(<= main_~i~0 28)} is VALID [2022-04-27 16:00:12,417 INFO L290 TraceCheckUtils]: 63: Hoare triple {2068#(<= main_~i~0 28)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2069#(<= main_~i~0 29)} is VALID [2022-04-27 16:00:12,417 INFO L290 TraceCheckUtils]: 64: Hoare triple {2069#(<= main_~i~0 29)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2069#(<= main_~i~0 29)} is VALID [2022-04-27 16:00:12,417 INFO L290 TraceCheckUtils]: 65: Hoare triple {2069#(<= main_~i~0 29)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2070#(<= main_~i~0 30)} is VALID [2022-04-27 16:00:12,418 INFO L290 TraceCheckUtils]: 66: Hoare triple {2070#(<= main_~i~0 30)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2070#(<= main_~i~0 30)} is VALID [2022-04-27 16:00:12,418 INFO L290 TraceCheckUtils]: 67: Hoare triple {2070#(<= main_~i~0 30)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2071#(<= main_~i~0 31)} is VALID [2022-04-27 16:00:12,418 INFO L290 TraceCheckUtils]: 68: Hoare triple {2071#(<= main_~i~0 31)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2071#(<= main_~i~0 31)} is VALID [2022-04-27 16:00:12,419 INFO L290 TraceCheckUtils]: 69: Hoare triple {2071#(<= main_~i~0 31)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2072#(<= main_~i~0 32)} is VALID [2022-04-27 16:00:12,419 INFO L290 TraceCheckUtils]: 70: Hoare triple {2072#(<= main_~i~0 32)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2072#(<= main_~i~0 32)} is VALID [2022-04-27 16:00:12,419 INFO L290 TraceCheckUtils]: 71: Hoare triple {2072#(<= main_~i~0 32)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2073#(<= main_~i~0 33)} is VALID [2022-04-27 16:00:12,420 INFO L290 TraceCheckUtils]: 72: Hoare triple {2073#(<= main_~i~0 33)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2073#(<= main_~i~0 33)} is VALID [2022-04-27 16:00:12,420 INFO L290 TraceCheckUtils]: 73: Hoare triple {2073#(<= main_~i~0 33)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2074#(<= main_~i~0 34)} is VALID [2022-04-27 16:00:12,420 INFO L290 TraceCheckUtils]: 74: Hoare triple {2074#(<= main_~i~0 34)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2074#(<= main_~i~0 34)} is VALID [2022-04-27 16:00:12,421 INFO L290 TraceCheckUtils]: 75: Hoare triple {2074#(<= main_~i~0 34)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2075#(<= main_~i~0 35)} is VALID [2022-04-27 16:00:12,421 INFO L290 TraceCheckUtils]: 76: Hoare triple {2075#(<= main_~i~0 35)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2075#(<= main_~i~0 35)} is VALID [2022-04-27 16:00:12,421 INFO L290 TraceCheckUtils]: 77: Hoare triple {2075#(<= main_~i~0 35)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2076#(<= main_~i~0 36)} is VALID [2022-04-27 16:00:12,422 INFO L290 TraceCheckUtils]: 78: Hoare triple {2076#(<= main_~i~0 36)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2076#(<= main_~i~0 36)} is VALID [2022-04-27 16:00:12,422 INFO L290 TraceCheckUtils]: 79: Hoare triple {2076#(<= main_~i~0 36)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2077#(<= main_~i~0 37)} is VALID [2022-04-27 16:00:12,422 INFO L290 TraceCheckUtils]: 80: Hoare triple {2077#(<= main_~i~0 37)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2077#(<= main_~i~0 37)} is VALID [2022-04-27 16:00:12,423 INFO L290 TraceCheckUtils]: 81: Hoare triple {2077#(<= main_~i~0 37)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2078#(<= main_~i~0 38)} is VALID [2022-04-27 16:00:12,423 INFO L290 TraceCheckUtils]: 82: Hoare triple {2078#(<= main_~i~0 38)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2078#(<= main_~i~0 38)} is VALID [2022-04-27 16:00:12,423 INFO L290 TraceCheckUtils]: 83: Hoare triple {2078#(<= main_~i~0 38)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2079#(<= main_~i~0 39)} is VALID [2022-04-27 16:00:12,424 INFO L290 TraceCheckUtils]: 84: Hoare triple {2079#(<= main_~i~0 39)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2079#(<= main_~i~0 39)} is VALID [2022-04-27 16:00:12,424 INFO L290 TraceCheckUtils]: 85: Hoare triple {2079#(<= main_~i~0 39)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2080#(<= main_~i~0 40)} is VALID [2022-04-27 16:00:12,424 INFO L290 TraceCheckUtils]: 86: Hoare triple {2080#(<= main_~i~0 40)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2080#(<= main_~i~0 40)} is VALID [2022-04-27 16:00:12,425 INFO L290 TraceCheckUtils]: 87: Hoare triple {2080#(<= main_~i~0 40)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2081#(<= main_~i~0 41)} is VALID [2022-04-27 16:00:12,425 INFO L290 TraceCheckUtils]: 88: Hoare triple {2081#(<= main_~i~0 41)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2081#(<= main_~i~0 41)} is VALID [2022-04-27 16:00:12,425 INFO L290 TraceCheckUtils]: 89: Hoare triple {2081#(<= main_~i~0 41)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2082#(<= main_~i~0 42)} is VALID [2022-04-27 16:00:12,425 INFO L290 TraceCheckUtils]: 90: Hoare triple {2082#(<= main_~i~0 42)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2082#(<= main_~i~0 42)} is VALID [2022-04-27 16:00:12,426 INFO L290 TraceCheckUtils]: 91: Hoare triple {2082#(<= main_~i~0 42)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2083#(<= main_~i~0 43)} is VALID [2022-04-27 16:00:12,426 INFO L290 TraceCheckUtils]: 92: Hoare triple {2083#(<= main_~i~0 43)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2083#(<= main_~i~0 43)} is VALID [2022-04-27 16:00:12,426 INFO L290 TraceCheckUtils]: 93: Hoare triple {2083#(<= main_~i~0 43)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2084#(<= main_~i~0 44)} is VALID [2022-04-27 16:00:12,427 INFO L290 TraceCheckUtils]: 94: Hoare triple {2084#(<= main_~i~0 44)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2084#(<= main_~i~0 44)} is VALID [2022-04-27 16:00:12,427 INFO L290 TraceCheckUtils]: 95: Hoare triple {2084#(<= main_~i~0 44)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2085#(<= main_~i~0 45)} is VALID [2022-04-27 16:00:12,427 INFO L290 TraceCheckUtils]: 96: Hoare triple {2085#(<= main_~i~0 45)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2085#(<= main_~i~0 45)} is VALID [2022-04-27 16:00:12,428 INFO L290 TraceCheckUtils]: 97: Hoare triple {2085#(<= main_~i~0 45)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2086#(<= main_~i~0 46)} is VALID [2022-04-27 16:00:12,428 INFO L290 TraceCheckUtils]: 98: Hoare triple {2086#(<= main_~i~0 46)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:12,428 INFO L290 TraceCheckUtils]: 99: Hoare triple {2036#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {2036#false} is VALID [2022-04-27 16:00:12,428 INFO L272 TraceCheckUtils]: 100: Hoare triple {2036#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {2036#false} is VALID [2022-04-27 16:00:12,428 INFO L290 TraceCheckUtils]: 101: Hoare triple {2036#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2036#false} is VALID [2022-04-27 16:00:12,428 INFO L290 TraceCheckUtils]: 102: Hoare triple {2036#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:12,428 INFO L290 TraceCheckUtils]: 103: Hoare triple {2036#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:12,429 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:12,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:12,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1373188636] [2022-04-27 16:00:12,430 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1373188636] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:00:12,430 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [734748323] [2022-04-27 16:00:12,430 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-27 16:00:12,430 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:12,430 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:12,431 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:00:12,432 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 16:00:30,651 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-04-27 16:00:30,652 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:00:30,693 INFO L263 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 48 conjunts are in the unsatisfiable core [2022-04-27 16:00:30,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:30,733 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:00:31,473 INFO L272 TraceCheckUtils]: 0: Hoare triple {2035#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:31,473 INFO L290 TraceCheckUtils]: 1: Hoare triple {2035#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2035#true} is VALID [2022-04-27 16:00:31,473 INFO L290 TraceCheckUtils]: 2: Hoare triple {2035#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:31,473 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2035#true} {2035#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:31,474 INFO L272 TraceCheckUtils]: 4: Hoare triple {2035#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:31,474 INFO L290 TraceCheckUtils]: 5: Hoare triple {2035#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {2106#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:31,474 INFO L290 TraceCheckUtils]: 6: Hoare triple {2106#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2106#(<= main_~i~0 0)} is VALID [2022-04-27 16:00:31,475 INFO L290 TraceCheckUtils]: 7: Hoare triple {2106#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2041#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:31,475 INFO L290 TraceCheckUtils]: 8: Hoare triple {2041#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2041#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:31,476 INFO L290 TraceCheckUtils]: 9: Hoare triple {2041#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2042#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:31,476 INFO L290 TraceCheckUtils]: 10: Hoare triple {2042#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2042#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:31,476 INFO L290 TraceCheckUtils]: 11: Hoare triple {2042#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2043#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:31,477 INFO L290 TraceCheckUtils]: 12: Hoare triple {2043#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2043#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:31,477 INFO L290 TraceCheckUtils]: 13: Hoare triple {2043#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2044#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:31,477 INFO L290 TraceCheckUtils]: 14: Hoare triple {2044#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2044#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:31,478 INFO L290 TraceCheckUtils]: 15: Hoare triple {2044#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2045#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:31,478 INFO L290 TraceCheckUtils]: 16: Hoare triple {2045#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2045#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:31,478 INFO L290 TraceCheckUtils]: 17: Hoare triple {2045#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2046#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:31,479 INFO L290 TraceCheckUtils]: 18: Hoare triple {2046#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2046#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:31,479 INFO L290 TraceCheckUtils]: 19: Hoare triple {2046#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2047#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:31,479 INFO L290 TraceCheckUtils]: 20: Hoare triple {2047#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2047#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:31,480 INFO L290 TraceCheckUtils]: 21: Hoare triple {2047#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2048#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:31,480 INFO L290 TraceCheckUtils]: 22: Hoare triple {2048#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2048#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:31,481 INFO L290 TraceCheckUtils]: 23: Hoare triple {2048#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2049#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:31,481 INFO L290 TraceCheckUtils]: 24: Hoare triple {2049#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2049#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:31,482 INFO L290 TraceCheckUtils]: 25: Hoare triple {2049#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2050#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:31,482 INFO L290 TraceCheckUtils]: 26: Hoare triple {2050#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2050#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:31,482 INFO L290 TraceCheckUtils]: 27: Hoare triple {2050#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2051#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:31,483 INFO L290 TraceCheckUtils]: 28: Hoare triple {2051#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2051#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:31,483 INFO L290 TraceCheckUtils]: 29: Hoare triple {2051#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2052#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:31,483 INFO L290 TraceCheckUtils]: 30: Hoare triple {2052#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2052#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:31,484 INFO L290 TraceCheckUtils]: 31: Hoare triple {2052#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2053#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:31,484 INFO L290 TraceCheckUtils]: 32: Hoare triple {2053#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2053#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:31,484 INFO L290 TraceCheckUtils]: 33: Hoare triple {2053#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2054#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:31,485 INFO L290 TraceCheckUtils]: 34: Hoare triple {2054#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2054#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:31,485 INFO L290 TraceCheckUtils]: 35: Hoare triple {2054#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2055#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:31,485 INFO L290 TraceCheckUtils]: 36: Hoare triple {2055#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2055#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:31,486 INFO L290 TraceCheckUtils]: 37: Hoare triple {2055#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2056#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:31,486 INFO L290 TraceCheckUtils]: 38: Hoare triple {2056#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2056#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:31,486 INFO L290 TraceCheckUtils]: 39: Hoare triple {2056#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2057#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:31,487 INFO L290 TraceCheckUtils]: 40: Hoare triple {2057#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2057#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:31,487 INFO L290 TraceCheckUtils]: 41: Hoare triple {2057#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2058#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:31,487 INFO L290 TraceCheckUtils]: 42: Hoare triple {2058#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2058#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:31,488 INFO L290 TraceCheckUtils]: 43: Hoare triple {2058#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2059#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:31,488 INFO L290 TraceCheckUtils]: 44: Hoare triple {2059#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2059#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:31,488 INFO L290 TraceCheckUtils]: 45: Hoare triple {2059#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2060#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:31,489 INFO L290 TraceCheckUtils]: 46: Hoare triple {2060#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2060#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:31,489 INFO L290 TraceCheckUtils]: 47: Hoare triple {2060#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2061#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:31,489 INFO L290 TraceCheckUtils]: 48: Hoare triple {2061#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2061#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:31,490 INFO L290 TraceCheckUtils]: 49: Hoare triple {2061#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2062#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:31,490 INFO L290 TraceCheckUtils]: 50: Hoare triple {2062#(<= main_~i~0 22)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2062#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:31,490 INFO L290 TraceCheckUtils]: 51: Hoare triple {2062#(<= main_~i~0 22)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2063#(<= main_~i~0 23)} is VALID [2022-04-27 16:00:31,491 INFO L290 TraceCheckUtils]: 52: Hoare triple {2063#(<= main_~i~0 23)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2063#(<= main_~i~0 23)} is VALID [2022-04-27 16:00:31,491 INFO L290 TraceCheckUtils]: 53: Hoare triple {2063#(<= main_~i~0 23)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2064#(<= main_~i~0 24)} is VALID [2022-04-27 16:00:31,492 INFO L290 TraceCheckUtils]: 54: Hoare triple {2064#(<= main_~i~0 24)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2064#(<= main_~i~0 24)} is VALID [2022-04-27 16:00:31,492 INFO L290 TraceCheckUtils]: 55: Hoare triple {2064#(<= main_~i~0 24)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2065#(<= main_~i~0 25)} is VALID [2022-04-27 16:00:31,492 INFO L290 TraceCheckUtils]: 56: Hoare triple {2065#(<= main_~i~0 25)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2065#(<= main_~i~0 25)} is VALID [2022-04-27 16:00:31,493 INFO L290 TraceCheckUtils]: 57: Hoare triple {2065#(<= main_~i~0 25)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2066#(<= main_~i~0 26)} is VALID [2022-04-27 16:00:31,493 INFO L290 TraceCheckUtils]: 58: Hoare triple {2066#(<= main_~i~0 26)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2066#(<= main_~i~0 26)} is VALID [2022-04-27 16:00:31,493 INFO L290 TraceCheckUtils]: 59: Hoare triple {2066#(<= main_~i~0 26)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2067#(<= main_~i~0 27)} is VALID [2022-04-27 16:00:31,494 INFO L290 TraceCheckUtils]: 60: Hoare triple {2067#(<= main_~i~0 27)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2067#(<= main_~i~0 27)} is VALID [2022-04-27 16:00:31,499 INFO L290 TraceCheckUtils]: 61: Hoare triple {2067#(<= main_~i~0 27)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2068#(<= main_~i~0 28)} is VALID [2022-04-27 16:00:31,499 INFO L290 TraceCheckUtils]: 62: Hoare triple {2068#(<= main_~i~0 28)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2068#(<= main_~i~0 28)} is VALID [2022-04-27 16:00:31,499 INFO L290 TraceCheckUtils]: 63: Hoare triple {2068#(<= main_~i~0 28)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2069#(<= main_~i~0 29)} is VALID [2022-04-27 16:00:31,500 INFO L290 TraceCheckUtils]: 64: Hoare triple {2069#(<= main_~i~0 29)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2069#(<= main_~i~0 29)} is VALID [2022-04-27 16:00:31,500 INFO L290 TraceCheckUtils]: 65: Hoare triple {2069#(<= main_~i~0 29)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2070#(<= main_~i~0 30)} is VALID [2022-04-27 16:00:31,500 INFO L290 TraceCheckUtils]: 66: Hoare triple {2070#(<= main_~i~0 30)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2070#(<= main_~i~0 30)} is VALID [2022-04-27 16:00:31,501 INFO L290 TraceCheckUtils]: 67: Hoare triple {2070#(<= main_~i~0 30)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2071#(<= main_~i~0 31)} is VALID [2022-04-27 16:00:31,506 INFO L290 TraceCheckUtils]: 68: Hoare triple {2071#(<= main_~i~0 31)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2071#(<= main_~i~0 31)} is VALID [2022-04-27 16:00:31,507 INFO L290 TraceCheckUtils]: 69: Hoare triple {2071#(<= main_~i~0 31)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2072#(<= main_~i~0 32)} is VALID [2022-04-27 16:00:31,507 INFO L290 TraceCheckUtils]: 70: Hoare triple {2072#(<= main_~i~0 32)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2072#(<= main_~i~0 32)} is VALID [2022-04-27 16:00:31,508 INFO L290 TraceCheckUtils]: 71: Hoare triple {2072#(<= main_~i~0 32)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2073#(<= main_~i~0 33)} is VALID [2022-04-27 16:00:31,508 INFO L290 TraceCheckUtils]: 72: Hoare triple {2073#(<= main_~i~0 33)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2073#(<= main_~i~0 33)} is VALID [2022-04-27 16:00:31,508 INFO L290 TraceCheckUtils]: 73: Hoare triple {2073#(<= main_~i~0 33)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2074#(<= main_~i~0 34)} is VALID [2022-04-27 16:00:31,508 INFO L290 TraceCheckUtils]: 74: Hoare triple {2074#(<= main_~i~0 34)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2074#(<= main_~i~0 34)} is VALID [2022-04-27 16:00:31,509 INFO L290 TraceCheckUtils]: 75: Hoare triple {2074#(<= main_~i~0 34)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2075#(<= main_~i~0 35)} is VALID [2022-04-27 16:00:31,512 INFO L290 TraceCheckUtils]: 76: Hoare triple {2075#(<= main_~i~0 35)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2075#(<= main_~i~0 35)} is VALID [2022-04-27 16:00:31,513 INFO L290 TraceCheckUtils]: 77: Hoare triple {2075#(<= main_~i~0 35)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2076#(<= main_~i~0 36)} is VALID [2022-04-27 16:00:31,513 INFO L290 TraceCheckUtils]: 78: Hoare triple {2076#(<= main_~i~0 36)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2076#(<= main_~i~0 36)} is VALID [2022-04-27 16:00:31,514 INFO L290 TraceCheckUtils]: 79: Hoare triple {2076#(<= main_~i~0 36)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2077#(<= main_~i~0 37)} is VALID [2022-04-27 16:00:31,514 INFO L290 TraceCheckUtils]: 80: Hoare triple {2077#(<= main_~i~0 37)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2077#(<= main_~i~0 37)} is VALID [2022-04-27 16:00:31,514 INFO L290 TraceCheckUtils]: 81: Hoare triple {2077#(<= main_~i~0 37)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2078#(<= main_~i~0 38)} is VALID [2022-04-27 16:00:31,514 INFO L290 TraceCheckUtils]: 82: Hoare triple {2078#(<= main_~i~0 38)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2078#(<= main_~i~0 38)} is VALID [2022-04-27 16:00:31,515 INFO L290 TraceCheckUtils]: 83: Hoare triple {2078#(<= main_~i~0 38)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2079#(<= main_~i~0 39)} is VALID [2022-04-27 16:00:31,515 INFO L290 TraceCheckUtils]: 84: Hoare triple {2079#(<= main_~i~0 39)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2079#(<= main_~i~0 39)} is VALID [2022-04-27 16:00:31,515 INFO L290 TraceCheckUtils]: 85: Hoare triple {2079#(<= main_~i~0 39)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2080#(<= main_~i~0 40)} is VALID [2022-04-27 16:00:31,516 INFO L290 TraceCheckUtils]: 86: Hoare triple {2080#(<= main_~i~0 40)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2080#(<= main_~i~0 40)} is VALID [2022-04-27 16:00:31,516 INFO L290 TraceCheckUtils]: 87: Hoare triple {2080#(<= main_~i~0 40)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2081#(<= main_~i~0 41)} is VALID [2022-04-27 16:00:31,516 INFO L290 TraceCheckUtils]: 88: Hoare triple {2081#(<= main_~i~0 41)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2081#(<= main_~i~0 41)} is VALID [2022-04-27 16:00:31,517 INFO L290 TraceCheckUtils]: 89: Hoare triple {2081#(<= main_~i~0 41)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2082#(<= main_~i~0 42)} is VALID [2022-04-27 16:00:31,517 INFO L290 TraceCheckUtils]: 90: Hoare triple {2082#(<= main_~i~0 42)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2082#(<= main_~i~0 42)} is VALID [2022-04-27 16:00:31,517 INFO L290 TraceCheckUtils]: 91: Hoare triple {2082#(<= main_~i~0 42)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2083#(<= main_~i~0 43)} is VALID [2022-04-27 16:00:31,518 INFO L290 TraceCheckUtils]: 92: Hoare triple {2083#(<= main_~i~0 43)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2083#(<= main_~i~0 43)} is VALID [2022-04-27 16:00:31,518 INFO L290 TraceCheckUtils]: 93: Hoare triple {2083#(<= main_~i~0 43)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2084#(<= main_~i~0 44)} is VALID [2022-04-27 16:00:31,518 INFO L290 TraceCheckUtils]: 94: Hoare triple {2084#(<= main_~i~0 44)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2084#(<= main_~i~0 44)} is VALID [2022-04-27 16:00:31,519 INFO L290 TraceCheckUtils]: 95: Hoare triple {2084#(<= main_~i~0 44)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2085#(<= main_~i~0 45)} is VALID [2022-04-27 16:00:31,519 INFO L290 TraceCheckUtils]: 96: Hoare triple {2085#(<= main_~i~0 45)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2085#(<= main_~i~0 45)} is VALID [2022-04-27 16:00:31,519 INFO L290 TraceCheckUtils]: 97: Hoare triple {2085#(<= main_~i~0 45)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2086#(<= main_~i~0 46)} is VALID [2022-04-27 16:00:31,520 INFO L290 TraceCheckUtils]: 98: Hoare triple {2086#(<= main_~i~0 46)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:31,520 INFO L290 TraceCheckUtils]: 99: Hoare triple {2036#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {2036#false} is VALID [2022-04-27 16:00:31,520 INFO L272 TraceCheckUtils]: 100: Hoare triple {2036#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {2036#false} is VALID [2022-04-27 16:00:31,520 INFO L290 TraceCheckUtils]: 101: Hoare triple {2036#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2036#false} is VALID [2022-04-27 16:00:31,520 INFO L290 TraceCheckUtils]: 102: Hoare triple {2036#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:31,520 INFO L290 TraceCheckUtils]: 103: Hoare triple {2036#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:31,521 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:31,521 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:00:34,242 INFO L290 TraceCheckUtils]: 103: Hoare triple {2036#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:34,242 INFO L290 TraceCheckUtils]: 102: Hoare triple {2036#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:34,242 INFO L290 TraceCheckUtils]: 101: Hoare triple {2036#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2036#false} is VALID [2022-04-27 16:00:34,242 INFO L272 TraceCheckUtils]: 100: Hoare triple {2036#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {2036#false} is VALID [2022-04-27 16:00:34,242 INFO L290 TraceCheckUtils]: 99: Hoare triple {2036#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {2036#false} is VALID [2022-04-27 16:00:34,242 INFO L290 TraceCheckUtils]: 98: Hoare triple {2416#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {2036#false} is VALID [2022-04-27 16:00:34,243 INFO L290 TraceCheckUtils]: 97: Hoare triple {2420#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2416#(< main_~i~0 1024)} is VALID [2022-04-27 16:00:34,243 INFO L290 TraceCheckUtils]: 96: Hoare triple {2420#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2420#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:34,243 INFO L290 TraceCheckUtils]: 95: Hoare triple {2427#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2420#(< main_~i~0 1023)} is VALID [2022-04-27 16:00:34,244 INFO L290 TraceCheckUtils]: 94: Hoare triple {2427#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2427#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:34,244 INFO L290 TraceCheckUtils]: 93: Hoare triple {2434#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2427#(< main_~i~0 1022)} is VALID [2022-04-27 16:00:34,244 INFO L290 TraceCheckUtils]: 92: Hoare triple {2434#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2434#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:34,245 INFO L290 TraceCheckUtils]: 91: Hoare triple {2441#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2434#(< main_~i~0 1021)} is VALID [2022-04-27 16:00:34,245 INFO L290 TraceCheckUtils]: 90: Hoare triple {2441#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2441#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:34,245 INFO L290 TraceCheckUtils]: 89: Hoare triple {2448#(< main_~i~0 1019)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2441#(< main_~i~0 1020)} is VALID [2022-04-27 16:00:34,245 INFO L290 TraceCheckUtils]: 88: Hoare triple {2448#(< main_~i~0 1019)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2448#(< main_~i~0 1019)} is VALID [2022-04-27 16:00:34,246 INFO L290 TraceCheckUtils]: 87: Hoare triple {2455#(< main_~i~0 1018)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2448#(< main_~i~0 1019)} is VALID [2022-04-27 16:00:34,246 INFO L290 TraceCheckUtils]: 86: Hoare triple {2455#(< main_~i~0 1018)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2455#(< main_~i~0 1018)} is VALID [2022-04-27 16:00:34,246 INFO L290 TraceCheckUtils]: 85: Hoare triple {2462#(< main_~i~0 1017)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2455#(< main_~i~0 1018)} is VALID [2022-04-27 16:00:34,247 INFO L290 TraceCheckUtils]: 84: Hoare triple {2462#(< main_~i~0 1017)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2462#(< main_~i~0 1017)} is VALID [2022-04-27 16:00:34,247 INFO L290 TraceCheckUtils]: 83: Hoare triple {2469#(< main_~i~0 1016)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2462#(< main_~i~0 1017)} is VALID [2022-04-27 16:00:34,247 INFO L290 TraceCheckUtils]: 82: Hoare triple {2469#(< main_~i~0 1016)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2469#(< main_~i~0 1016)} is VALID [2022-04-27 16:00:34,248 INFO L290 TraceCheckUtils]: 81: Hoare triple {2476#(< main_~i~0 1015)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2469#(< main_~i~0 1016)} is VALID [2022-04-27 16:00:34,248 INFO L290 TraceCheckUtils]: 80: Hoare triple {2476#(< main_~i~0 1015)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2476#(< main_~i~0 1015)} is VALID [2022-04-27 16:00:34,248 INFO L290 TraceCheckUtils]: 79: Hoare triple {2483#(< main_~i~0 1014)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2476#(< main_~i~0 1015)} is VALID [2022-04-27 16:00:34,248 INFO L290 TraceCheckUtils]: 78: Hoare triple {2483#(< main_~i~0 1014)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2483#(< main_~i~0 1014)} is VALID [2022-04-27 16:00:34,249 INFO L290 TraceCheckUtils]: 77: Hoare triple {2490#(< main_~i~0 1013)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2483#(< main_~i~0 1014)} is VALID [2022-04-27 16:00:34,249 INFO L290 TraceCheckUtils]: 76: Hoare triple {2490#(< main_~i~0 1013)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2490#(< main_~i~0 1013)} is VALID [2022-04-27 16:00:34,249 INFO L290 TraceCheckUtils]: 75: Hoare triple {2497#(< main_~i~0 1012)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2490#(< main_~i~0 1013)} is VALID [2022-04-27 16:00:34,250 INFO L290 TraceCheckUtils]: 74: Hoare triple {2497#(< main_~i~0 1012)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2497#(< main_~i~0 1012)} is VALID [2022-04-27 16:00:34,250 INFO L290 TraceCheckUtils]: 73: Hoare triple {2504#(< main_~i~0 1011)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2497#(< main_~i~0 1012)} is VALID [2022-04-27 16:00:34,250 INFO L290 TraceCheckUtils]: 72: Hoare triple {2504#(< main_~i~0 1011)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2504#(< main_~i~0 1011)} is VALID [2022-04-27 16:00:34,251 INFO L290 TraceCheckUtils]: 71: Hoare triple {2511#(< main_~i~0 1010)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2504#(< main_~i~0 1011)} is VALID [2022-04-27 16:00:34,251 INFO L290 TraceCheckUtils]: 70: Hoare triple {2511#(< main_~i~0 1010)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2511#(< main_~i~0 1010)} is VALID [2022-04-27 16:00:34,251 INFO L290 TraceCheckUtils]: 69: Hoare triple {2518#(< main_~i~0 1009)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2511#(< main_~i~0 1010)} is VALID [2022-04-27 16:00:34,251 INFO L290 TraceCheckUtils]: 68: Hoare triple {2518#(< main_~i~0 1009)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2518#(< main_~i~0 1009)} is VALID [2022-04-27 16:00:34,252 INFO L290 TraceCheckUtils]: 67: Hoare triple {2525#(< main_~i~0 1008)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2518#(< main_~i~0 1009)} is VALID [2022-04-27 16:00:34,252 INFO L290 TraceCheckUtils]: 66: Hoare triple {2525#(< main_~i~0 1008)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2525#(< main_~i~0 1008)} is VALID [2022-04-27 16:00:34,252 INFO L290 TraceCheckUtils]: 65: Hoare triple {2532#(< main_~i~0 1007)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2525#(< main_~i~0 1008)} is VALID [2022-04-27 16:00:34,253 INFO L290 TraceCheckUtils]: 64: Hoare triple {2532#(< main_~i~0 1007)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2532#(< main_~i~0 1007)} is VALID [2022-04-27 16:00:34,253 INFO L290 TraceCheckUtils]: 63: Hoare triple {2539#(< main_~i~0 1006)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2532#(< main_~i~0 1007)} is VALID [2022-04-27 16:00:34,253 INFO L290 TraceCheckUtils]: 62: Hoare triple {2539#(< main_~i~0 1006)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2539#(< main_~i~0 1006)} is VALID [2022-04-27 16:00:34,266 INFO L290 TraceCheckUtils]: 61: Hoare triple {2546#(< main_~i~0 1005)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2539#(< main_~i~0 1006)} is VALID [2022-04-27 16:00:34,267 INFO L290 TraceCheckUtils]: 60: Hoare triple {2546#(< main_~i~0 1005)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2546#(< main_~i~0 1005)} is VALID [2022-04-27 16:00:34,267 INFO L290 TraceCheckUtils]: 59: Hoare triple {2553#(< main_~i~0 1004)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2546#(< main_~i~0 1005)} is VALID [2022-04-27 16:00:34,267 INFO L290 TraceCheckUtils]: 58: Hoare triple {2553#(< main_~i~0 1004)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2553#(< main_~i~0 1004)} is VALID [2022-04-27 16:00:34,268 INFO L290 TraceCheckUtils]: 57: Hoare triple {2560#(< main_~i~0 1003)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2553#(< main_~i~0 1004)} is VALID [2022-04-27 16:00:34,268 INFO L290 TraceCheckUtils]: 56: Hoare triple {2560#(< main_~i~0 1003)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2560#(< main_~i~0 1003)} is VALID [2022-04-27 16:00:34,268 INFO L290 TraceCheckUtils]: 55: Hoare triple {2567#(< main_~i~0 1002)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2560#(< main_~i~0 1003)} is VALID [2022-04-27 16:00:34,269 INFO L290 TraceCheckUtils]: 54: Hoare triple {2567#(< main_~i~0 1002)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2567#(< main_~i~0 1002)} is VALID [2022-04-27 16:00:34,269 INFO L290 TraceCheckUtils]: 53: Hoare triple {2574#(< main_~i~0 1001)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2567#(< main_~i~0 1002)} is VALID [2022-04-27 16:00:34,269 INFO L290 TraceCheckUtils]: 52: Hoare triple {2574#(< main_~i~0 1001)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2574#(< main_~i~0 1001)} is VALID [2022-04-27 16:00:34,270 INFO L290 TraceCheckUtils]: 51: Hoare triple {2581#(< main_~i~0 1000)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2574#(< main_~i~0 1001)} is VALID [2022-04-27 16:00:34,270 INFO L290 TraceCheckUtils]: 50: Hoare triple {2581#(< main_~i~0 1000)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2581#(< main_~i~0 1000)} is VALID [2022-04-27 16:00:34,270 INFO L290 TraceCheckUtils]: 49: Hoare triple {2588#(< main_~i~0 999)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2581#(< main_~i~0 1000)} is VALID [2022-04-27 16:00:34,271 INFO L290 TraceCheckUtils]: 48: Hoare triple {2588#(< main_~i~0 999)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2588#(< main_~i~0 999)} is VALID [2022-04-27 16:00:34,271 INFO L290 TraceCheckUtils]: 47: Hoare triple {2595#(< main_~i~0 998)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2588#(< main_~i~0 999)} is VALID [2022-04-27 16:00:34,271 INFO L290 TraceCheckUtils]: 46: Hoare triple {2595#(< main_~i~0 998)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2595#(< main_~i~0 998)} is VALID [2022-04-27 16:00:34,274 INFO L290 TraceCheckUtils]: 45: Hoare triple {2602#(< main_~i~0 997)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2595#(< main_~i~0 998)} is VALID [2022-04-27 16:00:34,274 INFO L290 TraceCheckUtils]: 44: Hoare triple {2602#(< main_~i~0 997)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2602#(< main_~i~0 997)} is VALID [2022-04-27 16:00:34,275 INFO L290 TraceCheckUtils]: 43: Hoare triple {2609#(< main_~i~0 996)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2602#(< main_~i~0 997)} is VALID [2022-04-27 16:00:34,275 INFO L290 TraceCheckUtils]: 42: Hoare triple {2609#(< main_~i~0 996)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2609#(< main_~i~0 996)} is VALID [2022-04-27 16:00:34,275 INFO L290 TraceCheckUtils]: 41: Hoare triple {2616#(< main_~i~0 995)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2609#(< main_~i~0 996)} is VALID [2022-04-27 16:00:34,276 INFO L290 TraceCheckUtils]: 40: Hoare triple {2616#(< main_~i~0 995)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2616#(< main_~i~0 995)} is VALID [2022-04-27 16:00:34,276 INFO L290 TraceCheckUtils]: 39: Hoare triple {2623#(< main_~i~0 994)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2616#(< main_~i~0 995)} is VALID [2022-04-27 16:00:34,276 INFO L290 TraceCheckUtils]: 38: Hoare triple {2623#(< main_~i~0 994)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2623#(< main_~i~0 994)} is VALID [2022-04-27 16:00:34,277 INFO L290 TraceCheckUtils]: 37: Hoare triple {2630#(< main_~i~0 993)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2623#(< main_~i~0 994)} is VALID [2022-04-27 16:00:34,277 INFO L290 TraceCheckUtils]: 36: Hoare triple {2630#(< main_~i~0 993)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2630#(< main_~i~0 993)} is VALID [2022-04-27 16:00:34,277 INFO L290 TraceCheckUtils]: 35: Hoare triple {2637#(< main_~i~0 992)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2630#(< main_~i~0 993)} is VALID [2022-04-27 16:00:34,278 INFO L290 TraceCheckUtils]: 34: Hoare triple {2637#(< main_~i~0 992)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2637#(< main_~i~0 992)} is VALID [2022-04-27 16:00:34,278 INFO L290 TraceCheckUtils]: 33: Hoare triple {2644#(< main_~i~0 991)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2637#(< main_~i~0 992)} is VALID [2022-04-27 16:00:34,278 INFO L290 TraceCheckUtils]: 32: Hoare triple {2644#(< main_~i~0 991)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2644#(< main_~i~0 991)} is VALID [2022-04-27 16:00:34,279 INFO L290 TraceCheckUtils]: 31: Hoare triple {2651#(< main_~i~0 990)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2644#(< main_~i~0 991)} is VALID [2022-04-27 16:00:34,279 INFO L290 TraceCheckUtils]: 30: Hoare triple {2651#(< main_~i~0 990)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2651#(< main_~i~0 990)} is VALID [2022-04-27 16:00:34,279 INFO L290 TraceCheckUtils]: 29: Hoare triple {2658#(< main_~i~0 989)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2651#(< main_~i~0 990)} is VALID [2022-04-27 16:00:34,280 INFO L290 TraceCheckUtils]: 28: Hoare triple {2658#(< main_~i~0 989)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2658#(< main_~i~0 989)} is VALID [2022-04-27 16:00:34,280 INFO L290 TraceCheckUtils]: 27: Hoare triple {2665#(< main_~i~0 988)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2658#(< main_~i~0 989)} is VALID [2022-04-27 16:00:34,280 INFO L290 TraceCheckUtils]: 26: Hoare triple {2665#(< main_~i~0 988)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2665#(< main_~i~0 988)} is VALID [2022-04-27 16:00:34,281 INFO L290 TraceCheckUtils]: 25: Hoare triple {2672#(< main_~i~0 987)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2665#(< main_~i~0 988)} is VALID [2022-04-27 16:00:34,281 INFO L290 TraceCheckUtils]: 24: Hoare triple {2672#(< main_~i~0 987)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2672#(< main_~i~0 987)} is VALID [2022-04-27 16:00:34,281 INFO L290 TraceCheckUtils]: 23: Hoare triple {2679#(< main_~i~0 986)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2672#(< main_~i~0 987)} is VALID [2022-04-27 16:00:34,281 INFO L290 TraceCheckUtils]: 22: Hoare triple {2679#(< main_~i~0 986)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2679#(< main_~i~0 986)} is VALID [2022-04-27 16:00:34,282 INFO L290 TraceCheckUtils]: 21: Hoare triple {2686#(< main_~i~0 985)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2679#(< main_~i~0 986)} is VALID [2022-04-27 16:00:34,282 INFO L290 TraceCheckUtils]: 20: Hoare triple {2686#(< main_~i~0 985)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2686#(< main_~i~0 985)} is VALID [2022-04-27 16:00:34,283 INFO L290 TraceCheckUtils]: 19: Hoare triple {2693#(< main_~i~0 984)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2686#(< main_~i~0 985)} is VALID [2022-04-27 16:00:34,283 INFO L290 TraceCheckUtils]: 18: Hoare triple {2693#(< main_~i~0 984)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2693#(< main_~i~0 984)} is VALID [2022-04-27 16:00:34,283 INFO L290 TraceCheckUtils]: 17: Hoare triple {2700#(< main_~i~0 983)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2693#(< main_~i~0 984)} is VALID [2022-04-27 16:00:34,283 INFO L290 TraceCheckUtils]: 16: Hoare triple {2700#(< main_~i~0 983)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2700#(< main_~i~0 983)} is VALID [2022-04-27 16:00:34,284 INFO L290 TraceCheckUtils]: 15: Hoare triple {2707#(< main_~i~0 982)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2700#(< main_~i~0 983)} is VALID [2022-04-27 16:00:34,284 INFO L290 TraceCheckUtils]: 14: Hoare triple {2707#(< main_~i~0 982)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2707#(< main_~i~0 982)} is VALID [2022-04-27 16:00:34,284 INFO L290 TraceCheckUtils]: 13: Hoare triple {2714#(< main_~i~0 981)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2707#(< main_~i~0 982)} is VALID [2022-04-27 16:00:34,285 INFO L290 TraceCheckUtils]: 12: Hoare triple {2714#(< main_~i~0 981)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2714#(< main_~i~0 981)} is VALID [2022-04-27 16:00:34,285 INFO L290 TraceCheckUtils]: 11: Hoare triple {2721#(< main_~i~0 980)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2714#(< main_~i~0 981)} is VALID [2022-04-27 16:00:34,285 INFO L290 TraceCheckUtils]: 10: Hoare triple {2721#(< main_~i~0 980)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2721#(< main_~i~0 980)} is VALID [2022-04-27 16:00:34,286 INFO L290 TraceCheckUtils]: 9: Hoare triple {2728#(< main_~i~0 979)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2721#(< main_~i~0 980)} is VALID [2022-04-27 16:00:34,286 INFO L290 TraceCheckUtils]: 8: Hoare triple {2728#(< main_~i~0 979)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2728#(< main_~i~0 979)} is VALID [2022-04-27 16:00:34,286 INFO L290 TraceCheckUtils]: 7: Hoare triple {2735#(< main_~i~0 978)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2728#(< main_~i~0 979)} is VALID [2022-04-27 16:00:34,287 INFO L290 TraceCheckUtils]: 6: Hoare triple {2735#(< main_~i~0 978)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2735#(< main_~i~0 978)} is VALID [2022-04-27 16:00:34,287 INFO L290 TraceCheckUtils]: 5: Hoare triple {2035#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {2735#(< main_~i~0 978)} is VALID [2022-04-27 16:00:34,287 INFO L272 TraceCheckUtils]: 4: Hoare triple {2035#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:34,287 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2035#true} {2035#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:34,287 INFO L290 TraceCheckUtils]: 2: Hoare triple {2035#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:34,287 INFO L290 TraceCheckUtils]: 1: Hoare triple {2035#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2035#true} is VALID [2022-04-27 16:00:34,287 INFO L272 TraceCheckUtils]: 0: Hoare triple {2035#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2035#true} is VALID [2022-04-27 16:00:34,288 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:34,288 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [734748323] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:00:34,289 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:00:34,289 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49, 49] total 98 [2022-04-27 16:00:34,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2096950097] [2022-04-27 16:00:34,289 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:00:34,290 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 104 [2022-04-27 16:00:34,290 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:00:34,290 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:34,438 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 203 edges. 203 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:34,438 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-04-27 16:00:34,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:00:34,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-04-27 16:00:34,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4658, Invalid=4848, Unknown=0, NotChecked=0, Total=9506 [2022-04-27 16:00:34,442 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:38,072 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2022-04-27 16:00:38,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2022-04-27 16:00:38,073 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 104 [2022-04-27 16:00:38,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:00:38,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 249 transitions. [2022-04-27 16:00:38,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 249 transitions. [2022-04-27 16:00:38,085 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 97 states and 249 transitions. [2022-04-27 16:00:38,289 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 249 edges. 249 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:00:38,294 INFO L225 Difference]: With dead ends: 201 [2022-04-27 16:00:38,294 INFO L226 Difference]: Without dead ends: 201 [2022-04-27 16:00:38,301 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 352 GetRequests, 162 SyntacticMatches, 0 SemanticMatches, 190 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5728 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=13777, Invalid=22895, Unknown=0, NotChecked=0, Total=36672 [2022-04-27 16:00:38,302 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 195 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 216 mSolverCounterSat, 149 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 195 SdHoareTripleChecker+Valid, 34 SdHoareTripleChecker+Invalid, 365 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 149 IncrementalHoareTripleChecker+Valid, 216 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:00:38,302 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [195 Valid, 34 Invalid, 365 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [149 Valid, 216 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 16:00:38,303 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2022-04-27 16:00:38,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2022-04-27 16:00:38,309 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:00:38,309 INFO L82 GeneralOperation]: Start isEquivalent. First operand 201 states. Second operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,309 INFO L74 IsIncluded]: Start isIncluded. First operand 201 states. Second operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,310 INFO L87 Difference]: Start difference. First operand 201 states. Second operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:38,315 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2022-04-27 16:00:38,315 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2022-04-27 16:00:38,316 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:38,316 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:38,316 INFO L74 IsIncluded]: Start isIncluded. First operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 201 states. [2022-04-27 16:00:38,317 INFO L87 Difference]: Start difference. First operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 201 states. [2022-04-27 16:00:38,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:00:38,322 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2022-04-27 16:00:38,322 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2022-04-27 16:00:38,322 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:00:38,323 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:00:38,323 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:00:38,323 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:00:38,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2022-04-27 16:00:38,328 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 201 transitions. Word has length 104 [2022-04-27 16:00:38,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:00:38,328 INFO L495 AbstractCegarLoop]: Abstraction has 201 states and 201 transitions. [2022-04-27 16:00:38,329 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:00:38,329 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2022-04-27 16:00:38,330 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2022-04-27 16:00:38,330 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:00:38,330 INFO L195 NwaCegarLoop]: trace histogram [94, 94, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:00:38,366 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 16:00:38,555 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:38,555 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:00:38,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:00:38,556 INFO L85 PathProgramCache]: Analyzing trace with hash -560303625, now seen corresponding path program 6 times [2022-04-27 16:00:38,556 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:00:38,556 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [842264560] [2022-04-27 16:00:38,556 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:00:38,556 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:00:38,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:41,620 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:00:41,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:00:41,624 INFO L290 TraceCheckUtils]: 0: Hoare triple {3851#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3751#true} is VALID [2022-04-27 16:00:41,624 INFO L290 TraceCheckUtils]: 1: Hoare triple {3751#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3751#true} is VALID [2022-04-27 16:00:41,624 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3751#true} {3751#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3751#true} is VALID [2022-04-27 16:00:41,625 INFO L272 TraceCheckUtils]: 0: Hoare triple {3751#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3851#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:00:41,625 INFO L290 TraceCheckUtils]: 1: Hoare triple {3851#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3751#true} is VALID [2022-04-27 16:00:41,625 INFO L290 TraceCheckUtils]: 2: Hoare triple {3751#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3751#true} is VALID [2022-04-27 16:00:41,625 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3751#true} {3751#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3751#true} is VALID [2022-04-27 16:00:41,625 INFO L272 TraceCheckUtils]: 4: Hoare triple {3751#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3751#true} is VALID [2022-04-27 16:00:41,625 INFO L290 TraceCheckUtils]: 5: Hoare triple {3751#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {3756#(= main_~i~0 0)} is VALID [2022-04-27 16:00:41,625 INFO L290 TraceCheckUtils]: 6: Hoare triple {3756#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3756#(= main_~i~0 0)} is VALID [2022-04-27 16:00:41,626 INFO L290 TraceCheckUtils]: 7: Hoare triple {3756#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3757#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:41,626 INFO L290 TraceCheckUtils]: 8: Hoare triple {3757#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3757#(<= main_~i~0 1)} is VALID [2022-04-27 16:00:41,626 INFO L290 TraceCheckUtils]: 9: Hoare triple {3757#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3758#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:41,627 INFO L290 TraceCheckUtils]: 10: Hoare triple {3758#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3758#(<= main_~i~0 2)} is VALID [2022-04-27 16:00:41,627 INFO L290 TraceCheckUtils]: 11: Hoare triple {3758#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3759#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:41,627 INFO L290 TraceCheckUtils]: 12: Hoare triple {3759#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3759#(<= main_~i~0 3)} is VALID [2022-04-27 16:00:41,628 INFO L290 TraceCheckUtils]: 13: Hoare triple {3759#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3760#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:41,628 INFO L290 TraceCheckUtils]: 14: Hoare triple {3760#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3760#(<= main_~i~0 4)} is VALID [2022-04-27 16:00:41,628 INFO L290 TraceCheckUtils]: 15: Hoare triple {3760#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3761#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:41,628 INFO L290 TraceCheckUtils]: 16: Hoare triple {3761#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3761#(<= main_~i~0 5)} is VALID [2022-04-27 16:00:41,629 INFO L290 TraceCheckUtils]: 17: Hoare triple {3761#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3762#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:41,629 INFO L290 TraceCheckUtils]: 18: Hoare triple {3762#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3762#(<= main_~i~0 6)} is VALID [2022-04-27 16:00:41,629 INFO L290 TraceCheckUtils]: 19: Hoare triple {3762#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3763#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:41,630 INFO L290 TraceCheckUtils]: 20: Hoare triple {3763#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3763#(<= main_~i~0 7)} is VALID [2022-04-27 16:00:41,630 INFO L290 TraceCheckUtils]: 21: Hoare triple {3763#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3764#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:41,630 INFO L290 TraceCheckUtils]: 22: Hoare triple {3764#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3764#(<= main_~i~0 8)} is VALID [2022-04-27 16:00:41,631 INFO L290 TraceCheckUtils]: 23: Hoare triple {3764#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3765#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:41,631 INFO L290 TraceCheckUtils]: 24: Hoare triple {3765#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3765#(<= main_~i~0 9)} is VALID [2022-04-27 16:00:41,631 INFO L290 TraceCheckUtils]: 25: Hoare triple {3765#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3766#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:41,631 INFO L290 TraceCheckUtils]: 26: Hoare triple {3766#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3766#(<= main_~i~0 10)} is VALID [2022-04-27 16:00:41,632 INFO L290 TraceCheckUtils]: 27: Hoare triple {3766#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3767#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:41,632 INFO L290 TraceCheckUtils]: 28: Hoare triple {3767#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3767#(<= main_~i~0 11)} is VALID [2022-04-27 16:00:41,632 INFO L290 TraceCheckUtils]: 29: Hoare triple {3767#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3768#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:41,633 INFO L290 TraceCheckUtils]: 30: Hoare triple {3768#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3768#(<= main_~i~0 12)} is VALID [2022-04-27 16:00:41,633 INFO L290 TraceCheckUtils]: 31: Hoare triple {3768#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3769#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:41,633 INFO L290 TraceCheckUtils]: 32: Hoare triple {3769#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3769#(<= main_~i~0 13)} is VALID [2022-04-27 16:00:41,634 INFO L290 TraceCheckUtils]: 33: Hoare triple {3769#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3770#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:41,634 INFO L290 TraceCheckUtils]: 34: Hoare triple {3770#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3770#(<= main_~i~0 14)} is VALID [2022-04-27 16:00:41,634 INFO L290 TraceCheckUtils]: 35: Hoare triple {3770#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3771#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:41,634 INFO L290 TraceCheckUtils]: 36: Hoare triple {3771#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3771#(<= main_~i~0 15)} is VALID [2022-04-27 16:00:41,635 INFO L290 TraceCheckUtils]: 37: Hoare triple {3771#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3772#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:41,635 INFO L290 TraceCheckUtils]: 38: Hoare triple {3772#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3772#(<= main_~i~0 16)} is VALID [2022-04-27 16:00:41,635 INFO L290 TraceCheckUtils]: 39: Hoare triple {3772#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3773#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:41,636 INFO L290 TraceCheckUtils]: 40: Hoare triple {3773#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3773#(<= main_~i~0 17)} is VALID [2022-04-27 16:00:41,636 INFO L290 TraceCheckUtils]: 41: Hoare triple {3773#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3774#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:41,636 INFO L290 TraceCheckUtils]: 42: Hoare triple {3774#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3774#(<= main_~i~0 18)} is VALID [2022-04-27 16:00:41,637 INFO L290 TraceCheckUtils]: 43: Hoare triple {3774#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3775#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:41,637 INFO L290 TraceCheckUtils]: 44: Hoare triple {3775#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3775#(<= main_~i~0 19)} is VALID [2022-04-27 16:00:41,637 INFO L290 TraceCheckUtils]: 45: Hoare triple {3775#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3776#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:41,638 INFO L290 TraceCheckUtils]: 46: Hoare triple {3776#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3776#(<= main_~i~0 20)} is VALID [2022-04-27 16:00:41,638 INFO L290 TraceCheckUtils]: 47: Hoare triple {3776#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3777#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:41,638 INFO L290 TraceCheckUtils]: 48: Hoare triple {3777#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3777#(<= main_~i~0 21)} is VALID [2022-04-27 16:00:41,638 INFO L290 TraceCheckUtils]: 49: Hoare triple {3777#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3778#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:41,639 INFO L290 TraceCheckUtils]: 50: Hoare triple {3778#(<= main_~i~0 22)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3778#(<= main_~i~0 22)} is VALID [2022-04-27 16:00:41,639 INFO L290 TraceCheckUtils]: 51: Hoare triple {3778#(<= main_~i~0 22)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3779#(<= main_~i~0 23)} is VALID [2022-04-27 16:00:41,639 INFO L290 TraceCheckUtils]: 52: Hoare triple {3779#(<= main_~i~0 23)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3779#(<= main_~i~0 23)} is VALID [2022-04-27 16:00:41,640 INFO L290 TraceCheckUtils]: 53: Hoare triple {3779#(<= main_~i~0 23)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3780#(<= main_~i~0 24)} is VALID [2022-04-27 16:00:41,640 INFO L290 TraceCheckUtils]: 54: Hoare triple {3780#(<= main_~i~0 24)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3780#(<= main_~i~0 24)} is VALID [2022-04-27 16:00:41,640 INFO L290 TraceCheckUtils]: 55: Hoare triple {3780#(<= main_~i~0 24)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3781#(<= main_~i~0 25)} is VALID [2022-04-27 16:00:41,641 INFO L290 TraceCheckUtils]: 56: Hoare triple {3781#(<= main_~i~0 25)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3781#(<= main_~i~0 25)} is VALID [2022-04-27 16:00:41,641 INFO L290 TraceCheckUtils]: 57: Hoare triple {3781#(<= main_~i~0 25)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3782#(<= main_~i~0 26)} is VALID [2022-04-27 16:00:41,641 INFO L290 TraceCheckUtils]: 58: Hoare triple {3782#(<= main_~i~0 26)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3782#(<= main_~i~0 26)} is VALID [2022-04-27 16:00:41,641 INFO L290 TraceCheckUtils]: 59: Hoare triple {3782#(<= main_~i~0 26)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3783#(<= main_~i~0 27)} is VALID [2022-04-27 16:00:41,642 INFO L290 TraceCheckUtils]: 60: Hoare triple {3783#(<= main_~i~0 27)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3783#(<= main_~i~0 27)} is VALID [2022-04-27 16:00:41,642 INFO L290 TraceCheckUtils]: 61: Hoare triple {3783#(<= main_~i~0 27)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3784#(<= main_~i~0 28)} is VALID [2022-04-27 16:00:41,642 INFO L290 TraceCheckUtils]: 62: Hoare triple {3784#(<= main_~i~0 28)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3784#(<= main_~i~0 28)} is VALID [2022-04-27 16:00:41,643 INFO L290 TraceCheckUtils]: 63: Hoare triple {3784#(<= main_~i~0 28)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3785#(<= main_~i~0 29)} is VALID [2022-04-27 16:00:41,643 INFO L290 TraceCheckUtils]: 64: Hoare triple {3785#(<= main_~i~0 29)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3785#(<= main_~i~0 29)} is VALID [2022-04-27 16:00:41,643 INFO L290 TraceCheckUtils]: 65: Hoare triple {3785#(<= main_~i~0 29)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3786#(<= main_~i~0 30)} is VALID [2022-04-27 16:00:41,644 INFO L290 TraceCheckUtils]: 66: Hoare triple {3786#(<= main_~i~0 30)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3786#(<= main_~i~0 30)} is VALID [2022-04-27 16:00:41,644 INFO L290 TraceCheckUtils]: 67: Hoare triple {3786#(<= main_~i~0 30)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3787#(<= main_~i~0 31)} is VALID [2022-04-27 16:00:41,644 INFO L290 TraceCheckUtils]: 68: Hoare triple {3787#(<= main_~i~0 31)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3787#(<= main_~i~0 31)} is VALID [2022-04-27 16:00:41,644 INFO L290 TraceCheckUtils]: 69: Hoare triple {3787#(<= main_~i~0 31)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3788#(<= main_~i~0 32)} is VALID [2022-04-27 16:00:41,645 INFO L290 TraceCheckUtils]: 70: Hoare triple {3788#(<= main_~i~0 32)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3788#(<= main_~i~0 32)} is VALID [2022-04-27 16:00:41,645 INFO L290 TraceCheckUtils]: 71: Hoare triple {3788#(<= main_~i~0 32)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3789#(<= main_~i~0 33)} is VALID [2022-04-27 16:00:41,645 INFO L290 TraceCheckUtils]: 72: Hoare triple {3789#(<= main_~i~0 33)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3789#(<= main_~i~0 33)} is VALID [2022-04-27 16:00:41,646 INFO L290 TraceCheckUtils]: 73: Hoare triple {3789#(<= main_~i~0 33)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3790#(<= main_~i~0 34)} is VALID [2022-04-27 16:00:41,646 INFO L290 TraceCheckUtils]: 74: Hoare triple {3790#(<= main_~i~0 34)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3790#(<= main_~i~0 34)} is VALID [2022-04-27 16:00:41,646 INFO L290 TraceCheckUtils]: 75: Hoare triple {3790#(<= main_~i~0 34)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3791#(<= main_~i~0 35)} is VALID [2022-04-27 16:00:41,646 INFO L290 TraceCheckUtils]: 76: Hoare triple {3791#(<= main_~i~0 35)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3791#(<= main_~i~0 35)} is VALID [2022-04-27 16:00:41,647 INFO L290 TraceCheckUtils]: 77: Hoare triple {3791#(<= main_~i~0 35)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3792#(<= main_~i~0 36)} is VALID [2022-04-27 16:00:41,647 INFO L290 TraceCheckUtils]: 78: Hoare triple {3792#(<= main_~i~0 36)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3792#(<= main_~i~0 36)} is VALID [2022-04-27 16:00:41,647 INFO L290 TraceCheckUtils]: 79: Hoare triple {3792#(<= main_~i~0 36)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3793#(<= main_~i~0 37)} is VALID [2022-04-27 16:00:41,648 INFO L290 TraceCheckUtils]: 80: Hoare triple {3793#(<= main_~i~0 37)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3793#(<= main_~i~0 37)} is VALID [2022-04-27 16:00:41,648 INFO L290 TraceCheckUtils]: 81: Hoare triple {3793#(<= main_~i~0 37)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3794#(<= main_~i~0 38)} is VALID [2022-04-27 16:00:41,648 INFO L290 TraceCheckUtils]: 82: Hoare triple {3794#(<= main_~i~0 38)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3794#(<= main_~i~0 38)} is VALID [2022-04-27 16:00:41,649 INFO L290 TraceCheckUtils]: 83: Hoare triple {3794#(<= main_~i~0 38)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3795#(<= main_~i~0 39)} is VALID [2022-04-27 16:00:41,649 INFO L290 TraceCheckUtils]: 84: Hoare triple {3795#(<= main_~i~0 39)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3795#(<= main_~i~0 39)} is VALID [2022-04-27 16:00:41,649 INFO L290 TraceCheckUtils]: 85: Hoare triple {3795#(<= main_~i~0 39)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3796#(<= main_~i~0 40)} is VALID [2022-04-27 16:00:41,649 INFO L290 TraceCheckUtils]: 86: Hoare triple {3796#(<= main_~i~0 40)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3796#(<= main_~i~0 40)} is VALID [2022-04-27 16:00:41,650 INFO L290 TraceCheckUtils]: 87: Hoare triple {3796#(<= main_~i~0 40)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3797#(<= main_~i~0 41)} is VALID [2022-04-27 16:00:41,650 INFO L290 TraceCheckUtils]: 88: Hoare triple {3797#(<= main_~i~0 41)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3797#(<= main_~i~0 41)} is VALID [2022-04-27 16:00:41,650 INFO L290 TraceCheckUtils]: 89: Hoare triple {3797#(<= main_~i~0 41)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3798#(<= main_~i~0 42)} is VALID [2022-04-27 16:00:41,651 INFO L290 TraceCheckUtils]: 90: Hoare triple {3798#(<= main_~i~0 42)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3798#(<= main_~i~0 42)} is VALID [2022-04-27 16:00:41,651 INFO L290 TraceCheckUtils]: 91: Hoare triple {3798#(<= main_~i~0 42)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3799#(<= main_~i~0 43)} is VALID [2022-04-27 16:00:41,651 INFO L290 TraceCheckUtils]: 92: Hoare triple {3799#(<= main_~i~0 43)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3799#(<= main_~i~0 43)} is VALID [2022-04-27 16:00:41,652 INFO L290 TraceCheckUtils]: 93: Hoare triple {3799#(<= main_~i~0 43)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3800#(<= main_~i~0 44)} is VALID [2022-04-27 16:00:41,652 INFO L290 TraceCheckUtils]: 94: Hoare triple {3800#(<= main_~i~0 44)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3800#(<= main_~i~0 44)} is VALID [2022-04-27 16:00:41,652 INFO L290 TraceCheckUtils]: 95: Hoare triple {3800#(<= main_~i~0 44)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3801#(<= main_~i~0 45)} is VALID [2022-04-27 16:00:41,653 INFO L290 TraceCheckUtils]: 96: Hoare triple {3801#(<= main_~i~0 45)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3801#(<= main_~i~0 45)} is VALID [2022-04-27 16:00:41,653 INFO L290 TraceCheckUtils]: 97: Hoare triple {3801#(<= main_~i~0 45)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3802#(<= main_~i~0 46)} is VALID [2022-04-27 16:00:41,653 INFO L290 TraceCheckUtils]: 98: Hoare triple {3802#(<= main_~i~0 46)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3802#(<= main_~i~0 46)} is VALID [2022-04-27 16:00:41,653 INFO L290 TraceCheckUtils]: 99: Hoare triple {3802#(<= main_~i~0 46)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3803#(<= main_~i~0 47)} is VALID [2022-04-27 16:00:41,654 INFO L290 TraceCheckUtils]: 100: Hoare triple {3803#(<= main_~i~0 47)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3803#(<= main_~i~0 47)} is VALID [2022-04-27 16:00:41,654 INFO L290 TraceCheckUtils]: 101: Hoare triple {3803#(<= main_~i~0 47)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3804#(<= main_~i~0 48)} is VALID [2022-04-27 16:00:41,654 INFO L290 TraceCheckUtils]: 102: Hoare triple {3804#(<= main_~i~0 48)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3804#(<= main_~i~0 48)} is VALID [2022-04-27 16:00:41,655 INFO L290 TraceCheckUtils]: 103: Hoare triple {3804#(<= main_~i~0 48)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3805#(<= main_~i~0 49)} is VALID [2022-04-27 16:00:41,655 INFO L290 TraceCheckUtils]: 104: Hoare triple {3805#(<= main_~i~0 49)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3805#(<= main_~i~0 49)} is VALID [2022-04-27 16:00:41,655 INFO L290 TraceCheckUtils]: 105: Hoare triple {3805#(<= main_~i~0 49)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3806#(<= main_~i~0 50)} is VALID [2022-04-27 16:00:41,656 INFO L290 TraceCheckUtils]: 106: Hoare triple {3806#(<= main_~i~0 50)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3806#(<= main_~i~0 50)} is VALID [2022-04-27 16:00:41,659 INFO L290 TraceCheckUtils]: 107: Hoare triple {3806#(<= main_~i~0 50)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3807#(<= main_~i~0 51)} is VALID [2022-04-27 16:00:41,660 INFO L290 TraceCheckUtils]: 108: Hoare triple {3807#(<= main_~i~0 51)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3807#(<= main_~i~0 51)} is VALID [2022-04-27 16:00:41,660 INFO L290 TraceCheckUtils]: 109: Hoare triple {3807#(<= main_~i~0 51)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3808#(<= main_~i~0 52)} is VALID [2022-04-27 16:00:41,660 INFO L290 TraceCheckUtils]: 110: Hoare triple {3808#(<= main_~i~0 52)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3808#(<= main_~i~0 52)} is VALID [2022-04-27 16:00:41,661 INFO L290 TraceCheckUtils]: 111: Hoare triple {3808#(<= main_~i~0 52)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3809#(<= main_~i~0 53)} is VALID [2022-04-27 16:00:41,661 INFO L290 TraceCheckUtils]: 112: Hoare triple {3809#(<= main_~i~0 53)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3809#(<= main_~i~0 53)} is VALID [2022-04-27 16:00:41,661 INFO L290 TraceCheckUtils]: 113: Hoare triple {3809#(<= main_~i~0 53)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3810#(<= main_~i~0 54)} is VALID [2022-04-27 16:00:41,662 INFO L290 TraceCheckUtils]: 114: Hoare triple {3810#(<= main_~i~0 54)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3810#(<= main_~i~0 54)} is VALID [2022-04-27 16:00:41,662 INFO L290 TraceCheckUtils]: 115: Hoare triple {3810#(<= main_~i~0 54)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3811#(<= main_~i~0 55)} is VALID [2022-04-27 16:00:41,662 INFO L290 TraceCheckUtils]: 116: Hoare triple {3811#(<= main_~i~0 55)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3811#(<= main_~i~0 55)} is VALID [2022-04-27 16:00:41,663 INFO L290 TraceCheckUtils]: 117: Hoare triple {3811#(<= main_~i~0 55)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3812#(<= main_~i~0 56)} is VALID [2022-04-27 16:00:41,663 INFO L290 TraceCheckUtils]: 118: Hoare triple {3812#(<= main_~i~0 56)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3812#(<= main_~i~0 56)} is VALID [2022-04-27 16:00:41,664 INFO L290 TraceCheckUtils]: 119: Hoare triple {3812#(<= main_~i~0 56)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3813#(<= main_~i~0 57)} is VALID [2022-04-27 16:00:41,664 INFO L290 TraceCheckUtils]: 120: Hoare triple {3813#(<= main_~i~0 57)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3813#(<= main_~i~0 57)} is VALID [2022-04-27 16:00:41,664 INFO L290 TraceCheckUtils]: 121: Hoare triple {3813#(<= main_~i~0 57)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3814#(<= main_~i~0 58)} is VALID [2022-04-27 16:00:41,665 INFO L290 TraceCheckUtils]: 122: Hoare triple {3814#(<= main_~i~0 58)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3814#(<= main_~i~0 58)} is VALID [2022-04-27 16:00:41,665 INFO L290 TraceCheckUtils]: 123: Hoare triple {3814#(<= main_~i~0 58)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3815#(<= main_~i~0 59)} is VALID [2022-04-27 16:00:41,665 INFO L290 TraceCheckUtils]: 124: Hoare triple {3815#(<= main_~i~0 59)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3815#(<= main_~i~0 59)} is VALID [2022-04-27 16:00:41,666 INFO L290 TraceCheckUtils]: 125: Hoare triple {3815#(<= main_~i~0 59)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3816#(<= main_~i~0 60)} is VALID [2022-04-27 16:00:41,666 INFO L290 TraceCheckUtils]: 126: Hoare triple {3816#(<= main_~i~0 60)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3816#(<= main_~i~0 60)} is VALID [2022-04-27 16:00:41,667 INFO L290 TraceCheckUtils]: 127: Hoare triple {3816#(<= main_~i~0 60)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3817#(<= main_~i~0 61)} is VALID [2022-04-27 16:00:41,667 INFO L290 TraceCheckUtils]: 128: Hoare triple {3817#(<= main_~i~0 61)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3817#(<= main_~i~0 61)} is VALID [2022-04-27 16:00:41,667 INFO L290 TraceCheckUtils]: 129: Hoare triple {3817#(<= main_~i~0 61)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3818#(<= main_~i~0 62)} is VALID [2022-04-27 16:00:41,668 INFO L290 TraceCheckUtils]: 130: Hoare triple {3818#(<= main_~i~0 62)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3818#(<= main_~i~0 62)} is VALID [2022-04-27 16:00:41,668 INFO L290 TraceCheckUtils]: 131: Hoare triple {3818#(<= main_~i~0 62)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3819#(<= main_~i~0 63)} is VALID [2022-04-27 16:00:41,668 INFO L290 TraceCheckUtils]: 132: Hoare triple {3819#(<= main_~i~0 63)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3819#(<= main_~i~0 63)} is VALID [2022-04-27 16:00:41,669 INFO L290 TraceCheckUtils]: 133: Hoare triple {3819#(<= main_~i~0 63)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3820#(<= main_~i~0 64)} is VALID [2022-04-27 16:00:41,669 INFO L290 TraceCheckUtils]: 134: Hoare triple {3820#(<= main_~i~0 64)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3820#(<= main_~i~0 64)} is VALID [2022-04-27 16:00:41,669 INFO L290 TraceCheckUtils]: 135: Hoare triple {3820#(<= main_~i~0 64)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3821#(<= main_~i~0 65)} is VALID [2022-04-27 16:00:41,670 INFO L290 TraceCheckUtils]: 136: Hoare triple {3821#(<= main_~i~0 65)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3821#(<= main_~i~0 65)} is VALID [2022-04-27 16:00:41,670 INFO L290 TraceCheckUtils]: 137: Hoare triple {3821#(<= main_~i~0 65)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3822#(<= main_~i~0 66)} is VALID [2022-04-27 16:00:41,671 INFO L290 TraceCheckUtils]: 138: Hoare triple {3822#(<= main_~i~0 66)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3822#(<= main_~i~0 66)} is VALID [2022-04-27 16:00:41,671 INFO L290 TraceCheckUtils]: 139: Hoare triple {3822#(<= main_~i~0 66)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3823#(<= main_~i~0 67)} is VALID [2022-04-27 16:00:41,671 INFO L290 TraceCheckUtils]: 140: Hoare triple {3823#(<= main_~i~0 67)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3823#(<= main_~i~0 67)} is VALID [2022-04-27 16:00:41,672 INFO L290 TraceCheckUtils]: 141: Hoare triple {3823#(<= main_~i~0 67)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3824#(<= main_~i~0 68)} is VALID [2022-04-27 16:00:41,672 INFO L290 TraceCheckUtils]: 142: Hoare triple {3824#(<= main_~i~0 68)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3824#(<= main_~i~0 68)} is VALID [2022-04-27 16:00:41,672 INFO L290 TraceCheckUtils]: 143: Hoare triple {3824#(<= main_~i~0 68)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3825#(<= main_~i~0 69)} is VALID [2022-04-27 16:00:41,673 INFO L290 TraceCheckUtils]: 144: Hoare triple {3825#(<= main_~i~0 69)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3825#(<= main_~i~0 69)} is VALID [2022-04-27 16:00:41,673 INFO L290 TraceCheckUtils]: 145: Hoare triple {3825#(<= main_~i~0 69)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3826#(<= main_~i~0 70)} is VALID [2022-04-27 16:00:41,673 INFO L290 TraceCheckUtils]: 146: Hoare triple {3826#(<= main_~i~0 70)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3826#(<= main_~i~0 70)} is VALID [2022-04-27 16:00:41,674 INFO L290 TraceCheckUtils]: 147: Hoare triple {3826#(<= main_~i~0 70)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3827#(<= main_~i~0 71)} is VALID [2022-04-27 16:00:41,674 INFO L290 TraceCheckUtils]: 148: Hoare triple {3827#(<= main_~i~0 71)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3827#(<= main_~i~0 71)} is VALID [2022-04-27 16:00:41,675 INFO L290 TraceCheckUtils]: 149: Hoare triple {3827#(<= main_~i~0 71)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3828#(<= main_~i~0 72)} is VALID [2022-04-27 16:00:41,675 INFO L290 TraceCheckUtils]: 150: Hoare triple {3828#(<= main_~i~0 72)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3828#(<= main_~i~0 72)} is VALID [2022-04-27 16:00:41,675 INFO L290 TraceCheckUtils]: 151: Hoare triple {3828#(<= main_~i~0 72)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3829#(<= main_~i~0 73)} is VALID [2022-04-27 16:00:41,676 INFO L290 TraceCheckUtils]: 152: Hoare triple {3829#(<= main_~i~0 73)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3829#(<= main_~i~0 73)} is VALID [2022-04-27 16:00:41,676 INFO L290 TraceCheckUtils]: 153: Hoare triple {3829#(<= main_~i~0 73)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3830#(<= main_~i~0 74)} is VALID [2022-04-27 16:00:41,676 INFO L290 TraceCheckUtils]: 154: Hoare triple {3830#(<= main_~i~0 74)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3830#(<= main_~i~0 74)} is VALID [2022-04-27 16:00:41,677 INFO L290 TraceCheckUtils]: 155: Hoare triple {3830#(<= main_~i~0 74)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3831#(<= main_~i~0 75)} is VALID [2022-04-27 16:00:41,677 INFO L290 TraceCheckUtils]: 156: Hoare triple {3831#(<= main_~i~0 75)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3831#(<= main_~i~0 75)} is VALID [2022-04-27 16:00:41,678 INFO L290 TraceCheckUtils]: 157: Hoare triple {3831#(<= main_~i~0 75)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3832#(<= main_~i~0 76)} is VALID [2022-04-27 16:00:41,678 INFO L290 TraceCheckUtils]: 158: Hoare triple {3832#(<= main_~i~0 76)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3832#(<= main_~i~0 76)} is VALID [2022-04-27 16:00:41,678 INFO L290 TraceCheckUtils]: 159: Hoare triple {3832#(<= main_~i~0 76)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3833#(<= main_~i~0 77)} is VALID [2022-04-27 16:00:41,679 INFO L290 TraceCheckUtils]: 160: Hoare triple {3833#(<= main_~i~0 77)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3833#(<= main_~i~0 77)} is VALID [2022-04-27 16:00:41,679 INFO L290 TraceCheckUtils]: 161: Hoare triple {3833#(<= main_~i~0 77)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3834#(<= main_~i~0 78)} is VALID [2022-04-27 16:00:41,679 INFO L290 TraceCheckUtils]: 162: Hoare triple {3834#(<= main_~i~0 78)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3834#(<= main_~i~0 78)} is VALID [2022-04-27 16:00:41,680 INFO L290 TraceCheckUtils]: 163: Hoare triple {3834#(<= main_~i~0 78)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3835#(<= main_~i~0 79)} is VALID [2022-04-27 16:00:41,680 INFO L290 TraceCheckUtils]: 164: Hoare triple {3835#(<= main_~i~0 79)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3835#(<= main_~i~0 79)} is VALID [2022-04-27 16:00:41,681 INFO L290 TraceCheckUtils]: 165: Hoare triple {3835#(<= main_~i~0 79)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3836#(<= main_~i~0 80)} is VALID [2022-04-27 16:00:41,681 INFO L290 TraceCheckUtils]: 166: Hoare triple {3836#(<= main_~i~0 80)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3836#(<= main_~i~0 80)} is VALID [2022-04-27 16:00:41,681 INFO L290 TraceCheckUtils]: 167: Hoare triple {3836#(<= main_~i~0 80)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3837#(<= main_~i~0 81)} is VALID [2022-04-27 16:00:41,682 INFO L290 TraceCheckUtils]: 168: Hoare triple {3837#(<= main_~i~0 81)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3837#(<= main_~i~0 81)} is VALID [2022-04-27 16:00:41,682 INFO L290 TraceCheckUtils]: 169: Hoare triple {3837#(<= main_~i~0 81)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3838#(<= main_~i~0 82)} is VALID [2022-04-27 16:00:41,683 INFO L290 TraceCheckUtils]: 170: Hoare triple {3838#(<= main_~i~0 82)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3838#(<= main_~i~0 82)} is VALID [2022-04-27 16:00:41,683 INFO L290 TraceCheckUtils]: 171: Hoare triple {3838#(<= main_~i~0 82)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3839#(<= main_~i~0 83)} is VALID [2022-04-27 16:00:41,683 INFO L290 TraceCheckUtils]: 172: Hoare triple {3839#(<= main_~i~0 83)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3839#(<= main_~i~0 83)} is VALID [2022-04-27 16:00:41,684 INFO L290 TraceCheckUtils]: 173: Hoare triple {3839#(<= main_~i~0 83)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3840#(<= main_~i~0 84)} is VALID [2022-04-27 16:00:41,684 INFO L290 TraceCheckUtils]: 174: Hoare triple {3840#(<= main_~i~0 84)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3840#(<= main_~i~0 84)} is VALID [2022-04-27 16:00:41,685 INFO L290 TraceCheckUtils]: 175: Hoare triple {3840#(<= main_~i~0 84)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3841#(<= main_~i~0 85)} is VALID [2022-04-27 16:00:41,685 INFO L290 TraceCheckUtils]: 176: Hoare triple {3841#(<= main_~i~0 85)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3841#(<= main_~i~0 85)} is VALID [2022-04-27 16:00:41,685 INFO L290 TraceCheckUtils]: 177: Hoare triple {3841#(<= main_~i~0 85)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3842#(<= main_~i~0 86)} is VALID [2022-04-27 16:00:41,686 INFO L290 TraceCheckUtils]: 178: Hoare triple {3842#(<= main_~i~0 86)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3842#(<= main_~i~0 86)} is VALID [2022-04-27 16:00:41,686 INFO L290 TraceCheckUtils]: 179: Hoare triple {3842#(<= main_~i~0 86)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3843#(<= main_~i~0 87)} is VALID [2022-04-27 16:00:41,686 INFO L290 TraceCheckUtils]: 180: Hoare triple {3843#(<= main_~i~0 87)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3843#(<= main_~i~0 87)} is VALID [2022-04-27 16:00:41,687 INFO L290 TraceCheckUtils]: 181: Hoare triple {3843#(<= main_~i~0 87)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3844#(<= main_~i~0 88)} is VALID [2022-04-27 16:00:41,687 INFO L290 TraceCheckUtils]: 182: Hoare triple {3844#(<= main_~i~0 88)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3844#(<= main_~i~0 88)} is VALID [2022-04-27 16:00:41,687 INFO L290 TraceCheckUtils]: 183: Hoare triple {3844#(<= main_~i~0 88)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3845#(<= main_~i~0 89)} is VALID [2022-04-27 16:00:41,688 INFO L290 TraceCheckUtils]: 184: Hoare triple {3845#(<= main_~i~0 89)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3845#(<= main_~i~0 89)} is VALID [2022-04-27 16:00:41,688 INFO L290 TraceCheckUtils]: 185: Hoare triple {3845#(<= main_~i~0 89)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3846#(<= main_~i~0 90)} is VALID [2022-04-27 16:00:41,688 INFO L290 TraceCheckUtils]: 186: Hoare triple {3846#(<= main_~i~0 90)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3846#(<= main_~i~0 90)} is VALID [2022-04-27 16:00:41,689 INFO L290 TraceCheckUtils]: 187: Hoare triple {3846#(<= main_~i~0 90)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3847#(<= main_~i~0 91)} is VALID [2022-04-27 16:00:41,689 INFO L290 TraceCheckUtils]: 188: Hoare triple {3847#(<= main_~i~0 91)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3847#(<= main_~i~0 91)} is VALID [2022-04-27 16:00:41,689 INFO L290 TraceCheckUtils]: 189: Hoare triple {3847#(<= main_~i~0 91)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3848#(<= main_~i~0 92)} is VALID [2022-04-27 16:00:41,690 INFO L290 TraceCheckUtils]: 190: Hoare triple {3848#(<= main_~i~0 92)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3848#(<= main_~i~0 92)} is VALID [2022-04-27 16:00:41,690 INFO L290 TraceCheckUtils]: 191: Hoare triple {3848#(<= main_~i~0 92)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3849#(<= main_~i~0 93)} is VALID [2022-04-27 16:00:41,690 INFO L290 TraceCheckUtils]: 192: Hoare triple {3849#(<= main_~i~0 93)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3849#(<= main_~i~0 93)} is VALID [2022-04-27 16:00:41,691 INFO L290 TraceCheckUtils]: 193: Hoare triple {3849#(<= main_~i~0 93)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3850#(<= main_~i~0 94)} is VALID [2022-04-27 16:00:41,691 INFO L290 TraceCheckUtils]: 194: Hoare triple {3850#(<= main_~i~0 94)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {3752#false} is VALID [2022-04-27 16:00:41,691 INFO L290 TraceCheckUtils]: 195: Hoare triple {3752#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {3752#false} is VALID [2022-04-27 16:00:41,691 INFO L272 TraceCheckUtils]: 196: Hoare triple {3752#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {3752#false} is VALID [2022-04-27 16:00:41,691 INFO L290 TraceCheckUtils]: 197: Hoare triple {3752#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3752#false} is VALID [2022-04-27 16:00:41,691 INFO L290 TraceCheckUtils]: 198: Hoare triple {3752#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3752#false} is VALID [2022-04-27 16:00:41,692 INFO L290 TraceCheckUtils]: 199: Hoare triple {3752#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3752#false} is VALID [2022-04-27 16:00:41,694 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:00:41,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:00:41,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [842264560] [2022-04-27 16:00:41,695 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [842264560] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:00:41,695 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1876533991] [2022-04-27 16:00:41,695 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-04-27 16:00:41,695 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:00:41,695 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:00:41,700 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:00:41,700 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process