/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de41.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 16:38:26,783 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 16:38:26,796 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 16:38:26,854 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-27 16:38:26,906 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 16:38:26,907 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 16:38:26,909 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 16:38:26,910 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 16:38:26,921 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 16:38:26,921 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 16:38:26,923 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 16:38:26,923 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 16:38:26,923 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 16:38:26,923 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 16:38:26,923 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 16:38:26,923 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 16:38:26,923 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 16:38:26,924 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 16:38:26,924 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 16:38:26,924 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 16:38:26,925 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 16:38:26,925 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 16:38:26,925 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 16:38:26,925 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 16:38:26,925 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 16:38:26,925 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 16:38:26,925 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:38:26,925 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 16:38:26,926 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 16:38:26,926 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 16:38:26,926 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 16:38:27,162 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 16:38:27,192 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 16:38:27,194 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 16:38:27,195 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 16:38:27,196 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 16:38:27,197 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de41.c [2022-04-27 16:38:27,247 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cd09c1f0a/f3ea78f3b3a24b51b67736358f3135ce/FLAG884fa2edc [2022-04-27 16:38:27,633 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 16:38:27,633 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de41.c [2022-04-27 16:38:27,638 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cd09c1f0a/f3ea78f3b3a24b51b67736358f3135ce/FLAG884fa2edc [2022-04-27 16:38:28,048 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cd09c1f0a/f3ea78f3b3a24b51b67736358f3135ce [2022-04-27 16:38:28,050 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 16:38:28,051 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 16:38:28,053 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 16:38:28,053 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 16:38:28,055 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 16:38:28,056 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,057 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4a92484c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28, skipping insertion in model container [2022-04-27 16:38:28,057 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,063 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 16:38:28,075 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 16:38:28,224 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de41.c[368,381] [2022-04-27 16:38:28,251 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:38:28,266 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 16:38:28,277 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de41.c[368,381] [2022-04-27 16:38:28,289 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:38:28,299 INFO L208 MainTranslator]: Completed translation [2022-04-27 16:38:28,300 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28 WrapperNode [2022-04-27 16:38:28,300 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 16:38:28,301 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 16:38:28,301 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 16:38:28,301 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 16:38:28,310 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,310 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,316 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,316 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,336 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,343 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,348 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,352 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 16:38:28,353 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 16:38:28,354 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 16:38:28,354 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 16:38:28,355 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,368 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:38:28,378 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:38:28,393 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 16:38:28,404 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 16:38:28,429 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 16:38:28,430 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 16:38:28,430 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 16:38:28,430 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 16:38:28,430 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 16:38:28,430 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 16:38:28,431 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 16:38:28,431 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 16:38:28,431 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 16:38:28,431 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 16:38:28,431 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 16:38:28,431 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 16:38:28,432 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 16:38:28,432 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 16:38:28,432 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 16:38:28,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 16:38:28,433 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 16:38:28,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 16:38:28,494 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 16:38:28,497 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 16:38:28,711 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 16:38:28,717 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 16:38:28,717 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-27 16:38:28,719 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:38:28 BoogieIcfgContainer [2022-04-27 16:38:28,719 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 16:38:28,719 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 16:38:28,719 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 16:38:28,720 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 16:38:28,723 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:38:28" (1/1) ... [2022-04-27 16:38:28,725 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 16:38:29,131 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:38:29,132 INFO L91 elerationTransformer]: Accelerated Formula: (and (= (+ v_main_~x~0_3 1) v_main_~x~0_4) (= v_main_~y~0_5 (+ v_main_~y~0_6 1)) (< 0 (mod v_main_~x~0_4 4294967296))) InVars {main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_6} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-27 16:38:29,528 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:38:29,529 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_7 (+ v_main_~z~0_6 1)) (= v_main_~x~0_8 (+ v_main_~x~0_9 1)) (< 0 (mod v_main_~z~0_7 4294967296))) InVars {main_~x~0=v_main_~x~0_9, main_~z~0=v_main_~z~0_7} OutVars{main_~x~0=v_main_~x~0_8, main_~z~0=v_main_~z~0_6, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-27 16:38:30,885 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:38:30,885 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_4 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_4 (+ v_main_~y~0_3 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_3, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-27 16:38:31,223 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:38:31,224 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= (+ v_main_~y~0_8 1) v_main_~y~0_7)) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_8} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_7, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-27 16:38:31,228 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:38:31 BasicIcfg [2022-04-27 16:38:31,228 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 16:38:31,230 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 16:38:31,230 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 16:38:31,233 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 16:38:31,233 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 04:38:28" (1/4) ... [2022-04-27 16:38:31,233 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@696fe88b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:38:31, skipping insertion in model container [2022-04-27 16:38:31,233 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:38:28" (2/4) ... [2022-04-27 16:38:31,234 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@696fe88b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:38:31, skipping insertion in model container [2022-04-27 16:38:31,234 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:38:28" (3/4) ... [2022-04-27 16:38:31,234 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@696fe88b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 04:38:31, skipping insertion in model container [2022-04-27 16:38:31,234 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:38:31" (4/4) ... [2022-04-27 16:38:31,235 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de41.cJordan [2022-04-27 16:38:31,247 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 16:38:31,247 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 16:38:31,278 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 16:38:31,283 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@71f7cd30, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@630d41b3 [2022-04-27 16:38:31,283 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 16:38:31,290 INFO L276 IsEmpty]: Start isEmpty. Operand has 23 states, 15 states have (on average 1.6666666666666667) internal successors, (25), 16 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 16:38:31,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 16:38:31,296 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:38:31,296 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:38:31,296 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:38:31,301 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:38:31,301 INFO L85 PathProgramCache]: Analyzing trace with hash -2015447748, now seen corresponding path program 1 times [2022-04-27 16:38:31,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:38:31,309 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258616693] [2022-04-27 16:38:31,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:31,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:38:31,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:31,408 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:38:31,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:31,425 INFO L290 TraceCheckUtils]: 0: Hoare triple {31#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {26#true} is VALID [2022-04-27 16:38:31,425 INFO L290 TraceCheckUtils]: 1: Hoare triple {26#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-27 16:38:31,426 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {26#true} {26#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-27 16:38:31,427 INFO L272 TraceCheckUtils]: 0: Hoare triple {26#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:38:31,429 INFO L290 TraceCheckUtils]: 1: Hoare triple {31#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {26#true} is VALID [2022-04-27 16:38:31,429 INFO L290 TraceCheckUtils]: 2: Hoare triple {26#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-27 16:38:31,429 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {26#true} {26#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-27 16:38:31,430 INFO L272 TraceCheckUtils]: 4: Hoare triple {26#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#true} is VALID [2022-04-27 16:38:31,430 INFO L290 TraceCheckUtils]: 5: Hoare triple {26#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {26#true} is VALID [2022-04-27 16:38:31,431 INFO L290 TraceCheckUtils]: 6: Hoare triple {26#true} [81] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-27 16:38:31,431 INFO L290 TraceCheckUtils]: 7: Hoare triple {27#false} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {27#false} is VALID [2022-04-27 16:38:31,431 INFO L290 TraceCheckUtils]: 8: Hoare triple {27#false} [85] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-27 16:38:31,431 INFO L290 TraceCheckUtils]: 9: Hoare triple {27#false} [88] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-27 16:38:31,431 INFO L290 TraceCheckUtils]: 10: Hoare triple {27#false} [91] L35-1-->L35-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-27 16:38:31,432 INFO L272 TraceCheckUtils]: 11: Hoare triple {27#false} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {27#false} is VALID [2022-04-27 16:38:31,432 INFO L290 TraceCheckUtils]: 12: Hoare triple {27#false} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {27#false} is VALID [2022-04-27 16:38:31,432 INFO L290 TraceCheckUtils]: 13: Hoare triple {27#false} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-27 16:38:31,432 INFO L290 TraceCheckUtils]: 14: Hoare triple {27#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#false} is VALID [2022-04-27 16:38:31,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:31,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:38:31,433 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258616693] [2022-04-27 16:38:31,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258616693] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:38:31,434 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:38:31,435 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 16:38:31,437 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228842641] [2022-04-27 16:38:31,438 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:38:31,446 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:38:31,448 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:38:31,451 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,468 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:31,469 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 16:38:31,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:38:31,499 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 16:38:31,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:38:31,502 INFO L87 Difference]: Start difference. First operand has 23 states, 15 states have (on average 1.6666666666666667) internal successors, (25), 16 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:31,563 INFO L93 Difference]: Finished difference Result 23 states and 26 transitions. [2022-04-27 16:38:31,564 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 16:38:31,564 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:38:31,564 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:38:31,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 31 transitions. [2022-04-27 16:38:31,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 31 transitions. [2022-04-27 16:38:31,583 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 31 transitions. [2022-04-27 16:38:31,636 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:31,662 INFO L225 Difference]: With dead ends: 23 [2022-04-27 16:38:31,662 INFO L226 Difference]: Without dead ends: 16 [2022-04-27 16:38:31,664 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:38:31,667 INFO L413 NwaCegarLoop]: 25 mSDtfsCounter, 17 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 28 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:38:31,671 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [18 Valid, 28 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:38:31,685 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2022-04-27 16:38:31,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2022-04-27 16:38:31,694 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:38:31,696 INFO L82 GeneralOperation]: Start isEquivalent. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,696 INFO L74 IsIncluded]: Start isIncluded. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,696 INFO L87 Difference]: Start difference. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:31,703 INFO L93 Difference]: Finished difference Result 16 states and 19 transitions. [2022-04-27 16:38:31,703 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 19 transitions. [2022-04-27 16:38:31,703 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:31,703 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:31,704 INFO L74 IsIncluded]: Start isIncluded. First operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 16:38:31,705 INFO L87 Difference]: Start difference. First operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 16:38:31,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:31,707 INFO L93 Difference]: Finished difference Result 16 states and 19 transitions. [2022-04-27 16:38:31,707 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 19 transitions. [2022-04-27 16:38:31,708 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:31,708 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:31,709 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:38:31,709 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:38:31,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 11 states have internal predecessors, (15), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 19 transitions. [2022-04-27 16:38:31,720 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 19 transitions. Word has length 15 [2022-04-27 16:38:31,721 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:38:31,721 INFO L495 AbstractCegarLoop]: Abstraction has 16 states and 19 transitions. [2022-04-27 16:38:31,721 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:31,721 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 19 transitions. [2022-04-27 16:38:31,721 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 16:38:31,722 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:38:31,722 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:38:31,722 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 16:38:31,722 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:38:31,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:38:31,723 INFO L85 PathProgramCache]: Analyzing trace with hash 1389121438, now seen corresponding path program 1 times [2022-04-27 16:38:31,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:38:31,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [966175311] [2022-04-27 16:38:31,724 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:31,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:38:31,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:32,042 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:38:32,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:32,068 INFO L290 TraceCheckUtils]: 0: Hoare triple {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {105#true} is VALID [2022-04-27 16:38:32,069 INFO L290 TraceCheckUtils]: 1: Hoare triple {105#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-27 16:38:32,069 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {105#true} {105#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-27 16:38:32,070 INFO L272 TraceCheckUtils]: 0: Hoare triple {105#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:38:32,070 INFO L290 TraceCheckUtils]: 1: Hoare triple {115#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {105#true} is VALID [2022-04-27 16:38:32,070 INFO L290 TraceCheckUtils]: 2: Hoare triple {105#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-27 16:38:32,070 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {105#true} {105#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-27 16:38:32,071 INFO L272 TraceCheckUtils]: 4: Hoare triple {105#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {105#true} is VALID [2022-04-27 16:38:32,072 INFO L290 TraceCheckUtils]: 5: Hoare triple {105#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {110#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,073 INFO L290 TraceCheckUtils]: 6: Hoare triple {110#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,074 INFO L290 TraceCheckUtils]: 7: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,075 INFO L290 TraceCheckUtils]: 8: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,075 INFO L290 TraceCheckUtils]: 9: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,076 INFO L290 TraceCheckUtils]: 10: Hoare triple {111#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {112#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,078 INFO L272 TraceCheckUtils]: 11: Hoare triple {112#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {113#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:38:32,078 INFO L290 TraceCheckUtils]: 12: Hoare triple {113#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {114#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:38:32,079 INFO L290 TraceCheckUtils]: 13: Hoare triple {114#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {106#false} is VALID [2022-04-27 16:38:32,079 INFO L290 TraceCheckUtils]: 14: Hoare triple {106#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {106#false} is VALID [2022-04-27 16:38:32,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:32,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:38:32,080 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [966175311] [2022-04-27 16:38:32,080 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [966175311] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:38:32,080 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:38:32,080 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-27 16:38:32,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [35882025] [2022-04-27 16:38:32,082 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:38:32,083 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:38:32,084 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:38:32,084 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,099 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:32,100 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:38:32,100 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:38:32,101 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:38:32,101 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-27 16:38:32,102 INFO L87 Difference]: Start difference. First operand 16 states and 19 transitions. Second operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:32,332 INFO L93 Difference]: Finished difference Result 27 states and 36 transitions. [2022-04-27 16:38:32,332 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 16:38:32,332 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:38:32,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:38:32,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 37 transitions. [2022-04-27 16:38:32,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 37 transitions. [2022-04-27 16:38:32,336 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 37 transitions. [2022-04-27 16:38:32,384 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:32,385 INFO L225 Difference]: With dead ends: 27 [2022-04-27 16:38:32,385 INFO L226 Difference]: Without dead ends: 24 [2022-04-27 16:38:32,385 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2022-04-27 16:38:32,386 INFO L413 NwaCegarLoop]: 10 mSDtfsCounter, 20 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 42 SdHoareTripleChecker+Invalid, 71 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 4 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:38:32,387 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 42 Invalid, 71 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 59 Invalid, 0 Unknown, 4 Unchecked, 0.1s Time] [2022-04-27 16:38:32,387 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2022-04-27 16:38:32,389 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 21. [2022-04-27 16:38:32,389 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:38:32,389 INFO L82 GeneralOperation]: Start isEquivalent. First operand 24 states. Second operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,390 INFO L74 IsIncluded]: Start isIncluded. First operand 24 states. Second operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,390 INFO L87 Difference]: Start difference. First operand 24 states. Second operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:32,392 INFO L93 Difference]: Finished difference Result 24 states and 33 transitions. [2022-04-27 16:38:32,392 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 33 transitions. [2022-04-27 16:38:32,392 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:32,392 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:32,393 INFO L74 IsIncluded]: Start isIncluded. First operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 24 states. [2022-04-27 16:38:32,393 INFO L87 Difference]: Start difference. First operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 24 states. [2022-04-27 16:38:32,394 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:32,394 INFO L93 Difference]: Finished difference Result 24 states and 33 transitions. [2022-04-27 16:38:32,394 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 33 transitions. [2022-04-27 16:38:32,395 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:32,395 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:32,395 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:38:32,395 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:38:32,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 16 states have (on average 1.4375) internal successors, (23), 16 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 27 transitions. [2022-04-27 16:38:32,396 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 27 transitions. Word has length 15 [2022-04-27 16:38:32,396 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:38:32,397 INFO L495 AbstractCegarLoop]: Abstraction has 21 states and 27 transitions. [2022-04-27 16:38:32,397 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 1.5714285714285714) internal successors, (11), 6 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:32,397 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 27 transitions. [2022-04-27 16:38:32,397 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:38:32,397 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:38:32,398 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:38:32,398 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 16:38:32,398 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:38:32,398 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:38:32,398 INFO L85 PathProgramCache]: Analyzing trace with hash 139812261, now seen corresponding path program 1 times [2022-04-27 16:38:32,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:38:32,399 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209188952] [2022-04-27 16:38:32,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:32,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:38:32,417 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:38:32,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:32,461 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:38:32,559 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:38:32,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:32,571 INFO L290 TraceCheckUtils]: 0: Hoare triple {232#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 16:38:32,571 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:32,571 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {222#true} {222#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:32,572 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {232#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:38:32,572 INFO L290 TraceCheckUtils]: 1: Hoare triple {232#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 16:38:32,572 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:32,573 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:32,573 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:32,573 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {227#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,574 INFO L290 TraceCheckUtils]: 6: Hoare triple {227#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,575 INFO L290 TraceCheckUtils]: 7: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,576 INFO L290 TraceCheckUtils]: 8: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,576 INFO L290 TraceCheckUtils]: 9: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:32,578 INFO L290 TraceCheckUtils]: 10: Hoare triple {228#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:32,579 INFO L290 TraceCheckUtils]: 11: Hoare triple {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:32,580 INFO L272 TraceCheckUtils]: 12: Hoare triple {229#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {230#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:38:32,581 INFO L290 TraceCheckUtils]: 13: Hoare triple {230#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {231#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:38:32,581 INFO L290 TraceCheckUtils]: 14: Hoare triple {231#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 16:38:32,581 INFO L290 TraceCheckUtils]: 15: Hoare triple {223#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 16:38:32,582 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:32,582 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:38:32,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1209188952] [2022-04-27 16:38:32,582 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1209188952] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:38:32,582 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1606020086] [2022-04-27 16:38:32,583 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:32,583 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:38:32,583 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:38:32,587 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:38:32,621 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 16:38:32,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:32,640 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-27 16:38:32,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:32,663 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:38:33,347 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:33,348 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 16:38:33,348 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:33,348 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:33,348 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 16:38:33,350 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {251#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:38:33,351 INFO L290 TraceCheckUtils]: 6: Hoare triple {251#(= main_~n~0 main_~x~0)} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:38:33,352 INFO L290 TraceCheckUtils]: 7: Hoare triple {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:38:33,352 INFO L290 TraceCheckUtils]: 8: Hoare triple {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:38:33,353 INFO L290 TraceCheckUtils]: 9: Hoare triple {255#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:38:33,354 INFO L290 TraceCheckUtils]: 10: Hoare triple {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:38:33,355 INFO L290 TraceCheckUtils]: 11: Hoare triple {265#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {272#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:38:33,356 INFO L272 TraceCheckUtils]: 12: Hoare triple {272#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {276#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:38:33,357 INFO L290 TraceCheckUtils]: 13: Hoare triple {276#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {280#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:38:33,357 INFO L290 TraceCheckUtils]: 14: Hoare triple {280#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 16:38:33,357 INFO L290 TraceCheckUtils]: 15: Hoare triple {223#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 16:38:33,358 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:38:33,358 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 16:38:33,358 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1606020086] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:38:33,358 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 16:38:33,358 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [8] total 14 [2022-04-27 16:38:33,359 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114758287] [2022-04-27 16:38:33,359 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:38:33,359 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:38:33,360 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:38:33,360 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,375 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:33,376 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:38:33,376 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:38:33,377 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:38:33,377 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=142, Unknown=0, NotChecked=0, Total=182 [2022-04-27 16:38:33,377 INFO L87 Difference]: Start difference. First operand 21 states and 27 transitions. Second operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:33,491 INFO L93 Difference]: Finished difference Result 26 states and 33 transitions. [2022-04-27 16:38:33,491 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 16:38:33,492 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:38:33,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:38:33,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 31 transitions. [2022-04-27 16:38:33,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 31 transitions. [2022-04-27 16:38:33,495 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 31 transitions. [2022-04-27 16:38:33,521 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:33,522 INFO L225 Difference]: With dead ends: 26 [2022-04-27 16:38:33,522 INFO L226 Difference]: Without dead ends: 19 [2022-04-27 16:38:33,523 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 12 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=164, Unknown=0, NotChecked=0, Total=210 [2022-04-27 16:38:33,523 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 9 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 30 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 64 SdHoareTripleChecker+Invalid, 38 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 30 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 7 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:38:33,524 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [9 Valid, 64 Invalid, 38 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 30 Invalid, 0 Unknown, 7 Unchecked, 0.0s Time] [2022-04-27 16:38:33,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2022-04-27 16:38:33,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2022-04-27 16:38:33,526 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:38:33,526 INFO L82 GeneralOperation]: Start isEquivalent. First operand 19 states. Second operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,526 INFO L74 IsIncluded]: Start isIncluded. First operand 19 states. Second operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,526 INFO L87 Difference]: Start difference. First operand 19 states. Second operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:33,528 INFO L93 Difference]: Finished difference Result 19 states and 23 transitions. [2022-04-27 16:38:33,528 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 23 transitions. [2022-04-27 16:38:33,528 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:33,528 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:33,528 INFO L74 IsIncluded]: Start isIncluded. First operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 19 states. [2022-04-27 16:38:33,528 INFO L87 Difference]: Start difference. First operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 19 states. [2022-04-27 16:38:33,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:33,530 INFO L93 Difference]: Finished difference Result 19 states and 23 transitions. [2022-04-27 16:38:33,530 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 23 transitions. [2022-04-27 16:38:33,530 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:33,530 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:33,530 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:38:33,530 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:38:33,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 14 states have (on average 1.3571428571428572) internal successors, (19), 14 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 23 transitions. [2022-04-27 16:38:33,532 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 23 transitions. Word has length 16 [2022-04-27 16:38:33,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:38:33,532 INFO L495 AbstractCegarLoop]: Abstraction has 19 states and 23 transitions. [2022-04-27 16:38:33,532 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 7 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:33,533 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 23 transitions. [2022-04-27 16:38:33,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:38:33,533 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:38:33,533 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:38:33,559 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-04-27 16:38:33,734 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:38:33,734 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:38:33,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:38:33,735 INFO L85 PathProgramCache]: Analyzing trace with hash -894405051, now seen corresponding path program 1 times [2022-04-27 16:38:33,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:38:33,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135135072] [2022-04-27 16:38:33,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:33,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:38:33,746 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:38:33,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:33,776 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:38:33,911 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:38:33,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:33,918 INFO L290 TraceCheckUtils]: 0: Hoare triple {381#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {371#true} is VALID [2022-04-27 16:38:33,919 INFO L290 TraceCheckUtils]: 1: Hoare triple {371#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:33,919 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {371#true} {371#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:33,920 INFO L272 TraceCheckUtils]: 0: Hoare triple {371#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {381#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:38:33,920 INFO L290 TraceCheckUtils]: 1: Hoare triple {381#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {371#true} is VALID [2022-04-27 16:38:33,920 INFO L290 TraceCheckUtils]: 2: Hoare triple {371#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:33,920 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {371#true} {371#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:33,920 INFO L272 TraceCheckUtils]: 4: Hoare triple {371#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:33,921 INFO L290 TraceCheckUtils]: 5: Hoare triple {371#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {376#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,922 INFO L290 TraceCheckUtils]: 6: Hoare triple {376#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,922 INFO L290 TraceCheckUtils]: 7: Hoare triple {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,924 INFO L290 TraceCheckUtils]: 8: Hoare triple {377#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,925 INFO L290 TraceCheckUtils]: 9: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,925 INFO L290 TraceCheckUtils]: 10: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,926 INFO L290 TraceCheckUtils]: 11: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:33,927 INFO L272 TraceCheckUtils]: 12: Hoare triple {378#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {379#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:38:33,930 INFO L290 TraceCheckUtils]: 13: Hoare triple {379#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:38:33,931 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-27 16:38:33,931 INFO L290 TraceCheckUtils]: 15: Hoare triple {372#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-27 16:38:33,931 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:33,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:38:33,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135135072] [2022-04-27 16:38:33,932 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135135072] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:38:33,932 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [762619671] [2022-04-27 16:38:33,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:33,932 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:38:33,932 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:38:33,933 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:38:33,957 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 16:38:33,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:33,974 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 16:38:33,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:33,982 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:38:34,611 INFO L272 TraceCheckUtils]: 0: Hoare triple {371#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:34,612 INFO L290 TraceCheckUtils]: 1: Hoare triple {371#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {371#true} is VALID [2022-04-27 16:38:34,612 INFO L290 TraceCheckUtils]: 2: Hoare triple {371#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:34,612 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {371#true} {371#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:34,612 INFO L272 TraceCheckUtils]: 4: Hoare triple {371#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {371#true} is VALID [2022-04-27 16:38:34,613 INFO L290 TraceCheckUtils]: 5: Hoare triple {371#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {400#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:38:34,614 INFO L290 TraceCheckUtils]: 6: Hoare triple {400#(= main_~n~0 main_~x~0)} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:38:34,614 INFO L290 TraceCheckUtils]: 7: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:38:34,615 INFO L290 TraceCheckUtils]: 8: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:38:34,616 INFO L290 TraceCheckUtils]: 9: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {404#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:38:34,616 INFO L290 TraceCheckUtils]: 10: Hoare triple {404#(not (< 0 (mod main_~n~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:38:34,617 INFO L290 TraceCheckUtils]: 11: Hoare triple {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:38:34,618 INFO L272 TraceCheckUtils]: 12: Hoare triple {417#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {424#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:38:34,619 INFO L290 TraceCheckUtils]: 13: Hoare triple {424#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {428#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:38:34,621 INFO L290 TraceCheckUtils]: 14: Hoare triple {428#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-27 16:38:34,621 INFO L290 TraceCheckUtils]: 15: Hoare triple {372#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {372#false} is VALID [2022-04-27 16:38:34,622 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:38:34,622 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 16:38:34,622 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [762619671] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:38:34,622 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 16:38:34,622 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 13 [2022-04-27 16:38:34,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1996833308] [2022-04-27 16:38:34,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:38:34,623 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:38:34,623 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:38:34,624 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,642 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:34,642 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-04-27 16:38:34,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:38:34,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-04-27 16:38:34,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=122, Unknown=0, NotChecked=0, Total=156 [2022-04-27 16:38:34,643 INFO L87 Difference]: Start difference. First operand 19 states and 23 transitions. Second operand has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:34,750 INFO L93 Difference]: Finished difference Result 25 states and 31 transitions. [2022-04-27 16:38:34,751 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-27 16:38:34,751 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:38:34,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:38:34,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 32 transitions. [2022-04-27 16:38:34,752 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 32 transitions. [2022-04-27 16:38:34,753 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 32 transitions. [2022-04-27 16:38:34,786 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:34,787 INFO L225 Difference]: With dead ends: 25 [2022-04-27 16:38:34,787 INFO L226 Difference]: Without dead ends: 22 [2022-04-27 16:38:34,788 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2022-04-27 16:38:34,788 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 6 mSDsluCounter, 58 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 72 SdHoareTripleChecker+Invalid, 27 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 5 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:38:34,789 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 72 Invalid, 27 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 22 Invalid, 0 Unknown, 5 Unchecked, 0.0s Time] [2022-04-27 16:38:34,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2022-04-27 16:38:34,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2022-04-27 16:38:34,790 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:38:34,791 INFO L82 GeneralOperation]: Start isEquivalent. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,791 INFO L74 IsIncluded]: Start isIncluded. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,791 INFO L87 Difference]: Start difference. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:34,792 INFO L93 Difference]: Finished difference Result 22 states and 28 transitions. [2022-04-27 16:38:34,792 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 28 transitions. [2022-04-27 16:38:34,793 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:34,793 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:34,793 INFO L74 IsIncluded]: Start isIncluded. First operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-27 16:38:34,793 INFO L87 Difference]: Start difference. First operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-27 16:38:34,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:34,794 INFO L93 Difference]: Finished difference Result 22 states and 28 transitions. [2022-04-27 16:38:34,794 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 28 transitions. [2022-04-27 16:38:34,794 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:34,795 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:34,795 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:38:34,795 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:38:34,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 17 states have (on average 1.411764705882353) internal successors, (24), 17 states have internal predecessors, (24), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,802 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 28 transitions. [2022-04-27 16:38:34,802 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 28 transitions. Word has length 16 [2022-04-27 16:38:34,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:38:34,802 INFO L495 AbstractCegarLoop]: Abstraction has 22 states and 28 transitions. [2022-04-27 16:38:34,803 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 1.7142857142857142) internal successors, (12), 6 states have internal predecessors, (12), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:34,803 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 28 transitions. [2022-04-27 16:38:34,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:38:34,803 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:38:34,803 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:38:34,833 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 16:38:35,030 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 16:38:35,031 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:38:35,031 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:38:35,031 INFO L85 PathProgramCache]: Analyzing trace with hash 1590526661, now seen corresponding path program 1 times [2022-04-27 16:38:35,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:38:35,031 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079453804] [2022-04-27 16:38:35,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:35,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:38:35,043 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:38:35,052 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:35,060 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.1))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:38:35,204 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:38:35,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:35,210 INFO L290 TraceCheckUtils]: 0: Hoare triple {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-27 16:38:35,210 INFO L290 TraceCheckUtils]: 1: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:35,210 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:35,211 INFO L272 TraceCheckUtils]: 0: Hoare triple {529#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:38:35,211 INFO L290 TraceCheckUtils]: 1: Hoare triple {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-27 16:38:35,211 INFO L290 TraceCheckUtils]: 2: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:35,211 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:35,211 INFO L272 TraceCheckUtils]: 4: Hoare triple {529#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:35,212 INFO L290 TraceCheckUtils]: 5: Hoare triple {529#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:35,226 INFO L290 TraceCheckUtils]: 6: Hoare triple {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:38:35,227 INFO L290 TraceCheckUtils]: 7: Hoare triple {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:38:35,228 INFO L290 TraceCheckUtils]: 8: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:38:35,230 INFO L290 TraceCheckUtils]: 9: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:38:35,231 INFO L290 TraceCheckUtils]: 10: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:35,232 INFO L290 TraceCheckUtils]: 11: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:35,234 INFO L272 TraceCheckUtils]: 12: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {538#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:38:35,235 INFO L290 TraceCheckUtils]: 13: Hoare triple {538#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {539#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:38:35,244 INFO L290 TraceCheckUtils]: 14: Hoare triple {539#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-27 16:38:35,244 INFO L290 TraceCheckUtils]: 15: Hoare triple {530#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-27 16:38:35,244 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:35,244 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:38:35,244 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079453804] [2022-04-27 16:38:35,245 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079453804] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:38:35,245 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [679799953] [2022-04-27 16:38:35,245 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:35,245 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:38:35,245 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:38:35,248 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:38:35,249 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 16:38:35,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:35,307 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-27 16:38:35,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:35,332 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:38:37,153 INFO L272 TraceCheckUtils]: 0: Hoare triple {529#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:37,153 INFO L290 TraceCheckUtils]: 1: Hoare triple {529#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-27 16:38:37,154 INFO L290 TraceCheckUtils]: 2: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:37,154 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:37,154 INFO L272 TraceCheckUtils]: 4: Hoare triple {529#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:37,160 INFO L290 TraceCheckUtils]: 5: Hoare triple {529#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:37,176 INFO L290 TraceCheckUtils]: 6: Hoare triple {534#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {562#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} is VALID [2022-04-27 16:38:37,178 INFO L290 TraceCheckUtils]: 7: Hoare triple {562#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {566#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:38:37,181 INFO L290 TraceCheckUtils]: 8: Hoare triple {566#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {570#(and (= main_~z~0 main_~y~0) (or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0))))} is VALID [2022-04-27 16:38:37,196 INFO L290 TraceCheckUtils]: 9: Hoare triple {570#(and (= main_~z~0 main_~y~0) (or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (<= (div (+ main_~y~0 (* (- 1) main_~n~0)) (- 4294967296)) (div (+ main_~n~0 (* (- 1) main_~y~0)) 4294967296)) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:38:37,197 INFO L290 TraceCheckUtils]: 10: Hoare triple {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:38:37,197 INFO L290 TraceCheckUtils]: 11: Hoare triple {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:38:37,198 INFO L272 TraceCheckUtils]: 12: Hoare triple {574#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {584#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:38:37,199 INFO L290 TraceCheckUtils]: 13: Hoare triple {584#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {588#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:38:37,199 INFO L290 TraceCheckUtils]: 14: Hoare triple {588#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-27 16:38:37,199 INFO L290 TraceCheckUtils]: 15: Hoare triple {530#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-27 16:38:37,200 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:37,200 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:38:46,628 INFO L290 TraceCheckUtils]: 15: Hoare triple {530#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-27 16:38:46,629 INFO L290 TraceCheckUtils]: 14: Hoare triple {588#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {530#false} is VALID [2022-04-27 16:38:46,630 INFO L290 TraceCheckUtils]: 13: Hoare triple {584#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {588#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:38:46,631 INFO L272 TraceCheckUtils]: 12: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {584#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:38:46,632 INFO L290 TraceCheckUtils]: 11: Hoare triple {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:46,632 INFO L290 TraceCheckUtils]: 10: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {537#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:46,633 INFO L290 TraceCheckUtils]: 9: Hoare triple {613#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:38:46,633 INFO L290 TraceCheckUtils]: 8: Hoare triple {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {613#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:38:46,634 INFO L290 TraceCheckUtils]: 7: Hoare triple {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {536#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:38:48,637 WARN L290 TraceCheckUtils]: 6: Hoare triple {623#(or (forall ((aux_mod_v_main_~x~0_21_31 Int)) (or (> 0 aux_mod_v_main_~x~0_21_31) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~x~0_21_31 Int) (aux_div_v_main_~y~0_23_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296))) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_21_31 v_it_1 (* aux_div_v_main_~x~0_21_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))) (not (< (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_21_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296))))) (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_23_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_23_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) 1) (+ aux_mod_v_main_~x~0_21_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_21_31 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {535#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is UNKNOWN [2022-04-27 16:38:48,641 INFO L290 TraceCheckUtils]: 5: Hoare triple {529#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {623#(or (forall ((aux_mod_v_main_~x~0_21_31 Int)) (or (> 0 aux_mod_v_main_~x~0_21_31) (and (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~x~0_21_31 Int) (aux_div_v_main_~y~0_23_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~y~0_23_31 4294967296) (* aux_div_v_main_~x~0_21_31 4294967296))) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_21_31 v_it_1 (* aux_div_v_main_~x~0_21_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))) (not (< (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_21_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_21_31 (* aux_div_v_main_~x~0_21_31 4294967296))))) (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_23_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_23_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_23_31 4294967296) 1) (+ aux_mod_v_main_~x~0_21_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_21_31 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:38:48,641 INFO L272 TraceCheckUtils]: 4: Hoare triple {529#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:48,641 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {529#true} {529#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:48,641 INFO L290 TraceCheckUtils]: 2: Hoare triple {529#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:48,641 INFO L290 TraceCheckUtils]: 1: Hoare triple {529#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {529#true} is VALID [2022-04-27 16:38:48,641 INFO L272 TraceCheckUtils]: 0: Hoare triple {529#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {529#true} is VALID [2022-04-27 16:38:48,642 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:48,642 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [679799953] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:38:48,642 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:38:48,642 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 17 [2022-04-27 16:38:48,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1086255869] [2022-04-27 16:38:48,642 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:38:48,643 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:38:48,643 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:38:48,643 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:50,509 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:50,509 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-27 16:38:50,509 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:38:50,510 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-27 16:38:50,510 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=210, Unknown=3, NotChecked=0, Total=272 [2022-04-27 16:38:50,510 INFO L87 Difference]: Start difference. First operand 22 states and 28 transitions. Second operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:50,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:50,892 INFO L93 Difference]: Finished difference Result 30 states and 39 transitions. [2022-04-27 16:38:50,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 16:38:50,892 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:38:50,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:38:50,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:50,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 35 transitions. [2022-04-27 16:38:50,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:50,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 35 transitions. [2022-04-27 16:38:50,895 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 35 transitions. [2022-04-27 16:38:51,009 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:38:51,010 INFO L225 Difference]: With dead ends: 30 [2022-04-27 16:38:51,010 INFO L226 Difference]: Without dead ends: 27 [2022-04-27 16:38:51,011 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 21 SyntacticMatches, 6 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 7.4s TimeCoverageRelationStatistics Valid=118, Invalid=385, Unknown=3, NotChecked=0, Total=506 [2022-04-27 16:38:51,011 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 28 mSDsluCounter, 48 mSDsCounter, 0 mSdLazyCounter, 64 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 62 SdHoareTripleChecker+Invalid, 126 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 64 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 55 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:38:51,012 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 62 Invalid, 126 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 64 Invalid, 0 Unknown, 55 Unchecked, 0.1s Time] [2022-04-27 16:38:51,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2022-04-27 16:38:51,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 26. [2022-04-27 16:38:51,016 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:38:51,016 INFO L82 GeneralOperation]: Start isEquivalent. First operand 27 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:51,016 INFO L74 IsIncluded]: Start isIncluded. First operand 27 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:51,016 INFO L87 Difference]: Start difference. First operand 27 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:51,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:51,017 INFO L93 Difference]: Finished difference Result 27 states and 36 transitions. [2022-04-27 16:38:51,018 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 36 transitions. [2022-04-27 16:38:51,018 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:51,018 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:51,018 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 27 states. [2022-04-27 16:38:51,018 INFO L87 Difference]: Start difference. First operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 27 states. [2022-04-27 16:38:51,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:38:51,019 INFO L93 Difference]: Finished difference Result 27 states and 36 transitions. [2022-04-27 16:38:51,020 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 36 transitions. [2022-04-27 16:38:51,020 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:38:51,020 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:38:51,020 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:38:51,020 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:38:51,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:51,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 35 transitions. [2022-04-27 16:38:51,021 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 35 transitions. Word has length 16 [2022-04-27 16:38:51,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:38:51,021 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 35 transitions. [2022-04-27 16:38:51,022 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 14 states have internal predecessors, (25), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:38:51,022 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 35 transitions. [2022-04-27 16:38:51,022 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:38:51,022 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:38:51,022 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:38:51,048 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 16:38:51,241 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:38:51,241 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:38:51,242 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:38:51,242 INFO L85 PathProgramCache]: Analyzing trace with hash -1930032162, now seen corresponding path program 1 times [2022-04-27 16:38:51,242 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:38:51,242 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542689978] [2022-04-27 16:38:51,242 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:51,242 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:38:51,255 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:38:51,257 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-27 16:38:51,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:51,289 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:38:51,298 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.4))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-27 16:38:51,495 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:38:51,497 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:51,504 INFO L290 TraceCheckUtils]: 0: Hoare triple {780#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {767#true} is VALID [2022-04-27 16:38:51,504 INFO L290 TraceCheckUtils]: 1: Hoare triple {767#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:51,505 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {767#true} {767#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:51,506 INFO L272 TraceCheckUtils]: 0: Hoare triple {767#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {780#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:38:51,506 INFO L290 TraceCheckUtils]: 1: Hoare triple {780#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {767#true} is VALID [2022-04-27 16:38:51,506 INFO L290 TraceCheckUtils]: 2: Hoare triple {767#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:51,506 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {767#true} {767#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:51,506 INFO L272 TraceCheckUtils]: 4: Hoare triple {767#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:51,507 INFO L290 TraceCheckUtils]: 5: Hoare triple {767#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {772#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:38:51,508 INFO L290 TraceCheckUtils]: 6: Hoare triple {772#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:51,509 INFO L290 TraceCheckUtils]: 7: Hoare triple {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {774#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:51,510 INFO L290 TraceCheckUtils]: 8: Hoare triple {774#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {775#(and (= main_~z~0 0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:51,511 INFO L290 TraceCheckUtils]: 9: Hoare triple {775#(and (= main_~z~0 0) (<= (+ main_~z~0 main_~x~0) (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {776#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:51,511 INFO L290 TraceCheckUtils]: 10: Hoare triple {776#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {776#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:51,514 INFO L290 TraceCheckUtils]: 11: Hoare triple {776#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {777#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:51,515 INFO L290 TraceCheckUtils]: 12: Hoare triple {777#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {777#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:38:51,516 INFO L272 TraceCheckUtils]: 13: Hoare triple {777#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {778#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:38:51,517 INFO L290 TraceCheckUtils]: 14: Hoare triple {778#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {779#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:38:51,517 INFO L290 TraceCheckUtils]: 15: Hoare triple {779#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {768#false} is VALID [2022-04-27 16:38:51,517 INFO L290 TraceCheckUtils]: 16: Hoare triple {768#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#false} is VALID [2022-04-27 16:38:51,518 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:51,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:38:51,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542689978] [2022-04-27 16:38:51,518 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542689978] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:38:51,518 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [27440468] [2022-04-27 16:38:51,518 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:38:51,518 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:38:51,518 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:38:51,520 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:38:51,542 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 16:38:51,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:51,560 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-27 16:38:51,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:38:51,577 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:38:52,014 INFO L272 TraceCheckUtils]: 0: Hoare triple {767#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:52,015 INFO L290 TraceCheckUtils]: 1: Hoare triple {767#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {767#true} is VALID [2022-04-27 16:38:52,015 INFO L290 TraceCheckUtils]: 2: Hoare triple {767#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:52,015 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {767#true} {767#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:52,015 INFO L272 TraceCheckUtils]: 4: Hoare triple {767#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:38:52,016 INFO L290 TraceCheckUtils]: 5: Hoare triple {767#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {772#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,017 INFO L290 TraceCheckUtils]: 6: Hoare triple {772#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,017 INFO L290 TraceCheckUtils]: 7: Hoare triple {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {774#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,018 INFO L290 TraceCheckUtils]: 8: Hoare triple {774#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,019 INFO L290 TraceCheckUtils]: 9: Hoare triple {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,020 INFO L290 TraceCheckUtils]: 10: Hoare triple {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,021 INFO L290 TraceCheckUtils]: 11: Hoare triple {773#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {817#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,022 INFO L290 TraceCheckUtils]: 12: Hoare triple {817#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {817#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:38:52,023 INFO L272 TraceCheckUtils]: 13: Hoare triple {817#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {824#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:38:52,024 INFO L290 TraceCheckUtils]: 14: Hoare triple {824#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {828#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:38:52,024 INFO L290 TraceCheckUtils]: 15: Hoare triple {828#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {768#false} is VALID [2022-04-27 16:38:52,024 INFO L290 TraceCheckUtils]: 16: Hoare triple {768#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#false} is VALID [2022-04-27 16:38:52,024 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:38:52,024 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:39:11,854 WARN L855 $PredicateComparison]: unable to prove that (or (< 0 (mod c_main_~y~0 4294967296)) (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296) (= (mod c_main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (let ((.cse0 (< 0 (mod c_main_~z~0 4294967296))) (.cse1 (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31) c_main_~y~0))))) (and (or (not .cse0) (and (or (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int)) (or (< 0 aux_mod_v_main_~x~0_26_31) (exists ((v_it_2 Int)) (and (<= 1 v_it_2) (not (< 0 (mod (+ (* v_it_2 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_2 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))))) (< aux_mod_v_main_~x~0_26_31 0) (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) c_main_~x~0))) .cse1) (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 c_main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_v_main_~x~0_26_31) 4294967296))))) (<= aux_mod_v_main_~x~0_26_31 0) (exists ((v_it_2 Int)) (and (<= 1 v_it_2) (not (< 0 (mod (+ (* v_it_2 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_2 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31) c_main_~y~0) (<= 4294967296 aux_mod_v_main_~x~0_26_31) (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) c_main_~x~0))))) (or .cse0 (let ((.cse2 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= (+ v_it_4 c_main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (<= 1 v_it_4))) (not (< c_main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (not .cse2)) (or .cse2 .cse1))))))))) is different from true [2022-04-27 16:39:17,260 INFO L290 TraceCheckUtils]: 16: Hoare triple {768#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#false} is VALID [2022-04-27 16:39:17,261 INFO L290 TraceCheckUtils]: 15: Hoare triple {828#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {768#false} is VALID [2022-04-27 16:39:17,262 INFO L290 TraceCheckUtils]: 14: Hoare triple {824#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {828#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:39:17,262 INFO L272 TraceCheckUtils]: 13: Hoare triple {844#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {824#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:39:17,263 INFO L290 TraceCheckUtils]: 12: Hoare triple {844#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {844#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-27 16:39:17,313 INFO L290 TraceCheckUtils]: 11: Hoare triple {851#(forall ((aux_mod_v_main_~y~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))) (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296)))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {844#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-27 16:39:19,347 WARN L290 TraceCheckUtils]: 10: Hoare triple {855#(or (forall ((aux_mod_v_main_~y~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))) (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {851#(forall ((aux_mod_v_main_~y~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))) (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296)))} is UNKNOWN [2022-04-27 16:39:21,357 WARN L290 TraceCheckUtils]: 9: Hoare triple {855#(or (forall ((aux_mod_v_main_~y~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))) (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {855#(or (forall ((aux_mod_v_main_~y~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))) (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:39:23,375 WARN L290 TraceCheckUtils]: 8: Hoare triple {862#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~z~0 4294967296)) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31) main_~y~0) (<= aux_mod_v_main_~x~0_26_31 0) (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (<= 4294967296 aux_mod_v_main_~x~0_26_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_v_main_~x~0_26_31) 4294967296))))))) (or (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (< 0 aux_mod_v_main_~x~0_26_31) (< aux_mod_v_main_~x~0_26_31 0))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {855#(or (forall ((aux_mod_v_main_~y~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (and (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))) (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:39:25,384 WARN L290 TraceCheckUtils]: 7: Hoare triple {866#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {862#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~z~0 4294967296)) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int) (aux_div_v_main_~y~0_26_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31) main_~y~0) (<= aux_mod_v_main_~x~0_26_31 0) (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (<= 4294967296 aux_mod_v_main_~x~0_26_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_v_main_~x~0_26_31) 4294967296))))))) (or (forall ((aux_mod_v_main_~x~0_26_31 Int) (aux_div_v_main_~x~0_26_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296)) main_~x~0) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_26_31 (* aux_div_v_main_~x~0_26_31 4294967296))) (<= 1 v_it_2))) (< 0 aux_mod_v_main_~x~0_26_31) (< aux_mod_v_main_~x~0_26_31 0))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:39:25,387 INFO L290 TraceCheckUtils]: 6: Hoare triple {870#(or (< 0 (mod main_~x~0 4294967296)) (<= (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div (+ main_~y~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {866#(or (forall ((aux_mod_v_main_~y~0_26_31 Int)) (or (= (mod main_~n~0 4294967296) aux_mod_v_main_~y~0_26_31) (> 0 aux_mod_v_main_~y~0_26_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_26_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))))) (or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_div_v_main_~y~0_26_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_26_31 4294967296) aux_mod_v_main_~y~0_26_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))))) (>= aux_mod_v_main_~y~0_26_31 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:39:25,388 INFO L290 TraceCheckUtils]: 5: Hoare triple {767#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {870#(or (< 0 (mod main_~x~0 4294967296)) (<= (div (+ (- 1) (* (- 1) main_~y~0)) (- 4294967296)) (+ (div (+ main_~y~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:39:25,388 INFO L272 TraceCheckUtils]: 4: Hoare triple {767#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:39:25,388 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {767#true} {767#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:39:25,388 INFO L290 TraceCheckUtils]: 2: Hoare triple {767#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:39:25,389 INFO L290 TraceCheckUtils]: 1: Hoare triple {767#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {767#true} is VALID [2022-04-27 16:39:25,389 INFO L272 TraceCheckUtils]: 0: Hoare triple {767#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {767#true} is VALID [2022-04-27 16:39:25,389 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-27 16:39:25,389 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [27440468] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:39:25,389 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:39:25,389 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 8, 10] total 20 [2022-04-27 16:39:25,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [943111146] [2022-04-27 16:39:25,390 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:39:25,390 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:39:25,390 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:39:25,390 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:33,565 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 32 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:39:33,565 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-04-27 16:39:33,565 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:39:33,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-04-27 16:39:33,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=255, Unknown=4, NotChecked=34, Total=380 [2022-04-27 16:39:33,566 INFO L87 Difference]: Start difference. First operand 26 states and 35 transitions. Second operand has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:39:35,004 INFO L93 Difference]: Finished difference Result 35 states and 48 transitions. [2022-04-27 16:39:35,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-27 16:39:35,004 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:39:35,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:39:35,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 39 transitions. [2022-04-27 16:39:35,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 39 transitions. [2022-04-27 16:39:35,007 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 39 transitions. [2022-04-27 16:39:35,066 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:39:35,067 INFO L225 Difference]: With dead ends: 35 [2022-04-27 16:39:35,067 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:39:35,067 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 24 SyntacticMatches, 6 SemanticMatches, 24 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 129 ImplicationChecksByTransitivity, 13.8s TimeCoverageRelationStatistics Valid=145, Invalid=455, Unknown=4, NotChecked=46, Total=650 [2022-04-27 16:39:35,068 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 26 mSDsluCounter, 58 mSDsCounter, 0 mSdLazyCounter, 77 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 26 SdHoareTripleChecker+Valid, 70 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 77 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 60 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:39:35,068 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [26 Valid, 70 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 77 Invalid, 0 Unknown, 60 Unchecked, 0.2s Time] [2022-04-27 16:39:35,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:39:35,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 28. [2022-04-27 16:39:35,070 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:39:35,071 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,071 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,071 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:39:35,076 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:39:35,076 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:39:35,077 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:39:35,077 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:39:35,077 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:39:35,077 INFO L87 Difference]: Start difference. First operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:39:35,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:39:35,078 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:39:35,079 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:39:35,079 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:39:35,079 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:39:35,079 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:39:35,079 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:39:35,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 38 transitions. [2022-04-27 16:39:35,080 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 38 transitions. Word has length 17 [2022-04-27 16:39:35,081 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:39:35,081 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 38 transitions. [2022-04-27 16:39:35,081 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 1.45) internal successors, (29), 17 states have internal predecessors, (29), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:39:35,081 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 38 transitions. [2022-04-27 16:39:35,082 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:39:35,082 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:39:35,082 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:39:35,099 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2022-04-27 16:39:35,282 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:39:35,283 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:39:35,283 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:39:35,283 INFO L85 PathProgramCache]: Analyzing trace with hash 2088406878, now seen corresponding path program 1 times [2022-04-27 16:39:35,283 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:39:35,283 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1974400143] [2022-04-27 16:39:35,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:39:35,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:39:35,298 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:39:35,303 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_6 (* (- 4294967296) (div (+ .cse0 main_~x~0_6) 4294967296)))) 0)) [2022-04-27 16:39:35,322 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:39:35,329 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.2))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:39:35,348 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_6 (* (- 4294967296) (div (+ .cse0 main_~x~0_6) 4294967296)))) 0)) [2022-04-27 16:39:35,656 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:39:35,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:39:35,663 INFO L290 TraceCheckUtils]: 0: Hoare triple {1045#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 16:39:35,664 INFO L290 TraceCheckUtils]: 1: Hoare triple {1033#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:35,664 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1033#true} {1033#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:35,665 INFO L272 TraceCheckUtils]: 0: Hoare triple {1033#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1045#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:39:35,665 INFO L290 TraceCheckUtils]: 1: Hoare triple {1045#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 16:39:35,665 INFO L290 TraceCheckUtils]: 2: Hoare triple {1033#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:35,665 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1033#true} {1033#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:35,665 INFO L272 TraceCheckUtils]: 4: Hoare triple {1033#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:35,666 INFO L290 TraceCheckUtils]: 5: Hoare triple {1033#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1038#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:39:35,673 INFO L290 TraceCheckUtils]: 6: Hoare triple {1038#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1039#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:39:35,674 INFO L290 TraceCheckUtils]: 7: Hoare triple {1039#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} is VALID [2022-04-27 16:39:35,674 INFO L290 TraceCheckUtils]: 8: Hoare triple {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} is VALID [2022-04-27 16:39:35,675 INFO L290 TraceCheckUtils]: 9: Hoare triple {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} is VALID [2022-04-27 16:39:35,676 INFO L290 TraceCheckUtils]: 10: Hoare triple {1040#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1041#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:39:35,678 INFO L290 TraceCheckUtils]: 11: Hoare triple {1041#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:39:35,678 INFO L290 TraceCheckUtils]: 12: Hoare triple {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:39:35,679 INFO L272 TraceCheckUtils]: 13: Hoare triple {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1043#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:39:35,680 INFO L290 TraceCheckUtils]: 14: Hoare triple {1043#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1044#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:39:35,680 INFO L290 TraceCheckUtils]: 15: Hoare triple {1044#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 16:39:35,680 INFO L290 TraceCheckUtils]: 16: Hoare triple {1034#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 16:39:35,681 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:39:35,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:39:35,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1974400143] [2022-04-27 16:39:35,681 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1974400143] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:39:35,681 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1228740520] [2022-04-27 16:39:35,681 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:39:35,681 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:39:35,682 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:39:35,682 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:39:35,683 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 16:39:35,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:39:35,824 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-27 16:39:35,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:39:35,843 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:39:37,026 INFO L272 TraceCheckUtils]: 0: Hoare triple {1033#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:37,027 INFO L290 TraceCheckUtils]: 1: Hoare triple {1033#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 16:39:37,027 INFO L290 TraceCheckUtils]: 2: Hoare triple {1033#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:37,027 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1033#true} {1033#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:37,027 INFO L272 TraceCheckUtils]: 4: Hoare triple {1033#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:39:37,028 INFO L290 TraceCheckUtils]: 5: Hoare triple {1033#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1038#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:39:37,033 INFO L290 TraceCheckUtils]: 6: Hoare triple {1038#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1067#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} is VALID [2022-04-27 16:39:37,035 INFO L290 TraceCheckUtils]: 7: Hoare triple {1067#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1071#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-27 16:39:37,036 INFO L290 TraceCheckUtils]: 8: Hoare triple {1071#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1071#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-27 16:39:37,037 INFO L290 TraceCheckUtils]: 9: Hoare triple {1071#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1071#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-27 16:39:37,045 INFO L290 TraceCheckUtils]: 10: Hoare triple {1071#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1081#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:39:37,046 INFO L290 TraceCheckUtils]: 11: Hoare triple {1081#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1085#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:39:37,046 INFO L290 TraceCheckUtils]: 12: Hoare triple {1085#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1085#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:39:37,047 INFO L272 TraceCheckUtils]: 13: Hoare triple {1085#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1092#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:39:37,047 INFO L290 TraceCheckUtils]: 14: Hoare triple {1092#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1096#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:39:37,047 INFO L290 TraceCheckUtils]: 15: Hoare triple {1096#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 16:39:37,048 INFO L290 TraceCheckUtils]: 16: Hoare triple {1034#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 16:39:37,048 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:39:37,048 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:39:55,096 WARN L232 SmtUtils]: Spent 6.72s on a formula simplification that was a NOOP. DAG size: 52 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:40:05,430 INFO L290 TraceCheckUtils]: 16: Hoare triple {1034#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 16:40:05,431 INFO L290 TraceCheckUtils]: 15: Hoare triple {1096#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 16:40:05,431 INFO L290 TraceCheckUtils]: 14: Hoare triple {1092#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1096#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:40:05,433 INFO L272 TraceCheckUtils]: 13: Hoare triple {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1092#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:40:05,433 INFO L290 TraceCheckUtils]: 12: Hoare triple {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:07,441 WARN L290 TraceCheckUtils]: 11: Hoare triple {1118#(and (or (< 0 (mod main_~x~0 4294967296)) (and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))) (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1042#(and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is UNKNOWN [2022-04-27 16:40:09,475 WARN L290 TraceCheckUtils]: 10: Hoare triple {1122#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1118#(and (or (< 0 (mod main_~x~0 4294967296)) (and (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))) (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))))} is UNKNOWN [2022-04-27 16:40:10,376 INFO L290 TraceCheckUtils]: 9: Hoare triple {1122#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1122#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:40:12,387 WARN L290 TraceCheckUtils]: 8: Hoare triple {1122#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1122#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:40:12,389 INFO L290 TraceCheckUtils]: 7: Hoare triple {1039#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1122#(or (and (or (and (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (< main_~n~0 (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296) 1)) (> 0 aux_mod_v_main_~y~0_30_31) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_div_v_main_~y~0_30_31 Int) (aux_mod_v_main_~y~0_30_31 Int)) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31))) (>= aux_mod_v_main_~y~0_30_31 4294967296) (<= (+ aux_mod_v_main_~y~0_30_31 (* (div main_~n~0 4294967296) 4294967296)) main_~n~0) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_30_31 4294967296) aux_mod_v_main_~y~0_30_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))) (< 0 (mod main_~x~0 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:40:12,503 INFO L290 TraceCheckUtils]: 6: Hoare triple {1135#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (forall ((aux_mod_v_main_~x~0_31_31 Int)) (or (> 0 aux_mod_v_main_~x~0_31_31) (and (or (forall ((aux_div_v_main_~y~0_31_31 Int) (aux_div_v_main_~x~0_31_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296)) main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296))) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_31_31 v_it_1 (* aux_div_v_main_~x~0_31_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~x~0_31_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296))))) (forall ((aux_div_v_main_~y~0_31_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_31_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) 1) (+ aux_mod_v_main_~x~0_31_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_31_31 4294967296))))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1039#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:12,508 INFO L290 TraceCheckUtils]: 5: Hoare triple {1033#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1135#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (forall ((aux_mod_v_main_~x~0_31_31 Int)) (or (> 0 aux_mod_v_main_~x~0_31_31) (and (or (forall ((aux_div_v_main_~y~0_31_31 Int) (aux_div_v_main_~x~0_31_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296)) main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296))) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) (* aux_div_v_main_~x~0_31_31 4294967296) 1) (+ main_~y~0 main_~x~0)) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_31_31 v_it_1 (* aux_div_v_main_~x~0_31_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))))) (not (< 0 (mod main_~x~0 4294967296)))) (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~x~0_31_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_31_31 (* aux_div_v_main_~x~0_31_31 4294967296))))) (forall ((aux_div_v_main_~y~0_31_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_31_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_31_31 4294967296) 1) (+ aux_mod_v_main_~x~0_31_31 main_~y~0)))))) (>= aux_mod_v_main_~x~0_31_31 4294967296))))} is VALID [2022-04-27 16:40:12,508 INFO L272 TraceCheckUtils]: 4: Hoare triple {1033#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:40:12,508 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1033#true} {1033#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:40:12,508 INFO L290 TraceCheckUtils]: 2: Hoare triple {1033#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:40:12,508 INFO L290 TraceCheckUtils]: 1: Hoare triple {1033#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 16:40:12,508 INFO L272 TraceCheckUtils]: 0: Hoare triple {1033#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 16:40:12,509 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:40:12,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1228740520] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:40:12,509 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:40:12,509 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 19 [2022-04-27 16:40:12,509 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1923269010] [2022-04-27 16:40:12,509 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:40:12,510 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:40:12,510 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:40:12,510 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:20,742 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 33 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:40:20,742 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-04-27 16:40:20,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:40:20,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-04-27 16:40:20,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=261, Unknown=5, NotChecked=0, Total=342 [2022-04-27 16:40:20,743 INFO L87 Difference]: Start difference. First operand 28 states and 38 transitions. Second operand has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:22,083 INFO L93 Difference]: Finished difference Result 34 states and 45 transitions. [2022-04-27 16:40:22,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-27 16:40:22,084 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:40:22,084 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:40:22,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 38 transitions. [2022-04-27 16:40:22,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 38 transitions. [2022-04-27 16:40:22,087 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 38 transitions. [2022-04-27 16:40:22,153 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:40:22,154 INFO L225 Difference]: With dead ends: 34 [2022-04-27 16:40:22,154 INFO L226 Difference]: Without dead ends: 31 [2022-04-27 16:40:22,155 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 23 SyntacticMatches, 6 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 22.5s TimeCoverageRelationStatistics Valid=131, Invalid=464, Unknown=5, NotChecked=0, Total=600 [2022-04-27 16:40:22,155 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 24 mSDsluCounter, 50 mSDsCounter, 0 mSdLazyCounter, 38 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 66 SdHoareTripleChecker+Invalid, 77 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 38 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 32 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:40:22,156 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 66 Invalid, 77 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 38 Invalid, 0 Unknown, 32 Unchecked, 0.1s Time] [2022-04-27 16:40:22,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2022-04-27 16:40:22,158 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 28. [2022-04-27 16:40:22,158 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:40:22,158 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,158 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,158 INFO L87 Difference]: Start difference. First operand 31 states. Second operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:22,160 INFO L93 Difference]: Finished difference Result 31 states and 42 transitions. [2022-04-27 16:40:22,160 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 42 transitions. [2022-04-27 16:40:22,160 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:40:22,160 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:40:22,161 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 31 states. [2022-04-27 16:40:22,161 INFO L87 Difference]: Start difference. First operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 31 states. [2022-04-27 16:40:22,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:22,162 INFO L93 Difference]: Finished difference Result 31 states and 42 transitions. [2022-04-27 16:40:22,162 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 42 transitions. [2022-04-27 16:40:22,163 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:40:22,163 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:40:22,163 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:40:22,163 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:40:22,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 23 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 38 transitions. [2022-04-27 16:40:22,164 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 38 transitions. Word has length 17 [2022-04-27 16:40:22,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:40:22,164 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 38 transitions. [2022-04-27 16:40:22,165 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 1.5789473684210527) internal successors, (30), 16 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:22,165 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 38 transitions. [2022-04-27 16:40:22,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:40:22,165 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:40:22,165 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:40:22,189 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 16:40:22,383 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:40:22,384 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:40:22,384 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:40:22,384 INFO L85 PathProgramCache]: Analyzing trace with hash -1433573341, now seen corresponding path program 1 times [2022-04-27 16:40:22,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:40:22,384 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [981007686] [2022-04-27 16:40:22,384 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:40:22,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:40:22,399 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:22,400 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.1))) (+ main_~y~0_6 .cse0 (* (- 4294967296) (div (+ main_~y~0_6 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:22,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:22,440 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.2))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:22,447 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.3))) (+ main_~y~0_6 .cse0 (* (- 4294967296) (div (+ main_~y~0_6 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:22,861 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:40:22,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:22,866 INFO L290 TraceCheckUtils]: 0: Hoare triple {1308#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1294#true} is VALID [2022-04-27 16:40:22,866 INFO L290 TraceCheckUtils]: 1: Hoare triple {1294#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:22,867 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1294#true} {1294#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:22,867 INFO L272 TraceCheckUtils]: 0: Hoare triple {1294#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1308#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:40:22,867 INFO L290 TraceCheckUtils]: 1: Hoare triple {1308#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1294#true} is VALID [2022-04-27 16:40:22,868 INFO L290 TraceCheckUtils]: 2: Hoare triple {1294#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:22,868 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1294#true} {1294#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:22,868 INFO L272 TraceCheckUtils]: 4: Hoare triple {1294#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:22,868 INFO L290 TraceCheckUtils]: 5: Hoare triple {1294#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1299#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:40:22,881 INFO L290 TraceCheckUtils]: 6: Hoare triple {1299#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1300#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:22,882 INFO L290 TraceCheckUtils]: 7: Hoare triple {1300#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1301#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:22,882 INFO L290 TraceCheckUtils]: 8: Hoare triple {1301#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1302#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (and (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (= (+ main_~y~0 (* (- 1) main_~z~0)) 0)))} is VALID [2022-04-27 16:40:22,883 INFO L290 TraceCheckUtils]: 9: Hoare triple {1302#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (and (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (= (+ main_~y~0 (* (- 1) main_~z~0)) 0)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:40:22,884 INFO L290 TraceCheckUtils]: 10: Hoare triple {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1304#(< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 16:40:22,885 INFO L290 TraceCheckUtils]: 11: Hoare triple {1304#(< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:22,885 INFO L290 TraceCheckUtils]: 12: Hoare triple {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:22,887 INFO L272 TraceCheckUtils]: 13: Hoare triple {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1306#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:40:22,887 INFO L290 TraceCheckUtils]: 14: Hoare triple {1306#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1307#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:40:22,888 INFO L290 TraceCheckUtils]: 15: Hoare triple {1307#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1295#false} is VALID [2022-04-27 16:40:22,888 INFO L290 TraceCheckUtils]: 16: Hoare triple {1295#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1295#false} is VALID [2022-04-27 16:40:22,888 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:40:22,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:40:22,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [981007686] [2022-04-27 16:40:22,888 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [981007686] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:40:22,888 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [281203589] [2022-04-27 16:40:22,889 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:40:22,889 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:40:22,889 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:40:22,895 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:40:22,896 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 16:40:22,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:22,952 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 16:40:23,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:23,266 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:40:25,074 INFO L272 TraceCheckUtils]: 0: Hoare triple {1294#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:25,074 INFO L290 TraceCheckUtils]: 1: Hoare triple {1294#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1294#true} is VALID [2022-04-27 16:40:25,074 INFO L290 TraceCheckUtils]: 2: Hoare triple {1294#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:25,074 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1294#true} {1294#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:25,074 INFO L272 TraceCheckUtils]: 4: Hoare triple {1294#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:25,075 INFO L290 TraceCheckUtils]: 5: Hoare triple {1294#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1299#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:40:25,130 INFO L290 TraceCheckUtils]: 6: Hoare triple {1299#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1330#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:25,131 INFO L290 TraceCheckUtils]: 7: Hoare triple {1330#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1330#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:25,132 INFO L290 TraceCheckUtils]: 8: Hoare triple {1330#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1337#(or (and (= main_~z~0 0) (<= (mod main_~n~0 4294967296) 0)) (and (< 0 main_~z~0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~z~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:40:25,136 INFO L290 TraceCheckUtils]: 9: Hoare triple {1337#(or (and (= main_~z~0 0) (<= (mod main_~n~0 4294967296) 0)) (and (< 0 main_~z~0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~z~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:40:25,136 INFO L290 TraceCheckUtils]: 10: Hoare triple {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:40:25,136 INFO L290 TraceCheckUtils]: 11: Hoare triple {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1347#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:25,137 INFO L290 TraceCheckUtils]: 12: Hoare triple {1347#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1347#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:25,138 INFO L272 TraceCheckUtils]: 13: Hoare triple {1347#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1354#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:40:25,138 INFO L290 TraceCheckUtils]: 14: Hoare triple {1354#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1358#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:40:25,139 INFO L290 TraceCheckUtils]: 15: Hoare triple {1358#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1295#false} is VALID [2022-04-27 16:40:25,139 INFO L290 TraceCheckUtils]: 16: Hoare triple {1295#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1295#false} is VALID [2022-04-27 16:40:25,139 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:40:25,139 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:40:28,883 INFO L290 TraceCheckUtils]: 16: Hoare triple {1295#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1295#false} is VALID [2022-04-27 16:40:28,884 INFO L290 TraceCheckUtils]: 15: Hoare triple {1358#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1295#false} is VALID [2022-04-27 16:40:28,884 INFO L290 TraceCheckUtils]: 14: Hoare triple {1354#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1358#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:40:28,885 INFO L272 TraceCheckUtils]: 13: Hoare triple {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1354#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:40:28,886 INFO L290 TraceCheckUtils]: 12: Hoare triple {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:28,887 INFO L290 TraceCheckUtils]: 11: Hoare triple {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1305#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:28,887 INFO L290 TraceCheckUtils]: 10: Hoare triple {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [90] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:40:28,888 INFO L290 TraceCheckUtils]: 9: Hoare triple {1386#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1303#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:40:28,888 INFO L290 TraceCheckUtils]: 8: Hoare triple {1301#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1386#(or (< 0 (mod main_~z~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:28,889 INFO L290 TraceCheckUtils]: 7: Hoare triple {1301#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1301#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:28,942 INFO L290 TraceCheckUtils]: 6: Hoare triple {1396#(or (forall ((aux_div_v_main_~y~0_35_31 Int) (aux_mod_v_main_~y~0_35_31 Int)) (or (< aux_mod_v_main_~y~0_35_31 0) (and (or (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296))))) (not (< 0 (mod main_~x~0 4294967296))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296))))) (or (< 0 (mod main_~x~0 4294967296)) (not (= (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296)) main_~y~0)))) (< 0 aux_mod_v_main_~y~0_35_31))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1301#(or (< (* (div main_~y~0 4294967296) 4294967296) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:28,960 INFO L290 TraceCheckUtils]: 5: Hoare triple {1294#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1396#(or (forall ((aux_div_v_main_~y~0_35_31 Int) (aux_mod_v_main_~y~0_35_31 Int)) (or (< aux_mod_v_main_~y~0_35_31 0) (and (or (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296))))) (not (< 0 (mod main_~x~0 4294967296))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296))))) (or (< 0 (mod main_~x~0 4294967296)) (not (= (+ aux_mod_v_main_~y~0_35_31 (* aux_div_v_main_~y~0_35_31 4294967296)) main_~y~0)))) (< 0 aux_mod_v_main_~y~0_35_31))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:40:28,960 INFO L272 TraceCheckUtils]: 4: Hoare triple {1294#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:28,960 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1294#true} {1294#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:28,961 INFO L290 TraceCheckUtils]: 2: Hoare triple {1294#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:28,961 INFO L290 TraceCheckUtils]: 1: Hoare triple {1294#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1294#true} is VALID [2022-04-27 16:40:28,961 INFO L272 TraceCheckUtils]: 0: Hoare triple {1294#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1294#true} is VALID [2022-04-27 16:40:28,961 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:40:28,961 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [281203589] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:40:28,961 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:40:28,961 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 9, 9] total 19 [2022-04-27 16:40:28,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1209667239] [2022-04-27 16:40:28,962 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:40:28,962 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:40:28,963 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:40:28,963 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:29,052 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 36 edges. 36 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:40:29,052 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 19 states [2022-04-27 16:40:29,052 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:40:29,053 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2022-04-27 16:40:29,053 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=275, Unknown=1, NotChecked=0, Total=342 [2022-04-27 16:40:29,053 INFO L87 Difference]: Start difference. First operand 28 states and 38 transitions. Second operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:32,315 INFO L93 Difference]: Finished difference Result 35 states and 47 transitions. [2022-04-27 16:40:32,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 16:40:32,316 INFO L78 Accepts]: Start accepts. Automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:40:32,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:40:32,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 37 transitions. [2022-04-27 16:40:32,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 37 transitions. [2022-04-27 16:40:32,318 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 37 transitions. [2022-04-27 16:40:32,371 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:40:32,372 INFO L225 Difference]: With dead ends: 35 [2022-04-27 16:40:32,372 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:40:32,372 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 24 SyntacticMatches, 6 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=153, Invalid=547, Unknown=2, NotChecked=0, Total=702 [2022-04-27 16:40:32,373 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 24 mSDsluCounter, 88 mSDsCounter, 0 mSdLazyCounter, 94 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 106 SdHoareTripleChecker+Invalid, 169 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 94 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 66 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:40:32,373 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 106 Invalid, 169 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 94 Invalid, 0 Unknown, 66 Unchecked, 0.2s Time] [2022-04-27 16:40:32,374 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:40:32,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 27. [2022-04-27 16:40:32,376 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:40:32,376 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 27 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,376 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 27 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,376 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 27 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,377 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:32,378 INFO L93 Difference]: Finished difference Result 32 states and 44 transitions. [2022-04-27 16:40:32,378 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 44 transitions. [2022-04-27 16:40:32,378 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:40:32,378 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:40:32,378 INFO L74 IsIncluded]: Start isIncluded. First operand has 27 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:40:32,379 INFO L87 Difference]: Start difference. First operand has 27 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:40:32,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:32,380 INFO L93 Difference]: Finished difference Result 32 states and 44 transitions. [2022-04-27 16:40:32,380 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 44 transitions. [2022-04-27 16:40:32,380 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:40:32,380 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:40:32,380 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:40:32,380 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:40:32,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 22 states have (on average 1.4545454545454546) internal successors, (32), 22 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 36 transitions. [2022-04-27 16:40:32,382 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 36 transitions. Word has length 17 [2022-04-27 16:40:32,382 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:40:32,382 INFO L495 AbstractCegarLoop]: Abstraction has 27 states and 36 transitions. [2022-04-27 16:40:32,382 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 19 states, 19 states have (on average 1.5263157894736843) internal successors, (29), 16 states have internal predecessors, (29), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:32,382 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 36 transitions. [2022-04-27 16:40:32,382 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:40:32,383 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:40:32,383 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:40:32,402 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-27 16:40:32,591 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:40:32,591 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:40:32,592 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:40:32,592 INFO L85 PathProgramCache]: Analyzing trace with hash 1054189566, now seen corresponding path program 1 times [2022-04-27 16:40:32,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:40:32,592 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [627585387] [2022-04-27 16:40:32,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:40:32,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:40:32,605 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:32,606 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.1))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:32,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:32,629 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.3))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:32,641 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.4))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:33,107 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:40:33,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:33,112 INFO L290 TraceCheckUtils]: 0: Hoare triple {1572#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1560#true} is VALID [2022-04-27 16:40:33,112 INFO L290 TraceCheckUtils]: 1: Hoare triple {1560#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:33,113 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1560#true} {1560#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:33,113 INFO L272 TraceCheckUtils]: 0: Hoare triple {1560#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1572#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:40:33,113 INFO L290 TraceCheckUtils]: 1: Hoare triple {1572#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1560#true} is VALID [2022-04-27 16:40:33,113 INFO L290 TraceCheckUtils]: 2: Hoare triple {1560#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:33,114 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1560#true} {1560#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:33,114 INFO L272 TraceCheckUtils]: 4: Hoare triple {1560#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:33,114 INFO L290 TraceCheckUtils]: 5: Hoare triple {1560#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1565#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:40:33,123 INFO L290 TraceCheckUtils]: 6: Hoare triple {1565#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1566#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} is VALID [2022-04-27 16:40:33,126 INFO L290 TraceCheckUtils]: 7: Hoare triple {1566#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1567#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-27 16:40:33,128 INFO L290 TraceCheckUtils]: 8: Hoare triple {1567#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1568#(and (= (+ main_~y~0 (* (- 1) main_~z~0)) 0) (or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (< (* (div main_~z~0 4294967296) 4294967296) main_~z~0)))} is VALID [2022-04-27 16:40:33,181 INFO L290 TraceCheckUtils]: 9: Hoare triple {1568#(and (= (+ main_~y~0 (* (- 1) main_~z~0)) 0) (or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (< (* (div main_~z~0 4294967296) 4294967296) main_~z~0)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1567#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-27 16:40:33,183 INFO L290 TraceCheckUtils]: 10: Hoare triple {1567#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1567#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-27 16:40:33,184 INFO L290 TraceCheckUtils]: 11: Hoare triple {1567#(or (and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:40:33,185 INFO L290 TraceCheckUtils]: 12: Hoare triple {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:40:33,186 INFO L272 TraceCheckUtils]: 13: Hoare triple {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1570#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:40:33,187 INFO L290 TraceCheckUtils]: 14: Hoare triple {1570#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1571#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:40:33,187 INFO L290 TraceCheckUtils]: 15: Hoare triple {1571#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1561#false} is VALID [2022-04-27 16:40:33,187 INFO L290 TraceCheckUtils]: 16: Hoare triple {1561#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1561#false} is VALID [2022-04-27 16:40:33,187 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:40:33,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:40:33,187 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [627585387] [2022-04-27 16:40:33,187 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [627585387] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:40:33,188 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1819797603] [2022-04-27 16:40:33,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:40:33,188 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:40:33,188 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:40:33,189 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:40:33,189 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 16:40:33,239 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:33,240 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-27 16:40:35,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2022-04-27 16:40:35,176 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:40:36,181 INFO L272 TraceCheckUtils]: 0: Hoare triple {1560#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:36,182 INFO L290 TraceCheckUtils]: 1: Hoare triple {1560#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1560#true} is VALID [2022-04-27 16:40:36,182 INFO L290 TraceCheckUtils]: 2: Hoare triple {1560#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:36,182 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1560#true} {1560#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:36,182 INFO L272 TraceCheckUtils]: 4: Hoare triple {1560#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:36,183 INFO L290 TraceCheckUtils]: 5: Hoare triple {1560#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1565#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:40:36,193 INFO L290 TraceCheckUtils]: 6: Hoare triple {1565#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:36,194 INFO L290 TraceCheckUtils]: 7: Hoare triple {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:36,196 INFO L290 TraceCheckUtils]: 8: Hoare triple {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:36,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:36,198 INFO L290 TraceCheckUtils]: 10: Hoare triple {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} is VALID [2022-04-27 16:40:36,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {1594#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:40:36,200 INFO L290 TraceCheckUtils]: 12: Hoare triple {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} is VALID [2022-04-27 16:40:36,201 INFO L272 TraceCheckUtils]: 13: Hoare triple {1569#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1616#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:40:36,201 INFO L290 TraceCheckUtils]: 14: Hoare triple {1616#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1620#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:40:36,202 INFO L290 TraceCheckUtils]: 15: Hoare triple {1620#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1561#false} is VALID [2022-04-27 16:40:36,202 INFO L290 TraceCheckUtils]: 16: Hoare triple {1561#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1561#false} is VALID [2022-04-27 16:40:36,202 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:40:36,202 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:40:47,774 INFO L290 TraceCheckUtils]: 16: Hoare triple {1561#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1561#false} is VALID [2022-04-27 16:40:47,774 INFO L290 TraceCheckUtils]: 15: Hoare triple {1620#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1561#false} is VALID [2022-04-27 16:40:47,774 INFO L290 TraceCheckUtils]: 14: Hoare triple {1616#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1620#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:40:47,775 INFO L272 TraceCheckUtils]: 13: Hoare triple {1636#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1616#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:40:47,775 INFO L290 TraceCheckUtils]: 12: Hoare triple {1636#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1636#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-27 16:40:47,776 INFO L290 TraceCheckUtils]: 11: Hoare triple {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1636#(= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296))} is VALID [2022-04-27 16:40:47,776 INFO L290 TraceCheckUtils]: 10: Hoare triple {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:40:47,777 INFO L290 TraceCheckUtils]: 9: Hoare triple {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:40:47,777 INFO L290 TraceCheckUtils]: 8: Hoare triple {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:40:47,778 INFO L290 TraceCheckUtils]: 7: Hoare triple {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:40:49,835 WARN L290 TraceCheckUtils]: 6: Hoare triple {1659#(forall ((aux_mod_aux_mod_v_main_~y~0_38_31_42 Int) (aux_div_aux_mod_v_main_~y~0_38_31_42 Int) (aux_div_v_main_~y~0_38_31 Int)) (or (>= aux_mod_aux_mod_v_main_~y~0_38_31_42 4294967296) (= (mod main_~n~0 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) (< 0 (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)) (and (or (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))) (< 0 (mod main_~x~0 4294967296))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)))))) (< (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) 0) (> 0 aux_mod_aux_mod_v_main_~y~0_38_31_42)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1643#(or (= (mod main_~n~0 4294967296) (mod main_~y~0 4294967296)) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:40:49,854 INFO L290 TraceCheckUtils]: 5: Hoare triple {1560#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1659#(forall ((aux_mod_aux_mod_v_main_~y~0_38_31_42 Int) (aux_div_aux_mod_v_main_~y~0_38_31_42 Int) (aux_div_v_main_~y~0_38_31 Int)) (or (>= aux_mod_aux_mod_v_main_~y~0_38_31_42 4294967296) (= (mod main_~n~0 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) (< 0 (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)) (and (or (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))) (< 0 (mod main_~x~0 4294967296))) (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42))) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1) (<= (+ v_it_1 main_~y~0 1) (+ (* aux_div_v_main_~y~0_38_31 4294967296) (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42)))))) (< (+ (* aux_div_aux_mod_v_main_~y~0_38_31_42 4294967296) aux_mod_aux_mod_v_main_~y~0_38_31_42) 0) (> 0 aux_mod_aux_mod_v_main_~y~0_38_31_42)))} is VALID [2022-04-27 16:40:49,855 INFO L272 TraceCheckUtils]: 4: Hoare triple {1560#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:49,855 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1560#true} {1560#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:49,855 INFO L290 TraceCheckUtils]: 2: Hoare triple {1560#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:49,855 INFO L290 TraceCheckUtils]: 1: Hoare triple {1560#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1560#true} is VALID [2022-04-27 16:40:49,855 INFO L272 TraceCheckUtils]: 0: Hoare triple {1560#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1560#true} is VALID [2022-04-27 16:40:49,855 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:40:49,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1819797603] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:40:49,855 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:40:49,855 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 7] total 16 [2022-04-27 16:40:49,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [18997959] [2022-04-27 16:40:49,856 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:40:49,856 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:40:49,856 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:40:49,857 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:52,257 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 36 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-27 16:40:52,257 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 16:40:52,257 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:40:52,257 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 16:40:52,258 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=191, Unknown=4, NotChecked=0, Total=240 [2022-04-27 16:40:52,258 INFO L87 Difference]: Start difference. First operand 27 states and 36 transitions. Second operand has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:58,168 INFO L93 Difference]: Finished difference Result 35 states and 48 transitions. [2022-04-27 16:40:58,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:40:58,169 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:40:58,169 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:40:58,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 41 transitions. [2022-04-27 16:40:58,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 41 transitions. [2022-04-27 16:40:58,172 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 41 transitions. [2022-04-27 16:40:58,270 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:40:58,271 INFO L225 Difference]: With dead ends: 35 [2022-04-27 16:40:58,271 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:40:58,272 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 27 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 14.6s TimeCoverageRelationStatistics Valid=119, Invalid=427, Unknown=6, NotChecked=0, Total=552 [2022-04-27 16:40:58,273 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 20 mSDsluCounter, 50 mSDsCounter, 0 mSdLazyCounter, 53 mSolverCounterSat, 9 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 62 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 9 IncrementalHoareTripleChecker+Valid, 53 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 21 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:40:58,273 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 62 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [9 Valid, 53 Invalid, 0 Unknown, 21 Unchecked, 0.2s Time] [2022-04-27 16:40:58,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:40:58,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 29. [2022-04-27 16:40:58,276 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:40:58,276 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,276 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,276 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:58,278 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:40:58,278 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:40:58,278 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:40:58,278 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:40:58,278 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:40:58,278 INFO L87 Difference]: Start difference. First operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:40:58,279 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:40:58,280 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:40:58,280 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:40:58,280 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:40:58,280 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:40:58,280 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:40:58,280 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:40:58,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 24 states have (on average 1.5) internal successors, (36), 24 states have internal predecessors, (36), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 40 transitions. [2022-04-27 16:40:58,281 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 40 transitions. Word has length 17 [2022-04-27 16:40:58,281 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:40:58,281 INFO L495 AbstractCegarLoop]: Abstraction has 29 states and 40 transitions. [2022-04-27 16:40:58,282 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.875) internal successors, (30), 13 states have internal predecessors, (30), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:40:58,282 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 40 transitions. [2022-04-27 16:40:58,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:40:58,282 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:40:58,282 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:40:58,310 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-27 16:40:58,507 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:40:58,507 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:40:58,507 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:40:58,508 INFO L85 PathProgramCache]: Analyzing trace with hash -755846018, now seen corresponding path program 2 times [2022-04-27 16:40:58,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:40:58,508 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278471488] [2022-04-27 16:40:58,508 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:40:58,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:40:58,516 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:58,517 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.1))) (+ main_~x~0_6 .cse0 (* (- 4294967296) (div (+ main_~x~0_6 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:58,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:58,537 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.4))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:58,549 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.5))) (+ main_~x~0_6 .cse0 (* (- 4294967296) (div (+ main_~x~0_6 .cse0) 4294967296)))) 0)) [2022-04-27 16:40:59,224 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:40:59,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:40:59,229 INFO L290 TraceCheckUtils]: 0: Hoare triple {1838#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1824#true} is VALID [2022-04-27 16:40:59,230 INFO L290 TraceCheckUtils]: 1: Hoare triple {1824#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:40:59,230 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1824#true} {1824#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:40:59,230 INFO L272 TraceCheckUtils]: 0: Hoare triple {1824#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1838#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:40:59,230 INFO L290 TraceCheckUtils]: 1: Hoare triple {1838#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1824#true} is VALID [2022-04-27 16:40:59,231 INFO L290 TraceCheckUtils]: 2: Hoare triple {1824#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:40:59,231 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1824#true} {1824#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:40:59,231 INFO L272 TraceCheckUtils]: 4: Hoare triple {1824#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:40:59,237 INFO L290 TraceCheckUtils]: 5: Hoare triple {1824#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1829#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:40:59,256 INFO L290 TraceCheckUtils]: 6: Hoare triple {1829#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1830#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} is VALID [2022-04-27 16:40:59,281 INFO L290 TraceCheckUtils]: 7: Hoare triple {1830#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1831#(or (<= main_~y~0 (+ 4294967295 (* 4294967296 (div (+ (- 1) main_~y~0) 4294967296)))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} is VALID [2022-04-27 16:40:59,283 INFO L290 TraceCheckUtils]: 8: Hoare triple {1831#(or (<= main_~y~0 (+ 4294967295 (* 4294967296 (div (+ (- 1) main_~y~0) 4294967296)))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ main_~y~0 main_~x~0) (+ (* 4294967296 (div (+ (- 1) main_~y~0 main_~x~0) 4294967296)) 4294967295)))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1832#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} is VALID [2022-04-27 16:40:59,285 INFO L290 TraceCheckUtils]: 9: Hoare triple {1832#(or (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= (+ main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) (+ 4294967295 (* (div (+ (- 1) main_~y~0 (* 4294967296 (div main_~x~0 4294967296))) 4294967296) 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1833#(and (or (<= (+ (* (div main_~z~0 4294967296) 4294967296) 1) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))) (= (+ main_~y~0 (* (- 1) main_~z~0)) 0))} is VALID [2022-04-27 16:40:59,286 INFO L290 TraceCheckUtils]: 10: Hoare triple {1833#(and (or (<= (+ (* (div main_~z~0 4294967296) 4294967296) 1) main_~y~0) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))) (= (+ main_~y~0 (* (- 1) main_~z~0)) 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1834#(< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 16:40:59,287 INFO L290 TraceCheckUtils]: 11: Hoare triple {1834#(< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1835#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:59,288 INFO L290 TraceCheckUtils]: 12: Hoare triple {1835#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1835#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:40:59,289 INFO L272 TraceCheckUtils]: 13: Hoare triple {1835#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1836#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:40:59,289 INFO L290 TraceCheckUtils]: 14: Hoare triple {1836#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1837#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:40:59,290 INFO L290 TraceCheckUtils]: 15: Hoare triple {1837#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1825#false} is VALID [2022-04-27 16:40:59,290 INFO L290 TraceCheckUtils]: 16: Hoare triple {1825#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1825#false} is VALID [2022-04-27 16:40:59,290 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:40:59,290 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:40:59,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278471488] [2022-04-27 16:40:59,290 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278471488] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:40:59,290 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1887515224] [2022-04-27 16:40:59,290 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:40:59,290 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:40:59,291 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:40:59,291 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:40:59,292 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 16:40:59,511 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:40:59,511 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:40:59,512 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-27 16:41:01,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unknown [2022-04-27 16:41:01,546 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:41:20,405 WARN L833 $PredicateComparison]: unable to prove that (and (let ((.cse1 (mod c_main_~n~0 4294967296))) (or (and (or (and (< 0 c_main_~y~0) (<= (mod (+ (* 4294967295 c_main_~y~0) c_main_~n~0) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ c_main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) c_main_~y~0)) (not (<= 1 v_it_1))))) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (let ((.cse0 (* aux_div_v_main_~x~0_41_31 4294967296))) (and (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) c_main_~n~0)) (< 0 (mod (+ c_main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 c_main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) c_main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< c_main_~n~0 (+ aux_mod_v_main_~x~0_41_31 .cse0 c_main_~y~0)) (< (+ aux_mod_v_main_~x~0_41_31 .cse0) c_main_~n~0) (< 0 aux_mod_v_main_~x~0_41_31))))) (< 0 .cse1)) (and (<= .cse1 0) (= c_main_~y~0 0)))) (= c_main_~y~0 c_main_~z~0)) is different from false [2022-04-27 16:41:34,172 WARN L232 SmtUtils]: Spent 6.26s on a formula simplification. DAG size of input: 48 DAG size of output: 8 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:41:34,685 INFO L272 TraceCheckUtils]: 0: Hoare triple {1824#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:41:34,685 INFO L290 TraceCheckUtils]: 1: Hoare triple {1824#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1824#true} is VALID [2022-04-27 16:41:34,685 INFO L290 TraceCheckUtils]: 2: Hoare triple {1824#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:41:34,686 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1824#true} {1824#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:41:34,686 INFO L272 TraceCheckUtils]: 4: Hoare triple {1824#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1824#true} is VALID [2022-04-27 16:41:34,686 INFO L290 TraceCheckUtils]: 5: Hoare triple {1824#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1829#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:41:34,701 INFO L290 TraceCheckUtils]: 6: Hoare triple {1829#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1860#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} is VALID [2022-04-27 16:41:36,717 WARN L290 TraceCheckUtils]: 7: Hoare triple {1860#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} [83] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {1864#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (or (and (<= (mod (+ main_~n~0 (* main_~y~0 4294967295)) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 main_~y~0)) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (and (< main_~n~0 (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0)) (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) main_~n~0)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< 0 aux_mod_v_main_~x~0_41_31) (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~n~0)))) (< 0 (mod main_~n~0 4294967296))))} is UNKNOWN [2022-04-27 16:41:38,724 WARN L290 TraceCheckUtils]: 8: Hoare triple {1864#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (or (and (<= (mod (+ main_~n~0 (* main_~y~0 4294967295)) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 main_~y~0)) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (and (< main_~n~0 (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0)) (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) main_~n~0)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< 0 aux_mod_v_main_~x~0_41_31) (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~n~0)))) (< 0 (mod main_~n~0 4294967296))))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1864#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (or (and (<= (mod (+ main_~n~0 (* main_~y~0 4294967295)) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 main_~y~0)) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (and (< main_~n~0 (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0)) (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) main_~n~0)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< 0 aux_mod_v_main_~x~0_41_31) (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~n~0)))) (< 0 (mod main_~n~0 4294967296))))} is UNKNOWN [2022-04-27 16:41:40,739 WARN L290 TraceCheckUtils]: 9: Hoare triple {1864#(or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (or (and (<= (mod (+ main_~n~0 (* main_~y~0 4294967295)) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 main_~y~0)) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (and (< main_~n~0 (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0)) (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) main_~n~0)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< 0 aux_mod_v_main_~x~0_41_31) (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~n~0)))) (< 0 (mod main_~n~0 4294967296))))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1871#(and (= main_~z~0 main_~y~0) (or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (or (and (<= (mod (+ main_~n~0 (* main_~y~0 4294967295)) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 main_~y~0)) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (and (< main_~n~0 (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0)) (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) main_~n~0)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< 0 aux_mod_v_main_~x~0_41_31) (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~n~0)))) (< 0 (mod main_~n~0 4294967296)))))} is UNKNOWN [2022-04-27 16:41:41,065 INFO L290 TraceCheckUtils]: 10: Hoare triple {1871#(and (= main_~z~0 main_~y~0) (or (and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)) (and (or (and (<= (mod (+ main_~n~0 (* main_~y~0 4294967295)) 4294967296) 0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 main_~y~0)) (exists ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int)) (and (< main_~n~0 (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0)) (< aux_mod_v_main_~x~0_41_31 4294967296) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_1 1) main_~n~0)) (not (<= 1 v_it_1)))) (forall ((v_it_1 Int)) (or (not (<= (+ v_it_1 main_~n~0 1) (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) main_~y~0))) (< 0 (mod (+ aux_mod_v_main_~x~0_41_31 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)))) (< 0 aux_mod_v_main_~x~0_41_31) (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~n~0)))) (< 0 (mod main_~n~0 4294967296)))))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1875#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:41:41,066 INFO L290 TraceCheckUtils]: 11: Hoare triple {1875#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1875#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:41:41,067 INFO L290 TraceCheckUtils]: 12: Hoare triple {1875#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1875#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} is VALID [2022-04-27 16:41:41,068 INFO L272 TraceCheckUtils]: 13: Hoare triple {1875#(and (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {1885#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:41:41,069 INFO L290 TraceCheckUtils]: 14: Hoare triple {1885#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1889#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:41:41,069 INFO L290 TraceCheckUtils]: 15: Hoare triple {1889#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1825#false} is VALID [2022-04-27 16:41:41,070 INFO L290 TraceCheckUtils]: 16: Hoare triple {1825#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1825#false} is VALID [2022-04-27 16:41:41,070 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:41:41,070 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:43:06,275 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_div_v_main_~n~0_9_30 Int) (aux_mod_v_main_~n~0_9_30 Int) (aux_mod_v_main_~y~0_42_88 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_42_88) (<= aux_mod_v_main_~n~0_9_30 0) (forall ((aux_div_v_main_~x~0_42_31 Int) (aux_div_aux_mod_v_main_~x~0_42_31_87 Int) (aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int) (aux_div_v_main_~y~0_42_88 Int)) (let ((.cse2 (* aux_div_v_main_~n~0_9_30 4294967296))) (let ((.cse4 (+ .cse2 aux_mod_v_main_~n~0_9_30)) (.cse0 (* aux_div_v_main_~x~0_43_31 4294967296)) (.cse5 (+ .cse2 aux_mod_v_main_~n~0_9_30 (* 4294967296 aux_div_aux_mod_v_main_~x~0_42_31_87))) (.cse3 (* aux_div_v_main_~x~0_42_31 4294967296)) (.cse1 (* aux_div_v_main_~y~0_42_88 4294967296))) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (<= (+ aux_mod_v_main_~x~0_43_31 .cse0 aux_mod_v_main_~y~0_42_88 .cse1 1) (+ .cse2 .cse3 aux_mod_v_main_~n~0_9_30)) (<= (+ 4294967297 aux_mod_v_main_~y~0_42_88 .cse1) .cse4) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_43_31 v_it_1 (* aux_div_v_main_~x~0_43_31 4294967296) 1) (+ (* aux_div_v_main_~n~0_9_30 4294967296) aux_mod_v_main_~n~0_9_30)) (<= 1 v_it_1) (not (< 0 (mod (+ aux_mod_v_main_~n~0_9_30 (* v_it_1 4294967295)) 4294967296))))) (< .cse4 (+ aux_mod_v_main_~y~0_42_88 .cse1 1)) (<= (+ .cse3 4294967297 aux_mod_v_main_~y~0_42_88 .cse1) .cse5) (<= .cse4 (+ aux_mod_v_main_~x~0_43_31 .cse0)) (< .cse5 (+ .cse3 aux_mod_v_main_~y~0_42_88 .cse1 1)) (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~x~0_43_31 (* v_it_1 4294967295)) 4294967296))) (<= (let ((.cse6 (* aux_div_v_main_~n~0_9_30 4294967296))) (+ (* 4294967296 (div (+ (- 1) .cse6 (* (- 1) aux_mod_v_main_~y~0_42_88) (* aux_div_v_main_~y~0_42_88 (- 4294967296)) aux_mod_v_main_~n~0_9_30 (* 4294967296 aux_div_aux_mod_v_main_~x~0_42_31_87)) 4294967296)) .cse6 v_it_1 aux_mod_v_main_~n~0_9_30)) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296) aux_mod_v_main_~y~0_42_88 (* aux_div_v_main_~y~0_42_88 4294967296))) (<= 1 v_it_1))) (<= aux_mod_v_main_~x~0_43_31 0))))) (<= aux_mod_v_main_~y~0_42_88 4294967294) (<= 4294967296 aux_mod_v_main_~n~0_9_30))) is different from false [2022-04-27 16:43:08,288 WARN L855 $PredicateComparison]: unable to prove that (forall ((aux_div_v_main_~n~0_9_30 Int) (aux_mod_v_main_~n~0_9_30 Int) (aux_mod_v_main_~y~0_42_88 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_42_88) (<= aux_mod_v_main_~n~0_9_30 0) (forall ((aux_div_v_main_~x~0_42_31 Int) (aux_div_aux_mod_v_main_~x~0_42_31_87 Int) (aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int) (aux_div_v_main_~y~0_42_88 Int)) (let ((.cse2 (* aux_div_v_main_~n~0_9_30 4294967296))) (let ((.cse4 (+ .cse2 aux_mod_v_main_~n~0_9_30)) (.cse0 (* aux_div_v_main_~x~0_43_31 4294967296)) (.cse5 (+ .cse2 aux_mod_v_main_~n~0_9_30 (* 4294967296 aux_div_aux_mod_v_main_~x~0_42_31_87))) (.cse3 (* aux_div_v_main_~x~0_42_31 4294967296)) (.cse1 (* aux_div_v_main_~y~0_42_88 4294967296))) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (<= (+ aux_mod_v_main_~x~0_43_31 .cse0 aux_mod_v_main_~y~0_42_88 .cse1 1) (+ .cse2 .cse3 aux_mod_v_main_~n~0_9_30)) (<= (+ 4294967297 aux_mod_v_main_~y~0_42_88 .cse1) .cse4) (exists ((v_it_1 Int)) (and (<= (+ aux_mod_v_main_~x~0_43_31 v_it_1 (* aux_div_v_main_~x~0_43_31 4294967296) 1) (+ (* aux_div_v_main_~n~0_9_30 4294967296) aux_mod_v_main_~n~0_9_30)) (<= 1 v_it_1) (not (< 0 (mod (+ aux_mod_v_main_~n~0_9_30 (* v_it_1 4294967295)) 4294967296))))) (< .cse4 (+ aux_mod_v_main_~y~0_42_88 .cse1 1)) (<= (+ .cse3 4294967297 aux_mod_v_main_~y~0_42_88 .cse1) .cse5) (<= .cse4 (+ aux_mod_v_main_~x~0_43_31 .cse0)) (< .cse5 (+ .cse3 aux_mod_v_main_~y~0_42_88 .cse1 1)) (exists ((v_it_1 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~x~0_43_31 (* v_it_1 4294967295)) 4294967296))) (<= (let ((.cse6 (* aux_div_v_main_~n~0_9_30 4294967296))) (+ (* 4294967296 (div (+ (- 1) .cse6 (* (- 1) aux_mod_v_main_~y~0_42_88) (* aux_div_v_main_~y~0_42_88 (- 4294967296)) aux_mod_v_main_~n~0_9_30 (* 4294967296 aux_div_aux_mod_v_main_~x~0_42_31_87)) 4294967296)) .cse6 v_it_1 aux_mod_v_main_~n~0_9_30)) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296) aux_mod_v_main_~y~0_42_88 (* aux_div_v_main_~y~0_42_88 4294967296))) (<= 1 v_it_1))) (<= aux_mod_v_main_~x~0_43_31 0))))) (<= aux_mod_v_main_~y~0_42_88 4294967294) (<= 4294967296 aux_mod_v_main_~n~0_9_30))) is different from true [2022-04-27 16:43:42,623 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1887515224] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:43:42,623 INFO L184 FreeRefinementEngine]: Found 0 perfect and 2 imperfect interpolant sequences. [2022-04-27 16:43:42,623 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 9] total 18 [2022-04-27 16:43:42,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [8356225] [2022-04-27 16:43:42,623 INFO L85 oduleStraightlineAll]: Using 2 imperfect interpolants to construct interpolant automaton [2022-04-27 16:43:42,624 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:43:42,624 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:43:42,626 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:48,886 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 26 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:48,887 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-04-27 16:43:48,887 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:43:48,887 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-04-27 16:43:48,887 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=293, Unknown=21, NotChecked=74, Total=462 [2022-04-27 16:43:48,888 INFO L87 Difference]: Start difference. First operand 29 states and 40 transitions. Second operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:41,475 WARN L232 SmtUtils]: Spent 22.59s on a formula simplification. DAG size of input: 71 DAG size of output: 68 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:44:42,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:44:42,139 INFO L93 Difference]: Finished difference Result 39 states and 54 transitions. [2022-04-27 16:44:42,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-04-27 16:44:42,139 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:44:42,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:44:42,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:42,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 43 transitions. [2022-04-27 16:44:42,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:42,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 43 transitions. [2022-04-27 16:44:42,141 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 15 states and 43 transitions. [2022-04-27 16:44:48,339 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 40 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:44:48,340 INFO L225 Difference]: With dead ends: 39 [2022-04-27 16:44:48,340 INFO L226 Difference]: Without dead ends: 36 [2022-04-27 16:44:48,340 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 17 SyntacticMatches, 10 SemanticMatches, 29 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 239 ImplicationChecksByTransitivity, 115.9s TimeCoverageRelationStatistics Valid=172, Invalid=619, Unknown=29, NotChecked=110, Total=930 [2022-04-27 16:44:48,341 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 32 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 72 SdHoareTripleChecker+Invalid, 161 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 75 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 16:44:48,341 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 72 Invalid, 161 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 76 Invalid, 0 Unknown, 75 Unchecked, 0.3s Time] [2022-04-27 16:44:48,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2022-04-27 16:44:48,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 32. [2022-04-27 16:44:48,343 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:44:48,343 INFO L82 GeneralOperation]: Start isEquivalent. First operand 36 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:48,343 INFO L74 IsIncluded]: Start isIncluded. First operand 36 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:48,344 INFO L87 Difference]: Start difference. First operand 36 states. Second operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:48,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:44:48,345 INFO L93 Difference]: Finished difference Result 36 states and 51 transitions. [2022-04-27 16:44:48,345 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 51 transitions. [2022-04-27 16:44:48,345 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:44:48,345 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:44:48,345 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 36 states. [2022-04-27 16:44:48,345 INFO L87 Difference]: Start difference. First operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 36 states. [2022-04-27 16:44:48,346 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:44:48,346 INFO L93 Difference]: Finished difference Result 36 states and 51 transitions. [2022-04-27 16:44:48,346 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 51 transitions. [2022-04-27 16:44:48,347 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:44:48,347 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:44:48,347 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:44:48,347 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:44:48,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 27 states have (on average 1.5185185185185186) internal successors, (41), 27 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:48,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 45 transitions. [2022-04-27 16:44:48,348 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 45 transitions. Word has length 17 [2022-04-27 16:44:48,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:44:48,348 INFO L495 AbstractCegarLoop]: Abstraction has 32 states and 45 transitions. [2022-04-27 16:44:48,348 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 15 states have internal predecessors, (23), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:48,348 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:44:48,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:44:48,349 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:44:48,349 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:44:48,359 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-27 16:44:48,554 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-04-27 16:44:48,554 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:44:48,555 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:44:48,555 INFO L85 PathProgramCache]: Analyzing trace with hash 325265765, now seen corresponding path program 2 times [2022-04-27 16:44:48,555 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:44:48,555 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [563723470] [2022-04-27 16:44:48,555 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:44:48,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:44:48,564 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:44:48,566 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-27 16:44:48,567 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_11 (* (- 4294967296) (div (+ .cse0 main_~x~0_11) 4294967296)))) 0)) [2022-04-27 16:44:48,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:48,589 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.5))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:44:48,594 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.6))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-27 16:44:48,598 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.7))) (+ .cse0 main_~x~0_11 (* (- 4294967296) (div (+ .cse0 main_~x~0_11) 4294967296)))) 0)) [2022-04-27 16:44:49,234 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:44:49,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:49,239 INFO L290 TraceCheckUtils]: 0: Hoare triple {2119#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2106#true} is VALID [2022-04-27 16:44:49,240 INFO L290 TraceCheckUtils]: 1: Hoare triple {2106#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:49,240 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2106#true} {2106#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:49,241 INFO L272 TraceCheckUtils]: 0: Hoare triple {2106#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2119#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:44:49,241 INFO L290 TraceCheckUtils]: 1: Hoare triple {2119#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2106#true} is VALID [2022-04-27 16:44:49,241 INFO L290 TraceCheckUtils]: 2: Hoare triple {2106#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:49,241 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2106#true} {2106#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:49,241 INFO L272 TraceCheckUtils]: 4: Hoare triple {2106#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:49,242 INFO L290 TraceCheckUtils]: 5: Hoare triple {2106#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2111#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:49,243 INFO L290 TraceCheckUtils]: 6: Hoare triple {2111#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:49,243 INFO L290 TraceCheckUtils]: 7: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2113#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:49,245 INFO L290 TraceCheckUtils]: 8: Hoare triple {2113#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:49,245 INFO L290 TraceCheckUtils]: 9: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:49,246 INFO L290 TraceCheckUtils]: 10: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:49,249 INFO L290 TraceCheckUtils]: 11: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2114#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (+ main_~y~0 main_~x~0 (* (div (+ main_~n~0 (* (- 1) main_~x~0) (* (- 1) main_~y~0)) 4294967296) 4294967296))) (<= (* (div (+ main_~y~0 main_~x~0 4294967295) 4294967296) 4294967296) (+ main_~y~0 main_~x~0)))} is VALID [2022-04-27 16:44:49,255 INFO L290 TraceCheckUtils]: 12: Hoare triple {2114#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (+ main_~y~0 main_~x~0 (* (div (+ main_~n~0 (* (- 1) main_~x~0) (* (- 1) main_~y~0)) 4294967296) 4294967296))) (<= (* (div (+ main_~y~0 main_~x~0 4294967295) 4294967296) 4294967296) (+ main_~y~0 main_~x~0)))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2115#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) 4294967296 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0)) (and (<= (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0 (* (div main_~n~0 4294967296) 4294967296))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))))} is VALID [2022-04-27 16:44:49,256 INFO L290 TraceCheckUtils]: 13: Hoare triple {2115#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) 4294967296 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0)) (and (<= (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~y~0 main_~x~0 (* (div main_~n~0 4294967296) 4294967296))) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0))))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2116#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} is VALID [2022-04-27 16:44:49,257 INFO L272 TraceCheckUtils]: 14: Hoare triple {2116#(and (< (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0) (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296) 1)) (<= (+ main_~y~0 (* (div main_~n~0 4294967296) 4294967296)) (+ (* (div main_~y~0 4294967296) 4294967296) main_~n~0)))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {2117#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:44:49,258 INFO L290 TraceCheckUtils]: 15: Hoare triple {2117#(not (= |__VERIFIER_assert_#in~cond| 0))} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2118#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:44:49,258 INFO L290 TraceCheckUtils]: 16: Hoare triple {2118#(not (= __VERIFIER_assert_~cond 0))} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2107#false} is VALID [2022-04-27 16:44:49,258 INFO L290 TraceCheckUtils]: 17: Hoare triple {2107#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2107#false} is VALID [2022-04-27 16:44:49,259 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:44:49,259 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:44:49,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [563723470] [2022-04-27 16:44:49,259 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [563723470] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:44:49,259 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [300120710] [2022-04-27 16:44:49,259 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:44:49,259 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:44:49,259 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:44:49,260 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:44:49,260 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 16:44:49,294 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:44:49,294 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:44:49,295 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 14 conjunts are in the unsatisfiable core [2022-04-27 16:44:49,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:49,313 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:44:50,208 INFO L272 TraceCheckUtils]: 0: Hoare triple {2106#true} [75] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:50,209 INFO L290 TraceCheckUtils]: 1: Hoare triple {2106#true} [77] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2106#true} is VALID [2022-04-27 16:44:50,209 INFO L290 TraceCheckUtils]: 2: Hoare triple {2106#true} [80] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:50,209 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2106#true} {2106#true} [103] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:50,209 INFO L272 TraceCheckUtils]: 4: Hoare triple {2106#true} [76] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2106#true} is VALID [2022-04-27 16:44:50,209 INFO L290 TraceCheckUtils]: 5: Hoare triple {2106#true} [79] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2111#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,210 INFO L290 TraceCheckUtils]: 6: Hoare triple {2111#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [82] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,211 INFO L290 TraceCheckUtils]: 7: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [84] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2113#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,212 INFO L290 TraceCheckUtils]: 8: Hoare triple {2113#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [87] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_7 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_7 v_main_~z~0_6) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|) (<= .cse0 0)) (and (< v_main_~x~0_9 v_main_~x~0_8) (= v_main_~z~0_6 (+ (* (- 1) v_main_~x~0_8) v_main_~x~0_9 v_main_~z~0_7)) (forall ((v_it_2 Int)) (or (not (<= 1 v_it_2)) (not (<= (+ v_main_~x~0_9 v_it_2 1) v_main_~x~0_8)) (< 0 (mod (+ v_main_~z~0_7 (* v_it_2 4294967295)) 4294967296)))) (< 0 .cse0)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_6, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,212 INFO L290 TraceCheckUtils]: 9: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [86] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,213 INFO L290 TraceCheckUtils]: 10: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [89] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,214 INFO L290 TraceCheckUtils]: 11: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,215 INFO L290 TraceCheckUtils]: 12: Hoare triple {2112#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [93] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2159#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,216 INFO L290 TraceCheckUtils]: 13: Hoare triple {2159#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [92] L35-1-->L35-2: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2159#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:44:50,217 INFO L272 TraceCheckUtils]: 14: Hoare triple {2159#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (= main_~y~0 0))} [94] L35-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~n~0_3 4294967296) (mod v_main_~y~0_11 4294967296)) 1 0)) InVars {main_~y~0=v_main_~y~0_11, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0, main_~n~0] {2166#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:44:50,217 INFO L290 TraceCheckUtils]: 15: Hoare triple {2166#(<= 1 |__VERIFIER_assert_#in~cond|)} [96] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2170#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:44:50,217 INFO L290 TraceCheckUtils]: 16: Hoare triple {2170#(<= 1 __VERIFIER_assert_~cond)} [98] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2107#false} is VALID [2022-04-27 16:44:50,218 INFO L290 TraceCheckUtils]: 17: Hoare triple {2107#false} [100] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2107#false} is VALID [2022-04-27 16:44:50,218 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:44:50,218 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:44:54,823 WARN L833 $PredicateComparison]: unable to prove that (and (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~y~0_47_31 Int)) (or (< c_main_~n~0 (+ (* (div c_main_~n~0 4294967296) 4294967296) aux_mod_v_main_~y~0_47_31 1)) (< aux_mod_v_main_~y~0_47_31 0) (let ((.cse1 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (.cse0 (< 0 (mod c_main_~x~0 4294967296)))) (and (or .cse0 (not (= .cse1 c_main_~y~0))) (or (not (< c_main_~y~0 .cse1)) (not .cse0) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= (+ v_it_4 c_main_~y~0 1) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (<= 1 v_it_4)))))))) (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~y~0_47_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_47_31) (<= (+ (* (div c_main_~n~0 4294967296) 4294967296) aux_mod_v_main_~y~0_47_31) c_main_~n~0) (let ((.cse3 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (.cse2 (< 0 (mod c_main_~x~0 4294967296)))) (and (or .cse2 (not (= .cse3 c_main_~y~0))) (or (not (< c_main_~y~0 .cse3)) (not .cse2) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= (+ v_it_4 c_main_~y~0 1) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (<= 1 v_it_4))))))))) is different from false [2022-04-27 16:45:39,482 WARN L232 SmtUtils]: Spent 7.21s on a formula simplification that was a NOOP. DAG size: 85 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:46:06,845 WARN L232 SmtUtils]: Spent 12.22s on a formula simplification that was a NOOP. DAG size: 80 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate)