/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de51.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 16:41:40,563 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 16:41:40,564 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 16:41:40,599 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-27 16:41:40,610 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 16:41:40,611 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 16:41:40,612 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 16:41:40,614 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 16:41:40,614 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 16:41:40,615 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 16:41:40,616 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 16:41:40,620 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 16:41:40,621 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 16:41:40,622 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 16:41:40,622 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 16:41:40,623 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 16:41:40,624 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 16:41:40,628 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 16:41:40,633 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 16:41:40,634 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 16:41:40,635 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 16:41:40,635 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 16:41:40,643 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 16:41:40,643 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 16:41:40,644 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 16:41:40,644 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 16:41:40,644 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 16:41:40,644 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 16:41:40,644 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 16:41:40,644 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 16:41:40,644 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 16:41:40,645 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 16:41:40,645 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 16:41:40,645 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 16:41:40,645 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 16:41:40,645 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 16:41:40,645 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 16:41:40,645 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 16:41:40,646 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 16:41:40,646 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 16:41:40,646 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:41:40,646 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 16:41:40,646 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 16:41:40,647 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 16:41:40,647 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 16:41:40,806 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 16:41:40,820 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 16:41:40,822 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 16:41:40,822 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 16:41:40,823 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 16:41:40,824 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de51.c [2022-04-27 16:41:40,878 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c950fa0eb/55c9cdf0d5ed4df887377786b41c479a/FLAG530166353 [2022-04-27 16:41:41,224 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 16:41:41,224 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de51.c [2022-04-27 16:41:41,228 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c950fa0eb/55c9cdf0d5ed4df887377786b41c479a/FLAG530166353 [2022-04-27 16:41:41,235 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/c950fa0eb/55c9cdf0d5ed4df887377786b41c479a [2022-04-27 16:41:41,237 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 16:41:41,238 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 16:41:41,239 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 16:41:41,239 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 16:41:41,241 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 16:41:41,241 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,242 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@35c53648 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41, skipping insertion in model container [2022-04-27 16:41:41,242 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,246 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 16:41:41,253 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 16:41:41,341 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de51.c[368,381] [2022-04-27 16:41:41,351 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:41:41,356 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 16:41:41,365 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de51.c[368,381] [2022-04-27 16:41:41,368 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:41:41,382 INFO L208 MainTranslator]: Completed translation [2022-04-27 16:41:41,382 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41 WrapperNode [2022-04-27 16:41:41,382 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 16:41:41,383 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 16:41:41,383 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 16:41:41,383 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 16:41:41,390 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,390 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,396 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,396 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,408 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,414 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,418 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,419 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 16:41:41,419 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 16:41:41,419 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 16:41:41,419 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 16:41:41,421 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:41:41,433 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:41:41,444 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 16:41:41,460 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 16:41:41,474 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 16:41:41,474 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 16:41:41,474 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 16:41:41,474 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 16:41:41,474 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 16:41:41,475 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 16:41:41,515 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 16:41:41,516 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 16:41:41,663 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 16:41:41,667 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 16:41:41,667 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-04-27 16:41:41,668 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:41:41 BoogieIcfgContainer [2022-04-27 16:41:41,668 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 16:41:41,669 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 16:41:41,669 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 16:41:41,669 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 16:41:41,671 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:41:41" (1/1) ... [2022-04-27 16:41:41,672 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 16:41:42,051 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:41:42,052 INFO L91 elerationTransformer]: Accelerated Formula: (and (= (+ v_main_~x~0_3 1) v_main_~x~0_4) (= v_main_~y~0_5 (+ v_main_~y~0_6 1)) (< 0 (mod v_main_~x~0_4 4294967296))) InVars {main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_6} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-27 16:41:42,323 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:41:42,324 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_8 (+ v_main_~x~0_9 1)) (= v_main_~z~0_8 (+ v_main_~z~0_7 1)) (< 0 (mod v_main_~z~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_9, main_~z~0=v_main_~z~0_8} OutVars{main_~x~0=v_main_~x~0_8, main_~z~0=v_main_~z~0_7, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-27 16:41:42,549 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:41:42,549 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_4 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_4 (+ v_main_~y~0_3 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_3, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-27 16:41:42,751 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:41:42,751 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= (+ v_main_~y~0_8 1) v_main_~y~0_7)) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_8} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_7, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-27 16:41:43,000 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:41:43,001 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_10 (+ v_main_~z~0_9 1)) (< 0 (mod v_main_~z~0_10 4294967296)) (= v_main_~x~0_10 (+ v_main_~x~0_11 1))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] to Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] [2022-04-27 16:41:43,004 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:41:43 BasicIcfg [2022-04-27 16:41:43,004 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 16:41:43,005 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 16:41:43,005 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 16:41:43,007 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 16:41:43,007 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 04:41:41" (1/4) ... [2022-04-27 16:41:43,008 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@768848e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:41:43, skipping insertion in model container [2022-04-27 16:41:43,008 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:41:41" (2/4) ... [2022-04-27 16:41:43,008 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@768848e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:41:43, skipping insertion in model container [2022-04-27 16:41:43,008 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:41:41" (3/4) ... [2022-04-27 16:41:43,008 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@768848e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 04:41:43, skipping insertion in model container [2022-04-27 16:41:43,008 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:41:43" (4/4) ... [2022-04-27 16:41:43,009 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de51.cJordan [2022-04-27 16:41:43,018 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 16:41:43,018 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 16:41:43,048 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 16:41:43,052 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@73d12610, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@a5bc800 [2022-04-27 16:41:43,052 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 16:41:43,057 INFO L276 IsEmpty]: Start isEmpty. Operand has 24 states, 16 states have (on average 1.75) internal successors, (28), 17 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 16:41:43,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:41:43,061 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:41:43,061 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:41:43,061 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:41:43,064 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:41:43,064 INFO L85 PathProgramCache]: Analyzing trace with hash 702671213, now seen corresponding path program 1 times [2022-04-27 16:41:43,070 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:41:43,070 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1714029802] [2022-04-27 16:41:43,070 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:41:43,071 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:41:43,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,142 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:41:43,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,152 INFO L290 TraceCheckUtils]: 0: Hoare triple {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {27#true} is VALID [2022-04-27 16:41:43,153 INFO L290 TraceCheckUtils]: 1: Hoare triple {27#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:41:43,153 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {27#true} {27#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:41:43,154 INFO L272 TraceCheckUtils]: 0: Hoare triple {27#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:41:43,154 INFO L290 TraceCheckUtils]: 1: Hoare triple {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {27#true} is VALID [2022-04-27 16:41:43,154 INFO L290 TraceCheckUtils]: 2: Hoare triple {27#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:41:43,154 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {27#true} {27#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:41:43,155 INFO L272 TraceCheckUtils]: 4: Hoare triple {27#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:41:43,155 INFO L290 TraceCheckUtils]: 5: Hoare triple {27#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {27#true} is VALID [2022-04-27 16:41:43,155 INFO L290 TraceCheckUtils]: 6: Hoare triple {27#true} [92] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,156 INFO L290 TraceCheckUtils]: 7: Hoare triple {28#false} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {28#false} is VALID [2022-04-27 16:41:43,156 INFO L290 TraceCheckUtils]: 8: Hoare triple {28#false} [96] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,156 INFO L290 TraceCheckUtils]: 9: Hoare triple {28#false} [99] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,156 INFO L290 TraceCheckUtils]: 10: Hoare triple {28#false} [102] L35-1-->L41-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,156 INFO L290 TraceCheckUtils]: 11: Hoare triple {28#false} [105] L41-1-->L41-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,156 INFO L272 TraceCheckUtils]: 12: Hoare triple {28#false} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {28#false} is VALID [2022-04-27 16:41:43,157 INFO L290 TraceCheckUtils]: 13: Hoare triple {28#false} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {28#false} is VALID [2022-04-27 16:41:43,157 INFO L290 TraceCheckUtils]: 14: Hoare triple {28#false} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,157 INFO L290 TraceCheckUtils]: 15: Hoare triple {28#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:41:43,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:41:43,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:41:43,158 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1714029802] [2022-04-27 16:41:43,158 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1714029802] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:41:43,158 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:41:43,158 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 16:41:43,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107066164] [2022-04-27 16:41:43,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:41:43,162 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:41:43,163 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:41:43,166 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,182 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:41:43,182 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 16:41:43,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:41:43,207 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 16:41:43,208 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:41:43,210 INFO L87 Difference]: Start difference. First operand has 24 states, 16 states have (on average 1.75) internal successors, (28), 17 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:41:43,256 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2022-04-27 16:41:43,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 16:41:43,257 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:41:43,257 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:41:43,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-27 16:41:43,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-27 16:41:43,269 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 34 transitions. [2022-04-27 16:41:43,306 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:41:43,314 INFO L225 Difference]: With dead ends: 24 [2022-04-27 16:41:43,315 INFO L226 Difference]: Without dead ends: 17 [2022-04-27 16:41:43,316 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:41:43,318 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 19 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 30 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:41:43,318 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 30 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:41:43,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2022-04-27 16:41:43,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-04-27 16:41:43,333 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:41:43,334 INFO L82 GeneralOperation]: Start isEquivalent. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,334 INFO L74 IsIncluded]: Start isIncluded. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,334 INFO L87 Difference]: Start difference. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:41:43,336 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2022-04-27 16:41:43,336 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-27 16:41:43,336 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:41:43,336 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:41:43,337 INFO L74 IsIncluded]: Start isIncluded. First operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 17 states. [2022-04-27 16:41:43,337 INFO L87 Difference]: Start difference. First operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 17 states. [2022-04-27 16:41:43,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:41:43,338 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2022-04-27 16:41:43,338 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-27 16:41:43,339 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:41:43,339 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:41:43,339 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:41:43,339 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:41:43,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,341 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2022-04-27 16:41:43,342 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 21 transitions. Word has length 16 [2022-04-27 16:41:43,342 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:41:43,342 INFO L495 AbstractCegarLoop]: Abstraction has 17 states and 21 transitions. [2022-04-27 16:41:43,342 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,342 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-27 16:41:43,343 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:41:43,343 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:41:43,343 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:41:43,343 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 16:41:43,344 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:41:43,344 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:41:43,344 INFO L85 PathProgramCache]: Analyzing trace with hash -1128942900, now seen corresponding path program 1 times [2022-04-27 16:41:43,344 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:41:43,345 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50595669] [2022-04-27 16:41:43,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:41:43,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:41:43,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,491 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:41:43,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,506 INFO L290 TraceCheckUtils]: 0: Hoare triple {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-27 16:41:43,506 INFO L290 TraceCheckUtils]: 1: Hoare triple {110#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:41:43,506 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {110#true} {110#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:41:43,507 INFO L272 TraceCheckUtils]: 0: Hoare triple {110#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:41:43,507 INFO L290 TraceCheckUtils]: 1: Hoare triple {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-27 16:41:43,507 INFO L290 TraceCheckUtils]: 2: Hoare triple {110#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:41:43,508 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {110#true} {110#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:41:43,508 INFO L272 TraceCheckUtils]: 4: Hoare triple {110#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:41:43,508 INFO L290 TraceCheckUtils]: 5: Hoare triple {110#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,509 INFO L290 TraceCheckUtils]: 6: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,509 INFO L290 TraceCheckUtils]: 7: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,510 INFO L290 TraceCheckUtils]: 8: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,510 INFO L290 TraceCheckUtils]: 9: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,510 INFO L290 TraceCheckUtils]: 10: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,511 INFO L290 TraceCheckUtils]: 11: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:41:43,512 INFO L272 TraceCheckUtils]: 12: Hoare triple {115#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {116#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:41:43,512 INFO L290 TraceCheckUtils]: 13: Hoare triple {116#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {117#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:41:43,513 INFO L290 TraceCheckUtils]: 14: Hoare triple {117#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 16:41:43,513 INFO L290 TraceCheckUtils]: 15: Hoare triple {111#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 16:41:43,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:41:43,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:41:43,513 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50595669] [2022-04-27 16:41:43,513 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50595669] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:41:43,514 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:41:43,514 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 16:41:43,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [495074636] [2022-04-27 16:41:43,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:41:43,518 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:41:43,518 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:41:43,520 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,533 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:41:43,533 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 16:41:43,534 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:41:43,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 16:41:43,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-04-27 16:41:43,535 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. Second operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:41:43,638 INFO L93 Difference]: Finished difference Result 29 states and 40 transitions. [2022-04-27 16:41:43,638 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 16:41:43,639 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:41:43,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:41:43,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 41 transitions. [2022-04-27 16:41:43,648 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 41 transitions. [2022-04-27 16:41:43,652 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 41 transitions. [2022-04-27 16:41:43,687 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:41:43,688 INFO L225 Difference]: With dead ends: 29 [2022-04-27 16:41:43,688 INFO L226 Difference]: Without dead ends: 26 [2022-04-27 16:41:43,688 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2022-04-27 16:41:43,690 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 17 mSDsluCounter, 19 mSDsCounter, 0 mSdLazyCounter, 37 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 17 SdHoareTripleChecker+Valid, 33 SdHoareTripleChecker+Invalid, 51 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 37 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 7 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:41:43,690 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [17 Valid, 33 Invalid, 51 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 37 Invalid, 0 Unknown, 7 Unchecked, 0.0s Time] [2022-04-27 16:41:43,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-04-27 16:41:43,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 23. [2022-04-27 16:41:43,695 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:41:43,696 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand has 23 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,696 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand has 23 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,697 INFO L87 Difference]: Start difference. First operand 26 states. Second operand has 23 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:41:43,700 INFO L93 Difference]: Finished difference Result 26 states and 37 transitions. [2022-04-27 16:41:43,700 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 37 transitions. [2022-04-27 16:41:43,700 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:41:43,700 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:41:43,701 INFO L74 IsIncluded]: Start isIncluded. First operand has 23 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 26 states. [2022-04-27 16:41:43,701 INFO L87 Difference]: Start difference. First operand has 23 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 26 states. [2022-04-27 16:41:43,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:41:43,703 INFO L93 Difference]: Finished difference Result 26 states and 37 transitions. [2022-04-27 16:41:43,703 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 37 transitions. [2022-04-27 16:41:43,703 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:41:43,703 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:41:43,704 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:41:43,704 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:41:43,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 31 transitions. [2022-04-27 16:41:43,706 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 31 transitions. Word has length 16 [2022-04-27 16:41:43,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:41:43,706 INFO L495 AbstractCegarLoop]: Abstraction has 23 states and 31 transitions. [2022-04-27 16:41:43,707 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:41:43,707 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 31 transitions. [2022-04-27 16:41:43,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:41:43,707 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:41:43,707 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:41:43,708 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 16:41:43,708 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:41:43,708 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:41:43,708 INFO L85 PathProgramCache]: Analyzing trace with hash -610770875, now seen corresponding path program 1 times [2022-04-27 16:41:43,709 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:41:43,709 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1748955546] [2022-04-27 16:41:43,709 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:41:43,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:41:43,737 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:41:43,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,778 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:41:43,820 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:41:43,824 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,831 INFO L290 TraceCheckUtils]: 0: Hoare triple {240#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {231#true} is VALID [2022-04-27 16:41:43,831 INFO L290 TraceCheckUtils]: 1: Hoare triple {231#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:43,832 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {231#true} {231#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:43,832 INFO L272 TraceCheckUtils]: 0: Hoare triple {231#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {240#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:41:43,833 INFO L290 TraceCheckUtils]: 1: Hoare triple {240#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {231#true} is VALID [2022-04-27 16:41:43,833 INFO L290 TraceCheckUtils]: 2: Hoare triple {231#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:43,833 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {231#true} {231#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:43,834 INFO L272 TraceCheckUtils]: 4: Hoare triple {231#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:43,834 INFO L290 TraceCheckUtils]: 5: Hoare triple {231#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {236#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:41:43,836 INFO L290 TraceCheckUtils]: 6: Hoare triple {236#(= main_~n~0 main_~x~0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {236#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:41:43,836 INFO L290 TraceCheckUtils]: 7: Hoare triple {236#(= main_~n~0 main_~x~0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {236#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:41:43,842 INFO L290 TraceCheckUtils]: 8: Hoare triple {236#(= main_~n~0 main_~x~0)} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {237#(and (= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:41:43,843 INFO L290 TraceCheckUtils]: 9: Hoare triple {237#(and (= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {237#(and (= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:41:43,843 INFO L290 TraceCheckUtils]: 10: Hoare triple {237#(and (= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {237#(and (= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:41:43,845 INFO L290 TraceCheckUtils]: 11: Hoare triple {237#(and (= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {236#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:41:43,845 INFO L290 TraceCheckUtils]: 12: Hoare triple {236#(= main_~n~0 main_~x~0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {236#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:41:43,846 INFO L272 TraceCheckUtils]: 13: Hoare triple {236#(= main_~n~0 main_~x~0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {238#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:41:43,847 INFO L290 TraceCheckUtils]: 14: Hoare triple {238#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {239#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:41:43,848 INFO L290 TraceCheckUtils]: 15: Hoare triple {239#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {232#false} is VALID [2022-04-27 16:41:43,848 INFO L290 TraceCheckUtils]: 16: Hoare triple {232#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {232#false} is VALID [2022-04-27 16:41:43,849 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:41:43,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:41:43,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1748955546] [2022-04-27 16:41:43,849 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1748955546] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:41:43,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [206496789] [2022-04-27 16:41:43,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:41:43,850 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:41:43,850 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:41:43,856 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:41:43,860 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 16:41:43,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,894 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 16:41:43,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:41:43,920 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:41:44,201 INFO L272 TraceCheckUtils]: 0: Hoare triple {231#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:44,202 INFO L290 TraceCheckUtils]: 1: Hoare triple {231#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {231#true} is VALID [2022-04-27 16:41:44,202 INFO L290 TraceCheckUtils]: 2: Hoare triple {231#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:44,202 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {231#true} {231#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:44,202 INFO L272 TraceCheckUtils]: 4: Hoare triple {231#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:44,202 INFO L290 TraceCheckUtils]: 5: Hoare triple {231#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {236#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:41:44,203 INFO L290 TraceCheckUtils]: 6: Hoare triple {236#(= main_~n~0 main_~x~0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,203 INFO L290 TraceCheckUtils]: 7: Hoare triple {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,204 INFO L290 TraceCheckUtils]: 8: Hoare triple {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {269#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,204 INFO L290 TraceCheckUtils]: 9: Hoare triple {269#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {269#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,205 INFO L290 TraceCheckUtils]: 10: Hoare triple {269#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {269#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,206 INFO L290 TraceCheckUtils]: 11: Hoare triple {269#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,207 INFO L290 TraceCheckUtils]: 12: Hoare triple {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:41:44,207 INFO L272 TraceCheckUtils]: 13: Hoare triple {262#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {285#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:41:44,208 INFO L290 TraceCheckUtils]: 14: Hoare triple {285#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {289#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:41:44,208 INFO L290 TraceCheckUtils]: 15: Hoare triple {289#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {232#false} is VALID [2022-04-27 16:41:44,208 INFO L290 TraceCheckUtils]: 16: Hoare triple {232#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {232#false} is VALID [2022-04-27 16:41:44,208 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:41:44,208 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:41:46,856 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~z~0 4294967296))) (.cse0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (and (or (not (= .cse0 c_main_~x~0)) .cse1) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296))))) (not .cse1) (not (< c_main_~x~0 .cse0))))) (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (= aux_mod_v_main_~x~0_27_31 (mod c_main_~n~0 4294967296)))) is different from false [2022-04-27 16:41:48,289 INFO L290 TraceCheckUtils]: 16: Hoare triple {232#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {232#false} is VALID [2022-04-27 16:41:48,290 INFO L290 TraceCheckUtils]: 15: Hoare triple {289#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {232#false} is VALID [2022-04-27 16:41:48,290 INFO L290 TraceCheckUtils]: 14: Hoare triple {285#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {289#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:41:48,291 INFO L272 TraceCheckUtils]: 13: Hoare triple {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {285#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:41:48,291 INFO L290 TraceCheckUtils]: 12: Hoare triple {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:41:50,360 WARN L290 TraceCheckUtils]: 11: Hoare triple {312#(forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)) main_~x~0)))) (= aux_mod_v_main_~x~0_27_31 (mod main_~n~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is UNKNOWN [2022-04-27 16:41:52,405 WARN L290 TraceCheckUtils]: 10: Hoare triple {312#(forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)) main_~x~0)))) (= aux_mod_v_main_~x~0_27_31 (mod main_~n~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {312#(forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)) main_~x~0)))) (= aux_mod_v_main_~x~0_27_31 (mod main_~n~0 4294967296))))} is UNKNOWN [2022-04-27 16:41:54,465 WARN L290 TraceCheckUtils]: 9: Hoare triple {312#(forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)) main_~x~0)))) (= aux_mod_v_main_~x~0_27_31 (mod main_~n~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {312#(forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)) main_~x~0)))) (= aux_mod_v_main_~x~0_27_31 (mod main_~n~0 4294967296))))} is UNKNOWN [2022-04-27 16:41:54,479 INFO L290 TraceCheckUtils]: 8: Hoare triple {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {312#(forall ((aux_mod_v_main_~x~0_27_31 Int) (aux_div_v_main_~x~0_27_31 Int)) (or (> 0 aux_mod_v_main_~x~0_27_31) (>= aux_mod_v_main_~x~0_27_31 4294967296) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_27_31 (* aux_div_v_main_~x~0_27_31 4294967296)) main_~x~0)))) (= aux_mod_v_main_~x~0_27_31 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:41:54,480 INFO L290 TraceCheckUtils]: 7: Hoare triple {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:41:54,480 INFO L290 TraceCheckUtils]: 6: Hoare triple {328#(or (= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296)) (< 0 (mod main_~x~0 4294967296)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {305#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:41:54,481 INFO L290 TraceCheckUtils]: 5: Hoare triple {231#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {328#(or (= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296)) (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:41:54,481 INFO L272 TraceCheckUtils]: 4: Hoare triple {231#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:54,481 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {231#true} {231#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:54,481 INFO L290 TraceCheckUtils]: 2: Hoare triple {231#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:54,481 INFO L290 TraceCheckUtils]: 1: Hoare triple {231#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {231#true} is VALID [2022-04-27 16:41:54,482 INFO L272 TraceCheckUtils]: 0: Hoare triple {231#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#true} is VALID [2022-04-27 16:41:54,482 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-27 16:41:54,482 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [206496789] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:41:54,482 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:41:54,482 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 14 [2022-04-27 16:41:54,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1273443660] [2022-04-27 16:41:54,482 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:41:54,483 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:41:54,483 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:41:54,483 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:00,972 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 35 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:00,973 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:42:00,973 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:42:00,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:42:00,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=118, Unknown=1, NotChecked=22, Total=182 [2022-04-27 16:42:00,974 INFO L87 Difference]: Start difference. First operand 23 states and 31 transitions. Second operand has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:01,454 INFO L93 Difference]: Finished difference Result 34 states and 48 transitions. [2022-04-27 16:42:01,454 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-27 16:42:01,455 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:01,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:42:01,455 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 44 transitions. [2022-04-27 16:42:01,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 44 transitions. [2022-04-27 16:42:01,457 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 44 transitions. [2022-04-27 16:42:01,496 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:01,497 INFO L225 Difference]: With dead ends: 34 [2022-04-27 16:42:01,497 INFO L226 Difference]: Without dead ends: 31 [2022-04-27 16:42:01,497 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 27 SyntacticMatches, 4 SemanticMatches, 17 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=79, Invalid=230, Unknown=1, NotChecked=32, Total=342 [2022-04-27 16:42:01,498 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 19 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 60 SdHoareTripleChecker+Invalid, 107 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 20 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:42:01,498 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 60 Invalid, 107 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 76 Invalid, 0 Unknown, 20 Unchecked, 0.1s Time] [2022-04-27 16:42:01,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2022-04-27 16:42:01,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 26. [2022-04-27 16:42:01,500 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:42:01,501 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,501 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,501 INFO L87 Difference]: Start difference. First operand 31 states. Second operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:01,502 INFO L93 Difference]: Finished difference Result 31 states and 45 transitions. [2022-04-27 16:42:01,502 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 45 transitions. [2022-04-27 16:42:01,502 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:01,503 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:01,503 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 31 states. [2022-04-27 16:42:01,503 INFO L87 Difference]: Start difference. First operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 31 states. [2022-04-27 16:42:01,504 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:01,504 INFO L93 Difference]: Finished difference Result 31 states and 45 transitions. [2022-04-27 16:42:01,504 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 45 transitions. [2022-04-27 16:42:01,504 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:01,504 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:01,505 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:42:01,505 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:42:01,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 36 transitions. [2022-04-27 16:42:01,506 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 36 transitions. Word has length 17 [2022-04-27 16:42:01,506 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:42:01,506 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 36 transitions. [2022-04-27 16:42:01,506 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.2142857142857144) internal successors, (31), 11 states have internal predecessors, (31), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:01,506 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 36 transitions. [2022-04-27 16:42:01,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:42:01,506 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:42:01,506 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:42:01,525 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 16:42:01,722 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:01,722 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:42:01,723 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:42:01,723 INFO L85 PathProgramCache]: Analyzing trace with hash 162216202, now seen corresponding path program 1 times [2022-04-27 16:42:01,723 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:42:01,723 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143554134] [2022-04-27 16:42:01,723 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:01,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:42:01,741 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:42:01,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:01,755 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:42:01,933 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:42:01,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:01,938 INFO L290 TraceCheckUtils]: 0: Hoare triple {493#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:42:01,938 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:01,938 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:01,939 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {493#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:42:01,939 INFO L290 TraceCheckUtils]: 1: Hoare triple {493#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:42:01,939 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:01,939 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:01,939 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:01,940 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {487#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:42:01,940 INFO L290 TraceCheckUtils]: 6: Hoare triple {487#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:01,941 INFO L290 TraceCheckUtils]: 7: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:01,941 INFO L290 TraceCheckUtils]: 8: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:01,942 INFO L290 TraceCheckUtils]: 9: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:01,944 INFO L290 TraceCheckUtils]: 10: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {489#(and (<= (div main_~x~0 4294967296) (div main_~n~0 4294967296)) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:01,945 INFO L290 TraceCheckUtils]: 11: Hoare triple {489#(and (<= (div main_~x~0 4294967296) (div main_~n~0 4294967296)) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {490#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= (* 4294967296 (div main_~x~0 4294967296)) main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:01,945 INFO L290 TraceCheckUtils]: 12: Hoare triple {490#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= (* 4294967296 (div main_~x~0 4294967296)) main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {490#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= (* 4294967296 (div main_~x~0 4294967296)) main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:01,946 INFO L272 TraceCheckUtils]: 13: Hoare triple {490#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= (* 4294967296 (div main_~x~0 4294967296)) main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {491#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:42:01,947 INFO L290 TraceCheckUtils]: 14: Hoare triple {491#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {492#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:42:01,947 INFO L290 TraceCheckUtils]: 15: Hoare triple {492#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:42:01,947 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:42:01,948 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:42:01,948 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:42:01,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143554134] [2022-04-27 16:42:01,948 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143554134] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:42:01,948 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1081248699] [2022-04-27 16:42:01,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:01,948 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:01,948 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:42:01,969 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:42:01,970 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 16:42:01,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:02,000 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 16:42:02,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:02,008 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:42:02,374 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:02,374 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:42:02,375 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:02,375 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:02,375 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:42:02,375 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {487#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:42:02,376 INFO L290 TraceCheckUtils]: 6: Hoare triple {487#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,377 INFO L290 TraceCheckUtils]: 7: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,377 INFO L290 TraceCheckUtils]: 8: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,378 INFO L290 TraceCheckUtils]: 9: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,379 INFO L290 TraceCheckUtils]: 10: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,380 INFO L290 TraceCheckUtils]: 11: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,380 INFO L290 TraceCheckUtils]: 12: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:42:02,381 INFO L272 TraceCheckUtils]: 13: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {536#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:42:02,382 INFO L290 TraceCheckUtils]: 14: Hoare triple {536#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {540#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:42:02,382 INFO L290 TraceCheckUtils]: 15: Hoare triple {540#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:42:02,382 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:42:02,382 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:42:02,382 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 16:42:02,383 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1081248699] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:42:02,383 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 16:42:02,383 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [9] total 11 [2022-04-27 16:42:02,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1291043044] [2022-04-27 16:42:02,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:42:02,383 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:02,384 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:42:02,384 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,398 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:02,398 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 16:42:02,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:42:02,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 16:42:02,399 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2022-04-27 16:42:02,399 INFO L87 Difference]: Start difference. First operand 26 states and 36 transitions. Second operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:02,606 INFO L93 Difference]: Finished difference Result 32 states and 43 transitions. [2022-04-27 16:42:02,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 16:42:02,606 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:02,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:42:02,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 35 transitions. [2022-04-27 16:42:02,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 35 transitions. [2022-04-27 16:42:02,608 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 35 transitions. [2022-04-27 16:42:02,638 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:02,639 INFO L225 Difference]: With dead ends: 32 [2022-04-27 16:42:02,639 INFO L226 Difference]: Without dead ends: 29 [2022-04-27 16:42:02,639 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 13 SyntacticMatches, 4 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2022-04-27 16:42:02,640 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 8 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 21 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 8 SdHoareTripleChecker+Valid, 63 SdHoareTripleChecker+Invalid, 25 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 21 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 4 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:42:02,640 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [8 Valid, 63 Invalid, 25 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 21 Invalid, 0 Unknown, 4 Unchecked, 0.0s Time] [2022-04-27 16:42:02,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2022-04-27 16:42:02,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 26. [2022-04-27 16:42:02,642 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:42:02,642 INFO L82 GeneralOperation]: Start isEquivalent. First operand 29 states. Second operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,642 INFO L74 IsIncluded]: Start isIncluded. First operand 29 states. Second operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,642 INFO L87 Difference]: Start difference. First operand 29 states. Second operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:02,643 INFO L93 Difference]: Finished difference Result 29 states and 40 transitions. [2022-04-27 16:42:02,643 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 40 transitions. [2022-04-27 16:42:02,644 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:02,644 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:02,644 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 29 states. [2022-04-27 16:42:02,644 INFO L87 Difference]: Start difference. First operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 29 states. [2022-04-27 16:42:02,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:02,645 INFO L93 Difference]: Finished difference Result 29 states and 40 transitions. [2022-04-27 16:42:02,645 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 40 transitions. [2022-04-27 16:42:02,645 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:02,646 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:02,646 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:42:02,646 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:42:02,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 21 states have (on average 1.5238095238095237) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 36 transitions. [2022-04-27 16:42:02,647 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 36 transitions. Word has length 17 [2022-04-27 16:42:02,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:42:02,647 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 36 transitions. [2022-04-27 16:42:02,647 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:02,647 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 36 transitions. [2022-04-27 16:42:02,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:42:02,647 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:42:02,647 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:42:02,680 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 16:42:02,864 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 16:42:02,864 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:42:02,865 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:42:02,865 INFO L85 PathProgramCache]: Analyzing trace with hash -1833749398, now seen corresponding path program 1 times [2022-04-27 16:42:02,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:42:02,865 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [411241305] [2022-04-27 16:42:02,865 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:02,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:42:02,873 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:02,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:02,893 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:03,032 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:42:03,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:03,037 INFO L290 TraceCheckUtils]: 0: Hoare triple {675#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {664#true} is VALID [2022-04-27 16:42:03,037 INFO L290 TraceCheckUtils]: 1: Hoare triple {664#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,037 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {664#true} {664#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,038 INFO L272 TraceCheckUtils]: 0: Hoare triple {664#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {675#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:42:03,038 INFO L290 TraceCheckUtils]: 1: Hoare triple {675#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {664#true} is VALID [2022-04-27 16:42:03,038 INFO L290 TraceCheckUtils]: 2: Hoare triple {664#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,038 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {664#true} {664#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,038 INFO L272 TraceCheckUtils]: 4: Hoare triple {664#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,039 INFO L290 TraceCheckUtils]: 5: Hoare triple {664#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {669#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:42:03,039 INFO L290 TraceCheckUtils]: 6: Hoare triple {669#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {670#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:03,040 INFO L290 TraceCheckUtils]: 7: Hoare triple {670#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {670#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:03,041 INFO L290 TraceCheckUtils]: 8: Hoare triple {670#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {671#(< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 16:42:03,041 INFO L290 TraceCheckUtils]: 9: Hoare triple {671#(< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {671#(< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 16:42:03,042 INFO L290 TraceCheckUtils]: 10: Hoare triple {671#(< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {671#(< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 16:42:03,043 INFO L290 TraceCheckUtils]: 11: Hoare triple {671#(< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {672#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:03,043 INFO L290 TraceCheckUtils]: 12: Hoare triple {672#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {672#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:03,044 INFO L272 TraceCheckUtils]: 13: Hoare triple {672#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {673#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:42:03,044 INFO L290 TraceCheckUtils]: 14: Hoare triple {673#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {674#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:42:03,045 INFO L290 TraceCheckUtils]: 15: Hoare triple {674#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {665#false} is VALID [2022-04-27 16:42:03,045 INFO L290 TraceCheckUtils]: 16: Hoare triple {665#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {665#false} is VALID [2022-04-27 16:42:03,045 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:42:03,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:42:03,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [411241305] [2022-04-27 16:42:03,045 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [411241305] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:42:03,045 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [110236174] [2022-04-27 16:42:03,045 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:03,046 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:03,046 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:42:03,046 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:42:03,047 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 16:42:03,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:03,073 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 16:42:03,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:03,079 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:42:03,714 INFO L272 TraceCheckUtils]: 0: Hoare triple {664#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,715 INFO L290 TraceCheckUtils]: 1: Hoare triple {664#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {664#true} is VALID [2022-04-27 16:42:03,715 INFO L290 TraceCheckUtils]: 2: Hoare triple {664#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,715 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {664#true} {664#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,715 INFO L272 TraceCheckUtils]: 4: Hoare triple {664#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {664#true} is VALID [2022-04-27 16:42:03,715 INFO L290 TraceCheckUtils]: 5: Hoare triple {664#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {669#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:42:03,716 INFO L290 TraceCheckUtils]: 6: Hoare triple {669#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {697#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:42:03,717 INFO L290 TraceCheckUtils]: 7: Hoare triple {697#(not (< 0 (mod main_~n~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {697#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:42:03,717 INFO L290 TraceCheckUtils]: 8: Hoare triple {697#(not (< 0 (mod main_~n~0 4294967296)))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {697#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:42:03,717 INFO L290 TraceCheckUtils]: 9: Hoare triple {697#(not (< 0 (mod main_~n~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {697#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:42:03,718 INFO L290 TraceCheckUtils]: 10: Hoare triple {697#(not (< 0 (mod main_~n~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {697#(not (< 0 (mod main_~n~0 4294967296)))} is VALID [2022-04-27 16:42:03,718 INFO L290 TraceCheckUtils]: 11: Hoare triple {697#(not (< 0 (mod main_~n~0 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {713#(and (not (< 0 (mod main_~x~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:42:03,718 INFO L290 TraceCheckUtils]: 12: Hoare triple {713#(and (not (< 0 (mod main_~x~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {713#(and (not (< 0 (mod main_~x~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} is VALID [2022-04-27 16:42:03,719 INFO L272 TraceCheckUtils]: 13: Hoare triple {713#(and (not (< 0 (mod main_~x~0 4294967296))) (not (< 0 (mod main_~n~0 4294967296))))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {720#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:42:03,720 INFO L290 TraceCheckUtils]: 14: Hoare triple {720#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {724#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:42:03,720 INFO L290 TraceCheckUtils]: 15: Hoare triple {724#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {665#false} is VALID [2022-04-27 16:42:03,720 INFO L290 TraceCheckUtils]: 16: Hoare triple {665#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {665#false} is VALID [2022-04-27 16:42:03,720 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:42:03,720 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 16:42:03,721 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [110236174] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:42:03,721 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 16:42:03,721 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [9] total 13 [2022-04-27 16:42:03,721 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [870868695] [2022-04-27 16:42:03,721 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:42:03,721 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:03,721 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:42:03,721 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,734 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:03,734 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 7 states [2022-04-27 16:42:03,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:42:03,734 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2022-04-27 16:42:03,734 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=119, Unknown=0, NotChecked=0, Total=156 [2022-04-27 16:42:03,734 INFO L87 Difference]: Start difference. First operand 26 states and 36 transitions. Second operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:03,899 INFO L93 Difference]: Finished difference Result 35 states and 49 transitions. [2022-04-27 16:42:03,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-27 16:42:03,899 INFO L78 Accepts]: Start accepts. Automaton has has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:03,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:42:03,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 42 transitions. [2022-04-27 16:42:03,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 42 transitions. [2022-04-27 16:42:03,905 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 42 transitions. [2022-04-27 16:42:03,942 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 42 edges. 42 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:03,943 INFO L225 Difference]: With dead ends: 35 [2022-04-27 16:42:03,943 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:42:03,943 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 14 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2022-04-27 16:42:03,943 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 16 mSDsluCounter, 54 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 1 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 16 SdHoareTripleChecker+Valid, 68 SdHoareTripleChecker+Invalid, 25 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 1 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 4 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:42:03,944 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [16 Valid, 68 Invalid, 25 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [1 Valid, 20 Invalid, 0 Unknown, 4 Unchecked, 0.0s Time] [2022-04-27 16:42:03,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:42:03,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 29. [2022-04-27 16:42:03,945 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:42:03,945 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.5833333333333333) internal successors, (38), 24 states have internal predecessors, (38), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,945 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.5833333333333333) internal successors, (38), 24 states have internal predecessors, (38), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,946 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 29 states, 24 states have (on average 1.5833333333333333) internal successors, (38), 24 states have internal predecessors, (38), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:03,947 INFO L93 Difference]: Finished difference Result 32 states and 46 transitions. [2022-04-27 16:42:03,947 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 46 transitions. [2022-04-27 16:42:03,947 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:03,947 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:03,947 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 24 states have (on average 1.5833333333333333) internal successors, (38), 24 states have internal predecessors, (38), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:42:03,947 INFO L87 Difference]: Start difference. First operand has 29 states, 24 states have (on average 1.5833333333333333) internal successors, (38), 24 states have internal predecessors, (38), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:42:03,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:03,948 INFO L93 Difference]: Finished difference Result 32 states and 46 transitions. [2022-04-27 16:42:03,948 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 46 transitions. [2022-04-27 16:42:03,948 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:03,948 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:03,949 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:42:03,949 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:42:03,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 24 states have (on average 1.5833333333333333) internal successors, (38), 24 states have internal predecessors, (38), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,949 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 42 transitions. [2022-04-27 16:42:03,949 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 42 transitions. Word has length 17 [2022-04-27 16:42:03,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:42:03,950 INFO L495 AbstractCegarLoop]: Abstraction has 29 states and 42 transitions. [2022-04-27 16:42:03,950 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 7 states, 7 states have (on average 1.8571428571428572) internal successors, (13), 6 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:03,950 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 42 transitions. [2022-04-27 16:42:03,950 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:42:03,950 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:42:03,950 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:42:03,966 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 16:42:04,166 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:04,166 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:42:04,166 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:42:04,166 INFO L85 PathProgramCache]: Analyzing trace with hash -2110277654, now seen corresponding path program 1 times [2022-04-27 16:42:04,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:42:04,167 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [125894589] [2022-04-27 16:42:04,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:04,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:42:04,175 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.0))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:04,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:04,190 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_1.1))) (+ main_~x~0_5 .cse0 (* (- 4294967296) (div (+ main_~x~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:04,398 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:42:04,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:04,402 INFO L290 TraceCheckUtils]: 0: Hoare triple {872#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {861#true} is VALID [2022-04-27 16:42:04,403 INFO L290 TraceCheckUtils]: 1: Hoare triple {861#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:04,403 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {861#true} {861#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:04,403 INFO L272 TraceCheckUtils]: 0: Hoare triple {861#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {872#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:42:04,403 INFO L290 TraceCheckUtils]: 1: Hoare triple {872#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {861#true} is VALID [2022-04-27 16:42:04,403 INFO L290 TraceCheckUtils]: 2: Hoare triple {861#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:04,404 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {861#true} {861#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:04,404 INFO L272 TraceCheckUtils]: 4: Hoare triple {861#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:04,404 INFO L290 TraceCheckUtils]: 5: Hoare triple {861#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {866#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:42:04,413 INFO L290 TraceCheckUtils]: 6: Hoare triple {866#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [94] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {867#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:04,414 INFO L290 TraceCheckUtils]: 7: Hoare triple {867#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:42:04,414 INFO L290 TraceCheckUtils]: 8: Hoare triple {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:42:04,415 INFO L290 TraceCheckUtils]: 9: Hoare triple {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:42:04,415 INFO L290 TraceCheckUtils]: 10: Hoare triple {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:04,416 INFO L290 TraceCheckUtils]: 11: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:04,416 INFO L290 TraceCheckUtils]: 12: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:04,417 INFO L272 TraceCheckUtils]: 13: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {870#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:42:04,418 INFO L290 TraceCheckUtils]: 14: Hoare triple {870#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {871#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:42:04,418 INFO L290 TraceCheckUtils]: 15: Hoare triple {871#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {862#false} is VALID [2022-04-27 16:42:04,418 INFO L290 TraceCheckUtils]: 16: Hoare triple {862#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {862#false} is VALID [2022-04-27 16:42:04,418 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:42:04,419 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:42:04,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [125894589] [2022-04-27 16:42:04,419 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [125894589] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:42:04,419 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1933052295] [2022-04-27 16:42:04,419 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:04,419 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:04,419 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:42:04,420 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:42:04,421 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 16:42:04,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:04,460 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 16:42:04,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:04,472 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:42:05,800 INFO L272 TraceCheckUtils]: 0: Hoare triple {861#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:05,800 INFO L290 TraceCheckUtils]: 1: Hoare triple {861#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {861#true} is VALID [2022-04-27 16:42:05,801 INFO L290 TraceCheckUtils]: 2: Hoare triple {861#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:05,801 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {861#true} {861#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:05,801 INFO L272 TraceCheckUtils]: 4: Hoare triple {861#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:05,801 INFO L290 TraceCheckUtils]: 5: Hoare triple {861#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {866#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} is VALID [2022-04-27 16:42:05,811 INFO L290 TraceCheckUtils]: 6: Hoare triple {866#(and (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (= main_~y~0 0))} [94] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {894#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} is VALID [2022-04-27 16:42:05,812 INFO L290 TraceCheckUtils]: 7: Hoare triple {894#(or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (<= (mod main_~n~0 4294967296) 0) (= main_~y~0 0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {898#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} is VALID [2022-04-27 16:42:05,814 INFO L290 TraceCheckUtils]: 8: Hoare triple {898#(and (not (< 0 (mod main_~x~0 4294967296))) (or (and (= main_~x~0 (+ main_~n~0 (* (- 1) main_~y~0))) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~y~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (< 0 main_~y~0)) (and (= main_~n~0 main_~x~0) (= main_~y~0 0))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {902#(and (or (and (= main_~z~0 0) (= main_~n~0 main_~x~0)) (and (< 0 main_~z~0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~z~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (= (+ main_~n~0 (* (- 1) main_~z~0)) main_~x~0))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:05,820 INFO L290 TraceCheckUtils]: 9: Hoare triple {902#(and (or (and (= main_~z~0 0) (= main_~n~0 main_~x~0)) (and (< 0 main_~z~0) (forall ((v_it_1 Int)) (or (< 0 (mod (+ main_~n~0 (* v_it_1 4294967295)) 4294967296)) (not (<= (+ v_it_1 1) main_~z~0)) (not (<= 1 v_it_1)))) (< 0 (mod main_~n~0 4294967296)) (= (+ main_~n~0 (* (- 1) main_~z~0)) main_~x~0))) (not (< 0 (mod main_~x~0 4294967296))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:05,820 INFO L290 TraceCheckUtils]: 10: Hoare triple {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:05,820 INFO L290 TraceCheckUtils]: 11: Hoare triple {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:05,821 INFO L290 TraceCheckUtils]: 12: Hoare triple {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:05,822 INFO L272 TraceCheckUtils]: 13: Hoare triple {906#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {919#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:42:05,822 INFO L290 TraceCheckUtils]: 14: Hoare triple {919#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {923#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:42:05,825 INFO L290 TraceCheckUtils]: 15: Hoare triple {923#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {862#false} is VALID [2022-04-27 16:42:05,825 INFO L290 TraceCheckUtils]: 16: Hoare triple {862#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {862#false} is VALID [2022-04-27 16:42:05,826 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:42:05,826 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:42:09,974 INFO L290 TraceCheckUtils]: 16: Hoare triple {862#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {862#false} is VALID [2022-04-27 16:42:09,975 INFO L290 TraceCheckUtils]: 15: Hoare triple {923#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {862#false} is VALID [2022-04-27 16:42:09,975 INFO L290 TraceCheckUtils]: 14: Hoare triple {919#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {923#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:42:09,976 INFO L272 TraceCheckUtils]: 13: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {919#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:42:09,976 INFO L290 TraceCheckUtils]: 12: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:09,977 INFO L290 TraceCheckUtils]: 11: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:09,977 INFO L290 TraceCheckUtils]: 10: Hoare triple {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:09,978 INFO L290 TraceCheckUtils]: 9: Hoare triple {951#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (< 0 (mod main_~z~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {869#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:42:09,978 INFO L290 TraceCheckUtils]: 8: Hoare triple {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {951#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:42:09,980 INFO L290 TraceCheckUtils]: 7: Hoare triple {867#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {868#(or (and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1))) (<= (+ (* (div main_~y~0 4294967296) 4294967296) 1) main_~y~0))} is VALID [2022-04-27 16:42:12,000 WARN L290 TraceCheckUtils]: 6: Hoare triple {961#(forall ((aux_div_aux_mod_v_main_~x~0_31_31_87 Int) (aux_div_v_main_~x~0_31_31 Int) (aux_mod_aux_mod_v_main_~x~0_31_31_87 Int)) (or (>= aux_mod_aux_mod_v_main_~x~0_31_31_87 4294967296) (and (or (exists ((v_it_1 Int)) (and (<= (+ v_it_1 aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))) (forall ((aux_div_v_main_~y~0_22_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_22_31 4294967296) (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_v_main_~y~0_22_31 4294967296) (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296))))) (not (< 0 (mod main_~x~0 4294967296))) (not (< (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296)) main_~x~0))) (or (forall ((aux_div_v_main_~y~0_22_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_22_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_22_31 4294967296) 1) (+ main_~y~0 aux_mod_aux_mod_v_main_~x~0_31_31_87)))) (not (= main_~x~0 (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296)))))) (< (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296)) (* aux_div_v_main_~x~0_31_31 4294967296)) (< (+ main_~n~0 (* aux_div_v_main_~x~0_31_31 4294967296)) (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* (div main_~n~0 4294967296) 4294967296) (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296) 1)) (> 0 aux_mod_aux_mod_v_main_~x~0_31_31_87)))} [94] L16-2-->L16-2: Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] {867#(or (<= (+ (* (div main_~y~0 4294967296) 4294967296) (* 4294967296 (div main_~x~0 4294967296)) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is UNKNOWN [2022-04-27 16:42:12,010 INFO L290 TraceCheckUtils]: 5: Hoare triple {861#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {961#(forall ((aux_div_aux_mod_v_main_~x~0_31_31_87 Int) (aux_div_v_main_~x~0_31_31 Int) (aux_mod_aux_mod_v_main_~x~0_31_31_87 Int)) (or (>= aux_mod_aux_mod_v_main_~x~0_31_31_87 4294967296) (and (or (exists ((v_it_1 Int)) (and (<= (+ v_it_1 aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~x~0 (* v_it_1 4294967295)) 4294967296))) (<= 1 v_it_1))) (forall ((aux_div_v_main_~y~0_22_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_22_31 4294967296) (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296) 1) (+ main_~y~0 main_~x~0)) (< (+ main_~y~0 main_~x~0) (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_v_main_~y~0_22_31 4294967296) (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296))))) (not (< 0 (mod main_~x~0 4294967296))) (not (< (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296)) main_~x~0))) (or (forall ((aux_div_v_main_~y~0_22_31 Int)) (or (< main_~y~0 (* aux_div_v_main_~y~0_22_31 4294967296)) (<= (+ (* aux_div_v_main_~y~0_22_31 4294967296) 1) (+ main_~y~0 aux_mod_aux_mod_v_main_~x~0_31_31_87)))) (not (= main_~x~0 (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296)))))) (< (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296)) (* aux_div_v_main_~x~0_31_31 4294967296)) (< (+ main_~n~0 (* aux_div_v_main_~x~0_31_31 4294967296)) (+ aux_mod_aux_mod_v_main_~x~0_31_31_87 (* (div main_~n~0 4294967296) 4294967296) (* aux_div_aux_mod_v_main_~x~0_31_31_87 4294967296) 1)) (> 0 aux_mod_aux_mod_v_main_~x~0_31_31_87)))} is VALID [2022-04-27 16:42:12,010 INFO L272 TraceCheckUtils]: 4: Hoare triple {861#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:12,011 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {861#true} {861#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:12,011 INFO L290 TraceCheckUtils]: 2: Hoare triple {861#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:12,011 INFO L290 TraceCheckUtils]: 1: Hoare triple {861#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {861#true} is VALID [2022-04-27 16:42:12,011 INFO L272 TraceCheckUtils]: 0: Hoare triple {861#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {861#true} is VALID [2022-04-27 16:42:12,011 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:42:12,011 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1933052295] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:42:12,011 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:42:12,011 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 17 [2022-04-27 16:42:12,011 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979332239] [2022-04-27 16:42:12,012 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:42:12,012 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:12,012 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:42:12,012 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:14,143 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 34 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:14,143 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-27 16:42:14,143 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:42:14,144 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-27 16:42:14,144 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=216, Unknown=0, NotChecked=0, Total=272 [2022-04-27 16:42:14,144 INFO L87 Difference]: Start difference. First operand 29 states and 42 transitions. Second operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:15,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:15,349 INFO L93 Difference]: Finished difference Result 52 states and 80 transitions. [2022-04-27 16:42:15,349 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-04-27 16:42:15,350 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:42:15,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:42:15,350 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:15,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 60 transitions. [2022-04-27 16:42:15,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:15,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 60 transitions. [2022-04-27 16:42:15,353 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 15 states and 60 transitions. [2022-04-27 16:42:17,518 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 59 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-27 16:42:17,519 INFO L225 Difference]: With dead ends: 52 [2022-04-27 16:42:17,519 INFO L226 Difference]: Without dead ends: 48 [2022-04-27 16:42:17,520 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 23 SyntacticMatches, 6 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 160 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=146, Invalid=504, Unknown=0, NotChecked=0, Total=650 [2022-04-27 16:42:17,520 INFO L413 NwaCegarLoop]: 9 mSDtfsCounter, 59 mSDsluCounter, 37 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 59 SdHoareTripleChecker+Valid, 46 SdHoareTripleChecker+Invalid, 121 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 41 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:42:17,521 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [59 Valid, 46 Invalid, 121 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 68 Invalid, 0 Unknown, 41 Unchecked, 0.1s Time] [2022-04-27 16:42:17,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2022-04-27 16:42:17,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 34. [2022-04-27 16:42:17,522 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:42:17,523 INFO L82 GeneralOperation]: Start isEquivalent. First operand 48 states. Second operand has 34 states, 29 states have (on average 1.6206896551724137) internal successors, (47), 29 states have internal predecessors, (47), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:17,523 INFO L74 IsIncluded]: Start isIncluded. First operand 48 states. Second operand has 34 states, 29 states have (on average 1.6206896551724137) internal successors, (47), 29 states have internal predecessors, (47), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:17,523 INFO L87 Difference]: Start difference. First operand 48 states. Second operand has 34 states, 29 states have (on average 1.6206896551724137) internal successors, (47), 29 states have internal predecessors, (47), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:17,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:17,524 INFO L93 Difference]: Finished difference Result 48 states and 75 transitions. [2022-04-27 16:42:17,524 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 75 transitions. [2022-04-27 16:42:17,525 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:17,525 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:17,525 INFO L74 IsIncluded]: Start isIncluded. First operand has 34 states, 29 states have (on average 1.6206896551724137) internal successors, (47), 29 states have internal predecessors, (47), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 48 states. [2022-04-27 16:42:17,525 INFO L87 Difference]: Start difference. First operand has 34 states, 29 states have (on average 1.6206896551724137) internal successors, (47), 29 states have internal predecessors, (47), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 48 states. [2022-04-27 16:42:17,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:42:17,526 INFO L93 Difference]: Finished difference Result 48 states and 75 transitions. [2022-04-27 16:42:17,526 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 75 transitions. [2022-04-27 16:42:17,526 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:42:17,526 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:42:17,527 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:42:17,527 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:42:17,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 29 states have (on average 1.6206896551724137) internal successors, (47), 29 states have internal predecessors, (47), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:17,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 51 transitions. [2022-04-27 16:42:17,528 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 51 transitions. Word has length 17 [2022-04-27 16:42:17,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:42:17,528 INFO L495 AbstractCegarLoop]: Abstraction has 34 states and 51 transitions. [2022-04-27 16:42:17,528 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:42:17,528 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 51 transitions. [2022-04-27 16:42:17,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:42:17,528 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:42:17,528 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:42:17,562 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 16:42:17,729 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:17,729 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:42:17,729 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:42:17,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1727307284, now seen corresponding path program 2 times [2022-04-27 16:42:17,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:42:17,730 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332220899] [2022-04-27 16:42:17,730 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:42:17,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:42:17,774 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:17,775 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_11 .cse0 (* (- 4294967296) (div (+ main_~z~0_11 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:17,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:17,788 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:17,789 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_11 .cse0 (* (- 4294967296) (div (+ main_~z~0_11 .cse0) 4294967296)))) 0)) [2022-04-27 16:42:17,874 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:42:17,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:17,878 INFO L290 TraceCheckUtils]: 0: Hoare triple {1193#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1183#true} is VALID [2022-04-27 16:42:17,878 INFO L290 TraceCheckUtils]: 1: Hoare triple {1183#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:17,878 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1183#true} {1183#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:17,879 INFO L272 TraceCheckUtils]: 0: Hoare triple {1183#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1193#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:42:17,879 INFO L290 TraceCheckUtils]: 1: Hoare triple {1193#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1183#true} is VALID [2022-04-27 16:42:17,879 INFO L290 TraceCheckUtils]: 2: Hoare triple {1183#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:17,879 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1183#true} {1183#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:17,879 INFO L272 TraceCheckUtils]: 4: Hoare triple {1183#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:17,879 INFO L290 TraceCheckUtils]: 5: Hoare triple {1183#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1188#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:42:17,880 INFO L290 TraceCheckUtils]: 6: Hoare triple {1188#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1188#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:42:17,880 INFO L290 TraceCheckUtils]: 7: Hoare triple {1188#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} is VALID [2022-04-27 16:42:17,881 INFO L290 TraceCheckUtils]: 8: Hoare triple {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} is VALID [2022-04-27 16:42:17,881 INFO L290 TraceCheckUtils]: 9: Hoare triple {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} is VALID [2022-04-27 16:42:17,881 INFO L290 TraceCheckUtils]: 10: Hoare triple {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} is VALID [2022-04-27 16:42:17,882 INFO L290 TraceCheckUtils]: 11: Hoare triple {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} is VALID [2022-04-27 16:42:17,883 INFO L290 TraceCheckUtils]: 12: Hoare triple {1189#(and (= main_~z~0 0) (= main_~n~0 main_~x~0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1190#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:42:17,883 INFO L290 TraceCheckUtils]: 13: Hoare triple {1190#(= main_~n~0 main_~x~0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1190#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:42:17,884 INFO L272 TraceCheckUtils]: 14: Hoare triple {1190#(= main_~n~0 main_~x~0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1191#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:42:17,884 INFO L290 TraceCheckUtils]: 15: Hoare triple {1191#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1192#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:42:17,884 INFO L290 TraceCheckUtils]: 16: Hoare triple {1192#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1184#false} is VALID [2022-04-27 16:42:17,884 INFO L290 TraceCheckUtils]: 17: Hoare triple {1184#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1184#false} is VALID [2022-04-27 16:42:17,885 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:42:17,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:42:17,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332220899] [2022-04-27 16:42:17,885 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332220899] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:42:17,885 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1988680656] [2022-04-27 16:42:17,885 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:42:17,885 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:42:17,885 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:42:17,886 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:42:17,887 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 16:42:17,917 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:42:17,917 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:42:17,918 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-27 16:42:17,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:42:17,926 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:42:18,366 INFO L272 TraceCheckUtils]: 0: Hoare triple {1183#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:18,366 INFO L290 TraceCheckUtils]: 1: Hoare triple {1183#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1183#true} is VALID [2022-04-27 16:42:18,366 INFO L290 TraceCheckUtils]: 2: Hoare triple {1183#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:18,366 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1183#true} {1183#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:18,366 INFO L272 TraceCheckUtils]: 4: Hoare triple {1183#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:42:18,366 INFO L290 TraceCheckUtils]: 5: Hoare triple {1183#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1190#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:42:18,367 INFO L290 TraceCheckUtils]: 6: Hoare triple {1190#(= main_~n~0 main_~x~0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,367 INFO L290 TraceCheckUtils]: 7: Hoare triple {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,368 INFO L290 TraceCheckUtils]: 8: Hoare triple {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,368 INFO L290 TraceCheckUtils]: 9: Hoare triple {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,368 INFO L290 TraceCheckUtils]: 10: Hoare triple {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,370 INFO L290 TraceCheckUtils]: 11: Hoare triple {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,371 INFO L290 TraceCheckUtils]: 12: Hoare triple {1222#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,371 INFO L290 TraceCheckUtils]: 13: Hoare triple {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:42:18,372 INFO L272 TraceCheckUtils]: 14: Hoare triple {1215#(and (= main_~n~0 main_~x~0) (not (< 0 (mod main_~x~0 4294967296))))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1241#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:42:18,372 INFO L290 TraceCheckUtils]: 15: Hoare triple {1241#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1245#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:42:18,372 INFO L290 TraceCheckUtils]: 16: Hoare triple {1245#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1184#false} is VALID [2022-04-27 16:42:18,373 INFO L290 TraceCheckUtils]: 17: Hoare triple {1184#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1184#false} is VALID [2022-04-27 16:42:18,373 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:42:18,373 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:43:00,306 INFO L290 TraceCheckUtils]: 17: Hoare triple {1184#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1184#false} is VALID [2022-04-27 16:43:00,306 INFO L290 TraceCheckUtils]: 16: Hoare triple {1245#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1184#false} is VALID [2022-04-27 16:43:00,307 INFO L290 TraceCheckUtils]: 15: Hoare triple {1241#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1245#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:00,307 INFO L272 TraceCheckUtils]: 14: Hoare triple {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1241#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:00,307 INFO L290 TraceCheckUtils]: 13: Hoare triple {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:43:00,316 INFO L290 TraceCheckUtils]: 12: Hoare triple {1268#(forall ((aux_div_v_main_~x~0_35_31 Int) (aux_mod_v_main_~x~0_35_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))) (or (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))))) (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (> 0 aux_mod_v_main_~x~0_35_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:43:02,334 WARN L290 TraceCheckUtils]: 11: Hoare triple {1272#(forall ((aux_mod_v_main_~x~0_35_31 Int)) (or (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((v_main_~x~0_36 Int)) (or (not (< main_~x~0 v_main_~x~0_36)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_36))) (and (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (or (not (< v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ v_main_~x~0_36 v_it_5 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0 (* v_it_5 4294967295)) 4294967296))))))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296)))) (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))))) (> 0 aux_mod_v_main_~x~0_35_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1268#(forall ((aux_div_v_main_~x~0_35_31 Int) (aux_mod_v_main_~x~0_35_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))) (or (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))))) (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (> 0 aux_mod_v_main_~x~0_35_31)))} is UNKNOWN [2022-04-27 16:43:04,369 WARN L290 TraceCheckUtils]: 10: Hoare triple {1272#(forall ((aux_mod_v_main_~x~0_35_31 Int)) (or (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((v_main_~x~0_36 Int)) (or (not (< main_~x~0 v_main_~x~0_36)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_36))) (and (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (or (not (< v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ v_main_~x~0_36 v_it_5 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0 (* v_it_5 4294967295)) 4294967296))))))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296)))) (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))))) (> 0 aux_mod_v_main_~x~0_35_31)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1272#(forall ((aux_mod_v_main_~x~0_35_31 Int)) (or (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((v_main_~x~0_36 Int)) (or (not (< main_~x~0 v_main_~x~0_36)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_36))) (and (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (or (not (< v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ v_main_~x~0_36 v_it_5 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0 (* v_it_5 4294967295)) 4294967296))))))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296)))) (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))))) (> 0 aux_mod_v_main_~x~0_35_31)))} is UNKNOWN [2022-04-27 16:43:06,378 WARN L290 TraceCheckUtils]: 9: Hoare triple {1272#(forall ((aux_mod_v_main_~x~0_35_31 Int)) (or (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((v_main_~x~0_36 Int)) (or (not (< main_~x~0 v_main_~x~0_36)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_36))) (and (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (or (not (< v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ v_main_~x~0_36 v_it_5 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0 (* v_it_5 4294967295)) 4294967296))))))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296)))) (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))))) (> 0 aux_mod_v_main_~x~0_35_31)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1272#(forall ((aux_mod_v_main_~x~0_35_31 Int)) (or (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((v_main_~x~0_36 Int)) (or (not (< main_~x~0 v_main_~x~0_36)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_36))) (and (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (or (not (< v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ v_main_~x~0_36 v_it_5 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0 (* v_it_5 4294967295)) 4294967296))))))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296)))) (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))))) (> 0 aux_mod_v_main_~x~0_35_31)))} is UNKNOWN [2022-04-27 16:43:06,391 INFO L290 TraceCheckUtils]: 8: Hoare triple {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1272#(forall ((aux_mod_v_main_~x~0_35_31 Int)) (or (= aux_mod_v_main_~x~0_35_31 (mod main_~n~0 4294967296)) (>= aux_mod_v_main_~x~0_35_31 4294967296) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((v_main_~x~0_36 Int)) (or (not (< main_~x~0 v_main_~x~0_36)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_36))) (and (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (or (not (< v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ v_main_~x~0_36 v_it_5 1) (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0 (* v_it_5 4294967295)) 4294967296))))))) (not (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296)))) (or (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= v_main_~x~0_36 (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296))))) (< 0 (mod (+ (* v_main_~x~0_36 4294967295) main_~z~0 main_~x~0) 4294967296))))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_35_31 Int)) (not (= (+ aux_mod_v_main_~x~0_35_31 (* aux_div_v_main_~x~0_35_31 4294967296)) main_~x~0))))) (> 0 aux_mod_v_main_~x~0_35_31)))} is VALID [2022-04-27 16:43:06,391 INFO L290 TraceCheckUtils]: 7: Hoare triple {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:43:06,392 INFO L290 TraceCheckUtils]: 6: Hoare triple {1288#(or (= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296)) (< 0 (mod main_~x~0 4294967296)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1261#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:43:06,392 INFO L290 TraceCheckUtils]: 5: Hoare triple {1183#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1288#(or (= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296)) (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:06,392 INFO L272 TraceCheckUtils]: 4: Hoare triple {1183#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:43:06,392 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1183#true} {1183#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:43:06,393 INFO L290 TraceCheckUtils]: 2: Hoare triple {1183#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:43:06,393 INFO L290 TraceCheckUtils]: 1: Hoare triple {1183#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1183#true} is VALID [2022-04-27 16:43:06,393 INFO L272 TraceCheckUtils]: 0: Hoare triple {1183#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#true} is VALID [2022-04-27 16:43:06,393 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:06,393 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1988680656] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:43:06,393 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:43:06,393 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 8] total 16 [2022-04-27 16:43:06,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [874325217] [2022-04-27 16:43:06,393 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:43:06,394 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:43:06,394 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:43:06,394 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:14,542 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 42 edges. 38 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:14,542 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 16:43:14,542 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:43:14,543 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 16:43:14,543 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=176, Unknown=13, NotChecked=0, Total=240 [2022-04-27 16:43:14,543 INFO L87 Difference]: Start difference. First operand 34 states and 51 transitions. Second operand has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:19,104 INFO L93 Difference]: Finished difference Result 45 states and 68 transitions. [2022-04-27 16:43:19,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 16:43:19,105 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:43:19,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:43:19,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 44 transitions. [2022-04-27 16:43:19,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 44 transitions. [2022-04-27 16:43:19,107 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 44 transitions. [2022-04-27 16:43:19,147 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:19,148 INFO L225 Difference]: With dead ends: 45 [2022-04-27 16:43:19,148 INFO L226 Difference]: Without dead ends: 39 [2022-04-27 16:43:19,148 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 29 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 77 ImplicationChecksByTransitivity, 35.3s TimeCoverageRelationStatistics Valid=118, Invalid=373, Unknown=15, NotChecked=0, Total=506 [2022-04-27 16:43:19,149 INFO L413 NwaCegarLoop]: 10 mSDtfsCounter, 26 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 84 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 26 SdHoareTripleChecker+Valid, 59 SdHoareTripleChecker+Invalid, 134 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 84 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 39 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:43:19,149 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [26 Valid, 59 Invalid, 134 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 84 Invalid, 0 Unknown, 39 Unchecked, 0.1s Time] [2022-04-27 16:43:19,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2022-04-27 16:43:19,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 33. [2022-04-27 16:43:19,151 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:43:19,151 INFO L82 GeneralOperation]: Start isEquivalent. First operand 39 states. Second operand has 33 states, 28 states have (on average 1.6071428571428572) internal successors, (45), 28 states have internal predecessors, (45), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,151 INFO L74 IsIncluded]: Start isIncluded. First operand 39 states. Second operand has 33 states, 28 states have (on average 1.6071428571428572) internal successors, (45), 28 states have internal predecessors, (45), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,151 INFO L87 Difference]: Start difference. First operand 39 states. Second operand has 33 states, 28 states have (on average 1.6071428571428572) internal successors, (45), 28 states have internal predecessors, (45), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:19,152 INFO L93 Difference]: Finished difference Result 39 states and 61 transitions. [2022-04-27 16:43:19,152 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 61 transitions. [2022-04-27 16:43:19,152 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:19,152 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:19,152 INFO L74 IsIncluded]: Start isIncluded. First operand has 33 states, 28 states have (on average 1.6071428571428572) internal successors, (45), 28 states have internal predecessors, (45), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 39 states. [2022-04-27 16:43:19,153 INFO L87 Difference]: Start difference. First operand has 33 states, 28 states have (on average 1.6071428571428572) internal successors, (45), 28 states have internal predecessors, (45), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 39 states. [2022-04-27 16:43:19,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:19,154 INFO L93 Difference]: Finished difference Result 39 states and 61 transitions. [2022-04-27 16:43:19,154 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 61 transitions. [2022-04-27 16:43:19,154 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:19,154 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:19,154 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:43:19,154 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:43:19,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 28 states have (on average 1.6071428571428572) internal successors, (45), 28 states have internal predecessors, (45), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 49 transitions. [2022-04-27 16:43:19,155 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 49 transitions. Word has length 18 [2022-04-27 16:43:19,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:43:19,155 INFO L495 AbstractCegarLoop]: Abstraction has 33 states and 49 transitions. [2022-04-27 16:43:19,155 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.1875) internal successors, (35), 13 states have internal predecessors, (35), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:19,155 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 49 transitions. [2022-04-27 16:43:19,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:43:19,155 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:43:19,155 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:43:19,173 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 16:43:19,371 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:43:19,371 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:43:19,371 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:43:19,372 INFO L85 PathProgramCache]: Analyzing trace with hash 760455623, now seen corresponding path program 1 times [2022-04-27 16:43:19,372 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:43:19,372 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121948388] [2022-04-27 16:43:19,372 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:19,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:43:19,381 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:43:19,382 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:19,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:19,401 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:43:19,403 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:19,587 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:43:19,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:19,592 INFO L290 TraceCheckUtils]: 0: Hoare triple {1492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1480#true} is VALID [2022-04-27 16:43:19,592 INFO L290 TraceCheckUtils]: 1: Hoare triple {1480#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:19,592 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1480#true} {1480#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:19,592 INFO L272 TraceCheckUtils]: 0: Hoare triple {1480#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:43:19,592 INFO L290 TraceCheckUtils]: 1: Hoare triple {1492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1480#true} is VALID [2022-04-27 16:43:19,592 INFO L290 TraceCheckUtils]: 2: Hoare triple {1480#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:19,593 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1480#true} {1480#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:19,593 INFO L272 TraceCheckUtils]: 4: Hoare triple {1480#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:19,593 INFO L290 TraceCheckUtils]: 5: Hoare triple {1480#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1485#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:43:19,594 INFO L290 TraceCheckUtils]: 6: Hoare triple {1485#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:43:19,594 INFO L290 TraceCheckUtils]: 7: Hoare triple {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:43:19,595 INFO L290 TraceCheckUtils]: 8: Hoare triple {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:19,595 INFO L290 TraceCheckUtils]: 9: Hoare triple {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:19,597 INFO L290 TraceCheckUtils]: 10: Hoare triple {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1488#(and (<= main_~x~0 main_~n~0) (<= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:19,597 INFO L290 TraceCheckUtils]: 11: Hoare triple {1488#(and (<= main_~x~0 main_~n~0) (<= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1488#(and (<= main_~x~0 main_~n~0) (<= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:19,599 INFO L290 TraceCheckUtils]: 12: Hoare triple {1488#(and (<= main_~x~0 main_~n~0) (<= main_~n~0 main_~x~0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1489#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:43:19,599 INFO L290 TraceCheckUtils]: 13: Hoare triple {1489#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1489#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:43:19,600 INFO L272 TraceCheckUtils]: 14: Hoare triple {1489#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1490#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:43:19,601 INFO L290 TraceCheckUtils]: 15: Hoare triple {1490#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1491#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:43:19,601 INFO L290 TraceCheckUtils]: 16: Hoare triple {1491#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1481#false} is VALID [2022-04-27 16:43:19,601 INFO L290 TraceCheckUtils]: 17: Hoare triple {1481#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1481#false} is VALID [2022-04-27 16:43:19,601 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:19,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:43:19,601 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121948388] [2022-04-27 16:43:19,602 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121948388] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:43:19,602 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2146859818] [2022-04-27 16:43:19,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:19,602 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:43:19,602 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:43:19,603 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:43:19,608 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 16:43:19,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:19,642 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 10 conjunts are in the unsatisfiable core [2022-04-27 16:43:19,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:19,651 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:43:20,362 INFO L272 TraceCheckUtils]: 0: Hoare triple {1480#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:20,362 INFO L290 TraceCheckUtils]: 1: Hoare triple {1480#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1480#true} is VALID [2022-04-27 16:43:20,362 INFO L290 TraceCheckUtils]: 2: Hoare triple {1480#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:20,362 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1480#true} {1480#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:20,362 INFO L272 TraceCheckUtils]: 4: Hoare triple {1480#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:43:20,363 INFO L290 TraceCheckUtils]: 5: Hoare triple {1480#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1485#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:43:20,363 INFO L290 TraceCheckUtils]: 6: Hoare triple {1485#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:43:20,364 INFO L290 TraceCheckUtils]: 7: Hoare triple {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:43:20,365 INFO L290 TraceCheckUtils]: 8: Hoare triple {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:20,365 INFO L290 TraceCheckUtils]: 9: Hoare triple {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:20,367 INFO L290 TraceCheckUtils]: 10: Hoare triple {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:20,367 INFO L290 TraceCheckUtils]: 11: Hoare triple {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:43:20,369 INFO L290 TraceCheckUtils]: 12: Hoare triple {1487#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:43:20,369 INFO L290 TraceCheckUtils]: 13: Hoare triple {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} is VALID [2022-04-27 16:43:20,370 INFO L272 TraceCheckUtils]: 14: Hoare triple {1486#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= 0 (+ main_~x~0 (* (- 1) main_~n~0))))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1538#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:20,371 INFO L290 TraceCheckUtils]: 15: Hoare triple {1538#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1542#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:20,371 INFO L290 TraceCheckUtils]: 16: Hoare triple {1542#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1481#false} is VALID [2022-04-27 16:43:20,371 INFO L290 TraceCheckUtils]: 17: Hoare triple {1481#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1481#false} is VALID [2022-04-27 16:43:20,371 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:43:20,371 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:44:10,068 INFO L290 TraceCheckUtils]: 17: Hoare triple {1481#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1481#false} is VALID [2022-04-27 16:44:10,069 INFO L290 TraceCheckUtils]: 16: Hoare triple {1542#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1481#false} is VALID [2022-04-27 16:44:10,069 INFO L290 TraceCheckUtils]: 15: Hoare triple {1538#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1542#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:44:10,069 INFO L272 TraceCheckUtils]: 14: Hoare triple {1558#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1538#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:44:10,070 INFO L290 TraceCheckUtils]: 13: Hoare triple {1558#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1558#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:44:12,082 WARN L290 TraceCheckUtils]: 12: Hoare triple {1565#(forall ((aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (> 0 aux_mod_v_main_~x~0_40_31) (>= aux_mod_v_main_~x~0_40_31 4294967296) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1558#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is UNKNOWN [2022-04-27 16:44:12,085 INFO L290 TraceCheckUtils]: 11: Hoare triple {1569#(or (forall ((aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (> 0 aux_mod_v_main_~x~0_40_31) (>= aux_mod_v_main_~x~0_40_31 4294967296) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))))) (< 0 (mod main_~x~0 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1565#(forall ((aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (> 0 aux_mod_v_main_~x~0_40_31) (>= aux_mod_v_main_~x~0_40_31 4294967296) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296))))))} is VALID [2022-04-27 16:44:14,106 WARN L290 TraceCheckUtils]: 10: Hoare triple {1573#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (< aux_mod_v_main_~x~0_41_31 0) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (< 0 aux_mod_v_main_~x~0_41_31) (and (or (forall ((aux_div_v_main_~x~0_40_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_5 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_40_31 Int)) (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))))) (and (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_4 1) main_~x~0)))))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1569#(or (forall ((aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (> 0 aux_mod_v_main_~x~0_40_31) (>= aux_mod_v_main_~x~0_40_31 4294967296) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))))) (< 0 (mod main_~x~0 4294967296)))} is UNKNOWN [2022-04-27 16:44:16,138 WARN L290 TraceCheckUtils]: 9: Hoare triple {1573#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (< aux_mod_v_main_~x~0_41_31 0) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (< 0 aux_mod_v_main_~x~0_41_31) (and (or (forall ((aux_div_v_main_~x~0_40_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_5 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_40_31 Int)) (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))))) (and (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_4 1) main_~x~0)))))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1573#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (< aux_mod_v_main_~x~0_41_31 0) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (< 0 aux_mod_v_main_~x~0_41_31) (and (or (forall ((aux_div_v_main_~x~0_40_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_5 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_40_31 Int)) (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))))) (and (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_4 1) main_~x~0)))))))} is UNKNOWN [2022-04-27 16:44:18,147 WARN L290 TraceCheckUtils]: 8: Hoare triple {1580#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) (* aux_div_v_main_~x~0_41_31 4294967296)) (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (and (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296) v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)))) (< (* aux_div_v_main_~x~0_41_31 4294967296) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1573#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_41_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (< aux_mod_v_main_~x~0_41_31 0) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (< 0 aux_mod_v_main_~x~0_41_31) (and (or (forall ((aux_div_v_main_~x~0_40_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_5 1) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~x~0_40_31 Int)) (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296))))))) (and (not (= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (or (not (< (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ aux_mod_v_main_~x~0_41_31 (* aux_div_v_main_~x~0_41_31 4294967296) v_it_4 1) main_~x~0)))))))} is UNKNOWN [2022-04-27 16:44:18,337 INFO L290 TraceCheckUtils]: 7: Hoare triple {1580#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) (* aux_div_v_main_~x~0_41_31 4294967296)) (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (and (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296) v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)))) (< (* aux_div_v_main_~x~0_41_31 4294967296) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1580#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) (* aux_div_v_main_~x~0_41_31 4294967296)) (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (and (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296) v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)))) (< (* aux_div_v_main_~x~0_41_31 4294967296) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))))} is VALID [2022-04-27 16:44:18,340 INFO L290 TraceCheckUtils]: 6: Hoare triple {1587#(or (<= (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ (div (+ main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (< (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~x~0) 4294967296))))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1580#(forall ((aux_div_v_main_~x~0_41_31 Int) (aux_div_v_main_~x~0_40_31 Int) (aux_mod_v_main_~x~0_40_31 Int)) (or (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) (* aux_div_v_main_~x~0_41_31 4294967296)) (= aux_mod_v_main_~x~0_40_31 (mod main_~n~0 4294967296)) (<= 4294967296 aux_mod_v_main_~x~0_40_31) (< aux_mod_v_main_~x~0_40_31 0) (and (not (= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296) v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)) main_~x~0)))) (< (* aux_div_v_main_~x~0_41_31 4294967296) (+ aux_mod_v_main_~x~0_40_31 (* aux_div_v_main_~x~0_40_31 4294967296)))))} is VALID [2022-04-27 16:44:18,341 INFO L290 TraceCheckUtils]: 5: Hoare triple {1480#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1587#(or (<= (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ (div (+ main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (< (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~x~0) 4294967296))))} is VALID [2022-04-27 16:44:18,341 INFO L272 TraceCheckUtils]: 4: Hoare triple {1480#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:44:18,341 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1480#true} {1480#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:44:18,341 INFO L290 TraceCheckUtils]: 2: Hoare triple {1480#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:44:18,341 INFO L290 TraceCheckUtils]: 1: Hoare triple {1480#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1480#true} is VALID [2022-04-27 16:44:18,341 INFO L272 TraceCheckUtils]: 0: Hoare triple {1480#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1480#true} is VALID [2022-04-27 16:44:18,341 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:44:18,342 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2146859818] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:44:18,342 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:44:18,342 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 10] total 18 [2022-04-27 16:44:18,342 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1058901760] [2022-04-27 16:44:18,342 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:44:18,342 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:44:18,343 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:44:18,343 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:24,709 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 34 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:44:24,710 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-04-27 16:44:24,710 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:44:24,710 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-04-27 16:44:24,710 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=232, Unknown=10, NotChecked=0, Total=306 [2022-04-27 16:44:24,710 INFO L87 Difference]: Start difference. First operand 33 states and 49 transitions. Second operand has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:44:27,421 INFO L93 Difference]: Finished difference Result 45 states and 68 transitions. [2022-04-27 16:44:27,421 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 16:44:27,421 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:44:27,422 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:44:27,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,422 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 45 transitions. [2022-04-27 16:44:27,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 45 transitions. [2022-04-27 16:44:27,423 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 45 transitions. [2022-04-27 16:44:27,462 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:44:27,463 INFO L225 Difference]: With dead ends: 45 [2022-04-27 16:44:27,463 INFO L226 Difference]: Without dead ends: 42 [2022-04-27 16:44:27,463 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 23 SyntacticMatches, 7 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 126 ImplicationChecksByTransitivity, 23.8s TimeCoverageRelationStatistics Valid=110, Invalid=386, Unknown=10, NotChecked=0, Total=506 [2022-04-27 16:44:27,463 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 22 mSDsluCounter, 48 mSDsCounter, 0 mSdLazyCounter, 62 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 22 SdHoareTripleChecker+Valid, 63 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 62 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 35 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:44:27,464 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [22 Valid, 63 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 62 Invalid, 0 Unknown, 35 Unchecked, 0.1s Time] [2022-04-27 16:44:27,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2022-04-27 16:44:27,465 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 35. [2022-04-27 16:44:27,466 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:44:27,466 INFO L82 GeneralOperation]: Start isEquivalent. First operand 42 states. Second operand has 35 states, 30 states have (on average 1.6) internal successors, (48), 30 states have internal predecessors, (48), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,466 INFO L74 IsIncluded]: Start isIncluded. First operand 42 states. Second operand has 35 states, 30 states have (on average 1.6) internal successors, (48), 30 states have internal predecessors, (48), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,466 INFO L87 Difference]: Start difference. First operand 42 states. Second operand has 35 states, 30 states have (on average 1.6) internal successors, (48), 30 states have internal predecessors, (48), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:44:27,467 INFO L93 Difference]: Finished difference Result 42 states and 65 transitions. [2022-04-27 16:44:27,467 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 65 transitions. [2022-04-27 16:44:27,467 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:44:27,467 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:44:27,468 INFO L74 IsIncluded]: Start isIncluded. First operand has 35 states, 30 states have (on average 1.6) internal successors, (48), 30 states have internal predecessors, (48), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 42 states. [2022-04-27 16:44:27,468 INFO L87 Difference]: Start difference. First operand has 35 states, 30 states have (on average 1.6) internal successors, (48), 30 states have internal predecessors, (48), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 42 states. [2022-04-27 16:44:27,468 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:44:27,469 INFO L93 Difference]: Finished difference Result 42 states and 65 transitions. [2022-04-27 16:44:27,469 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 65 transitions. [2022-04-27 16:44:27,469 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:44:27,469 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:44:27,469 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:44:27,469 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:44:27,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35 states, 30 states have (on average 1.6) internal successors, (48), 30 states have internal predecessors, (48), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35 states to 35 states and 52 transitions. [2022-04-27 16:44:27,470 INFO L78 Accepts]: Start accepts. Automaton has 35 states and 52 transitions. Word has length 18 [2022-04-27 16:44:27,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:44:27,470 INFO L495 AbstractCegarLoop]: Abstraction has 35 states and 52 transitions. [2022-04-27 16:44:27,470 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 1.6666666666666667) internal successors, (30), 15 states have internal predecessors, (30), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:44:27,470 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 52 transitions. [2022-04-27 16:44:27,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:44:27,470 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:44:27,470 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:44:27,492 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-27 16:44:27,671 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:44:27,671 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:44:27,672 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:44:27,672 INFO L85 PathProgramCache]: Analyzing trace with hash 571694412, now seen corresponding path program 1 times [2022-04-27 16:44:27,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:44:27,672 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1286699225] [2022-04-27 16:44:27,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:44:27,672 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:44:27,684 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:44:27,685 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:44:27,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:27,701 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:44:27,714 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:44:27,881 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:44:27,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:27,885 INFO L290 TraceCheckUtils]: 0: Hoare triple {1793#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1782#true} is VALID [2022-04-27 16:44:27,885 INFO L290 TraceCheckUtils]: 1: Hoare triple {1782#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:27,885 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1782#true} {1782#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:27,885 INFO L272 TraceCheckUtils]: 0: Hoare triple {1782#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1793#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:44:27,885 INFO L290 TraceCheckUtils]: 1: Hoare triple {1793#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1782#true} is VALID [2022-04-27 16:44:27,885 INFO L290 TraceCheckUtils]: 2: Hoare triple {1782#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:27,886 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1782#true} {1782#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:27,886 INFO L272 TraceCheckUtils]: 4: Hoare triple {1782#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:27,886 INFO L290 TraceCheckUtils]: 5: Hoare triple {1782#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:27,886 INFO L290 TraceCheckUtils]: 6: Hoare triple {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:27,887 INFO L290 TraceCheckUtils]: 7: Hoare triple {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:27,887 INFO L290 TraceCheckUtils]: 8: Hoare triple {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:27,888 INFO L290 TraceCheckUtils]: 9: Hoare triple {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} is VALID [2022-04-27 16:44:27,888 INFO L290 TraceCheckUtils]: 10: Hoare triple {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} is VALID [2022-04-27 16:44:27,889 INFO L290 TraceCheckUtils]: 11: Hoare triple {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} is VALID [2022-04-27 16:44:27,891 INFO L290 TraceCheckUtils]: 12: Hoare triple {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1790#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:44:27,892 INFO L290 TraceCheckUtils]: 13: Hoare triple {1790#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1790#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:44:27,893 INFO L272 TraceCheckUtils]: 14: Hoare triple {1790#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (<= main_~x~0 main_~n~0) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1791#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:44:27,893 INFO L290 TraceCheckUtils]: 15: Hoare triple {1791#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1792#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:44:27,893 INFO L290 TraceCheckUtils]: 16: Hoare triple {1792#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1783#false} is VALID [2022-04-27 16:44:27,894 INFO L290 TraceCheckUtils]: 17: Hoare triple {1783#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1783#false} is VALID [2022-04-27 16:44:27,894 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:44:27,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:44:27,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1286699225] [2022-04-27 16:44:27,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1286699225] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:44:27,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1066098965] [2022-04-27 16:44:27,894 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:44:27,894 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:44:27,894 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:44:27,895 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:44:27,896 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 16:44:27,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:27,931 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 16:44:27,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:44:27,943 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:44:28,291 INFO L272 TraceCheckUtils]: 0: Hoare triple {1782#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:28,291 INFO L290 TraceCheckUtils]: 1: Hoare triple {1782#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1782#true} is VALID [2022-04-27 16:44:28,291 INFO L290 TraceCheckUtils]: 2: Hoare triple {1782#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:28,291 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1782#true} {1782#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:28,291 INFO L272 TraceCheckUtils]: 4: Hoare triple {1782#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:28,292 INFO L290 TraceCheckUtils]: 5: Hoare triple {1782#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:28,292 INFO L290 TraceCheckUtils]: 6: Hoare triple {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:28,292 INFO L290 TraceCheckUtils]: 7: Hoare triple {1787#(and (= main_~n~0 main_~x~0) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:28,293 INFO L290 TraceCheckUtils]: 8: Hoare triple {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} is VALID [2022-04-27 16:44:28,294 INFO L290 TraceCheckUtils]: 9: Hoare triple {1788#(and (= main_~z~0 0) (= main_~n~0 main_~x~0) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} is VALID [2022-04-27 16:44:28,294 INFO L290 TraceCheckUtils]: 10: Hoare triple {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} is VALID [2022-04-27 16:44:28,294 INFO L290 TraceCheckUtils]: 11: Hoare triple {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} is VALID [2022-04-27 16:44:28,296 INFO L290 TraceCheckUtils]: 12: Hoare triple {1789#(and (<= main_~z~0 0) (= main_~n~0 main_~x~0) (<= 0 main_~z~0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1833#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:44:28,296 INFO L290 TraceCheckUtils]: 13: Hoare triple {1833#(= main_~n~0 main_~x~0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1833#(= main_~n~0 main_~x~0)} is VALID [2022-04-27 16:44:28,296 INFO L272 TraceCheckUtils]: 14: Hoare triple {1833#(= main_~n~0 main_~x~0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1840#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:44:28,297 INFO L290 TraceCheckUtils]: 15: Hoare triple {1840#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1844#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:44:28,297 INFO L290 TraceCheckUtils]: 16: Hoare triple {1844#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1783#false} is VALID [2022-04-27 16:44:28,297 INFO L290 TraceCheckUtils]: 17: Hoare triple {1783#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1783#false} is VALID [2022-04-27 16:44:28,297 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:44:28,297 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:44:30,979 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod c_main_~n~0 4294967296)) (let ((.cse1 (< 0 (mod c_main_~z~0 4294967296))) (.cse0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (and (or (not (= .cse0 c_main_~x~0)) .cse1) (or (not .cse1) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) (not (< c_main_~x~0 .cse0))))))) is different from false [2022-04-27 16:44:45,079 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_44_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_39_31 Int) (aux_mod_v_main_~z~0_39_31 Int)) (or (let ((.cse1 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse0 (not (= .cse1 c_main_~z~0))) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3))) (not (< c_main_~z~0 .cse1)) (not .cse0)))) (< aux_mod_v_main_~z~0_39_31 0) (< 0 aux_mod_v_main_~z~0_39_31))) (forall ((aux_div_v_main_~x~0_44_31 Int)) (not (= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) c_main_~x~0)))) (forall ((aux_mod_v_main_~z~0_39_31 Int) (aux_div_v_main_~z~0_39_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_39_31 (* v_it_5 4294967295)) 4294967296))))) (let ((.cse3 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (.cse2 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse2 (not (= .cse3 c_main_~z~0))) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3))) (not (< c_main_~z~0 .cse3)) (not .cse2)))) (<= aux_mod_v_main_~z~0_39_31 0) (<= 4294967296 aux_mod_v_main_~z~0_39_31) (<= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) c_main_~x~0)))) (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod c_main_~n~0 4294967296)))) is different from false [2022-04-27 16:44:50,559 WARN L855 $PredicateComparison]: unable to prove that (or (< 0 (mod c_main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod c_main_~n~0 4294967296)) (and (or (forall ((aux_div_v_main_~z~0_39_31 Int) (aux_mod_v_main_~z~0_39_31 Int)) (or (let ((.cse1 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse0 (not (= .cse1 c_main_~z~0))) (or (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3))) (not (< c_main_~z~0 .cse1)) (not .cse0)))) (< aux_mod_v_main_~z~0_39_31 0) (< 0 aux_mod_v_main_~z~0_39_31))) (forall ((aux_div_v_main_~x~0_44_31 Int)) (not (= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) c_main_~x~0)))) (or (not (< 0 (mod c_main_~y~0 4294967296))) (forall ((aux_mod_v_main_~z~0_39_31 Int) (aux_div_v_main_~z~0_39_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_39_31 (* v_it_5 4294967295)) 4294967296))))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3))) (not (< c_main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (<= aux_mod_v_main_~z~0_39_31 0) (<= 4294967296 aux_mod_v_main_~z~0_39_31) (<= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) c_main_~x~0)))))))) is different from true [2022-04-27 16:44:51,131 INFO L290 TraceCheckUtils]: 17: Hoare triple {1783#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1783#false} is VALID [2022-04-27 16:44:51,132 INFO L290 TraceCheckUtils]: 16: Hoare triple {1844#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1783#false} is VALID [2022-04-27 16:44:51,132 INFO L290 TraceCheckUtils]: 15: Hoare triple {1840#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1844#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:44:51,133 INFO L272 TraceCheckUtils]: 14: Hoare triple {1860#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {1840#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:44:51,133 INFO L290 TraceCheckUtils]: 13: Hoare triple {1860#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1860#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is VALID [2022-04-27 16:44:53,198 WARN L290 TraceCheckUtils]: 12: Hoare triple {1867#(forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (< 0 (mod main_~z~0 4294967296))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1860#(= (mod main_~n~0 4294967296) (mod main_~x~0 4294967296))} is UNKNOWN [2022-04-27 16:44:53,200 INFO L290 TraceCheckUtils]: 11: Hoare triple {1867#(forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (< 0 (mod main_~z~0 4294967296))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1867#(forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (< 0 (mod main_~z~0 4294967296))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))))))} is VALID [2022-04-27 16:44:53,200 INFO L290 TraceCheckUtils]: 10: Hoare triple {1867#(forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (< 0 (mod main_~z~0 4294967296))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1867#(forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (< 0 (mod main_~z~0 4294967296))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))))))} is VALID [2022-04-27 16:44:55,233 WARN L290 TraceCheckUtils]: 9: Hoare triple {1877#(forall ((aux_mod_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (forall ((aux_mod_v_main_~z~0_39_31 Int) (aux_div_v_main_~z~0_39_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_39_31 (* v_it_5 4294967295)) 4294967296))))) (<= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) main_~x~0) (and (or (not (= (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (<= aux_mod_v_main_~z~0_39_31 0) (<= 4294967296 aux_mod_v_main_~z~0_39_31))) (or (forall ((aux_div_v_main_~z~0_39_31 Int) (aux_mod_v_main_~z~0_39_31 Int)) (or (< aux_mod_v_main_~z~0_39_31 0) (< 0 aux_mod_v_main_~z~0_39_31) (and (or (not (= (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (forall ((aux_div_v_main_~x~0_44_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))))))))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1867#(forall ((aux_mod_v_main_~x~0_44_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (< 0 (mod main_~z~0 4294967296))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))))))} is UNKNOWN [2022-04-27 16:44:57,395 WARN L290 TraceCheckUtils]: 8: Hoare triple {1881#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_44_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_39_31 Int) (aux_mod_v_main_~z~0_39_31 Int)) (or (< aux_mod_v_main_~z~0_39_31 0) (< 0 aux_mod_v_main_~z~0_39_31) (and (or (not (= (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (forall ((aux_div_v_main_~x~0_44_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_mod_v_main_~z~0_39_31 Int) (aux_div_v_main_~z~0_39_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_39_31 (* v_it_5 4294967295)) 4294967296))))) (<= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) main_~x~0) (<= aux_mod_v_main_~z~0_39_31 0) (<= 4294967296 aux_mod_v_main_~z~0_39_31) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1877#(forall ((aux_mod_v_main_~x~0_44_31 Int)) (or (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)) (and (forall ((aux_mod_v_main_~z~0_39_31 Int) (aux_div_v_main_~z~0_39_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_39_31 (* v_it_5 4294967295)) 4294967296))))) (<= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) main_~x~0) (and (or (not (= (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (<= aux_mod_v_main_~z~0_39_31 0) (<= 4294967296 aux_mod_v_main_~z~0_39_31))) (or (forall ((aux_div_v_main_~z~0_39_31 Int) (aux_mod_v_main_~z~0_39_31 Int)) (or (< aux_mod_v_main_~z~0_39_31 0) (< 0 aux_mod_v_main_~z~0_39_31) (and (or (not (= (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (forall ((aux_div_v_main_~x~0_44_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))))))))} is UNKNOWN [2022-04-27 16:44:57,440 INFO L290 TraceCheckUtils]: 7: Hoare triple {1885#(or (and (<= (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ (div (+ main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (<= (div (+ (- 1) main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) (div (+ main_~x~0 (- 4294967296)) 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1881#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_44_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_39_31 Int) (aux_mod_v_main_~z~0_39_31 Int)) (or (< aux_mod_v_main_~z~0_39_31 0) (< 0 aux_mod_v_main_~z~0_39_31) (and (or (not (= (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (forall ((aux_div_v_main_~x~0_44_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)))))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_mod_v_main_~z~0_39_31 Int) (aux_div_v_main_~z~0_39_31 Int) (aux_div_v_main_~x~0_44_31 Int)) (or (not (< main_~z~0 (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296))) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_39_31 (* v_it_5 4294967295)) 4294967296))))) (<= (+ aux_mod_v_main_~x~0_44_31 (* aux_div_v_main_~x~0_44_31 4294967296)) main_~x~0) (<= aux_mod_v_main_~z~0_39_31 0) (<= 4294967296 aux_mod_v_main_~z~0_39_31) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_39_31) aux_mod_v_main_~z~0_39_31)) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (>= aux_mod_v_main_~x~0_44_31 4294967296) (> 0 aux_mod_v_main_~x~0_44_31) (= aux_mod_v_main_~x~0_44_31 (mod main_~n~0 4294967296)))))} is VALID [2022-04-27 16:44:57,442 INFO L290 TraceCheckUtils]: 6: Hoare triple {1885#(or (and (<= (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ (div (+ main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (<= (div (+ (- 1) main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) (div (+ main_~x~0 (- 4294967296)) 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1885#(or (and (<= (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ (div (+ main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (<= (div (+ (- 1) main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) (div (+ main_~x~0 (- 4294967296)) 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:44:57,445 INFO L290 TraceCheckUtils]: 5: Hoare triple {1782#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1885#(or (and (<= (div (+ (- 1) (* (- 1) main_~x~0)) (- 4294967296)) (+ (div (+ main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) 1)) (<= (div (+ (- 1) main_~x~0 (* (- 1) (mod main_~n~0 4294967296))) 4294967296) (div (+ main_~x~0 (- 4294967296)) 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:44:57,445 INFO L272 TraceCheckUtils]: 4: Hoare triple {1782#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:57,445 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1782#true} {1782#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:57,445 INFO L290 TraceCheckUtils]: 2: Hoare triple {1782#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:57,445 INFO L290 TraceCheckUtils]: 1: Hoare triple {1782#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1782#true} is VALID [2022-04-27 16:44:57,445 INFO L272 TraceCheckUtils]: 0: Hoare triple {1782#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1782#true} is VALID [2022-04-27 16:44:57,445 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 2 not checked. [2022-04-27 16:44:57,445 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1066098965] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:44:57,446 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:44:57,446 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 9] total 17 [2022-04-27 16:44:57,446 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224381809] [2022-04-27 16:44:57,446 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:44:57,446 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:44:57,446 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:44:57,447 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:08,024 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 30 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:08,024 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-27 16:45:08,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:45:08,024 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-27 16:45:08,024 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=138, Unknown=3, NotChecked=78, Total=272 [2022-04-27 16:45:08,025 INFO L87 Difference]: Start difference. First operand 35 states and 52 transitions. Second operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:10,105 INFO L93 Difference]: Finished difference Result 47 states and 71 transitions. [2022-04-27 16:45:10,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 16:45:10,105 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:10,105 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:45:10,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 45 transitions. [2022-04-27 16:45:10,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 45 transitions. [2022-04-27 16:45:10,107 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 45 transitions. [2022-04-27 16:45:10,172 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:10,172 INFO L225 Difference]: With dead ends: 47 [2022-04-27 16:45:10,172 INFO L226 Difference]: Without dead ends: 44 [2022-04-27 16:45:10,173 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 29 SyntacticMatches, 5 SemanticMatches, 21 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 7.5s TimeCoverageRelationStatistics Valid=104, Invalid=285, Unknown=3, NotChecked=114, Total=506 [2022-04-27 16:45:10,173 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 28 mSDsluCounter, 52 mSDsCounter, 0 mSdLazyCounter, 87 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 64 SdHoareTripleChecker+Invalid, 160 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 87 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 62 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-04-27 16:45:10,173 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 64 Invalid, 160 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 87 Invalid, 0 Unknown, 62 Unchecked, 0.4s Time] [2022-04-27 16:45:10,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2022-04-27 16:45:10,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 37. [2022-04-27 16:45:10,175 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:45:10,175 INFO L82 GeneralOperation]: Start isEquivalent. First operand 44 states. Second operand has 37 states, 32 states have (on average 1.625) internal successors, (52), 32 states have internal predecessors, (52), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,175 INFO L74 IsIncluded]: Start isIncluded. First operand 44 states. Second operand has 37 states, 32 states have (on average 1.625) internal successors, (52), 32 states have internal predecessors, (52), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,175 INFO L87 Difference]: Start difference. First operand 44 states. Second operand has 37 states, 32 states have (on average 1.625) internal successors, (52), 32 states have internal predecessors, (52), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:10,176 INFO L93 Difference]: Finished difference Result 44 states and 68 transitions. [2022-04-27 16:45:10,176 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 68 transitions. [2022-04-27 16:45:10,176 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:10,176 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:10,177 INFO L74 IsIncluded]: Start isIncluded. First operand has 37 states, 32 states have (on average 1.625) internal successors, (52), 32 states have internal predecessors, (52), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 44 states. [2022-04-27 16:45:10,177 INFO L87 Difference]: Start difference. First operand has 37 states, 32 states have (on average 1.625) internal successors, (52), 32 states have internal predecessors, (52), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 44 states. [2022-04-27 16:45:10,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:10,178 INFO L93 Difference]: Finished difference Result 44 states and 68 transitions. [2022-04-27 16:45:10,178 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 68 transitions. [2022-04-27 16:45:10,178 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:10,178 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:10,178 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:45:10,178 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:45:10,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 32 states have (on average 1.625) internal successors, (52), 32 states have internal predecessors, (52), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 56 transitions. [2022-04-27 16:45:10,179 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 56 transitions. Word has length 18 [2022-04-27 16:45:10,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:45:10,179 INFO L495 AbstractCegarLoop]: Abstraction has 37 states and 56 transitions. [2022-04-27 16:45:10,179 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:10,179 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 56 transitions. [2022-04-27 16:45:10,179 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:45:10,179 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:10,179 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:10,198 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2022-04-27 16:45:10,385 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:10,386 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:10,386 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:10,386 INFO L85 PathProgramCache]: Analyzing trace with hash -984935833, now seen corresponding path program 1 times [2022-04-27 16:45:10,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:10,386 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1888162679] [2022-04-27 16:45:10,386 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:10,387 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:10,398 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:10,400 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:10,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:10,411 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:10,414 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:11,086 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:11,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:11,093 INFO L290 TraceCheckUtils]: 0: Hoare triple {2110#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2097#true} is VALID [2022-04-27 16:45:11,093 INFO L290 TraceCheckUtils]: 1: Hoare triple {2097#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:11,094 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2097#true} {2097#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:11,094 INFO L272 TraceCheckUtils]: 0: Hoare triple {2097#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2110#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:11,094 INFO L290 TraceCheckUtils]: 1: Hoare triple {2110#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2097#true} is VALID [2022-04-27 16:45:11,094 INFO L290 TraceCheckUtils]: 2: Hoare triple {2097#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:11,095 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2097#true} {2097#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:11,095 INFO L272 TraceCheckUtils]: 4: Hoare triple {2097#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:11,095 INFO L290 TraceCheckUtils]: 5: Hoare triple {2097#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2102#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:45:11,096 INFO L290 TraceCheckUtils]: 6: Hoare triple {2102#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2103#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:11,097 INFO L290 TraceCheckUtils]: 7: Hoare triple {2103#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2103#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:11,097 INFO L290 TraceCheckUtils]: 8: Hoare triple {2103#(and (= main_~n~0 main_~x~0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:45:11,098 INFO L290 TraceCheckUtils]: 9: Hoare triple {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:11,099 INFO L290 TraceCheckUtils]: 10: Hoare triple {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:11,100 INFO L290 TraceCheckUtils]: 11: Hoare triple {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2106#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:11,103 INFO L290 TraceCheckUtils]: 12: Hoare triple {2106#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:45:11,104 INFO L290 TraceCheckUtils]: 13: Hoare triple {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:45:11,105 INFO L272 TraceCheckUtils]: 14: Hoare triple {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {2108#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:45:11,105 INFO L290 TraceCheckUtils]: 15: Hoare triple {2108#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2109#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:45:11,106 INFO L290 TraceCheckUtils]: 16: Hoare triple {2109#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2098#false} is VALID [2022-04-27 16:45:11,106 INFO L290 TraceCheckUtils]: 17: Hoare triple {2098#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2098#false} is VALID [2022-04-27 16:45:11,106 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:11,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:11,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1888162679] [2022-04-27 16:45:11,106 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1888162679] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:45:11,106 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [275450359] [2022-04-27 16:45:11,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:11,106 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:11,106 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:45:11,107 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:45:11,119 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 16:45:11,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:11,149 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-27 16:45:11,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:11,157 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:45:14,150 INFO L272 TraceCheckUtils]: 0: Hoare triple {2097#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:14,151 INFO L290 TraceCheckUtils]: 1: Hoare triple {2097#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2097#true} is VALID [2022-04-27 16:45:14,151 INFO L290 TraceCheckUtils]: 2: Hoare triple {2097#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:14,151 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2097#true} {2097#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:14,151 INFO L272 TraceCheckUtils]: 4: Hoare triple {2097#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2097#true} is VALID [2022-04-27 16:45:14,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {2097#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2102#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} is VALID [2022-04-27 16:45:14,153 INFO L290 TraceCheckUtils]: 6: Hoare triple {2102#(= 0 (+ main_~x~0 (* (- 1) main_~n~0)))} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:45:14,153 INFO L290 TraceCheckUtils]: 7: Hoare triple {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:45:14,153 INFO L290 TraceCheckUtils]: 8: Hoare triple {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} is VALID [2022-04-27 16:45:14,154 INFO L290 TraceCheckUtils]: 9: Hoare triple {2104#(<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:14,155 INFO L290 TraceCheckUtils]: 10: Hoare triple {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:14,156 INFO L290 TraceCheckUtils]: 11: Hoare triple {2105#(and (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2106#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:14,158 INFO L290 TraceCheckUtils]: 12: Hoare triple {2106#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~x~0_11 v_main_~x~0_10) (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (= v_main_~x~0_10 (+ v_main_~x~0_11 v_main_~z~0_10 (* (- 1) v_main_~z~0_9))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)))) InVars {main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2150#(and (<= (div (- main_~x~0) (- 4294967296)) (div main_~x~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:14,159 INFO L290 TraceCheckUtils]: 13: Hoare triple {2150#(and (<= (div (- main_~x~0) (- 4294967296)) (div main_~x~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2150#(and (<= (div (- main_~x~0) (- 4294967296)) (div main_~x~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:14,160 INFO L272 TraceCheckUtils]: 14: Hoare triple {2150#(and (<= (div (- main_~x~0) (- 4294967296)) (div main_~x~0 4294967296)) (<= main_~n~0 (* (div main_~n~0 4294967296) 4294967296)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {2157#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:14,161 INFO L290 TraceCheckUtils]: 15: Hoare triple {2157#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2161#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:14,161 INFO L290 TraceCheckUtils]: 16: Hoare triple {2161#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2098#false} is VALID [2022-04-27 16:45:14,161 INFO L290 TraceCheckUtils]: 17: Hoare triple {2098#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2098#false} is VALID [2022-04-27 16:45:14,163 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:45:14,163 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:45:49,703 WARN L232 SmtUtils]: Spent 14.65s on a formula simplification that was a NOOP. DAG size: 51 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:46:21,171 INFO L290 TraceCheckUtils]: 17: Hoare triple {2098#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2098#false} is VALID [2022-04-27 16:46:21,172 INFO L290 TraceCheckUtils]: 16: Hoare triple {2161#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2098#false} is VALID [2022-04-27 16:46:21,172 INFO L290 TraceCheckUtils]: 15: Hoare triple {2157#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2161#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:46:21,174 INFO L272 TraceCheckUtils]: 14: Hoare triple {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~x~0_13 4294967296) (mod v_main_~n~0_3 4294967296)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~x~0=v_main_~x~0_13, main_~n~0=v_main_~n~0_3} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~n~0] {2157#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:46:21,174 INFO L290 TraceCheckUtils]: 13: Hoare triple {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2107#(and (<= (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296)) (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296)))) (< (+ main_~n~0 (* 4294967296 (div main_~x~0 4294967296))) (+ main_~x~0 (* (div main_~n~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 16:46:22,170 WARN L230 Executor]: External (MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) stderr output: (error "out of memory") [2022-04-27 16:46:22,171 WARN L319 FreeRefinementEngine]: Global settings require throwing the following exception [2022-04-27 16:46:22,187 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 101 [2022-04-27 16:46:22,187 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2022-04-27 16:46:22,371 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-04-27 16:46:22,372 FATAL L? ?]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:243) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:262) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.logic.WrapperScript.checkSat(WrapperScript.java:163) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUtils.isInductiveHelper(PredicateUtils.java:348) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.hoaretriple.MonolithicHoareTripleChecker.isInductive(MonolithicHoareTripleChecker.java:209) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.hoaretriple.MonolithicHoareTripleChecker.isInductive(MonolithicHoareTripleChecker.java:164) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.hoaretriple.MonolithicHoareTripleChecker.checkInternal(MonolithicHoareTripleChecker.java:91) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckUtils.checkInductivityAtPosition(TraceCheckUtils.java:289) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckUtils.checkInterpolantsInductivityBackward(TraceCheckUtils.java:252) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:345) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:185) at de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:163) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:108) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleSpWp.construct(IpTcStrategyModuleSpWp.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getOrConstruct(IpTcStrategyModuleBase.java:101) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.IpTcStrategyModuleBase.getInterpolantComputationStatus(IpTcStrategyModuleBase.java:77) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.tryExecuteInterpolantGenerator(AutomatonFreeRefinementEngine.java:266) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.generateProof(AutomatonFreeRefinementEngine.java:147) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.executeStrategy(AutomatonFreeRefinementEngine.java:137) at de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.tracehandling.AutomatonFreeRefinementEngine.(AutomatonFreeRefinementEngine.java:85) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:82) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:248) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:431) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.startCegar(AbstractCegarLoop.java:366) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.runCegar(AbstractCegarLoop.java:348) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.executeCegarLoop(TraceAbstractionStarter.java:409) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseProgram(TraceAbstractionStarter.java:300) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.analyseSequentialProgram(TraceAbstractionStarter.java:260) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:173) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:152) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:320) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:63) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1465) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:658) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:383) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:239) ... 42 more [2022-04-27 16:46:22,374 INFO L158 Benchmark]: Toolchain (without parser) took 281136.27ms. Allocated memory was 185.6MB in the beginning and 280.0MB in the end (delta: 94.4MB). Free memory was 129.6MB in the beginning and 173.2MB in the end (delta: -43.6MB). Peak memory consumption was 50.8MB. Max. memory is 8.0GB. [2022-04-27 16:46:22,374 INFO L158 Benchmark]: CDTParser took 0.09ms. Allocated memory is still 185.6MB. Free memory was 145.7MB in the beginning and 145.6MB in the end (delta: 75.2kB). There was no memory consumed. Max. memory is 8.0GB. [2022-04-27 16:46:22,374 INFO L158 Benchmark]: CACSL2BoogieTranslator took 143.96ms. Allocated memory was 185.6MB in the beginning and 232.8MB in the end (delta: 47.2MB). Free memory was 129.4MB in the beginning and 205.0MB in the end (delta: -75.7MB). Peak memory consumption was 15.0MB. Max. memory is 8.0GB. [2022-04-27 16:46:22,374 INFO L158 Benchmark]: Boogie Preprocessor took 35.69ms. Allocated memory is still 232.8MB. Free memory was 205.0MB in the beginning and 203.2MB in the end (delta: 1.9MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-04-27 16:46:22,375 INFO L158 Benchmark]: RCFGBuilder took 248.95ms. Allocated memory is still 232.8MB. Free memory was 203.2MB in the beginning and 190.0MB in the end (delta: 13.2MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. [2022-04-27 16:46:22,375 INFO L158 Benchmark]: IcfgTransformer took 1335.25ms. Allocated memory is still 232.8MB. Free memory was 190.0MB in the beginning and 176.2MB in the end (delta: 13.7MB). Peak memory consumption was 61.8MB. Max. memory is 8.0GB. [2022-04-27 16:46:22,375 INFO L158 Benchmark]: TraceAbstraction took 279368.22ms. Allocated memory was 232.8MB in the beginning and 280.0MB in the end (delta: 47.2MB). Free memory was 175.7MB in the beginning and 173.2MB in the end (delta: 2.5MB). Peak memory consumption was 50.0MB. Max. memory is 8.0GB. [2022-04-27 16:46:22,376 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from IcfgTransformer: - StatisticsResult: Jordan loop acceleration statistics 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult - StatisticsResult: Jordan loop acceleration statistics 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult - StatisticsResult: Jordan loop acceleration statistics 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult - StatisticsResult: Jordan loop acceleration statistics 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult - StatisticsResult: Jordan loop acceleration statistics 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09ms. Allocated memory is still 185.6MB. Free memory was 145.7MB in the beginning and 145.6MB in the end (delta: 75.2kB). There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 143.96ms. Allocated memory was 185.6MB in the beginning and 232.8MB in the end (delta: 47.2MB). Free memory was 129.4MB in the beginning and 205.0MB in the end (delta: -75.7MB). Peak memory consumption was 15.0MB. Max. memory is 8.0GB. * Boogie Preprocessor took 35.69ms. Allocated memory is still 232.8MB. Free memory was 205.0MB in the beginning and 203.2MB in the end (delta: 1.9MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 248.95ms. Allocated memory is still 232.8MB. Free memory was 203.2MB in the beginning and 190.0MB in the end (delta: 13.2MB). Peak memory consumption was 13.6MB. Max. memory is 8.0GB. * IcfgTransformer took 1335.25ms. Allocated memory is still 232.8MB. Free memory was 190.0MB in the beginning and 176.2MB in the end (delta: 13.7MB). Peak memory consumption was 61.8MB. Max. memory is 8.0GB. * TraceAbstraction took 279368.22ms. Allocated memory was 232.8MB in the beginning and 280.0MB in the end (delta: 47.2MB). Free memory was 175.7MB in the beginning and 173.2MB in the end (delta: 2.5MB). Peak memory consumption was 50.0MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1) with exit command (exit)) Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:243) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...