/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de52.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 16:43:27,989 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 16:43:27,991 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 16:43:28,035 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-27 16:43:28,045 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 16:43:28,045 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 16:43:28,046 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 16:43:28,047 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 16:43:28,047 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 16:43:28,048 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 16:43:28,049 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 16:43:28,050 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 16:43:28,051 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 16:43:28,051 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 16:43:28,052 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 16:43:28,053 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 16:43:28,053 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 16:43:28,055 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 16:43:28,060 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 16:43:28,061 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 16:43:28,062 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 16:43:28,062 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 16:43:28,068 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 16:43:28,069 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 16:43:28,069 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 16:43:28,069 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 16:43:28,070 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 16:43:28,071 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 16:43:28,071 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 16:43:28,071 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 16:43:28,071 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 16:43:28,071 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 16:43:28,071 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 16:43:28,071 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:43:28,071 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 16:43:28,072 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 16:43:28,072 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 16:43:28,072 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 16:43:28,217 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 16:43:28,229 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 16:43:28,231 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 16:43:28,231 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 16:43:28,232 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 16:43:28,232 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de52.c [2022-04-27 16:43:28,269 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2c4118d9e/c054aa858edf44e5b6abf55b11695d1a/FLAG483c7538c [2022-04-27 16:43:28,573 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 16:43:28,573 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de52.c [2022-04-27 16:43:28,577 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2c4118d9e/c054aa858edf44e5b6abf55b11695d1a/FLAG483c7538c [2022-04-27 16:43:29,022 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/2c4118d9e/c054aa858edf44e5b6abf55b11695d1a [2022-04-27 16:43:29,024 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 16:43:29,026 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 16:43:29,027 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 16:43:29,027 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 16:43:29,029 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 16:43:29,030 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,031 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1c7de137 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29, skipping insertion in model container [2022-04-27 16:43:29,031 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,036 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 16:43:29,045 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 16:43:29,143 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de52.c[368,381] [2022-04-27 16:43:29,152 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:43:29,163 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 16:43:29,183 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de52.c[368,381] [2022-04-27 16:43:29,186 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:43:29,204 INFO L208 MainTranslator]: Completed translation [2022-04-27 16:43:29,204 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29 WrapperNode [2022-04-27 16:43:29,205 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 16:43:29,205 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 16:43:29,205 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 16:43:29,206 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 16:43:29,212 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,212 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,217 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,218 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,231 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,238 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,243 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,244 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 16:43:29,245 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 16:43:29,245 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 16:43:29,245 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 16:43:29,250 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,260 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:43:29,267 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:43:29,276 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 16:43:29,290 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 16:43:29,302 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 16:43:29,302 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 16:43:29,302 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 16:43:29,302 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 16:43:29,303 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 16:43:29,303 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 16:43:29,304 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 16:43:29,342 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 16:43:29,343 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 16:43:29,518 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 16:43:29,523 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 16:43:29,523 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-04-27 16:43:29,531 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:43:29 BoogieIcfgContainer [2022-04-27 16:43:29,532 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 16:43:29,532 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 16:43:29,532 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 16:43:29,543 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 16:43:29,545 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:43:29" (1/1) ... [2022-04-27 16:43:29,547 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 16:43:29,900 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:43:29,900 INFO L91 elerationTransformer]: Accelerated Formula: (and (= (+ v_main_~x~0_3 1) v_main_~x~0_4) (= v_main_~y~0_5 (+ v_main_~y~0_6 1)) (< 0 (mod v_main_~x~0_4 4294967296))) InVars {main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_6} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_4 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~x~0_4 v_main_~x~0_3) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~y~0_6 v_main_~y~0_5)) (and (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_4 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_6 v_it_1 1) v_main_~y~0_5)))) (< v_main_~y~0_6 v_main_~y~0_5) (< 0 .cse0) (= v_main_~x~0_3 (+ v_main_~x~0_4 v_main_~y~0_6 (* (- 1) v_main_~y~0_5)))))) InVars {main_~y~0=v_main_~y~0_6, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_4, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_5, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_3, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-27 16:43:30,124 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:43:30,125 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_8 (+ v_main_~x~0_9 1)) (= v_main_~z~0_8 (+ v_main_~z~0_7 1)) (< 0 (mod v_main_~z~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_9, main_~z~0=v_main_~z~0_8} OutVars{main_~x~0=v_main_~x~0_8, main_~z~0=v_main_~z~0_7, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-27 16:43:30,368 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:43:30,368 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_4 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_4 (+ v_main_~y~0_3 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_3, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-27 16:43:30,617 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:43:30,618 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= (+ v_main_~y~0_8 1) v_main_~y~0_7)) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_8} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_7, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-27 16:43:30,816 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:43:30,817 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_10 (+ v_main_~z~0_9 1)) (< 0 (mod v_main_~z~0_10 4294967296)) (= v_main_~y~0_11 (+ v_main_~y~0_10 1))) InVars {main_~z~0=v_main_~z~0_10, main_~y~0=v_main_~y~0_11} OutVars{main_~z~0=v_main_~z~0_9, main_~y~0=v_main_~y~0_10, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] to Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] [2022-04-27 16:43:30,820 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:43:30 BasicIcfg [2022-04-27 16:43:30,820 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 16:43:30,821 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 16:43:30,821 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 16:43:30,823 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 16:43:30,823 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 04:43:29" (1/4) ... [2022-04-27 16:43:30,823 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bdef8b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:43:30, skipping insertion in model container [2022-04-27 16:43:30,823 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:43:29" (2/4) ... [2022-04-27 16:43:30,824 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bdef8b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:43:30, skipping insertion in model container [2022-04-27 16:43:30,824 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:43:29" (3/4) ... [2022-04-27 16:43:30,824 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@bdef8b9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 04:43:30, skipping insertion in model container [2022-04-27 16:43:30,824 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:43:30" (4/4) ... [2022-04-27 16:43:30,825 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de52.cJordan [2022-04-27 16:43:30,833 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 16:43:30,833 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 16:43:30,855 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 16:43:30,859 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@4453660d, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@596fb892 [2022-04-27 16:43:30,859 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 16:43:30,864 INFO L276 IsEmpty]: Start isEmpty. Operand has 24 states, 16 states have (on average 1.75) internal successors, (28), 17 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 16:43:30,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:43:30,868 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:43:30,868 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:43:30,868 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:43:30,871 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:43:30,871 INFO L85 PathProgramCache]: Analyzing trace with hash 702671213, now seen corresponding path program 1 times [2022-04-27 16:43:30,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:43:30,877 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [406137263] [2022-04-27 16:43:30,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:30,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:43:30,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:30,950 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:43:30,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:30,968 INFO L290 TraceCheckUtils]: 0: Hoare triple {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {27#true} is VALID [2022-04-27 16:43:30,968 INFO L290 TraceCheckUtils]: 1: Hoare triple {27#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:43:30,968 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {27#true} {27#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:43:30,969 INFO L272 TraceCheckUtils]: 0: Hoare triple {27#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:43:30,970 INFO L290 TraceCheckUtils]: 1: Hoare triple {32#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {27#true} is VALID [2022-04-27 16:43:30,970 INFO L290 TraceCheckUtils]: 2: Hoare triple {27#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:43:30,970 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {27#true} {27#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:43:30,970 INFO L272 TraceCheckUtils]: 4: Hoare triple {27#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#true} is VALID [2022-04-27 16:43:30,970 INFO L290 TraceCheckUtils]: 5: Hoare triple {27#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {27#true} is VALID [2022-04-27 16:43:30,971 INFO L290 TraceCheckUtils]: 6: Hoare triple {27#true} [92] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,971 INFO L290 TraceCheckUtils]: 7: Hoare triple {28#false} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {28#false} is VALID [2022-04-27 16:43:30,971 INFO L290 TraceCheckUtils]: 8: Hoare triple {28#false} [96] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,971 INFO L290 TraceCheckUtils]: 9: Hoare triple {28#false} [99] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,971 INFO L290 TraceCheckUtils]: 10: Hoare triple {28#false} [102] L35-1-->L41-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,971 INFO L290 TraceCheckUtils]: 11: Hoare triple {28#false} [105] L41-1-->L41-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,971 INFO L272 TraceCheckUtils]: 12: Hoare triple {28#false} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {28#false} is VALID [2022-04-27 16:43:30,972 INFO L290 TraceCheckUtils]: 13: Hoare triple {28#false} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {28#false} is VALID [2022-04-27 16:43:30,972 INFO L290 TraceCheckUtils]: 14: Hoare triple {28#false} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,972 INFO L290 TraceCheckUtils]: 15: Hoare triple {28#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#false} is VALID [2022-04-27 16:43:30,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:30,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:43:30,973 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [406137263] [2022-04-27 16:43:30,973 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [406137263] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:43:30,973 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:43:30,973 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 16:43:30,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [459017241] [2022-04-27 16:43:30,975 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:43:30,978 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:43:30,979 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:43:30,981 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:30,997 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:30,997 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 16:43:30,998 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:43:31,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 16:43:31,026 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:43:31,029 INFO L87 Difference]: Start difference. First operand has 24 states, 16 states have (on average 1.75) internal successors, (28), 17 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:31,069 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2022-04-27 16:43:31,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 16:43:31,070 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:43:31,070 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:43:31,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-27 16:43:31,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-27 16:43:31,078 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 34 transitions. [2022-04-27 16:43:31,111 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:31,117 INFO L225 Difference]: With dead ends: 24 [2022-04-27 16:43:31,117 INFO L226 Difference]: Without dead ends: 17 [2022-04-27 16:43:31,118 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:43:31,121 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 19 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 30 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:43:31,122 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 30 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:43:31,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2022-04-27 16:43:31,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2022-04-27 16:43:31,137 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:43:31,138 INFO L82 GeneralOperation]: Start isEquivalent. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,138 INFO L74 IsIncluded]: Start isIncluded. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,138 INFO L87 Difference]: Start difference. First operand 17 states. Second operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:31,140 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2022-04-27 16:43:31,140 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-27 16:43:31,140 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:31,140 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:31,141 INFO L74 IsIncluded]: Start isIncluded. First operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 17 states. [2022-04-27 16:43:31,141 INFO L87 Difference]: Start difference. First operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 17 states. [2022-04-27 16:43:31,142 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:31,142 INFO L93 Difference]: Finished difference Result 17 states and 21 transitions. [2022-04-27 16:43:31,142 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-27 16:43:31,142 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:31,143 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:31,143 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:43:31,143 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:43:31,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 12 states have (on average 1.4166666666666667) internal successors, (17), 12 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2022-04-27 16:43:31,144 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 21 transitions. Word has length 16 [2022-04-27 16:43:31,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:43:31,145 INFO L495 AbstractCegarLoop]: Abstraction has 17 states and 21 transitions. [2022-04-27 16:43:31,145 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 4.0) internal successors, (12), 2 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,145 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 21 transitions. [2022-04-27 16:43:31,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2022-04-27 16:43:31,145 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:43:31,145 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:43:31,146 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 16:43:31,146 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:43:31,146 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:43:31,146 INFO L85 PathProgramCache]: Analyzing trace with hash -1128942900, now seen corresponding path program 1 times [2022-04-27 16:43:31,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:43:31,146 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1162517942] [2022-04-27 16:43:31,147 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:31,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:43:31,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:31,230 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:43:31,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:31,235 INFO L290 TraceCheckUtils]: 0: Hoare triple {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-27 16:43:31,236 INFO L290 TraceCheckUtils]: 1: Hoare triple {110#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,236 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {110#true} {110#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,236 INFO L272 TraceCheckUtils]: 0: Hoare triple {110#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:43:31,237 INFO L290 TraceCheckUtils]: 1: Hoare triple {118#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-27 16:43:31,237 INFO L290 TraceCheckUtils]: 2: Hoare triple {110#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,237 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {110#true} {110#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,237 INFO L272 TraceCheckUtils]: 4: Hoare triple {110#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,237 INFO L290 TraceCheckUtils]: 5: Hoare triple {110#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {110#true} is VALID [2022-04-27 16:43:31,237 INFO L290 TraceCheckUtils]: 6: Hoare triple {110#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,237 INFO L290 TraceCheckUtils]: 7: Hoare triple {110#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {110#true} is VALID [2022-04-27 16:43:31,238 INFO L290 TraceCheckUtils]: 8: Hoare triple {110#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 16:43:31,238 INFO L290 TraceCheckUtils]: 9: Hoare triple {110#true} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} is VALID [2022-04-27 16:43:31,239 INFO L290 TraceCheckUtils]: 10: Hoare triple {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} is VALID [2022-04-27 16:43:31,239 INFO L290 TraceCheckUtils]: 11: Hoare triple {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} is VALID [2022-04-27 16:43:31,240 INFO L272 TraceCheckUtils]: 12: Hoare triple {115#(= (+ main_~y~0 (* (div main_~y~0 4294967296) (- 4294967296))) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {116#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:43:31,240 INFO L290 TraceCheckUtils]: 13: Hoare triple {116#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {117#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:43:31,241 INFO L290 TraceCheckUtils]: 14: Hoare triple {117#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 16:43:31,241 INFO L290 TraceCheckUtils]: 15: Hoare triple {111#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 16:43:31,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:31,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:43:31,241 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1162517942] [2022-04-27 16:43:31,241 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1162517942] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:43:31,242 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:43:31,242 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 16:43:31,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498359909] [2022-04-27 16:43:31,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:43:31,243 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:43:31,243 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:43:31,243 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,254 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 16 edges. 16 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:31,254 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 16:43:31,254 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:43:31,254 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 16:43:31,254 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-04-27 16:43:31,255 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. Second operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:31,375 INFO L93 Difference]: Finished difference Result 28 states and 38 transitions. [2022-04-27 16:43:31,375 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 16:43:31,376 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 16 [2022-04-27 16:43:31,376 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:43:31,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 39 transitions. [2022-04-27 16:43:31,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 39 transitions. [2022-04-27 16:43:31,385 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 39 transitions. [2022-04-27 16:43:31,420 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:31,421 INFO L225 Difference]: With dead ends: 28 [2022-04-27 16:43:31,421 INFO L226 Difference]: Without dead ends: 25 [2022-04-27 16:43:31,422 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2022-04-27 16:43:31,423 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 20 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 20 SdHoareTripleChecker+Valid, 34 SdHoareTripleChecker+Invalid, 48 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 7 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:43:31,424 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [20 Valid, 34 Invalid, 48 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 33 Invalid, 0 Unknown, 7 Unchecked, 0.0s Time] [2022-04-27 16:43:31,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-04-27 16:43:31,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 19. [2022-04-27 16:43:31,427 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:43:31,427 INFO L82 GeneralOperation]: Start isEquivalent. First operand 25 states. Second operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,427 INFO L74 IsIncluded]: Start isIncluded. First operand 25 states. Second operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,428 INFO L87 Difference]: Start difference. First operand 25 states. Second operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:31,430 INFO L93 Difference]: Finished difference Result 25 states and 35 transitions. [2022-04-27 16:43:31,430 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-27 16:43:31,430 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:31,430 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:31,431 INFO L74 IsIncluded]: Start isIncluded. First operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-27 16:43:31,431 INFO L87 Difference]: Start difference. First operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-27 16:43:31,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:31,433 INFO L93 Difference]: Finished difference Result 25 states and 35 transitions. [2022-04-27 16:43:31,433 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-27 16:43:31,434 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:31,434 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:31,434 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:43:31,434 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:43:31,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 19 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 14 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,435 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 24 transitions. [2022-04-27 16:43:31,435 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 24 transitions. Word has length 16 [2022-04-27 16:43:31,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:43:31,435 INFO L495 AbstractCegarLoop]: Abstraction has 19 states and 24 transitions. [2022-04-27 16:43:31,435 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.0) internal successors, (12), 4 states have internal predecessors, (12), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:31,436 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 24 transitions. [2022-04-27 16:43:31,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:43:31,436 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:43:31,437 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:43:31,437 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 16:43:31,437 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:43:31,437 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:43:31,437 INFO L85 PathProgramCache]: Analyzing trace with hash -610770875, now seen corresponding path program 1 times [2022-04-27 16:43:31,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:43:31,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [353775873] [2022-04-27 16:43:31,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:31,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:43:31,470 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:31,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:31,500 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:31,569 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:43:31,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:31,576 INFO L290 TraceCheckUtils]: 0: Hoare triple {235#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-27 16:43:31,576 INFO L290 TraceCheckUtils]: 1: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,576 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,577 INFO L272 TraceCheckUtils]: 0: Hoare triple {225#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {235#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:43:31,577 INFO L290 TraceCheckUtils]: 1: Hoare triple {235#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-27 16:43:31,577 INFO L290 TraceCheckUtils]: 2: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,577 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,577 INFO L272 TraceCheckUtils]: 4: Hoare triple {225#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,578 INFO L290 TraceCheckUtils]: 5: Hoare triple {225#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#(= main_~y~0 0)} is VALID [2022-04-27 16:43:31,578 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {230#(= main_~y~0 0)} is VALID [2022-04-27 16:43:31,578 INFO L290 TraceCheckUtils]: 7: Hoare triple {230#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {230#(= main_~y~0 0)} is VALID [2022-04-27 16:43:31,579 INFO L290 TraceCheckUtils]: 8: Hoare triple {230#(= main_~y~0 0)} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:43:31,579 INFO L290 TraceCheckUtils]: 9: Hoare triple {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:43:31,580 INFO L290 TraceCheckUtils]: 10: Hoare triple {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:43:31,581 INFO L290 TraceCheckUtils]: 11: Hoare triple {231#(and (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:31,581 INFO L290 TraceCheckUtils]: 12: Hoare triple {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:31,582 INFO L272 TraceCheckUtils]: 13: Hoare triple {232#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {233#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:43:31,582 INFO L290 TraceCheckUtils]: 14: Hoare triple {233#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {234#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:43:31,583 INFO L290 TraceCheckUtils]: 15: Hoare triple {234#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-27 16:43:31,583 INFO L290 TraceCheckUtils]: 16: Hoare triple {226#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-27 16:43:31,583 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:31,583 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:43:31,583 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [353775873] [2022-04-27 16:43:31,584 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [353775873] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:43:31,584 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [657272541] [2022-04-27 16:43:31,584 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:31,584 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:43:31,584 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:43:31,585 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:43:31,586 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 16:43:31,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:31,617 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:43:31,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:31,627 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:43:31,902 INFO L272 TraceCheckUtils]: 0: Hoare triple {225#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,902 INFO L290 TraceCheckUtils]: 1: Hoare triple {225#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-27 16:43:31,903 INFO L290 TraceCheckUtils]: 2: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,903 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,903 INFO L272 TraceCheckUtils]: 4: Hoare triple {225#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,903 INFO L290 TraceCheckUtils]: 5: Hoare triple {225#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {225#true} is VALID [2022-04-27 16:43:31,903 INFO L290 TraceCheckUtils]: 6: Hoare triple {225#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:31,903 INFO L290 TraceCheckUtils]: 7: Hoare triple {225#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {225#true} is VALID [2022-04-27 16:43:31,904 INFO L290 TraceCheckUtils]: 8: Hoare triple {225#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {263#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:43:31,904 INFO L290 TraceCheckUtils]: 9: Hoare triple {263#(not (< 0 (mod main_~z~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:43:31,905 INFO L290 TraceCheckUtils]: 10: Hoare triple {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:43:31,906 INFO L290 TraceCheckUtils]: 11: Hoare triple {267#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:31,906 INFO L290 TraceCheckUtils]: 12: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:31,907 INFO L272 TraceCheckUtils]: 13: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {281#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:31,907 INFO L290 TraceCheckUtils]: 14: Hoare triple {281#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {285#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:31,908 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-27 16:43:31,910 INFO L290 TraceCheckUtils]: 16: Hoare triple {226#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-27 16:43:31,910 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:31,910 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:43:40,005 INFO L290 TraceCheckUtils]: 16: Hoare triple {226#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-27 16:43:40,005 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {226#false} is VALID [2022-04-27 16:43:40,006 INFO L290 TraceCheckUtils]: 14: Hoare triple {281#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {285#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:40,007 INFO L272 TraceCheckUtils]: 13: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {281#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:40,026 INFO L290 TraceCheckUtils]: 12: Hoare triple {274#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:40,032 INFO L290 TraceCheckUtils]: 11: Hoare triple {307#(forall ((aux_div_v_main_~y~0_27_31 Int) (aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (<= aux_mod_v_main_~y~0_27_31 0)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {274#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:41,774 INFO L290 TraceCheckUtils]: 10: Hoare triple {307#(forall ((aux_div_v_main_~y~0_27_31 Int) (aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (<= aux_mod_v_main_~y~0_27_31 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {307#(forall ((aux_div_v_main_~y~0_27_31 Int) (aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (<= aux_mod_v_main_~y~0_27_31 0)))} is VALID [2022-04-27 16:43:41,776 INFO L290 TraceCheckUtils]: 9: Hoare triple {263#(not (< 0 (mod main_~z~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {307#(forall ((aux_div_v_main_~y~0_27_31 Int) (aux_mod_v_main_~y~0_27_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_27_31) (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_27_31 4294967296) v_it_5 aux_mod_v_main_~y~0_27_31 1) main_~y~0)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_27_31 4294967296) aux_mod_v_main_~y~0_27_31))))) (<= aux_mod_v_main_~y~0_27_31 0)))} is VALID [2022-04-27 16:43:41,777 INFO L290 TraceCheckUtils]: 8: Hoare triple {225#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {263#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:43:41,777 INFO L290 TraceCheckUtils]: 7: Hoare triple {225#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {225#true} is VALID [2022-04-27 16:43:41,777 INFO L290 TraceCheckUtils]: 6: Hoare triple {225#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:41,777 INFO L290 TraceCheckUtils]: 5: Hoare triple {225#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {225#true} is VALID [2022-04-27 16:43:41,777 INFO L272 TraceCheckUtils]: 4: Hoare triple {225#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:41,777 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {225#true} {225#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:41,777 INFO L290 TraceCheckUtils]: 2: Hoare triple {225#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:41,777 INFO L290 TraceCheckUtils]: 1: Hoare triple {225#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {225#true} is VALID [2022-04-27 16:43:41,778 INFO L272 TraceCheckUtils]: 0: Hoare triple {225#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {225#true} is VALID [2022-04-27 16:43:41,778 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:41,778 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [657272541] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:43:41,778 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:43:41,778 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 16:43:41,778 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1968744711] [2022-04-27 16:43:41,778 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:43:41,779 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:43:41,779 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:43:41,779 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,095 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 33 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:42,095 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:43:42,096 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:43:42,096 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:43:42,096 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=142, Unknown=1, NotChecked=0, Total=182 [2022-04-27 16:43:42,096 INFO L87 Difference]: Start difference. First operand 19 states and 24 transitions. Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:42,391 INFO L93 Difference]: Finished difference Result 36 states and 50 transitions. [2022-04-27 16:43:42,391 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:43:42,391 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:43:42,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:43:42,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 51 transitions. [2022-04-27 16:43:42,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 51 transitions. [2022-04-27 16:43:42,398 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 51 transitions. [2022-04-27 16:43:42,442 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:42,443 INFO L225 Difference]: With dead ends: 36 [2022-04-27 16:43:42,443 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:43:42,443 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 28 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 6.3s TimeCoverageRelationStatistics Valid=102, Invalid=359, Unknown=1, NotChecked=0, Total=462 [2022-04-27 16:43:42,444 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 27 mSDsluCounter, 49 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 62 SdHoareTripleChecker+Invalid, 114 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 19 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:43:42,444 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 62 Invalid, 114 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 76 Invalid, 0 Unknown, 19 Unchecked, 0.1s Time] [2022-04-27 16:43:42,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:43:42,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 22. [2022-04-27 16:43:42,446 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:43:42,447 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,447 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,447 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:42,448 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:43:42,448 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:43:42,449 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:42,449 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:42,449 INFO L74 IsIncluded]: Start isIncluded. First operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:43:42,449 INFO L87 Difference]: Start difference. First operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:43:42,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:42,450 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:43:42,450 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:43:42,450 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:42,450 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:42,450 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:43:42,451 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:43:42,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 17 states have (on average 1.4705882352941178) internal successors, (25), 17 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,451 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 29 transitions. [2022-04-27 16:43:42,451 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 29 transitions. Word has length 17 [2022-04-27 16:43:42,451 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:43:42,451 INFO L495 AbstractCegarLoop]: Abstraction has 22 states and 29 transitions. [2022-04-27 16:43:42,452 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:42,452 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 29 transitions. [2022-04-27 16:43:42,452 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:43:42,452 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:43:42,452 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:43:42,468 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 16:43:42,659 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:43:42,659 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:43:42,660 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:43:42,660 INFO L85 PathProgramCache]: Analyzing trace with hash 162216202, now seen corresponding path program 1 times [2022-04-27 16:43:42,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:43:42,660 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1381744254] [2022-04-27 16:43:42,660 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:42,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:43:42,670 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:43:42,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:42,680 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:43:42,736 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:43:42,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:42,742 INFO L290 TraceCheckUtils]: 0: Hoare triple {492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:43:42,743 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:42,743 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:42,743 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:43:42,743 INFO L290 TraceCheckUtils]: 1: Hoare triple {492#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:43:42,744 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:42,744 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:42,744 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:42,744 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {487#(= main_~y~0 0)} is VALID [2022-04-27 16:43:42,745 INFO L290 TraceCheckUtils]: 6: Hoare triple {487#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:43:42,746 INFO L290 TraceCheckUtils]: 7: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:43:42,747 INFO L290 TraceCheckUtils]: 8: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:43:42,748 INFO L290 TraceCheckUtils]: 9: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:43:42,749 INFO L290 TraceCheckUtils]: 10: Hoare triple {488#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:42,750 INFO L290 TraceCheckUtils]: 11: Hoare triple {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:42,750 INFO L290 TraceCheckUtils]: 12: Hoare triple {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:42,751 INFO L272 TraceCheckUtils]: 13: Hoare triple {489#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {490#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:43:42,751 INFO L290 TraceCheckUtils]: 14: Hoare triple {490#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {491#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:43:42,751 INFO L290 TraceCheckUtils]: 15: Hoare triple {491#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:43:42,752 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:43:42,752 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:42,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:43:42,753 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1381744254] [2022-04-27 16:43:42,754 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1381744254] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:43:42,754 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [210719944] [2022-04-27 16:43:42,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:42,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:43:42,755 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:43:42,755 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:43:42,767 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 16:43:42,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:42,790 INFO L263 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:43:42,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:42,797 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:43:43,070 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:43,070 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:43:43,070 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:43,070 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:43,070 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:43,070 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {482#true} is VALID [2022-04-27 16:43:43,072 INFO L290 TraceCheckUtils]: 6: Hoare triple {482#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:43,072 INFO L290 TraceCheckUtils]: 7: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:43,082 INFO L290 TraceCheckUtils]: 8: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:43,085 INFO L290 TraceCheckUtils]: 9: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {524#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:43:43,086 INFO L290 TraceCheckUtils]: 10: Hoare triple {524#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:43,087 INFO L290 TraceCheckUtils]: 11: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:43,088 INFO L290 TraceCheckUtils]: 12: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:43,088 INFO L272 TraceCheckUtils]: 13: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {538#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:43,089 INFO L290 TraceCheckUtils]: 14: Hoare triple {538#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {542#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:43,089 INFO L290 TraceCheckUtils]: 15: Hoare triple {542#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:43:43,089 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:43:43,089 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:43,089 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:43:44,703 INFO L290 TraceCheckUtils]: 16: Hoare triple {483#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:43:44,703 INFO L290 TraceCheckUtils]: 15: Hoare triple {542#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {483#false} is VALID [2022-04-27 16:43:44,703 INFO L290 TraceCheckUtils]: 14: Hoare triple {538#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {542#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:44,704 INFO L272 TraceCheckUtils]: 13: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {538#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:44,704 INFO L290 TraceCheckUtils]: 12: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:44,705 INFO L290 TraceCheckUtils]: 11: Hoare triple {528#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:44,710 INFO L290 TraceCheckUtils]: 10: Hoare triple {567#(forall ((aux_mod_v_main_~y~0_29_31 Int) (aux_div_v_main_~y~0_29_31 Int)) (or (<= aux_mod_v_main_~y~0_29_31 0) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296)) main_~y~0))) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296)))) (not (< 0 (mod main_~x~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_29_31)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {528#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:44,711 INFO L290 TraceCheckUtils]: 9: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {567#(forall ((aux_mod_v_main_~y~0_29_31 Int) (aux_div_v_main_~y~0_29_31 Int)) (or (<= aux_mod_v_main_~y~0_29_31 0) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296)) main_~y~0))) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296))) (<= 1 v_it_4))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_29_31 (* aux_div_v_main_~y~0_29_31 4294967296)))) (not (< 0 (mod main_~x~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_29_31)))} is VALID [2022-04-27 16:43:44,712 INFO L290 TraceCheckUtils]: 8: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:44,712 INFO L290 TraceCheckUtils]: 7: Hoare triple {514#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:44,712 INFO L290 TraceCheckUtils]: 6: Hoare triple {482#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {514#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:43:44,712 INFO L290 TraceCheckUtils]: 5: Hoare triple {482#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {482#true} is VALID [2022-04-27 16:43:44,713 INFO L272 TraceCheckUtils]: 4: Hoare triple {482#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:44,713 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {482#true} {482#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:44,713 INFO L290 TraceCheckUtils]: 2: Hoare triple {482#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:44,713 INFO L290 TraceCheckUtils]: 1: Hoare triple {482#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {482#true} is VALID [2022-04-27 16:43:44,713 INFO L272 TraceCheckUtils]: 0: Hoare triple {482#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {482#true} is VALID [2022-04-27 16:43:44,713 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:43:44,713 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [210719944] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:43:44,713 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:43:44,713 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 16:43:44,714 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468978067] [2022-04-27 16:43:44,714 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:43:44,714 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:43:44,714 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:43:44,714 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:44,756 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:44,756 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:43:44,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:43:44,756 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:43:44,756 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2022-04-27 16:43:44,757 INFO L87 Difference]: Start difference. First operand 22 states and 29 transitions. Second operand has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,092 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:45,093 INFO L93 Difference]: Finished difference Result 42 states and 60 transitions. [2022-04-27 16:43:45,093 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:43:45,093 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:43:45,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:43:45,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,094 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 57 transitions. [2022-04-27 16:43:45,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 57 transitions. [2022-04-27 16:43:45,096 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 57 transitions. [2022-04-27 16:43:45,171 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:43:45,172 INFO L225 Difference]: With dead ends: 42 [2022-04-27 16:43:45,172 INFO L226 Difference]: Without dead ends: 38 [2022-04-27 16:43:45,172 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 29 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 108 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=98, Invalid=364, Unknown=0, NotChecked=0, Total=462 [2022-04-27 16:43:45,173 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 27 mSDsluCounter, 62 mSDsCounter, 0 mSdLazyCounter, 112 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 78 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 112 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:43:45,173 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 78 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 112 Invalid, 0 Unknown, 24 Unchecked, 0.1s Time] [2022-04-27 16:43:45,175 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2022-04-27 16:43:45,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 25. [2022-04-27 16:43:45,191 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:43:45,192 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,194 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,195 INFO L87 Difference]: Start difference. First operand 38 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:45,196 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-27 16:43:45,196 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 55 transitions. [2022-04-27 16:43:45,196 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:45,196 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:45,196 INFO L74 IsIncluded]: Start isIncluded. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 38 states. [2022-04-27 16:43:45,197 INFO L87 Difference]: Start difference. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 38 states. [2022-04-27 16:43:45,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:43:45,198 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-27 16:43:45,198 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 55 transitions. [2022-04-27 16:43:45,198 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:43:45,198 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:43:45,198 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:43:45,198 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:43:45,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2022-04-27 16:43:45,199 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 35 transitions. Word has length 17 [2022-04-27 16:43:45,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:43:45,199 INFO L495 AbstractCegarLoop]: Abstraction has 25 states and 35 transitions. [2022-04-27 16:43:45,199 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.8571428571428572) internal successors, (26), 11 states have internal predecessors, (26), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:43:45,199 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-27 16:43:45,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:43:45,200 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:43:45,200 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:43:45,220 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 16:43:45,411 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 16:43:45,411 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:43:45,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:43:45,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1727307284, now seen corresponding path program 2 times [2022-04-27 16:43:45,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:43:45,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [951450676] [2022-04-27 16:43:45,413 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:43:45,413 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:43:45,423 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:45,424 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_11 .cse0 (* (- 4294967296) (div (+ main_~z~0_11 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:45,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:45,452 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:45,454 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_11 .cse0 (* (- 4294967296) (div (+ main_~z~0_11 .cse0) 4294967296)))) 0)) [2022-04-27 16:43:45,532 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:43:45,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:45,538 INFO L290 TraceCheckUtils]: 0: Hoare triple {772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-27 16:43:45,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,538 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,538 INFO L272 TraceCheckUtils]: 0: Hoare triple {762#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:43:45,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-27 16:43:45,538 INFO L290 TraceCheckUtils]: 2: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,538 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,539 INFO L272 TraceCheckUtils]: 4: Hoare triple {762#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,539 INFO L290 TraceCheckUtils]: 5: Hoare triple {762#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {767#(= main_~y~0 0)} is VALID [2022-04-27 16:43:45,539 INFO L290 TraceCheckUtils]: 6: Hoare triple {767#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {767#(= main_~y~0 0)} is VALID [2022-04-27 16:43:45,540 INFO L290 TraceCheckUtils]: 7: Hoare triple {767#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:43:45,540 INFO L290 TraceCheckUtils]: 8: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:43:45,540 INFO L290 TraceCheckUtils]: 9: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:43:45,541 INFO L290 TraceCheckUtils]: 10: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:43:45,541 INFO L290 TraceCheckUtils]: 11: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {768#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:43:45,542 INFO L290 TraceCheckUtils]: 12: Hoare triple {768#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:45,543 INFO L290 TraceCheckUtils]: 13: Hoare triple {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:43:45,543 INFO L272 TraceCheckUtils]: 14: Hoare triple {769#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {770#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:43:45,544 INFO L290 TraceCheckUtils]: 15: Hoare triple {770#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {771#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:43:45,544 INFO L290 TraceCheckUtils]: 16: Hoare triple {771#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-27 16:43:45,544 INFO L290 TraceCheckUtils]: 17: Hoare triple {763#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-27 16:43:45,544 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:43:45,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:43:45,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [951450676] [2022-04-27 16:43:45,544 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [951450676] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:43:45,544 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1960660802] [2022-04-27 16:43:45,545 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:43:45,545 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:43:45,545 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:43:45,545 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:43:45,546 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 16:43:45,579 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:43:45,579 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:43:45,579 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 16:43:45,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:43:45,591 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:43:45,841 INFO L272 TraceCheckUtils]: 0: Hoare triple {762#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,841 INFO L290 TraceCheckUtils]: 1: Hoare triple {762#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-27 16:43:45,842 INFO L290 TraceCheckUtils]: 2: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,842 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,842 INFO L272 TraceCheckUtils]: 4: Hoare triple {762#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,842 INFO L290 TraceCheckUtils]: 5: Hoare triple {762#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {762#true} is VALID [2022-04-27 16:43:45,842 INFO L290 TraceCheckUtils]: 6: Hoare triple {762#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:43:45,842 INFO L290 TraceCheckUtils]: 7: Hoare triple {762#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {762#true} is VALID [2022-04-27 16:43:45,843 INFO L290 TraceCheckUtils]: 8: Hoare triple {762#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {800#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:43:45,843 INFO L290 TraceCheckUtils]: 9: Hoare triple {800#(not (< 0 (mod main_~z~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:43:45,843 INFO L290 TraceCheckUtils]: 10: Hoare triple {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:43:45,844 INFO L290 TraceCheckUtils]: 11: Hoare triple {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:43:45,845 INFO L290 TraceCheckUtils]: 12: Hoare triple {804#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:45,845 INFO L290 TraceCheckUtils]: 13: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:43:45,846 INFO L272 TraceCheckUtils]: 14: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {821#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:43:45,847 INFO L290 TraceCheckUtils]: 15: Hoare triple {821#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {825#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:43:45,848 INFO L290 TraceCheckUtils]: 16: Hoare triple {825#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-27 16:43:45,848 INFO L290 TraceCheckUtils]: 17: Hoare triple {763#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-27 16:43:45,848 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:43:45,848 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:44:04,307 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (let ((.cse0 (< 0 (mod c_main_~z~0 4294967296)))) (and (or .cse0 (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) c_main_~y~0)))) (or (and (or (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) c_main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) c_main_~y~0) (<= 1 v_it_5))))) (< 0 (mod (+ (* 4294967295 c_main_~y~0) aux_mod_v_main_~y~0_32_31 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (let ((.cse1 (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70))) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* 4294967295 c_main_~y~0) (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 c_main_~z~0 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* 4294967296 c_main_~y~0) c_main_~z~0)) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_33_70 0) (<= (+ (* 4294967296 c_main_~y~0) c_main_~z~0) .cse1) (<= 4294967296 aux_mod_v_main_~y~0_33_70) (<= .cse1 (+ (* 4294967295 c_main_~y~0) (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 c_main_~z~0)))))) (not .cse0)))))) is different from false [2022-04-27 16:44:58,969 INFO L290 TraceCheckUtils]: 17: Hoare triple {763#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-27 16:44:58,969 INFO L290 TraceCheckUtils]: 16: Hoare triple {825#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {763#false} is VALID [2022-04-27 16:44:58,969 INFO L290 TraceCheckUtils]: 15: Hoare triple {821#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {825#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:44:58,970 INFO L272 TraceCheckUtils]: 14: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {821#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:44:58,970 INFO L290 TraceCheckUtils]: 13: Hoare triple {814#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {814#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:45:00,993 WARN L290 TraceCheckUtils]: 12: Hoare triple {847#(forall ((aux_mod_v_main_~y~0_32_31 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (and (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31)))) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {814#(<= (mod main_~y~0 4294967296) 0)} is UNKNOWN [2022-04-27 16:45:03,006 WARN L290 TraceCheckUtils]: 11: Hoare triple {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {847#(forall ((aux_mod_v_main_~y~0_32_31 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (and (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31)))) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))))} is UNKNOWN [2022-04-27 16:45:05,203 WARN L290 TraceCheckUtils]: 10: Hoare triple {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} is UNKNOWN [2022-04-27 16:45:07,214 WARN L290 TraceCheckUtils]: 9: Hoare triple {858#(or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295)) 4294967296)) (forall ((aux_div_main_~y~0_26 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_div_main_~y~0_26 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26)) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70))))))))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {851#(forall ((aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) main_~y~0)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) main_~y~0) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* main_~y~0 4294967296) main_~z~0)) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* main_~y~0 4294967295) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_32_31)))} is UNKNOWN [2022-04-27 16:45:07,216 INFO L290 TraceCheckUtils]: 8: Hoare triple {762#true} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {858#(or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_32_31 Int)) (or (<= aux_mod_v_main_~y~0_32_31 0) (<= 4294967296 aux_mod_v_main_~y~0_32_31) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (and (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295)) 4294967296)) (forall ((aux_div_main_~y~0_26 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 1) (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))))) (forall ((aux_div_v_main_~y~0_33_70 Int) (aux_div_main_~y~0_26 Int) (aux_mod_v_main_~y~0_33_70 Int) (aux_div_v_main_~y~0_32_31 Int)) (or (<= (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70) (+ main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26))) (<= aux_mod_v_main_~y~0_33_70 0) (<= 4294967296 aux_mod_v_main_~y~0_33_70) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70 1) (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ (* aux_mod_main_~y~0_26 4294967296) main_~z~0 (* 18446744073709551616 aux_div_main_~y~0_26)) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~y~0_33_70 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~z~0 (* aux_div_v_main_~y~0_32_31 4294967296) aux_mod_v_main_~y~0_32_31 (* aux_mod_main_~y~0_26 4294967295) (* 18446744069414584320 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_33_70 4294967296) aux_mod_v_main_~y~0_33_70))))))))))} is VALID [2022-04-27 16:45:07,216 INFO L290 TraceCheckUtils]: 7: Hoare triple {762#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {762#true} is VALID [2022-04-27 16:45:07,216 INFO L290 TraceCheckUtils]: 6: Hoare triple {762#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:45:07,216 INFO L290 TraceCheckUtils]: 5: Hoare triple {762#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {762#true} is VALID [2022-04-27 16:45:07,216 INFO L272 TraceCheckUtils]: 4: Hoare triple {762#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:45:07,216 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {762#true} {762#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:45:07,216 INFO L290 TraceCheckUtils]: 2: Hoare triple {762#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:45:07,217 INFO L290 TraceCheckUtils]: 1: Hoare triple {762#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {762#true} is VALID [2022-04-27 16:45:07,217 INFO L272 TraceCheckUtils]: 0: Hoare triple {762#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {762#true} is VALID [2022-04-27 16:45:07,217 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 2 not checked. [2022-04-27 16:45:07,217 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1960660802] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:45:07,217 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:45:07,217 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 8] total 16 [2022-04-27 16:45:07,217 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [630978342] [2022-04-27 16:45:07,218 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:45:07,218 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:07,218 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:45:07,218 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:13,731 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 34 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:13,731 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 16:45:13,731 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:45:13,731 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 16:45:13,732 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=162, Unknown=6, NotChecked=26, Total=240 [2022-04-27 16:45:13,732 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. Second operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:32,633 WARN L232 SmtUtils]: Spent 16.11s on a formula simplification. DAG size of input: 79 DAG size of output: 76 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:45:33,021 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:33,021 INFO L93 Difference]: Finished difference Result 42 states and 59 transitions. [2022-04-27 16:45:33,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:45:33,022 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:33,022 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:45:33,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 51 transitions. [2022-04-27 16:45:33,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 51 transitions. [2022-04-27 16:45:33,024 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 51 transitions. [2022-04-27 16:45:33,101 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:33,102 INFO L225 Difference]: With dead ends: 42 [2022-04-27 16:45:33,102 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:45:33,103 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 31 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 1 IntricatePredicates, 1 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 35.2s TimeCoverageRelationStatistics Valid=113, Invalid=391, Unknown=6, NotChecked=42, Total=552 [2022-04-27 16:45:33,103 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 34 mSDsluCounter, 63 mSDsCounter, 0 mSdLazyCounter, 71 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 34 SdHoareTripleChecker+Valid, 75 SdHoareTripleChecker+Invalid, 130 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 71 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 45 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:45:33,103 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [34 Valid, 75 Invalid, 130 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 71 Invalid, 0 Unknown, 45 Unchecked, 0.2s Time] [2022-04-27 16:45:33,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:45:33,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 24. [2022-04-27 16:45:33,105 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:45:33,105 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,105 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,105 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:33,106 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:45:33,106 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:45:33,106 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:33,106 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:33,107 INFO L74 IsIncluded]: Start isIncluded. First operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:45:33,107 INFO L87 Difference]: Start difference. First operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 32 states. [2022-04-27 16:45:33,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:33,107 INFO L93 Difference]: Finished difference Result 32 states and 45 transitions. [2022-04-27 16:45:33,108 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 45 transitions. [2022-04-27 16:45:33,108 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:33,108 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:33,108 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:45:33,108 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:45:33,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 19 states have (on average 1.4736842105263157) internal successors, (28), 19 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 32 transitions. [2022-04-27 16:45:33,109 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 32 transitions. Word has length 18 [2022-04-27 16:45:33,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:45:33,109 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 32 transitions. [2022-04-27 16:45:33,109 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.9375) internal successors, (31), 13 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:33,109 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 32 transitions. [2022-04-27 16:45:33,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:45:33,109 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:33,109 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:33,129 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 16:45:33,310 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:33,310 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:33,310 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:33,310 INFO L85 PathProgramCache]: Analyzing trace with hash 760455623, now seen corresponding path program 1 times [2022-04-27 16:45:33,310 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:33,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [861682402] [2022-04-27 16:45:33,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:33,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:33,323 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:45:33,325 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:33,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:33,334 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:45:33,336 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:33,562 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:33,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:33,566 INFO L290 TraceCheckUtils]: 0: Hoare triple {1049#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1037#true} is VALID [2022-04-27 16:45:33,566 INFO L290 TraceCheckUtils]: 1: Hoare triple {1037#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:33,566 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1037#true} {1037#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:33,567 INFO L272 TraceCheckUtils]: 0: Hoare triple {1037#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1049#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:33,567 INFO L290 TraceCheckUtils]: 1: Hoare triple {1049#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1037#true} is VALID [2022-04-27 16:45:33,570 INFO L290 TraceCheckUtils]: 2: Hoare triple {1037#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:33,570 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1037#true} {1037#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:33,570 INFO L272 TraceCheckUtils]: 4: Hoare triple {1037#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:33,571 INFO L290 TraceCheckUtils]: 5: Hoare triple {1037#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1042#(= main_~y~0 0)} is VALID [2022-04-27 16:45:33,571 INFO L290 TraceCheckUtils]: 6: Hoare triple {1042#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1043#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:33,572 INFO L290 TraceCheckUtils]: 7: Hoare triple {1043#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1043#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:33,573 INFO L290 TraceCheckUtils]: 8: Hoare triple {1043#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1044#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:45:33,573 INFO L290 TraceCheckUtils]: 9: Hoare triple {1044#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1044#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:45:33,575 INFO L290 TraceCheckUtils]: 10: Hoare triple {1044#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1045#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:33,575 INFO L290 TraceCheckUtils]: 11: Hoare triple {1045#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1045#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:33,576 INFO L290 TraceCheckUtils]: 12: Hoare triple {1045#(and (<= 0 main_~y~0) (<= main_~y~0 0) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1046#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:45:33,577 INFO L290 TraceCheckUtils]: 13: Hoare triple {1046#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1046#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:45:33,578 INFO L272 TraceCheckUtils]: 14: Hoare triple {1046#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1047#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:45:33,578 INFO L290 TraceCheckUtils]: 15: Hoare triple {1047#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1048#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:45:33,578 INFO L290 TraceCheckUtils]: 16: Hoare triple {1048#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1038#false} is VALID [2022-04-27 16:45:33,579 INFO L290 TraceCheckUtils]: 17: Hoare triple {1038#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1038#false} is VALID [2022-04-27 16:45:33,579 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:33,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:33,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [861682402] [2022-04-27 16:45:33,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [861682402] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:45:33,580 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1905535681] [2022-04-27 16:45:33,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:33,580 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:33,580 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:45:33,581 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:45:33,582 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 16:45:33,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:33,613 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 16:45:33,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:33,626 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:45:34,350 INFO L272 TraceCheckUtils]: 0: Hoare triple {1037#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:34,350 INFO L290 TraceCheckUtils]: 1: Hoare triple {1037#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1037#true} is VALID [2022-04-27 16:45:34,350 INFO L290 TraceCheckUtils]: 2: Hoare triple {1037#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:34,352 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1037#true} {1037#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:34,352 INFO L272 TraceCheckUtils]: 4: Hoare triple {1037#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:45:34,352 INFO L290 TraceCheckUtils]: 5: Hoare triple {1037#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1037#true} is VALID [2022-04-27 16:45:34,352 INFO L290 TraceCheckUtils]: 6: Hoare triple {1037#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1071#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:34,353 INFO L290 TraceCheckUtils]: 7: Hoare triple {1071#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1071#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:34,353 INFO L290 TraceCheckUtils]: 8: Hoare triple {1071#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1078#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:34,353 INFO L290 TraceCheckUtils]: 9: Hoare triple {1078#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1082#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:34,355 INFO L290 TraceCheckUtils]: 10: Hoare triple {1082#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1086#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-27 16:45:34,355 INFO L290 TraceCheckUtils]: 11: Hoare triple {1086#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1086#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-27 16:45:34,356 INFO L290 TraceCheckUtils]: 12: Hoare triple {1086#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1093#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:45:34,356 INFO L290 TraceCheckUtils]: 13: Hoare triple {1093#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1093#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:45:34,357 INFO L272 TraceCheckUtils]: 14: Hoare triple {1093#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1100#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:34,357 INFO L290 TraceCheckUtils]: 15: Hoare triple {1100#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1104#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:34,358 INFO L290 TraceCheckUtils]: 16: Hoare triple {1104#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1038#false} is VALID [2022-04-27 16:45:34,358 INFO L290 TraceCheckUtils]: 17: Hoare triple {1038#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1038#false} is VALID [2022-04-27 16:45:34,358 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:34,358 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:45:46,984 WARN L855 $PredicateComparison]: unable to prove that (forall ((v_main_~x~0_22 Int) (|main_#t~post11| Int) (v_main_~y~0_37 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (let ((.cse1 (< 0 (mod c_main_~z~0 4294967296))) (.cse0 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31))) (and (or (not (= v_main_~y~0_37 .cse0)) .cse1) (or (not .cse1) (not (< .cse0 v_main_~y~0_37)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37)))))))) (let ((.cse2 (mod c_main_~x~0 4294967296))) (and (or (not (= v_main_~y~0_37 c_main_~y~0)) (not (<= .cse2 0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (= v_main_~x~0_22 c_main_~x~0)) (not (= |v_main_#t~post12_9| |main_#t~post12|))) (or (not (= v_main_~y~0_37 (+ (* (- 1) v_main_~x~0_22) c_main_~x~0 c_main_~y~0))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_main_~x~0_22 v_it_4 1) c_main_~x~0))) (not (< 0 .cse2)) (not (< v_main_~x~0_22 c_main_~x~0))))))) is different from true [2022-04-27 16:46:04,664 INFO L290 TraceCheckUtils]: 17: Hoare triple {1038#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1038#false} is VALID [2022-04-27 16:46:04,664 INFO L290 TraceCheckUtils]: 16: Hoare triple {1104#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1038#false} is VALID [2022-04-27 16:46:04,665 INFO L290 TraceCheckUtils]: 15: Hoare triple {1100#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1104#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:46:04,665 INFO L272 TraceCheckUtils]: 14: Hoare triple {1093#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1100#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:46:04,666 INFO L290 TraceCheckUtils]: 13: Hoare triple {1093#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1093#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:46:04,674 INFO L290 TraceCheckUtils]: 12: Hoare triple {1126#(forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1093#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:46:04,701 INFO L290 TraceCheckUtils]: 11: Hoare triple {1126#(forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1126#(forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))))} is VALID [2022-04-27 16:46:06,709 WARN L290 TraceCheckUtils]: 10: Hoare triple {1133#(forall ((v_main_~x~0_22 Int) (|main_#t~post11| Int) (v_main_~y~0_37 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (and (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_main_~x~0_22 v_it_4 1) main_~x~0))) (not (< v_main_~x~0_22 main_~x~0)) (not (< 0 (mod main_~x~0 4294967296))) (not (= (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_22)) v_main_~y~0_37))) (or (not (= v_main_~x~0_22 main_~x~0)) (not (= v_main_~y~0_37 main_~y~0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (<= (mod main_~x~0 4294967296) 0)) (not (= |v_main_#t~post12_9| |main_#t~post12|)))) (forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< 0 (mod main_~z~0 4294967296))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37)))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0)))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1126#(forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) main_~y~0))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) main_~y~0))))))} is UNKNOWN [2022-04-27 16:46:08,721 WARN L290 TraceCheckUtils]: 9: Hoare triple {1137#(forall ((aux_div_main_~y~0_26 Int) (aux_mod_v_main_~y~0_36_31 Int) (aux_mod_main_~y~0_26 Int) (v_main_~y~0_37 Int)) (or (< aux_mod_main_~y~0_26 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (< 0 aux_mod_main_~y~0_26) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= v_main_~y~0_37 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))))) (or (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_37)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (<= aux_mod_v_main_~y~0_36_31 0)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1133#(forall ((v_main_~x~0_22 Int) (|main_#t~post11| Int) (v_main_~y~0_37 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (and (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_main_~x~0_22 v_it_4 1) main_~x~0))) (not (< v_main_~x~0_22 main_~x~0)) (not (< 0 (mod main_~x~0 4294967296))) (not (= (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_22)) v_main_~y~0_37))) (or (not (= v_main_~x~0_22 main_~x~0)) (not (= v_main_~y~0_37 main_~y~0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (<= (mod main_~x~0 4294967296) 0)) (not (= |v_main_#t~post12_9| |main_#t~post12|)))) (forall ((aux_mod_v_main_~y~0_36_31 Int) (aux_div_v_main_~y~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< 0 (mod main_~z~0 4294967296))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37)))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (<= aux_mod_v_main_~y~0_36_31 0)))))} is UNKNOWN [2022-04-27 16:46:08,724 INFO L290 TraceCheckUtils]: 8: Hoare triple {1071#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1137#(forall ((aux_div_main_~y~0_26 Int) (aux_mod_v_main_~y~0_36_31 Int) (aux_mod_main_~y~0_26 Int) (v_main_~y~0_37 Int)) (or (< aux_mod_main_~y~0_26 0) (and (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_36_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_36_31 4294967296) v_it_5 aux_mod_v_main_~y~0_36_31 1) v_main_~y~0_37))) (not (< (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31) v_main_~y~0_37))))) (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_36_31 Int)) (not (= v_main_~y~0_37 (+ (* aux_div_v_main_~y~0_36_31 4294967296) aux_mod_v_main_~y~0_36_31)))))) (<= 4294967296 aux_mod_v_main_~y~0_36_31) (< 0 aux_mod_main_~y~0_26) (and (or (< 0 (mod main_~x~0 4294967296)) (not (= v_main_~y~0_37 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26))))) (or (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_37)) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_37) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (<= aux_mod_v_main_~y~0_36_31 0)))} is VALID [2022-04-27 16:46:08,724 INFO L290 TraceCheckUtils]: 7: Hoare triple {1071#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1071#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:08,725 INFO L290 TraceCheckUtils]: 6: Hoare triple {1037#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1071#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:08,725 INFO L290 TraceCheckUtils]: 5: Hoare triple {1037#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1037#true} is VALID [2022-04-27 16:46:08,725 INFO L272 TraceCheckUtils]: 4: Hoare triple {1037#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:46:08,725 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1037#true} {1037#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:46:08,725 INFO L290 TraceCheckUtils]: 2: Hoare triple {1037#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:46:08,725 INFO L290 TraceCheckUtils]: 1: Hoare triple {1037#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1037#true} is VALID [2022-04-27 16:46:08,725 INFO L272 TraceCheckUtils]: 0: Hoare triple {1037#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1037#true} is VALID [2022-04-27 16:46:08,726 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-27 16:46:08,726 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1905535681] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:46:08,726 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:46:08,726 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 20 [2022-04-27 16:46:08,726 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071799413] [2022-04-27 16:46:08,726 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:46:08,726 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:46:08,727 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:46:08,727 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:12,891 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 35 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:12,892 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-04-27 16:46:12,892 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:46:12,892 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-04-27 16:46:12,892 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=269, Unknown=5, NotChecked=34, Total=380 [2022-04-27 16:46:12,893 INFO L87 Difference]: Start difference. First operand 24 states and 32 transitions. Second operand has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,938 WARN L232 SmtUtils]: Spent 20.26s on a formula simplification. DAG size of input: 88 DAG size of output: 85 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:46:34,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:34,525 INFO L93 Difference]: Finished difference Result 41 states and 56 transitions. [2022-04-27 16:46:34,525 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-04-27 16:46:34,525 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:46:34,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:46:34,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 56 transitions. [2022-04-27 16:46:34,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 56 transitions. [2022-04-27 16:46:34,529 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 19 states and 56 transitions. [2022-04-27 16:46:34,603 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:34,604 INFO L225 Difference]: With dead ends: 41 [2022-04-27 16:46:34,604 INFO L226 Difference]: Without dead ends: 37 [2022-04-27 16:46:34,604 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 25 SyntacticMatches, 4 SemanticMatches, 30 ConstructedPredicates, 1 IntricatePredicates, 1 DeprecatedPredicates, 256 ImplicationChecksByTransitivity, 36.8s TimeCoverageRelationStatistics Valid=188, Invalid=741, Unknown=5, NotChecked=58, Total=992 [2022-04-27 16:46:34,605 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 28 mSDsluCounter, 72 mSDsCounter, 0 mSdLazyCounter, 106 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 28 SdHoareTripleChecker+Valid, 87 SdHoareTripleChecker+Invalid, 188 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 106 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 63 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:46:34,605 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [28 Valid, 87 Invalid, 188 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 106 Invalid, 0 Unknown, 63 Unchecked, 0.2s Time] [2022-04-27 16:46:34,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-27 16:46:34,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 26. [2022-04-27 16:46:34,606 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:46:34,606 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,607 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,607 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:34,608 INFO L93 Difference]: Finished difference Result 37 states and 51 transitions. [2022-04-27 16:46:34,608 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 51 transitions. [2022-04-27 16:46:34,608 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:46:34,608 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:46:34,608 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 37 states. [2022-04-27 16:46:34,608 INFO L87 Difference]: Start difference. First operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 37 states. [2022-04-27 16:46:34,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:34,609 INFO L93 Difference]: Finished difference Result 37 states and 51 transitions. [2022-04-27 16:46:34,609 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 51 transitions. [2022-04-27 16:46:34,609 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:46:34,609 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:46:34,609 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:46:34,609 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:46:34,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 21 states have (on average 1.4761904761904763) internal successors, (31), 21 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 35 transitions. [2022-04-27 16:46:34,610 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 35 transitions. Word has length 18 [2022-04-27 16:46:34,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:46:34,610 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 35 transitions. [2022-04-27 16:46:34,610 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 1.55) internal successors, (31), 17 states have internal predecessors, (31), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:34,610 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 35 transitions. [2022-04-27 16:46:34,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:46:34,611 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:46:34,611 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:46:34,630 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Ended with exit code 0 [2022-04-27 16:46:34,821 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:46:34,822 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:46:34,822 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:46:34,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1533442700, now seen corresponding path program 2 times [2022-04-27 16:46:34,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:46:34,822 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245815211] [2022-04-27 16:46:34,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:46:34,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:46:34,832 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:46:34,833 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_10 (* (- 4294967296) (div (+ .cse0 main_~x~0_10) 4294967296)))) 0)) [2022-04-27 16:46:34,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:34,848 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.2))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:46:34,851 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_10 (* (- 4294967296) (div (+ .cse0 main_~x~0_10) 4294967296)))) 0)) [2022-04-27 16:46:35,033 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:46:35,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:35,037 INFO L290 TraceCheckUtils]: 0: Hoare triple {1343#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-27 16:46:35,037 INFO L290 TraceCheckUtils]: 1: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,038 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,038 INFO L272 TraceCheckUtils]: 0: Hoare triple {1333#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1343#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:46:35,038 INFO L290 TraceCheckUtils]: 1: Hoare triple {1343#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-27 16:46:35,038 INFO L290 TraceCheckUtils]: 2: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,038 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,038 INFO L272 TraceCheckUtils]: 4: Hoare triple {1333#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,039 INFO L290 TraceCheckUtils]: 5: Hoare triple {1333#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1338#(= main_~y~0 0)} is VALID [2022-04-27 16:46:35,039 INFO L290 TraceCheckUtils]: 6: Hoare triple {1338#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:35,040 INFO L290 TraceCheckUtils]: 7: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:35,040 INFO L290 TraceCheckUtils]: 8: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:35,040 INFO L290 TraceCheckUtils]: 9: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:35,042 INFO L290 TraceCheckUtils]: 10: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:35,043 INFO L290 TraceCheckUtils]: 11: Hoare triple {1339#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:46:35,044 INFO L290 TraceCheckUtils]: 12: Hoare triple {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:46:35,044 INFO L290 TraceCheckUtils]: 13: Hoare triple {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:46:35,045 INFO L272 TraceCheckUtils]: 14: Hoare triple {1340#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1341#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:46:35,045 INFO L290 TraceCheckUtils]: 15: Hoare triple {1341#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1342#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:46:35,046 INFO L290 TraceCheckUtils]: 16: Hoare triple {1342#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-27 16:46:35,046 INFO L290 TraceCheckUtils]: 17: Hoare triple {1334#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-27 16:46:35,046 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:46:35,046 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:46:35,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1245815211] [2022-04-27 16:46:35,046 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1245815211] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:46:35,046 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2067270927] [2022-04-27 16:46:35,046 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:46:35,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:46:35,055 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:46:35,056 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:46:35,057 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 16:46:35,088 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:46:35,088 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:46:35,088 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 16:46:35,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:35,097 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:46:35,590 INFO L272 TraceCheckUtils]: 0: Hoare triple {1333#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,590 INFO L290 TraceCheckUtils]: 1: Hoare triple {1333#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-27 16:46:35,590 INFO L290 TraceCheckUtils]: 2: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,590 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,590 INFO L272 TraceCheckUtils]: 4: Hoare triple {1333#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:46:35,591 INFO L290 TraceCheckUtils]: 5: Hoare triple {1333#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1333#true} is VALID [2022-04-27 16:46:35,591 INFO L290 TraceCheckUtils]: 6: Hoare triple {1333#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1365#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,591 INFO L290 TraceCheckUtils]: 7: Hoare triple {1365#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1365#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,591 INFO L290 TraceCheckUtils]: 8: Hoare triple {1365#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1365#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,592 INFO L290 TraceCheckUtils]: 9: Hoare triple {1365#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:46:35,593 INFO L290 TraceCheckUtils]: 10: Hoare triple {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:46:35,594 INFO L290 TraceCheckUtils]: 11: Hoare triple {1375#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:46:35,594 INFO L290 TraceCheckUtils]: 12: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:46:35,594 INFO L290 TraceCheckUtils]: 13: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:46:35,595 INFO L272 TraceCheckUtils]: 14: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:46:35,595 INFO L290 TraceCheckUtils]: 15: Hoare triple {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1396#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:46:35,596 INFO L290 TraceCheckUtils]: 16: Hoare triple {1396#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-27 16:46:35,596 INFO L290 TraceCheckUtils]: 17: Hoare triple {1334#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-27 16:46:35,596 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:46:35,596 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:48:06,018 WARN L232 SmtUtils]: Spent 6.33s on a formula simplification that was a NOOP. DAG size: 77 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:48:28,306 INFO L290 TraceCheckUtils]: 17: Hoare triple {1334#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-27 16:48:28,306 INFO L290 TraceCheckUtils]: 16: Hoare triple {1396#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1334#false} is VALID [2022-04-27 16:48:28,307 INFO L290 TraceCheckUtils]: 15: Hoare triple {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1396#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:48:28,307 INFO L272 TraceCheckUtils]: 14: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1392#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:48:28,308 INFO L290 TraceCheckUtils]: 13: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:48:28,308 INFO L290 TraceCheckUtils]: 12: Hoare triple {1382#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:48:28,315 INFO L290 TraceCheckUtils]: 11: Hoare triple {1421#(forall ((aux_mod_v_main_~y~0_40_31 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31) (and (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)) (< 0 (mod main_~x~0 4294967296))))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1382#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:48:30,327 WARN L290 TraceCheckUtils]: 10: Hoare triple {1425#(forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)))) (or (forall ((v_main_~y~0_41 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_41))) (not (< main_~y~0 v_main_~y~0_41)) (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (or (forall ((aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))))))) (not (< 0 (mod main_~x~0 4294967296)))))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1421#(forall ((aux_mod_v_main_~y~0_40_31 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31) (and (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296)))) (or (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)) (< 0 (mod main_~x~0 4294967296))))))} is UNKNOWN [2022-04-27 16:48:32,436 WARN L290 TraceCheckUtils]: 9: Hoare triple {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1425#(forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31) (and (or (< 0 (mod main_~x~0 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) main_~y~0)))) (or (forall ((v_main_~y~0_41 Int)) (or (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4) (<= (+ v_it_4 main_~y~0 1) v_main_~y~0_41))) (not (< main_~y~0 v_main_~y~0_41)) (and (or (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_40_31 Int)) (not (= v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (or (forall ((aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~y~0_41 (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31))))) (not (< 0 (mod (+ main_~y~0 main_~x~0 (* v_main_~y~0_41 4294967295)) 4294967296))))))) (not (< 0 (mod main_~x~0 4294967296)))))))} is UNKNOWN [2022-04-27 16:48:34,593 WARN L290 TraceCheckUtils]: 8: Hoare triple {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} is UNKNOWN [2022-04-27 16:48:36,815 WARN L290 TraceCheckUtils]: 7: Hoare triple {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} is UNKNOWN [2022-04-27 16:48:36,819 INFO L290 TraceCheckUtils]: 6: Hoare triple {1333#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1429#(or (not (< 0 (mod main_~x~0 4294967296))) (forall ((aux_mod_v_main_~y~0_40_31 Int)) (or (and (forall ((aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_92 Int) (aux_div_aux_mod_main_~y~0_26_92 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (< aux_mod_aux_mod_main_~y~0_26_92 0) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296)) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26))) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_92 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) main_~x~0 (* aux_mod_v_main_~y~0_40_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (< (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92) (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0)) (< 0 aux_mod_aux_mod_main_~y~0_26_92) (< (+ (* 4294967295 aux_mod_v_main_~y~0_40_31) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_92 4294967296) aux_mod_aux_mod_main_~y~0_26_92)))) (forall ((v_main_~y~0_41 Int) (aux_div_main_~y~0_26 Int) (aux_mod_aux_mod_main_~y~0_26_81 Int) (aux_div_aux_mod_main_~y~0_26_81 Int) (aux_div_v_main_~y~0_40_31 Int)) (or (exists ((v_it_4 Int)) (and (<= (+ v_main_~y~0_41 v_it_4 1) (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31)) (<= 1 v_it_4) (not (< 0 (mod (+ (* v_it_4 4294967295) aux_mod_aux_mod_main_~y~0_26_81) 4294967296))))) (< (+ main_~x~0 (* v_main_~y~0_41 4294967295)) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81)) (<= (+ (* v_main_~y~0_41 4294967296) main_~x~0) (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26))) (< (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) aux_mod_aux_mod_main_~y~0_26_81) (+ main_~x~0 (* v_main_~y~0_41 4294967295))) (<= (+ (* aux_div_v_main_~y~0_40_31 4294967296) aux_mod_v_main_~y~0_40_31) v_main_~y~0_41) (exists ((v_it_4 Int)) (and (<= (+ (* aux_div_aux_mod_main_~y~0_26_81 4294967296) v_it_4 aux_mod_aux_mod_main_~y~0_26_81 (* 4294967296 aux_div_main_~y~0_26) 1) (+ (* v_main_~y~0_41 4294967296) main_~x~0)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= 4294967296 aux_mod_aux_mod_main_~y~0_26_81) (<= aux_mod_aux_mod_main_~y~0_26_81 0)))) (<= aux_mod_v_main_~y~0_40_31 0) (<= 4294967296 aux_mod_v_main_~y~0_40_31))))} is VALID [2022-04-27 16:48:36,820 INFO L290 TraceCheckUtils]: 5: Hoare triple {1333#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1333#true} is VALID [2022-04-27 16:48:36,820 INFO L272 TraceCheckUtils]: 4: Hoare triple {1333#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:48:36,820 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1333#true} {1333#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:48:36,820 INFO L290 TraceCheckUtils]: 2: Hoare triple {1333#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:48:36,820 INFO L290 TraceCheckUtils]: 1: Hoare triple {1333#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1333#true} is VALID [2022-04-27 16:48:36,820 INFO L272 TraceCheckUtils]: 0: Hoare triple {1333#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1333#true} is VALID [2022-04-27 16:48:36,820 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:48:36,821 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2067270927] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:48:36,821 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:48:36,821 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 8] total 16 [2022-04-27 16:48:36,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [72569420] [2022-04-27 16:48:36,821 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:48:36,822 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:48:36,822 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:48:36,822 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:45,400 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 34 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:45,400 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 16:48:45,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:48:45,400 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 16:48:45,400 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=176, Unknown=16, NotChecked=0, Total=240 [2022-04-27 16:48:45,401 INFO L87 Difference]: Start difference. First operand 26 states and 35 transitions. Second operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:02,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:49:02,934 INFO L93 Difference]: Finished difference Result 43 states and 60 transitions. [2022-04-27 16:49:02,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 16:49:02,934 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:49:02,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:49:02,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:02,935 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 52 transitions. [2022-04-27 16:49:02,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:02,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 52 transitions. [2022-04-27 16:49:02,937 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 52 transitions. [2022-04-27 16:49:02,987 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:49:02,995 INFO L225 Difference]: With dead ends: 43 [2022-04-27 16:49:02,995 INFO L226 Difference]: Without dead ends: 39 [2022-04-27 16:49:02,996 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 29 SyntacticMatches, 3 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 56.3s TimeCoverageRelationStatistics Valid=104, Invalid=380, Unknown=22, NotChecked=0, Total=506 [2022-04-27 16:49:02,997 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 34 mSDsluCounter, 63 mSDsCounter, 0 mSdLazyCounter, 79 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 34 SdHoareTripleChecker+Valid, 76 SdHoareTripleChecker+Invalid, 131 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 79 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 38 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:49:02,997 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [34 Valid, 76 Invalid, 131 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 79 Invalid, 0 Unknown, 38 Unchecked, 0.2s Time] [2022-04-27 16:49:02,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2022-04-27 16:49:03,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 27. [2022-04-27 16:49:03,002 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:49:03,002 INFO L82 GeneralOperation]: Start isEquivalent. First operand 39 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:03,002 INFO L74 IsIncluded]: Start isIncluded. First operand 39 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:03,002 INFO L87 Difference]: Start difference. First operand 39 states. Second operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:03,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:49:03,003 INFO L93 Difference]: Finished difference Result 39 states and 55 transitions. [2022-04-27 16:49:03,003 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 55 transitions. [2022-04-27 16:49:03,003 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:49:03,004 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:49:03,004 INFO L74 IsIncluded]: Start isIncluded. First operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 39 states. [2022-04-27 16:49:03,004 INFO L87 Difference]: Start difference. First operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 39 states. [2022-04-27 16:49:03,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:49:03,005 INFO L93 Difference]: Finished difference Result 39 states and 55 transitions. [2022-04-27 16:49:03,005 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 55 transitions. [2022-04-27 16:49:03,005 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:49:03,005 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:49:03,005 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:49:03,005 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:49:03,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 22 states have (on average 1.5) internal successors, (33), 22 states have internal predecessors, (33), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:03,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 37 transitions. [2022-04-27 16:49:03,006 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 37 transitions. Word has length 18 [2022-04-27 16:49:03,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:49:03,006 INFO L495 AbstractCegarLoop]: Abstraction has 27 states and 37 transitions. [2022-04-27 16:49:03,006 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 13 states have internal predecessors, (32), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:03,006 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 37 transitions. [2022-04-27 16:49:03,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:49:03,006 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:49:03,006 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:49:03,024 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2022-04-27 16:49:03,222 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:49:03,222 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:49:03,222 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:49:03,222 INFO L85 PathProgramCache]: Analyzing trace with hash 571694412, now seen corresponding path program 1 times [2022-04-27 16:49:03,223 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:49:03,223 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [991944578] [2022-04-27 16:49:03,223 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:49:03,223 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:49:03,230 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:49:03,231 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:49:03,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:49:03,242 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:49:03,246 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:49:03,449 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:49:03,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:49:03,457 INFO L290 TraceCheckUtils]: 0: Hoare triple {1632#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-27 16:49:03,458 INFO L290 TraceCheckUtils]: 1: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,458 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,458 INFO L272 TraceCheckUtils]: 0: Hoare triple {1622#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1632#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:49:03,458 INFO L290 TraceCheckUtils]: 1: Hoare triple {1632#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-27 16:49:03,458 INFO L290 TraceCheckUtils]: 2: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,458 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,458 INFO L272 TraceCheckUtils]: 4: Hoare triple {1622#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,459 INFO L290 TraceCheckUtils]: 5: Hoare triple {1622#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1627#(= main_~y~0 0)} is VALID [2022-04-27 16:49:03,459 INFO L290 TraceCheckUtils]: 6: Hoare triple {1627#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1627#(= main_~y~0 0)} is VALID [2022-04-27 16:49:03,459 INFO L290 TraceCheckUtils]: 7: Hoare triple {1627#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,460 INFO L290 TraceCheckUtils]: 8: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,461 INFO L290 TraceCheckUtils]: 9: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,462 INFO L290 TraceCheckUtils]: 10: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,462 INFO L290 TraceCheckUtils]: 11: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,465 INFO L290 TraceCheckUtils]: 12: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:49:03,466 INFO L290 TraceCheckUtils]: 13: Hoare triple {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:49:03,467 INFO L272 TraceCheckUtils]: 14: Hoare triple {1629#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1630#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:49:03,467 INFO L290 TraceCheckUtils]: 15: Hoare triple {1630#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1631#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:49:03,473 INFO L290 TraceCheckUtils]: 16: Hoare triple {1631#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-27 16:49:03,473 INFO L290 TraceCheckUtils]: 17: Hoare triple {1623#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-27 16:49:03,473 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:49:03,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:49:03,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [991944578] [2022-04-27 16:49:03,473 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [991944578] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:49:03,473 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [580177925] [2022-04-27 16:49:03,474 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:49:03,474 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:49:03,474 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:49:03,475 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:49:03,475 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 16:49:03,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:49:03,510 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 10 conjunts are in the unsatisfiable core [2022-04-27 16:49:03,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:49:03,525 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:49:03,698 INFO L272 TraceCheckUtils]: 0: Hoare triple {1622#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,698 INFO L290 TraceCheckUtils]: 1: Hoare triple {1622#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-27 16:49:03,698 INFO L290 TraceCheckUtils]: 2: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,698 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,698 INFO L272 TraceCheckUtils]: 4: Hoare triple {1622#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:03,698 INFO L290 TraceCheckUtils]: 5: Hoare triple {1622#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1627#(= main_~y~0 0)} is VALID [2022-04-27 16:49:03,699 INFO L290 TraceCheckUtils]: 6: Hoare triple {1627#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1627#(= main_~y~0 0)} is VALID [2022-04-27 16:49:03,699 INFO L290 TraceCheckUtils]: 7: Hoare triple {1627#(= main_~y~0 0)} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,699 INFO L290 TraceCheckUtils]: 8: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,700 INFO L290 TraceCheckUtils]: 9: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,700 INFO L290 TraceCheckUtils]: 10: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,701 INFO L290 TraceCheckUtils]: 11: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1628#(and (= main_~z~0 0) (= main_~y~0 0))} is VALID [2022-04-27 16:49:03,701 INFO L290 TraceCheckUtils]: 12: Hoare triple {1628#(and (= main_~z~0 0) (= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1627#(= main_~y~0 0)} is VALID [2022-04-27 16:49:03,702 INFO L290 TraceCheckUtils]: 13: Hoare triple {1627#(= main_~y~0 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1627#(= main_~y~0 0)} is VALID [2022-04-27 16:49:03,702 INFO L272 TraceCheckUtils]: 14: Hoare triple {1627#(= main_~y~0 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:49:03,702 INFO L290 TraceCheckUtils]: 15: Hoare triple {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1682#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:49:03,703 INFO L290 TraceCheckUtils]: 16: Hoare triple {1682#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-27 16:49:03,703 INFO L290 TraceCheckUtils]: 17: Hoare triple {1623#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-27 16:49:03,703 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:49:03,703 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:49:25,970 WARN L855 $PredicateComparison]: unable to prove that (or (not (< 0 (mod c_main_~y~0 4294967296))) (forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (and (or (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) c_main_~y~0)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) c_main_~y~0) (<= 1 v_it_3))))) (< 0 (mod (+ (* 4294967295 aux_mod_v_main_~y~0_44_31) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (let ((.cse0 (* 4294967296 aux_div_v_main_~z~0_34_31))) (or (<= 4294967296 aux_mod_v_main_~z~0_34_31) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ c_main_~y~0 c_main_~z~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= (+ .cse0 aux_mod_v_main_~z~0_34_31) c_main_~z~0) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)))) (<= (+ c_main_~y~0 c_main_~z~0) (+ .cse0 aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))))) (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31))) (< 0 (mod c_main_~z~0 4294967296))) is different from true [2022-04-27 16:49:26,008 INFO L290 TraceCheckUtils]: 17: Hoare triple {1623#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-27 16:49:26,009 INFO L290 TraceCheckUtils]: 16: Hoare triple {1682#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1623#false} is VALID [2022-04-27 16:49:26,009 INFO L290 TraceCheckUtils]: 15: Hoare triple {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1682#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:49:26,010 INFO L272 TraceCheckUtils]: 14: Hoare triple {1698#(= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1678#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:49:26,010 INFO L290 TraceCheckUtils]: 13: Hoare triple {1698#(= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1698#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:49:26,020 INFO L290 TraceCheckUtils]: 12: Hoare triple {1705#(forall ((aux_div_v_main_~y~0_44_31 Int) (aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31) (and (or (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (< 0 (mod main_~z~0 4294967296))) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))))))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {1698#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:49:26,021 INFO L290 TraceCheckUtils]: 11: Hoare triple {1705#(forall ((aux_div_v_main_~y~0_44_31 Int) (aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31) (and (or (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (< 0 (mod main_~z~0 4294967296))) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))))))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1705#(forall ((aux_div_v_main_~y~0_44_31 Int) (aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31) (and (or (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (< 0 (mod main_~z~0 4294967296))) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))))))} is VALID [2022-04-27 16:49:26,021 INFO L290 TraceCheckUtils]: 10: Hoare triple {1705#(forall ((aux_div_v_main_~y~0_44_31 Int) (aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31) (and (or (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (< 0 (mod main_~z~0 4294967296))) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1705#(forall ((aux_div_v_main_~y~0_44_31 Int) (aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31) (and (or (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (< 0 (mod main_~z~0 4294967296))) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))))))} is VALID [2022-04-27 16:49:28,034 WARN L290 TraceCheckUtils]: 9: Hoare triple {1715#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296)))))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))) (< 0 (mod main_~y~0 4294967296)))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1705#(forall ((aux_div_v_main_~y~0_44_31 Int) (aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31) (and (or (not (= (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (< 0 (mod main_~z~0 4294967296))) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))))))} is UNKNOWN [2022-04-27 16:49:30,054 WARN L290 TraceCheckUtils]: 8: Hoare triple {1719#(or (not (< 0 (mod main_~y~0 4294967296))) (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31))))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1715#(forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296)))))))))) (or (not (< 0 (mod main_~z~0 4294967296))) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0))))) (< 0 (mod main_~y~0 4294967296)))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31)))} is UNKNOWN [2022-04-27 16:49:30,056 INFO L290 TraceCheckUtils]: 7: Hoare triple {1622#true} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1719#(or (not (< 0 (mod main_~y~0 4294967296))) (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~y~0_44_31 Int)) (or (= aux_mod_v_main_~y~0_44_31 0) (and (forall ((aux_mod_v_main_~z~0_34_31 Int) (aux_div_v_main_~y~0_44_31 Int) (aux_div_v_main_~z~0_34_31 Int)) (or (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 main_~z~0 1) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31)) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31) main_~z~0) (exists ((v_it_5 Int)) (and (<= (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 v_it_5 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) (+ main_~z~0 main_~y~0)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~z~0_34_31 (* v_it_5 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_34_31) (<= (+ main_~z~0 main_~y~0) (+ (* 4294967296 aux_div_v_main_~z~0_34_31) aux_mod_v_main_~z~0_34_31 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31)) (<= aux_mod_v_main_~z~0_34_31 0))) (or (< 0 (mod (+ main_~z~0 main_~y~0 (* 4294967295 aux_mod_v_main_~y~0_44_31)) 4294967296)) (forall ((aux_div_v_main_~y~0_44_31 Int)) (or (not (< (+ (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_44_31 4294967296) aux_mod_v_main_~y~0_44_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))))) (>= aux_mod_v_main_~y~0_44_31 4294967296) (> 0 aux_mod_v_main_~y~0_44_31))))} is VALID [2022-04-27 16:49:30,056 INFO L290 TraceCheckUtils]: 6: Hoare triple {1622#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:30,056 INFO L290 TraceCheckUtils]: 5: Hoare triple {1622#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1622#true} is VALID [2022-04-27 16:49:30,056 INFO L272 TraceCheckUtils]: 4: Hoare triple {1622#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:30,056 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1622#true} {1622#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:30,056 INFO L290 TraceCheckUtils]: 2: Hoare triple {1622#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:30,056 INFO L290 TraceCheckUtils]: 1: Hoare triple {1622#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1622#true} is VALID [2022-04-27 16:49:30,056 INFO L272 TraceCheckUtils]: 0: Hoare triple {1622#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1622#true} is VALID [2022-04-27 16:49:30,057 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:49:30,057 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [580177925] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:49:30,057 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:49:30,057 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 8] total 14 [2022-04-27 16:49:30,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103483042] [2022-04-27 16:49:30,057 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:49:30,057 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:49:30,058 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:49:30,058 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:34,617 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 33 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-27 16:49:34,617 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:49:34,617 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:49:34,618 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:49:34,618 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=121, Unknown=4, NotChecked=22, Total=182 [2022-04-27 16:49:34,618 INFO L87 Difference]: Start difference. First operand 27 states and 37 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:49:53,312 WARN L232 SmtUtils]: Spent 10.14s on a formula simplification that was a NOOP. DAG size: 76 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:50:22,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:22,006 INFO L93 Difference]: Finished difference Result 45 states and 63 transitions. [2022-04-27 16:50:22,006 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:50:22,006 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:50:22,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:50:22,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:22,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 54 transitions. [2022-04-27 16:50:22,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:22,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 54 transitions. [2022-04-27 16:50:22,015 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 54 transitions. [2022-04-27 16:50:28,401 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 51 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:50:28,402 INFO L225 Difference]: With dead ends: 45 [2022-04-27 16:50:28,402 INFO L226 Difference]: Without dead ends: 41 [2022-04-27 16:50:28,402 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 32 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 50.1s TimeCoverageRelationStatistics Valid=91, Invalid=318, Unknown=15, NotChecked=38, Total=462 [2022-04-27 16:50:28,403 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 32 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 61 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 60 SdHoareTripleChecker+Invalid, 149 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 61 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 75 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:50:28,403 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 60 Invalid, 149 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 61 Invalid, 0 Unknown, 75 Unchecked, 0.1s Time] [2022-04-27 16:50:28,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states. [2022-04-27 16:50:28,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 34. [2022-04-27 16:50:28,405 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:50:28,405 INFO L82 GeneralOperation]: Start isEquivalent. First operand 41 states. Second operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:28,405 INFO L74 IsIncluded]: Start isIncluded. First operand 41 states. Second operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:28,405 INFO L87 Difference]: Start difference. First operand 41 states. Second operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:28,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:28,406 INFO L93 Difference]: Finished difference Result 41 states and 58 transitions. [2022-04-27 16:50:28,406 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 58 transitions. [2022-04-27 16:50:28,406 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:50:28,406 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:50:28,406 INFO L74 IsIncluded]: Start isIncluded. First operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 41 states. [2022-04-27 16:50:28,406 INFO L87 Difference]: Start difference. First operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 41 states. [2022-04-27 16:50:28,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:28,407 INFO L93 Difference]: Finished difference Result 41 states and 58 transitions. [2022-04-27 16:50:28,407 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 58 transitions. [2022-04-27 16:50:28,407 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:50:28,407 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:50:28,408 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:50:28,408 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:50:28,408 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 29 states have (on average 1.5862068965517242) internal successors, (46), 29 states have internal predecessors, (46), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:28,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 50 transitions. [2022-04-27 16:50:28,408 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 50 transitions. Word has length 18 [2022-04-27 16:50:28,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:50:28,408 INFO L495 AbstractCegarLoop]: Abstraction has 34 states and 50 transitions. [2022-04-27 16:50:28,409 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:28,409 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 50 transitions. [2022-04-27 16:50:28,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:50:28,409 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:50:28,409 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:50:28,424 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2022-04-27 16:50:28,623 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:50:28,623 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:50:28,624 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:50:28,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1344681489, now seen corresponding path program 1 times [2022-04-27 16:50:28,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:50:28,624 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864136709] [2022-04-27 16:50:28,624 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:50:28,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:50:28,634 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:28,636 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:50:28,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:28,650 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:28,651 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:50:28,809 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:50:28,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:28,814 INFO L290 TraceCheckUtils]: 0: Hoare triple {1935#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-27 16:50:28,814 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:28,814 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:28,818 INFO L272 TraceCheckUtils]: 0: Hoare triple {1925#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1935#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:50:28,818 INFO L290 TraceCheckUtils]: 1: Hoare triple {1935#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-27 16:50:28,818 INFO L290 TraceCheckUtils]: 2: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:28,819 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:28,819 INFO L272 TraceCheckUtils]: 4: Hoare triple {1925#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:28,819 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1930#(= main_~y~0 0)} is VALID [2022-04-27 16:50:28,820 INFO L290 TraceCheckUtils]: 6: Hoare triple {1930#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:28,820 INFO L290 TraceCheckUtils]: 7: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:28,820 INFO L290 TraceCheckUtils]: 8: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:28,821 INFO L290 TraceCheckUtils]: 9: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:28,822 INFO L290 TraceCheckUtils]: 10: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:28,823 INFO L290 TraceCheckUtils]: 11: Hoare triple {1931#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:28,824 INFO L290 TraceCheckUtils]: 12: Hoare triple {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:28,824 INFO L290 TraceCheckUtils]: 13: Hoare triple {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:28,825 INFO L272 TraceCheckUtils]: 14: Hoare triple {1932#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1933#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:50:28,825 INFO L290 TraceCheckUtils]: 15: Hoare triple {1933#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1934#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:50:28,825 INFO L290 TraceCheckUtils]: 16: Hoare triple {1934#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-27 16:50:28,826 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-27 16:50:28,826 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:50:28,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:50:28,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864136709] [2022-04-27 16:50:28,826 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864136709] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:50:28,826 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [714541493] [2022-04-27 16:50:28,826 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:50:28,826 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:50:28,826 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:50:28,827 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:50:28,827 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 16:50:28,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:28,863 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:50:28,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:28,872 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:50:29,396 INFO L272 TraceCheckUtils]: 0: Hoare triple {1925#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:29,396 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-27 16:50:29,396 INFO L290 TraceCheckUtils]: 2: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:29,397 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:29,397 INFO L272 TraceCheckUtils]: 4: Hoare triple {1925#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:29,397 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1925#true} is VALID [2022-04-27 16:50:29,397 INFO L290 TraceCheckUtils]: 6: Hoare triple {1925#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:29,400 INFO L290 TraceCheckUtils]: 7: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:29,400 INFO L290 TraceCheckUtils]: 8: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:29,401 INFO L290 TraceCheckUtils]: 9: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:29,401 INFO L290 TraceCheckUtils]: 10: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1970#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:50:29,402 INFO L290 TraceCheckUtils]: 11: Hoare triple {1970#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:29,403 INFO L290 TraceCheckUtils]: 12: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:29,403 INFO L290 TraceCheckUtils]: 13: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:29,403 INFO L272 TraceCheckUtils]: 14: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:50:29,404 INFO L290 TraceCheckUtils]: 15: Hoare triple {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1988#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:50:29,404 INFO L290 TraceCheckUtils]: 16: Hoare triple {1988#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-27 16:50:29,404 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-27 16:50:29,404 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:50:29,404 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:50:38,515 INFO L290 TraceCheckUtils]: 17: Hoare triple {1926#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-27 16:50:38,516 INFO L290 TraceCheckUtils]: 16: Hoare triple {1988#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1926#false} is VALID [2022-04-27 16:50:38,516 INFO L290 TraceCheckUtils]: 15: Hoare triple {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1988#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:50:38,517 INFO L272 TraceCheckUtils]: 14: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {1984#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:50:38,517 INFO L290 TraceCheckUtils]: 13: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:38,518 INFO L290 TraceCheckUtils]: 12: Hoare triple {1974#(<= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:38,528 INFO L290 TraceCheckUtils]: 11: Hoare triple {2013#(forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~y~0_47_31 Int)) (or (and (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31))) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))) (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31))))) (<= 4294967296 aux_mod_v_main_~y~0_47_31) (<= aux_mod_v_main_~y~0_47_31 0)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1974#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:38,535 INFO L290 TraceCheckUtils]: 10: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2013#(forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~y~0_47_31 Int)) (or (and (or (not (< main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31))) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4)))) (or (< 0 (mod main_~x~0 4294967296)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31))))) (<= 4294967296 aux_mod_v_main_~y~0_47_31) (<= aux_mod_v_main_~y~0_47_31 0)))} is VALID [2022-04-27 16:50:38,535 INFO L290 TraceCheckUtils]: 9: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [101] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_4 4294967296))) (or (and (= (+ (* (- 1) v_main_~y~0_3) v_main_~y~0_4 v_main_~z~0_3) v_main_~z~0_2) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_4 (* v_it_3 4294967295)) 4294967296)) (not (<= (+ v_main_~y~0_3 v_it_3 1) v_main_~y~0_4)))) (< v_main_~y~0_3 v_main_~y~0_4)) (and (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= v_main_~y~0_4 v_main_~y~0_3) (<= .cse0 0) (= |v_main_#t~post9_3| |v_main_#t~post9_1|)))) InVars {main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_3, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:38,535 INFO L290 TraceCheckUtils]: 8: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:38,535 INFO L290 TraceCheckUtils]: 7: Hoare triple {1957#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:38,536 INFO L290 TraceCheckUtils]: 6: Hoare triple {1925#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {1957#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:38,536 INFO L290 TraceCheckUtils]: 5: Hoare triple {1925#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1925#true} is VALID [2022-04-27 16:50:38,536 INFO L272 TraceCheckUtils]: 4: Hoare triple {1925#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:38,536 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1925#true} {1925#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:38,536 INFO L290 TraceCheckUtils]: 2: Hoare triple {1925#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:38,536 INFO L290 TraceCheckUtils]: 1: Hoare triple {1925#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1925#true} is VALID [2022-04-27 16:50:38,536 INFO L272 TraceCheckUtils]: 0: Hoare triple {1925#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1925#true} is VALID [2022-04-27 16:50:38,536 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:50:38,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [714541493] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:50:38,537 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:50:38,537 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 16:50:38,537 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087873191] [2022-04-27 16:50:38,537 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:50:38,537 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:50:38,537 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:50:38,538 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:38,632 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:50:38,633 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:50:38,633 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:50:38,633 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:50:38,633 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=141, Unknown=2, NotChecked=0, Total=182 [2022-04-27 16:50:38,633 INFO L87 Difference]: Start difference. First operand 34 states and 50 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:39,605 INFO L93 Difference]: Finished difference Result 53 states and 77 transitions. [2022-04-27 16:50:39,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-04-27 16:50:39,606 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:50:39,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:50:39,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 60 transitions. [2022-04-27 16:50:39,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 60 transitions. [2022-04-27 16:50:39,608 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 15 states and 60 transitions. [2022-04-27 16:50:39,667 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:50:39,667 INFO L225 Difference]: With dead ends: 53 [2022-04-27 16:50:39,667 INFO L226 Difference]: Without dead ends: 49 [2022-04-27 16:50:39,668 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 32 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 7.9s TimeCoverageRelationStatistics Valid=98, Invalid=362, Unknown=2, NotChecked=0, Total=462 [2022-04-27 16:50:39,668 INFO L413 NwaCegarLoop]: 17 mSDtfsCounter, 40 mSDsluCounter, 41 mSDsCounter, 0 mSdLazyCounter, 70 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 58 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 70 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 23 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:50:39,668 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 58 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 70 Invalid, 0 Unknown, 23 Unchecked, 0.2s Time] [2022-04-27 16:50:39,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-04-27 16:50:39,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 36. [2022-04-27 16:50:39,670 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:50:39,670 INFO L82 GeneralOperation]: Start isEquivalent. First operand 49 states. Second operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,670 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,670 INFO L87 Difference]: Start difference. First operand 49 states. Second operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:39,672 INFO L93 Difference]: Finished difference Result 49 states and 72 transitions. [2022-04-27 16:50:39,672 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 72 transitions. [2022-04-27 16:50:39,672 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:50:39,672 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:50:39,672 INFO L74 IsIncluded]: Start isIncluded. First operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 49 states. [2022-04-27 16:50:39,672 INFO L87 Difference]: Start difference. First operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 49 states. [2022-04-27 16:50:39,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:39,673 INFO L93 Difference]: Finished difference Result 49 states and 72 transitions. [2022-04-27 16:50:39,673 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 72 transitions. [2022-04-27 16:50:39,673 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:50:39,673 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:50:39,673 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:50:39,673 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:50:39,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 31 states have (on average 1.6129032258064515) internal successors, (50), 31 states have internal predecessors, (50), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 54 transitions. [2022-04-27 16:50:39,674 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 54 transitions. Word has length 18 [2022-04-27 16:50:39,674 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:50:39,674 INFO L495 AbstractCegarLoop]: Abstraction has 36 states and 54 transitions. [2022-04-27 16:50:39,675 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:39,675 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 54 transitions. [2022-04-27 16:50:39,675 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:50:39,675 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:50:39,675 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:50:39,691 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Ended with exit code 0 [2022-04-27 16:50:39,883 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:50:39,884 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:50:39,884 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:50:39,884 INFO L85 PathProgramCache]: Analyzing trace with hash -211948756, now seen corresponding path program 1 times [2022-04-27 16:50:39,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:50:39,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [4438936] [2022-04-27 16:50:39,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:50:39,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:50:39,892 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:39,893 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-27 16:50:39,898 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:39,904 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.2))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:39,908 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_8 (* (- 4294967296) (div (+ .cse0 main_~x~0_8) 4294967296)))) 0)) [2022-04-27 16:50:40,162 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:50:40,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:40,166 INFO L290 TraceCheckUtils]: 0: Hoare triple {2266#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-27 16:50:40,166 INFO L290 TraceCheckUtils]: 1: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,166 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,167 INFO L272 TraceCheckUtils]: 0: Hoare triple {2255#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2266#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:50:40,167 INFO L290 TraceCheckUtils]: 1: Hoare triple {2266#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-27 16:50:40,167 INFO L290 TraceCheckUtils]: 2: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,167 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,167 INFO L272 TraceCheckUtils]: 4: Hoare triple {2255#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,168 INFO L290 TraceCheckUtils]: 5: Hoare triple {2255#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2260#(= main_~y~0 0)} is VALID [2022-04-27 16:50:40,169 INFO L290 TraceCheckUtils]: 6: Hoare triple {2260#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,169 INFO L290 TraceCheckUtils]: 7: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,171 INFO L290 TraceCheckUtils]: 8: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,171 INFO L290 TraceCheckUtils]: 9: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,171 INFO L290 TraceCheckUtils]: 10: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,174 INFO L290 TraceCheckUtils]: 11: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:40,174 INFO L290 TraceCheckUtils]: 12: Hoare triple {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:40,175 INFO L290 TraceCheckUtils]: 13: Hoare triple {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:40,176 INFO L272 TraceCheckUtils]: 14: Hoare triple {2263#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2264#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:50:40,176 INFO L290 TraceCheckUtils]: 15: Hoare triple {2264#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2265#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:50:40,176 INFO L290 TraceCheckUtils]: 16: Hoare triple {2265#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-27 16:50:40,176 INFO L290 TraceCheckUtils]: 17: Hoare triple {2256#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-27 16:50:40,176 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:50:40,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:50:40,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [4438936] [2022-04-27 16:50:40,177 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [4438936] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:50:40,177 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1858582912] [2022-04-27 16:50:40,177 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:50:40,177 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:50:40,177 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:50:40,178 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:50:40,178 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 16:50:40,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:40,205 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-27 16:50:40,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:40,214 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:50:40,710 INFO L272 TraceCheckUtils]: 0: Hoare triple {2255#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,710 INFO L290 TraceCheckUtils]: 1: Hoare triple {2255#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-27 16:50:40,710 INFO L290 TraceCheckUtils]: 2: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,710 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,710 INFO L272 TraceCheckUtils]: 4: Hoare triple {2255#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:40,710 INFO L290 TraceCheckUtils]: 5: Hoare triple {2255#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2260#(= main_~y~0 0)} is VALID [2022-04-27 16:50:40,711 INFO L290 TraceCheckUtils]: 6: Hoare triple {2260#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,711 INFO L290 TraceCheckUtils]: 7: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,713 INFO L290 TraceCheckUtils]: 8: Hoare triple {2262#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,713 INFO L290 TraceCheckUtils]: 9: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,713 INFO L290 TraceCheckUtils]: 10: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:40,714 INFO L290 TraceCheckUtils]: 11: Hoare triple {2261#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2260#(= main_~y~0 0)} is VALID [2022-04-27 16:50:40,715 INFO L290 TraceCheckUtils]: 12: Hoare triple {2260#(= main_~y~0 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2260#(= main_~y~0 0)} is VALID [2022-04-27 16:50:40,715 INFO L290 TraceCheckUtils]: 13: Hoare triple {2260#(= main_~y~0 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2260#(= main_~y~0 0)} is VALID [2022-04-27 16:50:40,716 INFO L272 TraceCheckUtils]: 14: Hoare triple {2260#(= main_~y~0 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:50:40,716 INFO L290 TraceCheckUtils]: 15: Hoare triple {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2316#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:50:40,716 INFO L290 TraceCheckUtils]: 16: Hoare triple {2316#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-27 16:50:40,717 INFO L290 TraceCheckUtils]: 17: Hoare triple {2256#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-27 16:50:40,717 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:50:40,717 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:50:43,396 INFO L290 TraceCheckUtils]: 17: Hoare triple {2256#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-27 16:50:43,397 INFO L290 TraceCheckUtils]: 16: Hoare triple {2316#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2256#false} is VALID [2022-04-27 16:50:43,397 INFO L290 TraceCheckUtils]: 15: Hoare triple {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2316#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:50:43,398 INFO L272 TraceCheckUtils]: 14: Hoare triple {2332#(= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2312#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:50:43,398 INFO L290 TraceCheckUtils]: 13: Hoare triple {2332#(= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2332#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:43,398 INFO L290 TraceCheckUtils]: 12: Hoare triple {2332#(= (mod main_~y~0 4294967296) 0)} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2332#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:43,418 INFO L290 TraceCheckUtils]: 11: Hoare triple {2342#(forall ((aux_mod_v_main_~y~0_50_31 Int) (aux_div_v_main_~y~0_50_31 Int)) (or (> 0 aux_mod_v_main_~y~0_50_31) (= aux_mod_v_main_~y~0_50_31 0) (and (or (not (= (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)) main_~y~0)) (< 0 (mod main_~x~0 4294967296))) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)))))) (>= aux_mod_v_main_~y~0_50_31 4294967296)))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2332#(= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:43,419 INFO L290 TraceCheckUtils]: 10: Hoare triple {2346#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2342#(forall ((aux_mod_v_main_~y~0_50_31 Int) (aux_div_v_main_~y~0_50_31 Int)) (or (> 0 aux_mod_v_main_~y~0_50_31) (= aux_mod_v_main_~y~0_50_31 0) (and (or (not (= (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)) main_~y~0)) (< 0 (mod main_~x~0 4294967296))) (or (exists ((v_it_4 Int)) (and (<= (+ v_it_4 main_~y~0 1) (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296))) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))) (not (< main_~y~0 (+ aux_mod_v_main_~y~0_50_31 (* aux_div_v_main_~y~0_50_31 4294967296)))))) (>= aux_mod_v_main_~y~0_50_31 4294967296)))} is VALID [2022-04-27 16:50:43,420 INFO L290 TraceCheckUtils]: 9: Hoare triple {2346#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2346#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:50:45,431 WARN L290 TraceCheckUtils]: 8: Hoare triple {2353#(or (forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))) (<= 1 v_it_2))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31))) (< 0 (mod main_~y~0 4294967296)))} [98] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (= v_main_~x~0_9 v_main_~x~0_8) (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)) (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= (+ v_main_~x~0_9 v_main_~z~0_8 (* (- 1) v_main_~z~0_7)) v_main_~x~0_8) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)))) InVars {main_~x~0=v_main_~x~0_9, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_8, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2346#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:50:45,432 INFO L290 TraceCheckUtils]: 7: Hoare triple {2346#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2353#(or (forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (exists ((v_it_2 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_2 4294967295)) 4294967296))) (<= (+ v_it_2 main_~x~0 1) (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296))) (<= 1 v_it_2))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))))) (<= 4294967296 aux_mod_v_main_~x~0_32_31))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:50:45,433 INFO L290 TraceCheckUtils]: 6: Hoare triple {2255#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2346#(or (not (< 0 (mod main_~x~0 4294967296))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:50:45,433 INFO L290 TraceCheckUtils]: 5: Hoare triple {2255#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2255#true} is VALID [2022-04-27 16:50:45,433 INFO L272 TraceCheckUtils]: 4: Hoare triple {2255#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:45,433 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2255#true} {2255#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:45,433 INFO L290 TraceCheckUtils]: 2: Hoare triple {2255#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:45,433 INFO L290 TraceCheckUtils]: 1: Hoare triple {2255#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2255#true} is VALID [2022-04-27 16:50:45,433 INFO L272 TraceCheckUtils]: 0: Hoare triple {2255#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2255#true} is VALID [2022-04-27 16:50:45,433 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:50:45,434 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1858582912] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:50:45,434 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:50:45,434 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7, 8] total 15 [2022-04-27 16:50:45,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2075322392] [2022-04-27 16:50:45,434 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:50:45,434 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:50:45,434 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:50:45,434 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:45,527 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 39 edges. 39 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:50:45,527 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-04-27 16:50:45,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:50:45,527 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-04-27 16:50:45,527 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=165, Unknown=0, NotChecked=0, Total=210 [2022-04-27 16:50:45,528 INFO L87 Difference]: Start difference. First operand 36 states and 54 transitions. Second operand has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:46,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:46,876 INFO L93 Difference]: Finished difference Result 58 states and 86 transitions. [2022-04-27 16:50:46,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-04-27 16:50:46,876 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:50:46,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:50:46,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:46,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 57 transitions. [2022-04-27 16:50:46,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:46,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 57 transitions. [2022-04-27 16:50:46,878 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 17 states and 57 transitions. [2022-04-27 16:50:46,997 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:50:46,998 INFO L225 Difference]: With dead ends: 58 [2022-04-27 16:50:46,998 INFO L226 Difference]: Without dead ends: 54 [2022-04-27 16:50:46,998 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 31 SyntacticMatches, 5 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 137 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=127, Invalid=473, Unknown=0, NotChecked=0, Total=600 [2022-04-27 16:50:46,999 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 34 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 67 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 34 SdHoareTripleChecker+Valid, 61 SdHoareTripleChecker+Invalid, 125 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 67 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 43 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:50:46,999 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [34 Valid, 61 Invalid, 125 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 67 Invalid, 0 Unknown, 43 Unchecked, 0.2s Time] [2022-04-27 16:50:46,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2022-04-27 16:50:47,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 40. [2022-04-27 16:50:47,001 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:50:47,001 INFO L82 GeneralOperation]: Start isEquivalent. First operand 54 states. Second operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:47,001 INFO L74 IsIncluded]: Start isIncluded. First operand 54 states. Second operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:47,001 INFO L87 Difference]: Start difference. First operand 54 states. Second operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:47,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:47,002 INFO L93 Difference]: Finished difference Result 54 states and 81 transitions. [2022-04-27 16:50:47,003 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 81 transitions. [2022-04-27 16:50:47,003 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:50:47,003 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:50:47,003 INFO L74 IsIncluded]: Start isIncluded. First operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 54 states. [2022-04-27 16:50:47,003 INFO L87 Difference]: Start difference. First operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 54 states. [2022-04-27 16:50:47,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:50:47,004 INFO L93 Difference]: Finished difference Result 54 states and 81 transitions. [2022-04-27 16:50:47,004 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 81 transitions. [2022-04-27 16:50:47,004 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:50:47,004 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:50:47,004 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:50:47,004 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:50:47,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 35 states have (on average 1.6285714285714286) internal successors, (57), 35 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:47,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 61 transitions. [2022-04-27 16:50:47,005 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 61 transitions. Word has length 18 [2022-04-27 16:50:47,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:50:47,005 INFO L495 AbstractCegarLoop]: Abstraction has 40 states and 61 transitions. [2022-04-27 16:50:47,006 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 2.1333333333333333) internal successors, (32), 12 states have internal predecessors, (32), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:50:47,006 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 61 transitions. [2022-04-27 16:50:47,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:50:47,006 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:50:47,006 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:50:47,022 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-27 16:50:47,220 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable9 [2022-04-27 16:50:47,220 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:50:47,220 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:50:47,220 INFO L85 PathProgramCache]: Analyzing trace with hash 2126008490, now seen corresponding path program 2 times [2022-04-27 16:50:47,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:50:47,221 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962515692] [2022-04-27 16:50:47,221 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:50:47,221 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:50:47,231 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:50:47,232 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:47,232 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_12 .cse0 (* (- 4294967296) (div (+ main_~z~0_12 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:47,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:47,249 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.3))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:50:47,250 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.4))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:47,252 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_12 .cse0 (* (- 4294967296) (div (+ main_~z~0_12 .cse0) 4294967296)))) 0)) [2022-04-27 16:50:47,546 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:50:47,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:47,550 INFO L290 TraceCheckUtils]: 0: Hoare triple {2620#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2608#true} is VALID [2022-04-27 16:50:47,550 INFO L290 TraceCheckUtils]: 1: Hoare triple {2608#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:47,550 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2608#true} {2608#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:47,550 INFO L272 TraceCheckUtils]: 0: Hoare triple {2608#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2620#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:50:47,551 INFO L290 TraceCheckUtils]: 1: Hoare triple {2620#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2608#true} is VALID [2022-04-27 16:50:47,551 INFO L290 TraceCheckUtils]: 2: Hoare triple {2608#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:47,551 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2608#true} {2608#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:47,551 INFO L272 TraceCheckUtils]: 4: Hoare triple {2608#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:47,551 INFO L290 TraceCheckUtils]: 5: Hoare triple {2608#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2613#(= main_~y~0 0)} is VALID [2022-04-27 16:50:47,552 INFO L290 TraceCheckUtils]: 6: Hoare triple {2613#(= main_~y~0 0)} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2614#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:47,553 INFO L290 TraceCheckUtils]: 7: Hoare triple {2614#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2615#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:47,553 INFO L290 TraceCheckUtils]: 8: Hoare triple {2615#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2615#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:47,553 INFO L290 TraceCheckUtils]: 9: Hoare triple {2615#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2615#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:50:47,555 INFO L290 TraceCheckUtils]: 10: Hoare triple {2615#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2616#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} is VALID [2022-04-27 16:50:47,555 INFO L290 TraceCheckUtils]: 11: Hoare triple {2616#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2616#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} is VALID [2022-04-27 16:50:47,556 INFO L290 TraceCheckUtils]: 12: Hoare triple {2616#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2616#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} is VALID [2022-04-27 16:50:47,557 INFO L290 TraceCheckUtils]: 13: Hoare triple {2616#(and (<= 0 main_~y~0) (= main_~z~0 0) (<= main_~y~0 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2617#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:47,558 INFO L290 TraceCheckUtils]: 14: Hoare triple {2617#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2617#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:50:47,559 INFO L272 TraceCheckUtils]: 15: Hoare triple {2617#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2618#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:50:47,559 INFO L290 TraceCheckUtils]: 16: Hoare triple {2618#(not (= |__VERIFIER_assert_#in~cond| 0))} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2619#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:50:47,559 INFO L290 TraceCheckUtils]: 17: Hoare triple {2619#(not (= __VERIFIER_assert_~cond 0))} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2609#false} is VALID [2022-04-27 16:50:47,559 INFO L290 TraceCheckUtils]: 18: Hoare triple {2609#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2609#false} is VALID [2022-04-27 16:50:47,559 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:50:47,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:50:47,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [962515692] [2022-04-27 16:50:47,560 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [962515692] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:50:47,560 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1731986120] [2022-04-27 16:50:47,560 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:50:47,560 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:50:47,560 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:50:47,561 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:50:47,562 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 16:50:47,593 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:50:47,593 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:50:47,593 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-27 16:50:47,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:50:47,605 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:50:48,427 INFO L272 TraceCheckUtils]: 0: Hoare triple {2608#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:48,427 INFO L290 TraceCheckUtils]: 1: Hoare triple {2608#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2608#true} is VALID [2022-04-27 16:50:48,427 INFO L290 TraceCheckUtils]: 2: Hoare triple {2608#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:48,427 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2608#true} {2608#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:48,427 INFO L272 TraceCheckUtils]: 4: Hoare triple {2608#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:50:48,427 INFO L290 TraceCheckUtils]: 5: Hoare triple {2608#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2608#true} is VALID [2022-04-27 16:50:48,428 INFO L290 TraceCheckUtils]: 6: Hoare triple {2608#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2642#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:48,428 INFO L290 TraceCheckUtils]: 7: Hoare triple {2642#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2642#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:48,428 INFO L290 TraceCheckUtils]: 8: Hoare triple {2642#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2649#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:50:48,429 INFO L290 TraceCheckUtils]: 9: Hoare triple {2649#(and (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2653#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} is VALID [2022-04-27 16:50:48,430 INFO L290 TraceCheckUtils]: 10: Hoare triple {2653#(and (not (< 0 (mod main_~y~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))) (not (< 0 (mod main_~x~0 4294967296))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2657#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-27 16:50:48,430 INFO L290 TraceCheckUtils]: 11: Hoare triple {2657#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2657#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-27 16:50:48,431 INFO L290 TraceCheckUtils]: 12: Hoare triple {2657#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2657#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} is VALID [2022-04-27 16:50:48,432 INFO L290 TraceCheckUtils]: 13: Hoare triple {2657#(and (<= (mod main_~y~0 4294967296) 0) (<= (mod main_~z~0 4294967296) 0))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2667#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:48,433 INFO L290 TraceCheckUtils]: 14: Hoare triple {2667#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2667#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:50:48,433 INFO L272 TraceCheckUtils]: 15: Hoare triple {2667#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2674#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:50:48,434 INFO L290 TraceCheckUtils]: 16: Hoare triple {2674#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2678#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:50:48,434 INFO L290 TraceCheckUtils]: 17: Hoare triple {2678#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2609#false} is VALID [2022-04-27 16:50:48,434 INFO L290 TraceCheckUtils]: 18: Hoare triple {2609#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2609#false} is VALID [2022-04-27 16:50:48,434 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:50:48,434 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:56:40,772 INFO L290 TraceCheckUtils]: 18: Hoare triple {2609#false} [114] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2609#false} is VALID [2022-04-27 16:56:40,772 INFO L290 TraceCheckUtils]: 17: Hoare triple {2678#(<= 1 __VERIFIER_assert_~cond)} [112] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2609#false} is VALID [2022-04-27 16:56:40,773 INFO L290 TraceCheckUtils]: 16: Hoare triple {2674#(<= 1 |__VERIFIER_assert_#in~cond|)} [110] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2678#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:56:40,773 INFO L272 TraceCheckUtils]: 15: Hoare triple {2667#(<= (mod main_~y~0 4294967296) 0)} [108] L41-2-->__VERIFIER_assertENTRY: Formula: (= (ite (= (mod v_main_~y~0_13 4294967296) 0) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~y~0=v_main_~y~0_13} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~y~0] {2674#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:56:40,774 INFO L290 TraceCheckUtils]: 14: Hoare triple {2667#(<= (mod main_~y~0 4294967296) 0)} [106] L41-1-->L41-2: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2667#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:56:40,790 INFO L290 TraceCheckUtils]: 13: Hoare triple {2700#(forall ((aux_mod_v_main_~y~0_54_31 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2667#(<= (mod main_~y~0 4294967296) 0)} is VALID [2022-04-27 16:56:42,806 WARN L290 TraceCheckUtils]: 12: Hoare triple {2704#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [107] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (= v_main_~y~0_10 (+ v_main_~y~0_11 v_main_~z~0_9 (* (- 1) v_main_~z~0_10))) (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10)) (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~z~0_10 v_main_~z~0_9) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)))) InVars {main_~y~0=v_main_~y~0_11, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~z~0, main_~y~0, main_#t~post13, main_#t~post14] {2700#(forall ((aux_mod_v_main_~y~0_54_31 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-27 16:56:44,989 WARN L290 TraceCheckUtils]: 11: Hoare triple {2704#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} [103] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2704#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-27 16:56:46,998 WARN L290 TraceCheckUtils]: 10: Hoare triple {2711#(forall ((v_main_~x~0_34 Int) (|v_main_#t~post11_19| Int) (|v_main_#t~post12_19| Int) (|main_#t~post11| Int) (v_main_~y~0_56 Int) (|main_#t~post12| Int)) (or (and (or (not (= |v_main_#t~post12_19| |main_#t~post12|)) (not (= |v_main_#t~post11_19| |main_#t~post11|)) (not (= v_main_~y~0_56 main_~y~0)) (not (= v_main_~x~0_34 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0))) (or (not (< v_main_~x~0_34 main_~x~0)) (not (= v_main_~y~0_56 (+ (* (- 1) v_main_~x~0_34) main_~y~0 main_~x~0))) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_34 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))))} [104] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (forall ((v_it_4 Int)) (or (not (<= (+ v_main_~x~0_6 v_it_4 1) v_main_~x~0_7)) (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_7) 4294967296)) (not (<= 1 v_it_4)))) (< 0 .cse0) (< v_main_~x~0_6 v_main_~x~0_7) (= (+ (* (- 1) v_main_~x~0_6) v_main_~x~0_7 v_main_~y~0_8) v_main_~y~0_7)) (and (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (<= .cse0 0) (= v_main_~y~0_8 v_main_~y~0_7) (= v_main_~x~0_7 v_main_~x~0_6)))) InVars {main_~y~0=v_main_~y~0_8, main_~x~0=v_main_~x~0_7, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_7, main_~x~0=v_main_~x~0_6, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {2704#(forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= main_~y~0 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)))))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ (* main_~y~0 4294967296) main_~z~0)))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295) (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 1 v_it_5) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* main_~y~0 4294967296) main_~z~0) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (<= 4294967296 aux_mod_v_main_~y~0_55_70))) (or (< 0 (mod (+ main_~z~0 aux_mod_v_main_~y~0_54_31 (* main_~y~0 4294967295)) 4294967296)) (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) main_~y~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) main_~y~0))))))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))} is UNKNOWN [2022-04-27 16:56:49,437 WARN L290 TraceCheckUtils]: 9: Hoare triple {2715#(forall ((aux_div_main_~y~0_26 Int) (v_main_~y~0_56 Int) (aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31) (and (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_56) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_56))) (or (not (= v_main_~y~0_56 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))) (< 0 (mod main_~x~0 4294967296))))))} [100] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2711#(forall ((v_main_~x~0_34 Int) (|v_main_#t~post11_19| Int) (|v_main_#t~post12_19| Int) (|main_#t~post11| Int) (v_main_~y~0_56 Int) (|main_#t~post12| Int)) (or (and (or (not (= |v_main_#t~post12_19| |main_#t~post12|)) (not (= |v_main_#t~post11_19| |main_#t~post11|)) (not (= v_main_~y~0_56 main_~y~0)) (not (= v_main_~x~0_34 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0))) (or (not (< v_main_~x~0_34 main_~x~0)) (not (= v_main_~y~0_56 (+ (* (- 1) v_main_~x~0_34) main_~y~0 main_~x~0))) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_34 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))))) (forall ((aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31)))))} is UNKNOWN [2022-04-27 16:56:49,506 INFO L290 TraceCheckUtils]: 8: Hoare triple {2642#(not (< 0 (mod main_~x~0 4294967296)))} [97] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2715#(forall ((aux_div_main_~y~0_26 Int) (v_main_~y~0_56 Int) (aux_mod_main_~y~0_26 Int) (aux_mod_v_main_~y~0_54_31 Int)) (or (<= aux_mod_v_main_~y~0_54_31 0) (< aux_mod_main_~y~0_26 0) (< 0 aux_mod_main_~y~0_26) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (not (= v_main_~y~0_56 (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))))) (< 0 (mod main_~z~0 4294967296))) (or (not (< 0 (mod main_~z~0 4294967296))) (and (or (forall ((aux_div_v_main_~y~0_54_31 Int)) (or (not (< (+ aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296)) v_main_~y~0_56)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) v_main_~y~0_56))))) (< 0 (mod (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31) 4294967296))) (forall ((aux_div_v_main_~y~0_55_70 Int) (aux_mod_v_main_~y~0_55_70 Int) (aux_div_v_main_~y~0_54_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) v_it_5 aux_mod_v_main_~y~0_55_70 1) (+ main_~z~0 (* v_main_~y~0_56 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= aux_mod_v_main_~y~0_55_70 0) (<= (+ main_~z~0 (* v_main_~y~0_56 4294967296)) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (exists ((v_it_5 Int)) (and (<= 1 v_it_5) (<= (+ (* v_main_~y~0_56 4294967295) v_it_5 main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296) 1) (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_55_70 (* v_it_5 4294967295)) 4294967296))))) (<= (+ (* aux_div_v_main_~y~0_55_70 4294967296) aux_mod_v_main_~y~0_55_70) (+ (* v_main_~y~0_56 4294967295) main_~z~0 aux_mod_v_main_~y~0_54_31 (* aux_div_v_main_~y~0_54_31 4294967296))) (<= 4294967296 aux_mod_v_main_~y~0_55_70)))))) (<= 4294967296 aux_mod_v_main_~y~0_54_31) (and (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ aux_mod_main_~y~0_26 v_it_4 (* 4294967296 aux_div_main_~y~0_26) 1) v_main_~y~0_56) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)) v_main_~y~0_56))) (or (not (= v_main_~y~0_56 (+ aux_mod_main_~y~0_26 (* 4294967296 aux_div_main_~y~0_26)))) (< 0 (mod main_~x~0 4294967296))))))} is VALID [2022-04-27 16:56:49,506 INFO L290 TraceCheckUtils]: 7: Hoare triple {2642#(not (< 0 (mod main_~x~0 4294967296)))} [95] L16-3-->L23-2: Formula: (= v_main_~y~0_9 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_9} OutVars{main_~y~0=v_main_~y~0_9, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2642#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:56:49,506 INFO L290 TraceCheckUtils]: 6: Hoare triple {2608#true} [93] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_2 4294967296))) InVars {main_~x~0=v_main_~x~0_2} OutVars{main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[] {2642#(not (< 0 (mod main_~x~0 4294967296)))} is VALID [2022-04-27 16:56:49,507 INFO L290 TraceCheckUtils]: 5: Hoare triple {2608#true} [90] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2608#true} is VALID [2022-04-27 16:56:49,507 INFO L272 TraceCheckUtils]: 4: Hoare triple {2608#true} [87] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:56:49,507 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2608#true} {2608#true} [117] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:56:49,507 INFO L290 TraceCheckUtils]: 2: Hoare triple {2608#true} [91] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:56:49,507 INFO L290 TraceCheckUtils]: 1: Hoare triple {2608#true} [88] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2608#true} is VALID [2022-04-27 16:56:49,507 INFO L272 TraceCheckUtils]: 0: Hoare triple {2608#true} [86] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2608#true} is VALID [2022-04-27 16:56:49,507 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:56:49,507 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1731986120] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:56:49,507 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:56:49,507 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 10] total 21 [2022-04-27 16:56:49,508 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1493114117] [2022-04-27 16:56:49,508 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:56:49,514 INFO L78 Accepts]: Start accepts. Automaton has has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:56:49,515 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:56:49,516 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:56:57,982 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 36 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:56:57,982 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 21 states [2022-04-27 16:56:57,983 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:56:57,987 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2022-04-27 16:56:57,987 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=314, Unknown=26, NotChecked=0, Total=420 [2022-04-27 16:56:57,987 INFO L87 Difference]: Start difference. First operand 40 states and 61 transitions. Second operand has 21 states, 21 states have (on average 1.619047619047619) internal successors, (34), 18 states have internal predecessors, (34), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1)