/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/in-de62.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 16:45:15,309 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 16:45:15,318 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 16:45:15,380 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-27 16:45:15,385 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 16:45:15,385 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 16:45:15,386 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 16:45:15,387 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 16:45:15,387 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 16:45:15,388 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 16:45:15,389 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 16:45:15,390 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 16:45:15,391 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 16:45:15,394 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 16:45:15,395 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 16:45:15,396 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 16:45:15,396 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 16:45:15,398 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 16:45:15,403 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 16:45:15,403 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 16:45:15,406 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 16:45:15,406 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 16:45:15,413 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 16:45:15,413 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 16:45:15,414 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 16:45:15,414 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 16:45:15,414 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 16:45:15,415 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 16:45:15,416 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 16:45:15,416 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 16:45:15,416 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 16:45:15,416 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 16:45:15,416 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 16:45:15,416 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:45:15,416 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 16:45:15,416 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 16:45:15,417 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 16:45:15,417 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 16:45:15,579 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 16:45:15,598 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 16:45:15,599 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 16:45:15,600 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 16:45:15,602 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 16:45:15,603 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/in-de62.c [2022-04-27 16:45:15,665 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bc236bed1/82e18a32768f402287439c8a27e91973/FLAG8f8bbd2e8 [2022-04-27 16:45:16,021 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 16:45:16,022 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de62.c [2022-04-27 16:45:16,026 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bc236bed1/82e18a32768f402287439c8a27e91973/FLAG8f8bbd2e8 [2022-04-27 16:45:16,035 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/bc236bed1/82e18a32768f402287439c8a27e91973 [2022-04-27 16:45:16,037 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 16:45:16,038 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 16:45:16,041 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 16:45:16,041 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 16:45:16,044 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 16:45:16,045 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,046 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@364eaa1f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16, skipping insertion in model container [2022-04-27 16:45:16,046 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,051 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 16:45:16,064 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 16:45:16,188 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de62.c[368,381] [2022-04-27 16:45:16,212 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:45:16,219 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 16:45:16,245 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/in-de62.c[368,381] [2022-04-27 16:45:16,249 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:45:16,290 INFO L208 MainTranslator]: Completed translation [2022-04-27 16:45:16,291 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16 WrapperNode [2022-04-27 16:45:16,291 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 16:45:16,292 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 16:45:16,292 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 16:45:16,292 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 16:45:16,302 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,302 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,310 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,310 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,315 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,324 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,325 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,326 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 16:45:16,327 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 16:45:16,327 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 16:45:16,327 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 16:45:16,330 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,339 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:45:16,346 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:45:16,357 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 16:45:16,375 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 16:45:16,389 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 16:45:16,389 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 16:45:16,389 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 16:45:16,390 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 16:45:16,390 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 16:45:16,390 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 16:45:16,391 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 16:45:16,391 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 16:45:16,391 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 16:45:16,391 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 16:45:16,437 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 16:45:16,438 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 16:45:16,653 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 16:45:16,658 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 16:45:16,658 INFO L299 CfgBuilder]: Removed 6 assume(true) statements. [2022-04-27 16:45:16,659 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:45:16 BoogieIcfgContainer [2022-04-27 16:45:16,659 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 16:45:16,660 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 16:45:16,660 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 16:45:16,661 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 16:45:16,664 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:45:16" (1/1) ... [2022-04-27 16:45:16,665 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 16:45:17,106 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:45:17,106 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~x~0_7 (+ v_main_~x~0_6 1)) (< 0 (mod v_main_~x~0_7 4294967296)) (= v_main_~y~0_8 (+ v_main_~y~0_9 1))) InVars {main_~x~0=v_main_~x~0_7, main_~y~0=v_main_~y~0_9} OutVars{main_~x~0=v_main_~x~0_6, main_~y~0=v_main_~y~0_8, main_#t~post5=|v_main_#t~post5_1|, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] to Formula: (let ((.cse0 (mod v_main_~x~0_7 4294967296))) (or (and (= |v_main_#t~post5_3| |v_main_#t~post5_1|) (= v_main_~y~0_9 v_main_~y~0_8) (= |v_main_#t~post6_3| |v_main_#t~post6_1|) (<= .cse0 0) (= v_main_~x~0_7 v_main_~x~0_6)) (and (< 0 .cse0) (= v_main_~x~0_6 (+ (* (- 1) v_main_~y~0_8) v_main_~x~0_7 v_main_~y~0_9)) (< v_main_~y~0_9 v_main_~y~0_8) (forall ((v_it_1 Int)) (or (< 0 (mod (+ v_main_~x~0_7 (* v_it_1 4294967295)) 4294967296)) (not (<= 1 v_it_1)) (not (<= (+ v_main_~y~0_9 v_it_1 1) v_main_~y~0_8))))))) InVars {main_~y~0=v_main_~y~0_9, main_#t~post5=|v_main_#t~post5_3|, main_~x~0=v_main_~x~0_7, main_#t~post6=|v_main_#t~post6_3|} OutVars{main_~y~0=v_main_~y~0_8, main_#t~post5=|v_main_#t~post5_1|, main_~x~0=v_main_~x~0_6, main_#t~post6=|v_main_#t~post6_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post5, main_#t~post6] [2022-04-27 16:45:17,384 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:45:17,384 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_8 (+ v_main_~z~0_7 1)) (< 0 (mod v_main_~z~0_8 4294967296)) (= v_main_~x~0_11 (+ v_main_~x~0_12 1))) InVars {main_~x~0=v_main_~x~0_12, main_~z~0=v_main_~z~0_8} OutVars{main_~x~0=v_main_~x~0_11, main_~z~0=v_main_~z~0_7, main_#t~post8=|v_main_#t~post8_1|, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] to Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] [2022-04-27 16:45:19,713 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:45:19,714 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_5 4294967296)) (= (+ v_main_~z~0_3 1) v_main_~z~0_2) (= v_main_~y~0_5 (+ v_main_~y~0_4 1))) InVars {main_~z~0=v_main_~z~0_3, main_~y~0=v_main_~y~0_5} OutVars{main_#t~post10=|v_main_#t~post10_1|, main_~z~0=v_main_~z~0_2, main_~y~0=v_main_~y~0_4, main_#t~post9=|v_main_#t~post9_1|} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] to Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] [2022-04-27 16:45:19,954 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:45:19,955 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~x~0_10 4294967296)) (= v_main_~x~0_10 (+ v_main_~x~0_9 1)) (= v_main_~y~0_10 (+ v_main_~y~0_11 1))) InVars {main_~x~0=v_main_~x~0_10, main_~y~0=v_main_~y~0_11} OutVars{main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_10, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] to Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] [2022-04-27 16:45:20,215 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:45:20,215 INFO L91 elerationTransformer]: Accelerated Formula: (and (= v_main_~z~0_10 (+ v_main_~z~0_9 1)) (< 0 (mod v_main_~z~0_10 4294967296)) (= v_main_~x~0_13 (+ v_main_~x~0_14 1))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] to Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] [2022-04-27 16:45:20,408 INFO L89 elerationTransformer]: Jordan loop acceleration statistics: 2 HavocedVariables, 2 AssignedVariables, 0 ReadonlyVariables, Eigenvalues: {1={1=1, 2=1}}, 1 SequentialAcceleration, 0 AlternatingAcceleration, 0 QuantifierFreeResult [2022-04-27 16:45:20,409 INFO L91 elerationTransformer]: Accelerated Formula: (and (< 0 (mod v_main_~y~0_7 4294967296)) (= v_main_~y~0_7 (+ v_main_~y~0_6 1)) (= v_main_~x~0_3 (+ v_main_~x~0_2 1))) InVars {main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_7} OutVars{main_~x~0=v_main_~x~0_2, main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] to Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] [2022-04-27 16:45:20,412 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:45:20 BasicIcfg [2022-04-27 16:45:20,412 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 16:45:20,413 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 16:45:20,413 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 16:45:20,415 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 16:45:20,416 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 04:45:16" (1/4) ... [2022-04-27 16:45:20,416 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@333f90e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:45:20, skipping insertion in model container [2022-04-27 16:45:20,416 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:45:16" (2/4) ... [2022-04-27 16:45:20,416 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@333f90e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:45:20, skipping insertion in model container [2022-04-27 16:45:20,416 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:45:16" (3/4) ... [2022-04-27 16:45:20,417 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@333f90e2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 04:45:20, skipping insertion in model container [2022-04-27 16:45:20,417 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:45:20" (4/4) ... [2022-04-27 16:45:20,418 INFO L111 eAbstractionObserver]: Analyzing ICFG in-de62.cJordan [2022-04-27 16:45:20,428 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 16:45:20,428 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 16:45:20,456 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 16:45:20,461 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@2bff86c0, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@673a143 [2022-04-27 16:45:20,461 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 16:45:20,467 INFO L276 IsEmpty]: Start isEmpty. Operand has 25 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 18 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 16:45:20,471 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:45:20,472 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:20,472 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:20,472 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:20,476 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:20,476 INFO L85 PathProgramCache]: Analyzing trace with hash 430051023, now seen corresponding path program 1 times [2022-04-27 16:45:20,483 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:20,483 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129642971] [2022-04-27 16:45:20,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:20,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:20,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:20,574 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:20,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:20,585 INFO L290 TraceCheckUtils]: 0: Hoare triple {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {28#true} is VALID [2022-04-27 16:45:20,585 INFO L290 TraceCheckUtils]: 1: Hoare triple {28#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 16:45:20,586 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {28#true} {28#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 16:45:20,587 INFO L272 TraceCheckUtils]: 0: Hoare triple {28#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:20,587 INFO L290 TraceCheckUtils]: 1: Hoare triple {33#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {28#true} is VALID [2022-04-27 16:45:20,587 INFO L290 TraceCheckUtils]: 2: Hoare triple {28#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 16:45:20,588 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {28#true} {28#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 16:45:20,588 INFO L272 TraceCheckUtils]: 4: Hoare triple {28#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {28#true} is VALID [2022-04-27 16:45:20,588 INFO L290 TraceCheckUtils]: 5: Hoare triple {28#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {28#true} is VALID [2022-04-27 16:45:20,588 INFO L290 TraceCheckUtils]: 6: Hoare triple {28#true} [103] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L290 TraceCheckUtils]: 7: Hoare triple {29#false} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L290 TraceCheckUtils]: 8: Hoare triple {29#false} [107] L23-2-->L29-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L290 TraceCheckUtils]: 9: Hoare triple {29#false} [110] L29-1-->L35-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L290 TraceCheckUtils]: 10: Hoare triple {29#false} [113] L35-1-->L41-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L290 TraceCheckUtils]: 11: Hoare triple {29#false} [116] L41-1-->L47-1: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L290 TraceCheckUtils]: 12: Hoare triple {29#false} [119] L47-1-->L47-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,589 INFO L272 TraceCheckUtils]: 13: Hoare triple {29#false} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {29#false} is VALID [2022-04-27 16:45:20,590 INFO L290 TraceCheckUtils]: 14: Hoare triple {29#false} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {29#false} is VALID [2022-04-27 16:45:20,590 INFO L290 TraceCheckUtils]: 15: Hoare triple {29#false} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,590 INFO L290 TraceCheckUtils]: 16: Hoare triple {29#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {29#false} is VALID [2022-04-27 16:45:20,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:20,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:20,591 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129642971] [2022-04-27 16:45:20,591 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129642971] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:45:20,591 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:45:20,592 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 16:45:20,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116625665] [2022-04-27 16:45:20,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:45:20,597 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:45:20,599 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:45:20,601 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,613 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:20,614 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 16:45:20,614 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:45:20,649 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 16:45:20,650 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:45:20,652 INFO L87 Difference]: Start difference. First operand has 25 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 18 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:20,709 INFO L93 Difference]: Finished difference Result 25 states and 30 transitions. [2022-04-27 16:45:20,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 16:45:20,709 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:45:20,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:45:20,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,716 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2022-04-27 16:45:20,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2022-04-27 16:45:20,718 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 37 transitions. [2022-04-27 16:45:20,749 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:20,754 INFO L225 Difference]: With dead ends: 25 [2022-04-27 16:45:20,754 INFO L226 Difference]: Without dead ends: 18 [2022-04-27 16:45:20,755 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:45:20,758 INFO L413 NwaCegarLoop]: 29 mSDtfsCounter, 21 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 22 SdHoareTripleChecker+Valid, 32 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:45:20,758 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [22 Valid, 32 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:45:20,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2022-04-27 16:45:20,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2022-04-27 16:45:20,777 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:45:20,777 INFO L82 GeneralOperation]: Start isEquivalent. First operand 18 states. Second operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,778 INFO L74 IsIncluded]: Start isIncluded. First operand 18 states. Second operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,778 INFO L87 Difference]: Start difference. First operand 18 states. Second operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:20,793 INFO L93 Difference]: Finished difference Result 18 states and 23 transitions. [2022-04-27 16:45:20,793 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 23 transitions. [2022-04-27 16:45:20,793 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:20,793 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:20,793 INFO L74 IsIncluded]: Start isIncluded. First operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 18 states. [2022-04-27 16:45:20,794 INFO L87 Difference]: Start difference. First operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 18 states. [2022-04-27 16:45:20,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:20,796 INFO L93 Difference]: Finished difference Result 18 states and 23 transitions. [2022-04-27 16:45:20,796 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 23 transitions. [2022-04-27 16:45:20,796 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:20,796 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:20,796 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:45:20,796 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:45:20,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 13 states have (on average 1.4615384615384615) internal successors, (19), 13 states have internal predecessors, (19), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 23 transitions. [2022-04-27 16:45:20,798 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 23 transitions. Word has length 17 [2022-04-27 16:45:20,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:45:20,799 INFO L495 AbstractCegarLoop]: Abstraction has 18 states and 23 transitions. [2022-04-27 16:45:20,799 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 4.333333333333333) internal successors, (13), 2 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,799 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 23 transitions. [2022-04-27 16:45:20,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:45:20,800 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:20,800 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:20,800 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 16:45:20,800 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:20,800 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:20,800 INFO L85 PathProgramCache]: Analyzing trace with hash -514488111, now seen corresponding path program 1 times [2022-04-27 16:45:20,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:20,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329597243] [2022-04-27 16:45:20,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:20,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:20,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:20,881 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:20,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:20,896 INFO L290 TraceCheckUtils]: 0: Hoare triple {123#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {115#true} is VALID [2022-04-27 16:45:20,896 INFO L290 TraceCheckUtils]: 1: Hoare triple {115#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 16:45:20,896 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {115#true} {115#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 16:45:20,897 INFO L272 TraceCheckUtils]: 0: Hoare triple {115#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {123#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:20,898 INFO L290 TraceCheckUtils]: 1: Hoare triple {123#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {115#true} is VALID [2022-04-27 16:45:20,898 INFO L290 TraceCheckUtils]: 2: Hoare triple {115#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 16:45:20,898 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {115#true} {115#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 16:45:20,898 INFO L272 TraceCheckUtils]: 4: Hoare triple {115#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 16:45:20,898 INFO L290 TraceCheckUtils]: 5: Hoare triple {115#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {115#true} is VALID [2022-04-27 16:45:20,899 INFO L290 TraceCheckUtils]: 6: Hoare triple {115#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,900 INFO L290 TraceCheckUtils]: 7: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,900 INFO L290 TraceCheckUtils]: 8: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,900 INFO L290 TraceCheckUtils]: 9: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,901 INFO L290 TraceCheckUtils]: 10: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,901 INFO L290 TraceCheckUtils]: 11: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,902 INFO L290 TraceCheckUtils]: 12: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} is VALID [2022-04-27 16:45:20,902 INFO L272 TraceCheckUtils]: 13: Hoare triple {120#(= (+ (* (- 4294967296) (div main_~x~0 4294967296)) main_~x~0) 0)} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {121#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:45:20,903 INFO L290 TraceCheckUtils]: 14: Hoare triple {121#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {122#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:45:20,903 INFO L290 TraceCheckUtils]: 15: Hoare triple {122#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-27 16:45:20,904 INFO L290 TraceCheckUtils]: 16: Hoare triple {116#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-27 16:45:20,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:20,905 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:20,905 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1329597243] [2022-04-27 16:45:20,905 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1329597243] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:45:20,907 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:45:20,908 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 16:45:20,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104508297] [2022-04-27 16:45:20,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:45:20,909 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:45:20,909 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:45:20,910 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:20,926 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:20,926 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 16:45:20,927 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:45:20,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 16:45:20,928 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2022-04-27 16:45:20,928 INFO L87 Difference]: Start difference. First operand 18 states and 23 transitions. Second operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:21,088 INFO L93 Difference]: Finished difference Result 28 states and 39 transitions. [2022-04-27 16:45:21,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 16:45:21,088 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:45:21,088 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:45:21,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 40 transitions. [2022-04-27 16:45:21,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 40 transitions. [2022-04-27 16:45:21,093 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 40 transitions. [2022-04-27 16:45:21,131 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:21,132 INFO L225 Difference]: With dead ends: 28 [2022-04-27 16:45:21,132 INFO L226 Difference]: Without dead ends: 25 [2022-04-27 16:45:21,133 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=49, Unknown=0, NotChecked=0, Total=72 [2022-04-27 16:45:21,134 INFO L413 NwaCegarLoop]: 17 mSDtfsCounter, 18 mSDsluCounter, 20 mSDsCounter, 0 mSdLazyCounter, 34 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 37 SdHoareTripleChecker+Invalid, 54 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 34 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 12 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:45:21,134 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [18 Valid, 37 Invalid, 54 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 34 Invalid, 0 Unknown, 12 Unchecked, 0.0s Time] [2022-04-27 16:45:21,134 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2022-04-27 16:45:21,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 20. [2022-04-27 16:45:21,136 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:45:21,136 INFO L82 GeneralOperation]: Start isEquivalent. First operand 25 states. Second operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,136 INFO L74 IsIncluded]: Start isIncluded. First operand 25 states. Second operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,137 INFO L87 Difference]: Start difference. First operand 25 states. Second operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:21,138 INFO L93 Difference]: Finished difference Result 25 states and 36 transitions. [2022-04-27 16:45:21,138 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 36 transitions. [2022-04-27 16:45:21,138 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:21,138 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:21,139 INFO L74 IsIncluded]: Start isIncluded. First operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-27 16:45:21,139 INFO L87 Difference]: Start difference. First operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 25 states. [2022-04-27 16:45:21,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:21,140 INFO L93 Difference]: Finished difference Result 25 states and 36 transitions. [2022-04-27 16:45:21,140 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 36 transitions. [2022-04-27 16:45:21,140 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:21,140 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:21,140 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:45:21,141 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:45:21,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 15 states have (on average 1.4666666666666666) internal successors, (22), 15 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 26 transitions. [2022-04-27 16:45:21,142 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 26 transitions. Word has length 17 [2022-04-27 16:45:21,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:45:21,142 INFO L495 AbstractCegarLoop]: Abstraction has 20 states and 26 transitions. [2022-04-27 16:45:21,142 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 2.1666666666666665) internal successors, (13), 4 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:21,142 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 26 transitions. [2022-04-27 16:45:21,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:45:21,143 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:21,143 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:21,143 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 16:45:21,143 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:21,144 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:21,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1257458414, now seen corresponding path program 1 times [2022-04-27 16:45:21,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:21,144 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882157499] [2022-04-27 16:45:21,144 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:21,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:21,157 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:21,165 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:21,179 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:21,243 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:21,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:21,258 INFO L290 TraceCheckUtils]: 0: Hoare triple {239#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-27 16:45:21,258 INFO L290 TraceCheckUtils]: 1: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:21,258 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:21,259 INFO L272 TraceCheckUtils]: 0: Hoare triple {230#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {239#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:21,260 INFO L290 TraceCheckUtils]: 1: Hoare triple {239#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-27 16:45:21,262 INFO L290 TraceCheckUtils]: 2: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:21,262 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:21,266 INFO L272 TraceCheckUtils]: 4: Hoare triple {230#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:21,266 INFO L290 TraceCheckUtils]: 5: Hoare triple {230#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#true} is VALID [2022-04-27 16:45:21,269 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:21,275 INFO L290 TraceCheckUtils]: 7: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:21,275 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:21,276 INFO L290 TraceCheckUtils]: 9: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:21,277 INFO L290 TraceCheckUtils]: 10: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:21,277 INFO L290 TraceCheckUtils]: 11: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:21,279 INFO L290 TraceCheckUtils]: 12: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:21,281 INFO L290 TraceCheckUtils]: 13: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:21,281 INFO L272 TraceCheckUtils]: 14: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {237#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:45:21,282 INFO L290 TraceCheckUtils]: 15: Hoare triple {237#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {238#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:45:21,282 INFO L290 TraceCheckUtils]: 16: Hoare triple {238#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-27 16:45:21,282 INFO L290 TraceCheckUtils]: 17: Hoare triple {231#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-27 16:45:21,283 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:21,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:21,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882157499] [2022-04-27 16:45:21,283 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882157499] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:45:21,283 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [770657469] [2022-04-27 16:45:21,283 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:21,285 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:21,285 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:45:21,286 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:45:21,316 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 16:45:21,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:21,338 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:45:21,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:21,351 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:45:22,077 INFO L272 TraceCheckUtils]: 0: Hoare triple {230#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:22,078 INFO L290 TraceCheckUtils]: 1: Hoare triple {230#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-27 16:45:22,078 INFO L290 TraceCheckUtils]: 2: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:22,078 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:22,078 INFO L272 TraceCheckUtils]: 4: Hoare triple {230#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:22,078 INFO L290 TraceCheckUtils]: 5: Hoare triple {230#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#true} is VALID [2022-04-27 16:45:22,079 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:22,079 INFO L290 TraceCheckUtils]: 7: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:22,080 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:22,080 INFO L290 TraceCheckUtils]: 9: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:22,081 INFO L290 TraceCheckUtils]: 10: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:22,081 INFO L290 TraceCheckUtils]: 11: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:22,083 INFO L290 TraceCheckUtils]: 12: Hoare triple {236#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:22,083 INFO L290 TraceCheckUtils]: 13: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:22,084 INFO L272 TraceCheckUtils]: 14: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {285#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:22,085 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {289#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:22,085 INFO L290 TraceCheckUtils]: 16: Hoare triple {289#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-27 16:45:22,085 INFO L290 TraceCheckUtils]: 17: Hoare triple {231#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-27 16:45:22,086 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:22,086 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:45:26,062 INFO L290 TraceCheckUtils]: 17: Hoare triple {231#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-27 16:45:26,062 INFO L290 TraceCheckUtils]: 16: Hoare triple {289#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {231#false} is VALID [2022-04-27 16:45:26,063 INFO L290 TraceCheckUtils]: 15: Hoare triple {285#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {289#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:26,064 INFO L272 TraceCheckUtils]: 14: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {285#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:26,064 INFO L290 TraceCheckUtils]: 13: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,218 INFO L290 TraceCheckUtils]: 12: Hoare triple {311#(forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (<= 4294967296 aux_mod_v_main_~x~0_32_31) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0))))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,246 INFO L290 TraceCheckUtils]: 11: Hoare triple {311#(forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (<= 4294967296 aux_mod_v_main_~x~0_32_31) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0))))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {311#(forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (<= 4294967296 aux_mod_v_main_~x~0_32_31) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0))))))} is VALID [2022-04-27 16:45:26,276 INFO L290 TraceCheckUtils]: 10: Hoare triple {311#(forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (<= 4294967296 aux_mod_v_main_~x~0_32_31) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0))))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {311#(forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (<= 4294967296 aux_mod_v_main_~x~0_32_31) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0))))))} is VALID [2022-04-27 16:45:26,277 INFO L290 TraceCheckUtils]: 9: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {311#(forall ((aux_div_v_main_~x~0_32_31 Int) (aux_mod_v_main_~x~0_32_31 Int)) (or (<= aux_mod_v_main_~x~0_32_31 0) (<= 4294967296 aux_mod_v_main_~x~0_32_31) (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_32_31 v_it_6 (* aux_div_v_main_~x~0_32_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_32_31 (* aux_div_v_main_~x~0_32_31 4294967296)) main_~x~0))))))} is VALID [2022-04-27 16:45:26,286 INFO L290 TraceCheckUtils]: 8: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,287 INFO L290 TraceCheckUtils]: 7: Hoare triple {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,287 INFO L290 TraceCheckUtils]: 6: Hoare triple {230#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {235#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,288 INFO L290 TraceCheckUtils]: 5: Hoare triple {230#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {230#true} is VALID [2022-04-27 16:45:26,288 INFO L272 TraceCheckUtils]: 4: Hoare triple {230#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:26,288 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {230#true} {230#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:26,288 INFO L290 TraceCheckUtils]: 2: Hoare triple {230#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:26,288 INFO L290 TraceCheckUtils]: 1: Hoare triple {230#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {230#true} is VALID [2022-04-27 16:45:26,288 INFO L272 TraceCheckUtils]: 0: Hoare triple {230#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {230#true} is VALID [2022-04-27 16:45:26,288 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:26,289 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [770657469] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:45:26,289 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:45:26,289 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 16:45:26,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [564996942] [2022-04-27 16:45:26,289 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:45:26,289 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:26,290 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:45:26,290 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,332 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:26,332 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 16:45:26,332 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:45:26,333 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 16:45:26,333 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=68, Unknown=1, NotChecked=0, Total=90 [2022-04-27 16:45:26,333 INFO L87 Difference]: Start difference. First operand 20 states and 26 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:26,577 INFO L93 Difference]: Finished difference Result 31 states and 43 transitions. [2022-04-27 16:45:26,577 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-27 16:45:26,577 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:26,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:45:26,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 44 transitions. [2022-04-27 16:45:26,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 44 transitions. [2022-04-27 16:45:26,580 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 44 transitions. [2022-04-27 16:45:26,623 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:26,623 INFO L225 Difference]: With dead ends: 31 [2022-04-27 16:45:26,624 INFO L226 Difference]: Without dead ends: 28 [2022-04-27 16:45:26,624 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 30 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=45, Invalid=136, Unknown=1, NotChecked=0, Total=182 [2022-04-27 16:45:26,624 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 23 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 52 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 94 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 52 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 32 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:45:26,625 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [23 Valid, 52 Invalid, 94 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 52 Invalid, 0 Unknown, 32 Unchecked, 0.1s Time] [2022-04-27 16:45:26,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-27 16:45:26,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 25. [2022-04-27 16:45:26,627 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:45:26,627 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,627 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,628 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:26,629 INFO L93 Difference]: Finished difference Result 28 states and 40 transitions. [2022-04-27 16:45:26,629 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 40 transitions. [2022-04-27 16:45:26,629 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:26,629 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:26,629 INFO L74 IsIncluded]: Start isIncluded. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 28 states. [2022-04-27 16:45:26,629 INFO L87 Difference]: Start difference. First operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 28 states. [2022-04-27 16:45:26,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:26,631 INFO L93 Difference]: Finished difference Result 28 states and 40 transitions. [2022-04-27 16:45:26,631 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 40 transitions. [2022-04-27 16:45:26,631 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:26,631 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:26,631 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:45:26,631 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:45:26,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 20 states have (on average 1.55) internal successors, (31), 20 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 35 transitions. [2022-04-27 16:45:26,632 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 35 transitions. Word has length 18 [2022-04-27 16:45:26,632 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:45:26,632 INFO L495 AbstractCegarLoop]: Abstraction has 25 states and 35 transitions. [2022-04-27 16:45:26,632 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:26,632 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 35 transitions. [2022-04-27 16:45:26,633 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2022-04-27 16:45:26,633 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:26,633 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:26,652 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 16:45:26,851 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:26,852 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:26,852 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:26,852 INFO L85 PathProgramCache]: Analyzing trace with hash 2030445491, now seen corresponding path program 1 times [2022-04-27 16:45:26,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:26,853 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364259673] [2022-04-27 16:45:26,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:26,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:26,867 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:26,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:26,898 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:26,960 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:26,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:26,967 INFO L290 TraceCheckUtils]: 0: Hoare triple {479#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-27 16:45:26,967 INFO L290 TraceCheckUtils]: 1: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:26,967 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:26,968 INFO L272 TraceCheckUtils]: 0: Hoare triple {470#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {479#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:26,968 INFO L290 TraceCheckUtils]: 1: Hoare triple {479#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-27 16:45:26,968 INFO L290 TraceCheckUtils]: 2: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:26,968 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:26,968 INFO L272 TraceCheckUtils]: 4: Hoare triple {470#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:26,968 INFO L290 TraceCheckUtils]: 5: Hoare triple {470#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {470#true} is VALID [2022-04-27 16:45:26,971 INFO L290 TraceCheckUtils]: 6: Hoare triple {470#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,972 INFO L290 TraceCheckUtils]: 7: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,973 INFO L290 TraceCheckUtils]: 8: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:26,973 INFO L290 TraceCheckUtils]: 9: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:26,974 INFO L290 TraceCheckUtils]: 10: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:26,975 INFO L290 TraceCheckUtils]: 11: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,975 INFO L290 TraceCheckUtils]: 12: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,976 INFO L290 TraceCheckUtils]: 13: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:26,976 INFO L272 TraceCheckUtils]: 14: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {477#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:45:26,977 INFO L290 TraceCheckUtils]: 15: Hoare triple {477#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {478#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:45:26,978 INFO L290 TraceCheckUtils]: 16: Hoare triple {478#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-27 16:45:26,978 INFO L290 TraceCheckUtils]: 17: Hoare triple {471#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-27 16:45:26,978 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:26,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:26,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364259673] [2022-04-27 16:45:26,979 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364259673] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:45:26,979 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1255065105] [2022-04-27 16:45:26,979 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:26,979 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:26,979 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:45:26,980 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:45:26,981 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 16:45:27,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:27,026 INFO L263 TraceCheckSpWp]: Trace formula consists of 63 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:45:27,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:27,043 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:45:27,667 INFO L272 TraceCheckUtils]: 0: Hoare triple {470#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:27,667 INFO L290 TraceCheckUtils]: 1: Hoare triple {470#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-27 16:45:27,667 INFO L290 TraceCheckUtils]: 2: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:27,667 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:27,667 INFO L272 TraceCheckUtils]: 4: Hoare triple {470#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:27,668 INFO L290 TraceCheckUtils]: 5: Hoare triple {470#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {470#true} is VALID [2022-04-27 16:45:27,676 INFO L290 TraceCheckUtils]: 6: Hoare triple {470#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:27,677 INFO L290 TraceCheckUtils]: 7: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:27,678 INFO L290 TraceCheckUtils]: 8: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:27,679 INFO L290 TraceCheckUtils]: 9: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:27,679 INFO L290 TraceCheckUtils]: 10: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:45:27,680 INFO L290 TraceCheckUtils]: 11: Hoare triple {476#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:27,681 INFO L290 TraceCheckUtils]: 12: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:27,681 INFO L290 TraceCheckUtils]: 13: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:27,682 INFO L272 TraceCheckUtils]: 14: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {525#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:27,682 INFO L290 TraceCheckUtils]: 15: Hoare triple {525#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {529#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:27,682 INFO L290 TraceCheckUtils]: 16: Hoare triple {529#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-27 16:45:27,683 INFO L290 TraceCheckUtils]: 17: Hoare triple {471#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-27 16:45:27,683 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:27,683 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:45:31,469 INFO L290 TraceCheckUtils]: 17: Hoare triple {471#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-27 16:45:31,470 INFO L290 TraceCheckUtils]: 16: Hoare triple {529#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {471#false} is VALID [2022-04-27 16:45:31,470 INFO L290 TraceCheckUtils]: 15: Hoare triple {525#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {529#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:31,472 INFO L272 TraceCheckUtils]: 14: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {525#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:31,472 INFO L290 TraceCheckUtils]: 13: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:31,472 INFO L290 TraceCheckUtils]: 12: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:31,480 INFO L290 TraceCheckUtils]: 11: Hoare triple {554#(forall ((aux_mod_v_main_~x~0_34_31 Int) (aux_div_v_main_~x~0_34_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:31,533 INFO L290 TraceCheckUtils]: 10: Hoare triple {554#(forall ((aux_mod_v_main_~x~0_34_31 Int) (aux_div_v_main_~x~0_34_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {554#(forall ((aux_mod_v_main_~x~0_34_31 Int) (aux_div_v_main_~x~0_34_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} is VALID [2022-04-27 16:45:31,546 INFO L290 TraceCheckUtils]: 9: Hoare triple {554#(forall ((aux_mod_v_main_~x~0_34_31 Int) (aux_div_v_main_~x~0_34_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {554#(forall ((aux_mod_v_main_~x~0_34_31 Int) (aux_div_v_main_~x~0_34_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} is VALID [2022-04-27 16:45:31,548 INFO L290 TraceCheckUtils]: 8: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {554#(forall ((aux_mod_v_main_~x~0_34_31 Int) (aux_div_v_main_~x~0_34_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_34_31 (* aux_div_v_main_~x~0_34_31 4294967296)) main_~x~0)))) (<= aux_mod_v_main_~x~0_34_31 0) (<= 4294967296 aux_mod_v_main_~x~0_34_31)))} is VALID [2022-04-27 16:45:31,548 INFO L290 TraceCheckUtils]: 7: Hoare triple {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:31,549 INFO L290 TraceCheckUtils]: 6: Hoare triple {470#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {475#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:31,549 INFO L290 TraceCheckUtils]: 5: Hoare triple {470#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {470#true} is VALID [2022-04-27 16:45:31,549 INFO L272 TraceCheckUtils]: 4: Hoare triple {470#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:31,549 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {470#true} {470#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:31,549 INFO L290 TraceCheckUtils]: 2: Hoare triple {470#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:31,549 INFO L290 TraceCheckUtils]: 1: Hoare triple {470#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {470#true} is VALID [2022-04-27 16:45:31,549 INFO L272 TraceCheckUtils]: 0: Hoare triple {470#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {470#true} is VALID [2022-04-27 16:45:31,549 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:31,550 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1255065105] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:45:31,550 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:45:31,550 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 16:45:31,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1537238633] [2022-04-27 16:45:31,550 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:45:31,550 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:31,550 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:45:31,551 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,642 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:31,642 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 16:45:31,642 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:45:31,642 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 16:45:31,642 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=68, Unknown=1, NotChecked=0, Total=90 [2022-04-27 16:45:31,643 INFO L87 Difference]: Start difference. First operand 25 states and 35 transitions. Second operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:31,852 INFO L93 Difference]: Finished difference Result 38 states and 55 transitions. [2022-04-27 16:45:31,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-27 16:45:31,852 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 18 [2022-04-27 16:45:31,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:45:31,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 47 transitions. [2022-04-27 16:45:31,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 47 transitions. [2022-04-27 16:45:31,855 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 47 transitions. [2022-04-27 16:45:31,910 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:45:31,911 INFO L225 Difference]: With dead ends: 38 [2022-04-27 16:45:31,911 INFO L226 Difference]: Without dead ends: 35 [2022-04-27 16:45:31,911 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 30 SyntacticMatches, 6 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=45, Invalid=136, Unknown=1, NotChecked=0, Total=182 [2022-04-27 16:45:31,912 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 23 mSDsluCounter, 31 mSDsCounter, 0 mSdLazyCounter, 48 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 23 SdHoareTripleChecker+Valid, 46 SdHoareTripleChecker+Invalid, 83 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 48 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:45:31,912 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [23 Valid, 46 Invalid, 83 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 48 Invalid, 0 Unknown, 24 Unchecked, 0.1s Time] [2022-04-27 16:45:31,912 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 35 states. [2022-04-27 16:45:31,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 35 to 28. [2022-04-27 16:45:31,914 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:45:31,914 INFO L82 GeneralOperation]: Start isEquivalent. First operand 35 states. Second operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,914 INFO L74 IsIncluded]: Start isIncluded. First operand 35 states. Second operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,914 INFO L87 Difference]: Start difference. First operand 35 states. Second operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:31,916 INFO L93 Difference]: Finished difference Result 35 states and 52 transitions. [2022-04-27 16:45:31,916 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 52 transitions. [2022-04-27 16:45:31,916 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:31,916 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:31,916 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 35 states. [2022-04-27 16:45:31,916 INFO L87 Difference]: Start difference. First operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 35 states. [2022-04-27 16:45:31,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:45:31,918 INFO L93 Difference]: Finished difference Result 35 states and 52 transitions. [2022-04-27 16:45:31,918 INFO L276 IsEmpty]: Start isEmpty. Operand 35 states and 52 transitions. [2022-04-27 16:45:31,918 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:45:31,918 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:45:31,918 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:45:31,918 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:45:31,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 23 states have (on average 1.608695652173913) internal successors, (37), 23 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 41 transitions. [2022-04-27 16:45:31,919 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 41 transitions. Word has length 18 [2022-04-27 16:45:31,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:45:31,919 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 41 transitions. [2022-04-27 16:45:31,919 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.1) internal successors, (21), 7 states have internal predecessors, (21), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:45:31,919 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 41 transitions. [2022-04-27 16:45:31,920 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:45:31,920 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:45:31,920 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:45:31,938 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 16:45:32,135 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 16:45:32,136 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:45:32,136 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:45:32,136 INFO L85 PathProgramCache]: Analyzing trace with hash 1868584369, now seen corresponding path program 1 times [2022-04-27 16:45:32,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:45:32,136 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430483230] [2022-04-27 16:45:32,136 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:32,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:45:32,145 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:32,150 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:32,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:32,194 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.2))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:32,198 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.3))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:45:32,295 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:45:32,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:32,301 INFO L290 TraceCheckUtils]: 0: Hoare triple {746#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-27 16:45:32,302 INFO L290 TraceCheckUtils]: 1: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,302 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,302 INFO L272 TraceCheckUtils]: 0: Hoare triple {734#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {746#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:45:32,302 INFO L290 TraceCheckUtils]: 1: Hoare triple {746#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-27 16:45:32,303 INFO L290 TraceCheckUtils]: 2: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,303 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,303 INFO L272 TraceCheckUtils]: 4: Hoare triple {734#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,303 INFO L290 TraceCheckUtils]: 5: Hoare triple {734#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {739#(= main_~y~0 0)} is VALID [2022-04-27 16:45:32,304 INFO L290 TraceCheckUtils]: 6: Hoare triple {739#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:32,304 INFO L290 TraceCheckUtils]: 7: Hoare triple {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:32,304 INFO L290 TraceCheckUtils]: 8: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:32,305 INFO L290 TraceCheckUtils]: 9: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,305 INFO L290 TraceCheckUtils]: 10: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,307 INFO L290 TraceCheckUtils]: 11: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,308 INFO L290 TraceCheckUtils]: 12: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,308 INFO L290 TraceCheckUtils]: 13: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:32,309 INFO L290 TraceCheckUtils]: 14: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:32,310 INFO L272 TraceCheckUtils]: 15: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {744#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:45:32,310 INFO L290 TraceCheckUtils]: 16: Hoare triple {744#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {745#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:45:32,310 INFO L290 TraceCheckUtils]: 17: Hoare triple {745#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-27 16:45:32,310 INFO L290 TraceCheckUtils]: 18: Hoare triple {735#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-27 16:45:32,310 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:45:32,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:45:32,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [430483230] [2022-04-27 16:45:32,311 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [430483230] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:45:32,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [157494694] [2022-04-27 16:45:32,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:45:32,311 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:45:32,311 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:45:32,312 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:45:32,334 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 16:45:32,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:32,357 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-27 16:45:32,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:45:32,371 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:45:32,642 INFO L272 TraceCheckUtils]: 0: Hoare triple {734#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,642 INFO L290 TraceCheckUtils]: 1: Hoare triple {734#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-27 16:45:32,642 INFO L290 TraceCheckUtils]: 2: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,642 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,642 INFO L272 TraceCheckUtils]: 4: Hoare triple {734#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:32,643 INFO L290 TraceCheckUtils]: 5: Hoare triple {734#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {739#(= main_~y~0 0)} is VALID [2022-04-27 16:45:32,643 INFO L290 TraceCheckUtils]: 6: Hoare triple {739#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:32,644 INFO L290 TraceCheckUtils]: 7: Hoare triple {740#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:32,644 INFO L290 TraceCheckUtils]: 8: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:45:32,646 INFO L290 TraceCheckUtils]: 9: Hoare triple {741#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,646 INFO L290 TraceCheckUtils]: 10: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,646 INFO L290 TraceCheckUtils]: 11: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:45:32,647 INFO L290 TraceCheckUtils]: 12: Hoare triple {742#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:32,648 INFO L290 TraceCheckUtils]: 13: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:32,648 INFO L290 TraceCheckUtils]: 14: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:32,649 INFO L272 TraceCheckUtils]: 15: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {795#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:32,649 INFO L290 TraceCheckUtils]: 16: Hoare triple {795#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {799#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:32,650 INFO L290 TraceCheckUtils]: 17: Hoare triple {799#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-27 16:45:32,650 INFO L290 TraceCheckUtils]: 18: Hoare triple {735#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-27 16:45:32,650 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:45:32,650 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:45:48,662 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0) (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (let ((.cse1 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse0 (not (= .cse1 c_main_~z~0))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 .cse1)) (not .cse0)))) (<= aux_mod_v_main_~z~0_27_31 0))) (or (forall ((aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (let ((.cse3 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (.cse2 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse2 (not (= .cse3 c_main_~z~0))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 .cse3)) (not .cse2)))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0))))))) is different from false [2022-04-27 16:45:53,447 WARN L855 $PredicateComparison]: unable to prove that (or (< 0 (mod c_main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (or (not (< 0 (mod c_main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))) (<= aux_mod_v_main_~z~0_27_31 0)))) (or (forall ((aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (let ((.cse1 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (.cse0 (< 0 (mod c_main_~y~0 4294967296)))) (and (or .cse0 (not (= .cse1 c_main_~z~0))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))))) (not (< c_main_~z~0 .cse1)) (not .cse0)))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) c_main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))) is different from true [2022-04-27 16:45:53,909 INFO L290 TraceCheckUtils]: 18: Hoare triple {735#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-27 16:45:53,909 INFO L290 TraceCheckUtils]: 17: Hoare triple {799#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {735#false} is VALID [2022-04-27 16:45:53,910 INFO L290 TraceCheckUtils]: 16: Hoare triple {795#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {799#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:45:53,910 INFO L272 TraceCheckUtils]: 15: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {795#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:45:53,911 INFO L290 TraceCheckUtils]: 14: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:53,911 INFO L290 TraceCheckUtils]: 13: Hoare triple {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:53,923 INFO L290 TraceCheckUtils]: 12: Hoare triple {824#(forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {743#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:45:53,946 INFO L290 TraceCheckUtils]: 11: Hoare triple {824#(forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {824#(forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} is VALID [2022-04-27 16:45:53,952 INFO L290 TraceCheckUtils]: 10: Hoare triple {824#(forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {824#(forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} is VALID [2022-04-27 16:45:55,960 WARN L290 TraceCheckUtils]: 9: Hoare triple {834#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (and (or (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {824#(forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} is UNKNOWN [2022-04-27 16:45:57,978 WARN L290 TraceCheckUtils]: 8: Hoare triple {838#(or (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5)))))) (or (forall ((aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0))) (< 0 (mod main_~z~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {834#(forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (and (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (and (or (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= 4294967296 aux_mod_v_main_~x~0_36_31) (<= aux_mod_v_main_~x~0_36_31 0)))} is UNKNOWN [2022-04-27 16:45:57,981 INFO L290 TraceCheckUtils]: 7: Hoare triple {842#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {838#(or (forall ((aux_mod_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_36_31 Int) (aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0) (<= 4294967296 aux_mod_v_main_~z~0_27_31) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))) (<= aux_mod_v_main_~z~0_27_31 0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_27_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (<= 1 v_it_5)))))) (or (forall ((aux_div_v_main_~z~0_27_31 Int) (aux_mod_v_main_~z~0_27_31 Int)) (or (< 0 aux_mod_v_main_~z~0_27_31) (and (or (not (= (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)) main_~z~0)) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_27_31 (* 4294967296 aux_div_v_main_~z~0_27_31)))))) (< aux_mod_v_main_~z~0_27_31 0))) (forall ((aux_div_v_main_~x~0_36_31 Int)) (not (= (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)) main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0))) (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:45:57,982 INFO L290 TraceCheckUtils]: 6: Hoare triple {734#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {842#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:45:57,983 INFO L290 TraceCheckUtils]: 5: Hoare triple {734#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {734#true} is VALID [2022-04-27 16:45:57,983 INFO L272 TraceCheckUtils]: 4: Hoare triple {734#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:57,983 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {734#true} {734#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:57,983 INFO L290 TraceCheckUtils]: 2: Hoare triple {734#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:57,983 INFO L290 TraceCheckUtils]: 1: Hoare triple {734#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {734#true} is VALID [2022-04-27 16:45:57,983 INFO L272 TraceCheckUtils]: 0: Hoare triple {734#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {734#true} is VALID [2022-04-27 16:45:57,983 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-27 16:45:57,984 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [157494694] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:45:57,984 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:45:57,984 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 16 [2022-04-27 16:45:57,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184071288] [2022-04-27 16:45:57,984 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:45:57,984 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:45:57,985 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:45:57,985 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:03,151 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 32 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:03,152 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 16:46:03,152 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:46:03,152 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 16:46:03,152 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=143, Unknown=3, NotChecked=50, Total=240 [2022-04-27 16:46:03,152 INFO L87 Difference]: Start difference. First operand 28 states and 41 transitions. Second operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:17,917 WARN L232 SmtUtils]: Spent 8.26s on a formula simplification that was a NOOP. DAG size: 85 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:46:22,097 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (forall ((aux_mod_v_main_~x~0_36_31 Int) (aux_div_v_main_~x~0_36_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_36_31) (let ((.cse1 (< 0 (mod c_main_~z~0 4294967296))) (.cse0 (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296)))) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_36_31 (* aux_div_v_main_~x~0_36_31 4294967296))) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) (not (< c_main_~x~0 .cse0)) (not .cse1)) (or .cse1 (not (= .cse0 c_main_~x~0))))) (<= aux_mod_v_main_~x~0_36_31 0))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 16:46:26,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:26,284 INFO L93 Difference]: Finished difference Result 58 states and 89 transitions. [2022-04-27 16:46:26,284 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2022-04-27 16:46:26,284 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:46:26,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:46:26,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:26,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 70 transitions. [2022-04-27 16:46:26,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:26,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 70 transitions. [2022-04-27 16:46:26,288 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 20 states and 70 transitions. [2022-04-27 16:46:33,181 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 70 edges. 67 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:33,183 INFO L225 Difference]: With dead ends: 58 [2022-04-27 16:46:33,183 INFO L226 Difference]: Without dead ends: 54 [2022-04-27 16:46:33,183 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 31 SyntacticMatches, 5 SemanticMatches, 26 ConstructedPredicates, 3 IntricatePredicates, 1 DeprecatedPredicates, 130 ImplicationChecksByTransitivity, 28.3s TimeCoverageRelationStatistics Valid=143, Invalid=462, Unknown=7, NotChecked=144, Total=756 [2022-04-27 16:46:33,184 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 40 mSDsluCounter, 46 mSDsCounter, 0 mSdLazyCounter, 68 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 40 SdHoareTripleChecker+Valid, 57 SdHoareTripleChecker+Invalid, 139 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 68 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 58 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:46:33,184 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [40 Valid, 57 Invalid, 139 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 68 Invalid, 0 Unknown, 58 Unchecked, 0.1s Time] [2022-04-27 16:46:33,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2022-04-27 16:46:33,188 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 37. [2022-04-27 16:46:33,188 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:46:33,188 INFO L82 GeneralOperation]: Start isEquivalent. First operand 54 states. Second operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,188 INFO L74 IsIncluded]: Start isIncluded. First operand 54 states. Second operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,188 INFO L87 Difference]: Start difference. First operand 54 states. Second operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:33,190 INFO L93 Difference]: Finished difference Result 54 states and 84 transitions. [2022-04-27 16:46:33,190 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 84 transitions. [2022-04-27 16:46:33,190 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:46:33,190 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:46:33,190 INFO L74 IsIncluded]: Start isIncluded. First operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 54 states. [2022-04-27 16:46:33,191 INFO L87 Difference]: Start difference. First operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 54 states. [2022-04-27 16:46:33,192 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:33,192 INFO L93 Difference]: Finished difference Result 54 states and 84 transitions. [2022-04-27 16:46:33,192 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 84 transitions. [2022-04-27 16:46:33,193 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:46:33,193 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:46:33,193 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:46:33,193 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:46:33,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 32 states have (on average 1.6875) internal successors, (54), 32 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 58 transitions. [2022-04-27 16:46:33,194 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 58 transitions. Word has length 19 [2022-04-27 16:46:33,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:46:33,194 INFO L495 AbstractCegarLoop]: Abstraction has 37 states and 58 transitions. [2022-04-27 16:46:33,194 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 1.75) internal successors, (28), 13 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,194 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 58 transitions. [2022-04-27 16:46:33,203 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:46:33,203 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:46:33,203 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:46:33,221 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 16:46:33,411 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:46:33,411 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:46:33,412 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:46:33,412 INFO L85 PathProgramCache]: Analyzing trace with hash 353225841, now seen corresponding path program 2 times [2022-04-27 16:46:33,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:46:33,412 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [58995715] [2022-04-27 16:46:33,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:46:33,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:46:33,421 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,422 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_12 .cse0 (* (- 4294967296) (div (+ main_~y~0_12 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:33,441 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.5))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,444 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_12 .cse0 (* (- 4294967296) (div (+ main_~y~0_12 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,526 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:46:33,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:33,531 INFO L290 TraceCheckUtils]: 0: Hoare triple {1104#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1094#true} is VALID [2022-04-27 16:46:33,531 INFO L290 TraceCheckUtils]: 1: Hoare triple {1094#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1094#true} is VALID [2022-04-27 16:46:33,531 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1094#true} {1094#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1094#true} is VALID [2022-04-27 16:46:33,532 INFO L272 TraceCheckUtils]: 0: Hoare triple {1094#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1104#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:46:33,532 INFO L290 TraceCheckUtils]: 1: Hoare triple {1104#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1094#true} is VALID [2022-04-27 16:46:33,532 INFO L290 TraceCheckUtils]: 2: Hoare triple {1094#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1094#true} is VALID [2022-04-27 16:46:33,532 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1094#true} {1094#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1094#true} is VALID [2022-04-27 16:46:33,532 INFO L272 TraceCheckUtils]: 4: Hoare triple {1094#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1094#true} is VALID [2022-04-27 16:46:33,533 INFO L290 TraceCheckUtils]: 5: Hoare triple {1094#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1099#(= main_~y~0 0)} is VALID [2022-04-27 16:46:33,533 INFO L290 TraceCheckUtils]: 6: Hoare triple {1099#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,534 INFO L290 TraceCheckUtils]: 7: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,534 INFO L290 TraceCheckUtils]: 8: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,535 INFO L290 TraceCheckUtils]: 9: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,535 INFO L290 TraceCheckUtils]: 10: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,535 INFO L290 TraceCheckUtils]: 11: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,537 INFO L290 TraceCheckUtils]: 12: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,538 INFO L290 TraceCheckUtils]: 13: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:46:33,538 INFO L290 TraceCheckUtils]: 14: Hoare triple {1100#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1101#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:33,539 INFO L272 TraceCheckUtils]: 15: Hoare triple {1101#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1102#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:46:33,539 INFO L290 TraceCheckUtils]: 16: Hoare triple {1102#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1103#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:46:33,539 INFO L290 TraceCheckUtils]: 17: Hoare triple {1103#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1095#false} is VALID [2022-04-27 16:46:33,540 INFO L290 TraceCheckUtils]: 18: Hoare triple {1095#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1095#false} is VALID [2022-04-27 16:46:33,540 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-27 16:46:33,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:46:33,540 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [58995715] [2022-04-27 16:46:33,540 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [58995715] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:46:33,540 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:46:33,540 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-27 16:46:33,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1155431948] [2022-04-27 16:46:33,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:46:33,541 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:46:33,542 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:46:33,542 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,557 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:33,557 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:46:33,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:46:33,557 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:46:33,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-27 16:46:33,558 INFO L87 Difference]: Start difference. First operand 37 states and 58 transitions. Second operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:33,763 INFO L93 Difference]: Finished difference Result 52 states and 80 transitions. [2022-04-27 16:46:33,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-27 16:46:33,763 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:46:33,763 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:46:33,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 55 transitions. [2022-04-27 16:46:33,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 55 transitions. [2022-04-27 16:46:33,766 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 55 transitions. [2022-04-27 16:46:33,814 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 55 edges. 55 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:33,818 INFO L225 Difference]: With dead ends: 52 [2022-04-27 16:46:33,818 INFO L226 Difference]: Without dead ends: 46 [2022-04-27 16:46:33,818 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2022-04-27 16:46:33,819 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 31 mSDsluCounter, 34 mSDsCounter, 0 mSdLazyCounter, 69 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 47 SdHoareTripleChecker+Invalid, 89 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 69 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 6 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:46:33,819 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [31 Valid, 47 Invalid, 89 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 69 Invalid, 0 Unknown, 6 Unchecked, 0.1s Time] [2022-04-27 16:46:33,819 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2022-04-27 16:46:33,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 39. [2022-04-27 16:46:33,824 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:46:33,824 INFO L82 GeneralOperation]: Start isEquivalent. First operand 46 states. Second operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,825 INFO L74 IsIncluded]: Start isIncluded. First operand 46 states. Second operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,825 INFO L87 Difference]: Start difference. First operand 46 states. Second operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:33,826 INFO L93 Difference]: Finished difference Result 46 states and 73 transitions. [2022-04-27 16:46:33,826 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 73 transitions. [2022-04-27 16:46:33,828 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:46:33,828 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:46:33,828 INFO L74 IsIncluded]: Start isIncluded. First operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 46 states. [2022-04-27 16:46:33,829 INFO L87 Difference]: Start difference. First operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 46 states. [2022-04-27 16:46:33,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:46:33,833 INFO L93 Difference]: Finished difference Result 46 states and 73 transitions. [2022-04-27 16:46:33,833 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 73 transitions. [2022-04-27 16:46:33,838 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:46:33,838 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:46:33,838 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:46:33,838 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:46:33,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 34 states have internal predecessors, (57), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 61 transitions. [2022-04-27 16:46:33,847 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 61 transitions. Word has length 19 [2022-04-27 16:46:33,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:46:33,847 INFO L495 AbstractCegarLoop]: Abstraction has 39 states and 61 transitions. [2022-04-27 16:46:33,847 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.0) internal successors, (14), 6 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:33,848 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 61 transitions. [2022-04-27 16:46:33,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:46:33,848 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:46:33,848 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:46:33,848 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-04-27 16:46:33,849 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:46:33,849 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:46:33,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1453978548, now seen corresponding path program 1 times [2022-04-27 16:46:33,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:46:33,849 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028325417] [2022-04-27 16:46:33,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:46:33,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:46:33,867 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,868 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:33,886 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,896 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:46:33,979 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:46:33,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:33,984 INFO L290 TraceCheckUtils]: 0: Hoare triple {1311#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1300#true} is VALID [2022-04-27 16:46:33,984 INFO L290 TraceCheckUtils]: 1: Hoare triple {1300#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:33,984 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1300#true} {1300#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:33,984 INFO L272 TraceCheckUtils]: 0: Hoare triple {1300#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1311#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:46:33,985 INFO L290 TraceCheckUtils]: 1: Hoare triple {1311#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1300#true} is VALID [2022-04-27 16:46:33,985 INFO L290 TraceCheckUtils]: 2: Hoare triple {1300#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:33,985 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1300#true} {1300#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:33,985 INFO L272 TraceCheckUtils]: 4: Hoare triple {1300#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:33,985 INFO L290 TraceCheckUtils]: 5: Hoare triple {1300#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1300#true} is VALID [2022-04-27 16:46:33,986 INFO L290 TraceCheckUtils]: 6: Hoare triple {1300#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:33,986 INFO L290 TraceCheckUtils]: 7: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:33,987 INFO L290 TraceCheckUtils]: 8: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1306#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:46:33,987 INFO L290 TraceCheckUtils]: 9: Hoare triple {1306#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:46:33,988 INFO L290 TraceCheckUtils]: 10: Hoare triple {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:46:33,989 INFO L290 TraceCheckUtils]: 11: Hoare triple {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:46:33,990 INFO L290 TraceCheckUtils]: 12: Hoare triple {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:46:33,991 INFO L290 TraceCheckUtils]: 13: Hoare triple {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:33,992 INFO L290 TraceCheckUtils]: 14: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:33,993 INFO L272 TraceCheckUtils]: 15: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1309#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:46:33,993 INFO L290 TraceCheckUtils]: 16: Hoare triple {1309#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1310#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:46:33,994 INFO L290 TraceCheckUtils]: 17: Hoare triple {1310#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1301#false} is VALID [2022-04-27 16:46:33,994 INFO L290 TraceCheckUtils]: 18: Hoare triple {1301#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1301#false} is VALID [2022-04-27 16:46:33,994 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:46:33,994 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:46:33,994 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028325417] [2022-04-27 16:46:33,994 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028325417] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:46:33,994 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1595036959] [2022-04-27 16:46:33,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:46:33,994 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:46:33,994 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:46:33,995 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:46:33,996 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 16:46:34,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:34,028 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 16:46:34,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:46:34,042 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:46:35,180 INFO L272 TraceCheckUtils]: 0: Hoare triple {1300#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:35,180 INFO L290 TraceCheckUtils]: 1: Hoare triple {1300#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1300#true} is VALID [2022-04-27 16:46:35,180 INFO L290 TraceCheckUtils]: 2: Hoare triple {1300#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:35,180 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1300#true} {1300#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:35,180 INFO L272 TraceCheckUtils]: 4: Hoare triple {1300#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:35,180 INFO L290 TraceCheckUtils]: 5: Hoare triple {1300#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1300#true} is VALID [2022-04-27 16:46:35,181 INFO L290 TraceCheckUtils]: 6: Hoare triple {1300#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,181 INFO L290 TraceCheckUtils]: 7: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,182 INFO L290 TraceCheckUtils]: 8: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1306#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:46:35,183 INFO L290 TraceCheckUtils]: 9: Hoare triple {1306#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:46:35,183 INFO L290 TraceCheckUtils]: 10: Hoare triple {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:46:35,185 INFO L290 TraceCheckUtils]: 11: Hoare triple {1307#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:46:35,185 INFO L290 TraceCheckUtils]: 12: Hoare triple {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:46:35,187 INFO L290 TraceCheckUtils]: 13: Hoare triple {1308#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,187 INFO L290 TraceCheckUtils]: 14: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:35,188 INFO L272 TraceCheckUtils]: 15: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1360#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:46:35,188 INFO L290 TraceCheckUtils]: 16: Hoare triple {1360#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1364#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:46:35,188 INFO L290 TraceCheckUtils]: 17: Hoare triple {1364#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1301#false} is VALID [2022-04-27 16:46:35,189 INFO L290 TraceCheckUtils]: 18: Hoare triple {1301#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1301#false} is VALID [2022-04-27 16:46:35,189 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:46:35,189 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:46:42,052 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~x~0_40 Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~z~0_30 Int) (|v_main_#t~post14_11| Int) (|v_main_#t~post13_11| Int)) (or (forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31) (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296))) (.cse1 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (and (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ (* v_it_6 4294967295) c_main_~y~0) 4294967296))))) (not .cse0) (not (< .cse1 v_main_~x~0_40))) (or .cse0 (not (= v_main_~x~0_40 .cse1))))))) (let ((.cse2 (mod c_main_~z~0 4294967296))) (and (or (not (< 0 .cse2)) (exists ((v_it_5 Int)) (and (<= (+ v_main_~z~0_30 v_it_5 1) c_main_~z~0) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) (not (< v_main_~z~0_30 c_main_~z~0)) (not (= v_main_~x~0_40 (+ (* (- 1) v_main_~z~0_30) c_main_~x~0 c_main_~z~0)))) (or (not (= |v_main_#t~post13_11| |main_#t~post13|)) (not (<= .cse2 0)) (not (= v_main_~z~0_30 c_main_~z~0)) (not (= v_main_~x~0_40 c_main_~x~0)) (not (= |v_main_#t~post14_11| |main_#t~post14|))))))) is different from false [2022-04-27 16:46:48,580 INFO L290 TraceCheckUtils]: 18: Hoare triple {1301#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1301#false} is VALID [2022-04-27 16:46:48,581 INFO L290 TraceCheckUtils]: 17: Hoare triple {1364#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1301#false} is VALID [2022-04-27 16:46:48,581 INFO L290 TraceCheckUtils]: 16: Hoare triple {1360#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1364#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:46:48,582 INFO L272 TraceCheckUtils]: 15: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1360#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:46:48,582 INFO L290 TraceCheckUtils]: 14: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:48,639 INFO L290 TraceCheckUtils]: 13: Hoare triple {1386#(forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))) (or (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:48,647 INFO L290 TraceCheckUtils]: 12: Hoare triple {1386#(forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))) (or (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1386#(forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))) (or (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} is VALID [2022-04-27 16:46:50,657 WARN L290 TraceCheckUtils]: 11: Hoare triple {1393#(forall ((v_main_~x~0_40 Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~z~0_30 Int) (|v_main_#t~post14_11| Int) (|v_main_#t~post13_11| Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_30 v_it_5 1) main_~z~0))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~z~0_30 main_~z~0)) (not (= (+ (* (- 1) v_main_~z~0_30) main_~z~0 main_~x~0) v_main_~x~0_40))) (or (not (= |v_main_#t~post13_11| |main_#t~post13|)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~z~0_30 main_~z~0)) (not (= v_main_~x~0_40 main_~x~0)) (not (= |v_main_#t~post14_11| |main_#t~post14|)))) (forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))) (or (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1386#(forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) main_~x~0)))) (or (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} is UNKNOWN [2022-04-27 16:46:52,674 WARN L290 TraceCheckUtils]: 10: Hoare triple {1393#(forall ((v_main_~x~0_40 Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~z~0_30 Int) (|v_main_#t~post14_11| Int) (|v_main_#t~post13_11| Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_30 v_it_5 1) main_~z~0))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~z~0_30 main_~z~0)) (not (= (+ (* (- 1) v_main_~z~0_30) main_~z~0 main_~x~0) v_main_~x~0_40))) (or (not (= |v_main_#t~post13_11| |main_#t~post13|)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~z~0_30 main_~z~0)) (not (= v_main_~x~0_40 main_~x~0)) (not (= |v_main_#t~post14_11| |main_#t~post14|)))) (forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))) (or (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1393#(forall ((v_main_~x~0_40 Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~z~0_30 Int) (|v_main_#t~post14_11| Int) (|v_main_#t~post13_11| Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_30 v_it_5 1) main_~z~0))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~z~0_30 main_~z~0)) (not (= (+ (* (- 1) v_main_~z~0_30) main_~z~0 main_~x~0) v_main_~x~0_40))) (or (not (= |v_main_#t~post13_11| |main_#t~post13|)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~z~0_30 main_~z~0)) (not (= v_main_~x~0_40 main_~x~0)) (not (= |v_main_#t~post14_11| |main_#t~post14|)))) (forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))) (or (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))))} is UNKNOWN [2022-04-27 16:46:52,682 INFO L290 TraceCheckUtils]: 9: Hoare triple {1400#(forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1393#(forall ((v_main_~x~0_40 Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~z~0_30 Int) (|v_main_#t~post14_11| Int) (|v_main_#t~post13_11| Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_30 v_it_5 1) main_~z~0))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~z~0_30 main_~z~0)) (not (= (+ (* (- 1) v_main_~z~0_30) main_~z~0 main_~x~0) v_main_~x~0_40))) (or (not (= |v_main_#t~post13_11| |main_#t~post13|)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~z~0_30 main_~z~0)) (not (= v_main_~x~0_40 main_~x~0)) (not (= |v_main_#t~post14_11| |main_#t~post14|)))) (forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (<= aux_mod_v_main_~x~0_39_31 0) (and (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_39_31 v_it_6 (* aux_div_v_main_~x~0_39_31 4294967296) 1) v_main_~x~0_40) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) v_main_~x~0_40))) (or (not (= v_main_~x~0_40 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))))} is VALID [2022-04-27 16:46:52,684 INFO L290 TraceCheckUtils]: 8: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1400#(forall ((aux_div_v_main_~x~0_39_31 Int) (aux_mod_v_main_~x~0_39_31 Int)) (or (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296))))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (not (= (+ aux_mod_v_main_~x~0_39_31 (* aux_div_v_main_~x~0_39_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_39_31 0) (<= 4294967296 aux_mod_v_main_~x~0_39_31)))} is VALID [2022-04-27 16:46:52,684 INFO L290 TraceCheckUtils]: 7: Hoare triple {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:52,685 INFO L290 TraceCheckUtils]: 6: Hoare triple {1300#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1305#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:46:52,685 INFO L290 TraceCheckUtils]: 5: Hoare triple {1300#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1300#true} is VALID [2022-04-27 16:46:52,685 INFO L272 TraceCheckUtils]: 4: Hoare triple {1300#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:52,685 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1300#true} {1300#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:52,685 INFO L290 TraceCheckUtils]: 2: Hoare triple {1300#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:52,685 INFO L290 TraceCheckUtils]: 1: Hoare triple {1300#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1300#true} is VALID [2022-04-27 16:46:52,685 INFO L272 TraceCheckUtils]: 0: Hoare triple {1300#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1300#true} is VALID [2022-04-27 16:46:52,685 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 1 not checked. [2022-04-27 16:46:52,685 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1595036959] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:46:52,685 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:46:52,686 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 14 [2022-04-27 16:46:52,686 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1831732505] [2022-04-27 16:46:52,686 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:46:52,686 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:46:52,686 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:46:52,686 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:46:58,268 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 30 edges. 28 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-27 16:46:58,268 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:46:58,268 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:46:58,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:46:58,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=122, Unknown=2, NotChecked=22, Total=182 [2022-04-27 16:46:58,269 INFO L87 Difference]: Start difference. First operand 39 states and 61 transitions. Second operand has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,023 WARN L232 SmtUtils]: Spent 19.60s on a formula simplification. DAG size of input: 94 DAG size of output: 91 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:47:20,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:47:20,165 INFO L93 Difference]: Finished difference Result 52 states and 80 transitions. [2022-04-27 16:47:20,165 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-27 16:47:20,165 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:47:20,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:47:20,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 43 transitions. [2022-04-27 16:47:20,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 43 transitions. [2022-04-27 16:47:20,168 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 43 transitions. [2022-04-27 16:47:20,211 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 43 edges. 43 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:47:20,211 INFO L225 Difference]: With dead ends: 52 [2022-04-27 16:47:20,211 INFO L226 Difference]: Without dead ends: 49 [2022-04-27 16:47:20,212 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 28 SyntacticMatches, 9 SemanticMatches, 18 ConstructedPredicates, 1 IntricatePredicates, 1 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 24.0s TimeCoverageRelationStatistics Valid=84, Invalid=260, Unknown=2, NotChecked=34, Total=380 [2022-04-27 16:47:20,212 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 19 mSDsluCounter, 48 mSDsCounter, 0 mSdLazyCounter, 45 mSolverCounterSat, 7 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 19 SdHoareTripleChecker+Valid, 66 SdHoareTripleChecker+Invalid, 113 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 7 IncrementalHoareTripleChecker+Valid, 45 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 61 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:47:20,212 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [19 Valid, 66 Invalid, 113 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [7 Valid, 45 Invalid, 0 Unknown, 61 Unchecked, 0.0s Time] [2022-04-27 16:47:20,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-04-27 16:47:20,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 41. [2022-04-27 16:47:20,214 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:47:20,215 INFO L82 GeneralOperation]: Start isEquivalent. First operand 49 states. Second operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,215 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,215 INFO L87 Difference]: Start difference. First operand 49 states. Second operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:47:20,216 INFO L93 Difference]: Finished difference Result 49 states and 77 transitions. [2022-04-27 16:47:20,216 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 77 transitions. [2022-04-27 16:47:20,216 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:47:20,216 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:47:20,217 INFO L74 IsIncluded]: Start isIncluded. First operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 49 states. [2022-04-27 16:47:20,217 INFO L87 Difference]: Start difference. First operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 49 states. [2022-04-27 16:47:20,218 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:47:20,218 INFO L93 Difference]: Finished difference Result 49 states and 77 transitions. [2022-04-27 16:47:20,218 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 77 transitions. [2022-04-27 16:47:20,218 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:47:20,218 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:47:20,218 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:47:20,218 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:47:20,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41 states, 36 states have (on average 1.6944444444444444) internal successors, (61), 36 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41 states to 41 states and 65 transitions. [2022-04-27 16:47:20,219 INFO L78 Accepts]: Start accepts. Automaton has 41 states and 65 transitions. Word has length 19 [2022-04-27 16:47:20,220 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:47:20,220 INFO L495 AbstractCegarLoop]: Abstraction has 41 states and 65 transitions. [2022-04-27 16:47:20,220 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.7142857142857142) internal successors, (24), 11 states have internal predecessors, (24), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,220 INFO L276 IsEmpty]: Start isEmpty. Operand 41 states and 65 transitions. [2022-04-27 16:47:20,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:47:20,220 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:47:20,220 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:47:20,247 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 16:47:20,438 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:47:20,438 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:47:20,438 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:47:20,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1642739759, now seen corresponding path program 1 times [2022-04-27 16:47:20,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:47:20,438 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [559291320] [2022-04-27 16:47:20,438 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:47:20,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:47:20,447 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:47:20,449 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_10 .cse0 (* (- 4294967296) (div (+ main_~y~0_10 .cse0) 4294967296)))) 0)) [2022-04-27 16:47:20,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:47:20,469 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.5))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:47:20,472 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_10 .cse0 (* (- 4294967296) (div (+ main_~y~0_10 .cse0) 4294967296)))) 0)) [2022-04-27 16:47:20,552 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:47:20,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:47:20,556 INFO L290 TraceCheckUtils]: 0: Hoare triple {1644#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1634#true} is VALID [2022-04-27 16:47:20,557 INFO L290 TraceCheckUtils]: 1: Hoare triple {1634#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1634#true} is VALID [2022-04-27 16:47:20,557 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1634#true} {1634#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1634#true} is VALID [2022-04-27 16:47:20,557 INFO L272 TraceCheckUtils]: 0: Hoare triple {1634#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1644#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:47:20,557 INFO L290 TraceCheckUtils]: 1: Hoare triple {1644#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1634#true} is VALID [2022-04-27 16:47:20,557 INFO L290 TraceCheckUtils]: 2: Hoare triple {1634#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1634#true} is VALID [2022-04-27 16:47:20,558 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1634#true} {1634#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1634#true} is VALID [2022-04-27 16:47:20,558 INFO L272 TraceCheckUtils]: 4: Hoare triple {1634#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1634#true} is VALID [2022-04-27 16:47:20,558 INFO L290 TraceCheckUtils]: 5: Hoare triple {1634#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1639#(= main_~y~0 0)} is VALID [2022-04-27 16:47:20,559 INFO L290 TraceCheckUtils]: 6: Hoare triple {1639#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,559 INFO L290 TraceCheckUtils]: 7: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,559 INFO L290 TraceCheckUtils]: 8: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,560 INFO L290 TraceCheckUtils]: 9: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,561 INFO L290 TraceCheckUtils]: 10: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,562 INFO L290 TraceCheckUtils]: 11: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,562 INFO L290 TraceCheckUtils]: 12: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,563 INFO L290 TraceCheckUtils]: 13: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:47:20,563 INFO L290 TraceCheckUtils]: 14: Hoare triple {1640#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1641#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:20,564 INFO L272 TraceCheckUtils]: 15: Hoare triple {1641#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1642#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:47:20,564 INFO L290 TraceCheckUtils]: 16: Hoare triple {1642#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1643#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:47:20,565 INFO L290 TraceCheckUtils]: 17: Hoare triple {1643#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1635#false} is VALID [2022-04-27 16:47:20,565 INFO L290 TraceCheckUtils]: 18: Hoare triple {1635#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1635#false} is VALID [2022-04-27 16:47:20,565 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-27 16:47:20,565 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:47:20,565 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [559291320] [2022-04-27 16:47:20,565 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [559291320] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:47:20,565 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:47:20,565 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-27 16:47:20,565 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [190374689] [2022-04-27 16:47:20,565 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:47:20,566 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:47:20,566 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:47:20,566 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,580 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:47:20,581 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:47:20,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:47:20,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:47:20,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-27 16:47:20,581 INFO L87 Difference]: Start difference. First operand 41 states and 65 transitions. Second operand has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:47:20,749 INFO L93 Difference]: Finished difference Result 57 states and 89 transitions. [2022-04-27 16:47:20,749 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-27 16:47:20,750 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:47:20,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:47:20,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,751 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 57 transitions. [2022-04-27 16:47:20,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 57 transitions. [2022-04-27 16:47:20,752 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 57 transitions. [2022-04-27 16:47:20,806 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:47:20,807 INFO L225 Difference]: With dead ends: 57 [2022-04-27 16:47:20,807 INFO L226 Difference]: Without dead ends: 52 [2022-04-27 16:47:20,807 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2022-04-27 16:47:20,808 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 33 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 54 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 33 SdHoareTripleChecker+Valid, 41 SdHoareTripleChecker+Invalid, 75 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 54 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 6 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:47:20,808 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [33 Valid, 41 Invalid, 75 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 54 Invalid, 0 Unknown, 6 Unchecked, 0.1s Time] [2022-04-27 16:47:20,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2022-04-27 16:47:20,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 43. [2022-04-27 16:47:20,810 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:47:20,810 INFO L82 GeneralOperation]: Start isEquivalent. First operand 52 states. Second operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,811 INFO L74 IsIncluded]: Start isIncluded. First operand 52 states. Second operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,811 INFO L87 Difference]: Start difference. First operand 52 states. Second operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:47:20,812 INFO L93 Difference]: Finished difference Result 52 states and 83 transitions. [2022-04-27 16:47:20,812 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 83 transitions. [2022-04-27 16:47:20,812 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:47:20,812 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:47:20,812 INFO L74 IsIncluded]: Start isIncluded. First operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 52 states. [2022-04-27 16:47:20,813 INFO L87 Difference]: Start difference. First operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 52 states. [2022-04-27 16:47:20,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:47:20,814 INFO L93 Difference]: Finished difference Result 52 states and 83 transitions. [2022-04-27 16:47:20,814 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 83 transitions. [2022-04-27 16:47:20,814 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:47:20,814 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:47:20,814 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:47:20,814 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:47:20,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 38 states have internal predecessors, (64), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,815 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 68 transitions. [2022-04-27 16:47:20,815 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 68 transitions. Word has length 19 [2022-04-27 16:47:20,815 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:47:20,815 INFO L495 AbstractCegarLoop]: Abstraction has 43 states and 68 transitions. [2022-04-27 16:47:20,815 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.142857142857143) internal successors, (15), 6 states have internal predecessors, (15), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:47:20,815 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 68 transitions. [2022-04-27 16:47:20,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:47:20,816 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:47:20,816 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:47:20,816 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-04-27 16:47:20,816 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:47:20,816 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:47:20,816 INFO L85 PathProgramCache]: Analyzing trace with hash -869752682, now seen corresponding path program 1 times [2022-04-27 16:47:20,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:47:20,816 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1822148343] [2022-04-27 16:47:20,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:47:20,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:47:20,832 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.0))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:47:20,833 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:47:20,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:47:20,851 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.5))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:47:20,854 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.6))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:47:20,929 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:47:20,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:47:20,934 INFO L290 TraceCheckUtils]: 0: Hoare triple {1870#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1861#true} is VALID [2022-04-27 16:47:20,934 INFO L290 TraceCheckUtils]: 1: Hoare triple {1861#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:20,935 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1861#true} {1861#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:20,935 INFO L272 TraceCheckUtils]: 0: Hoare triple {1861#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1870#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:47:20,935 INFO L290 TraceCheckUtils]: 1: Hoare triple {1870#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1861#true} is VALID [2022-04-27 16:47:20,935 INFO L290 TraceCheckUtils]: 2: Hoare triple {1861#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:20,935 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1861#true} {1861#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:20,935 INFO L272 TraceCheckUtils]: 4: Hoare triple {1861#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:20,935 INFO L290 TraceCheckUtils]: 5: Hoare triple {1861#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1861#true} is VALID [2022-04-27 16:47:20,936 INFO L290 TraceCheckUtils]: 6: Hoare triple {1861#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:20,936 INFO L290 TraceCheckUtils]: 7: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:20,937 INFO L290 TraceCheckUtils]: 8: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:20,937 INFO L290 TraceCheckUtils]: 9: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:20,939 INFO L290 TraceCheckUtils]: 10: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:20,939 INFO L290 TraceCheckUtils]: 11: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:20,941 INFO L290 TraceCheckUtils]: 12: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:20,941 INFO L290 TraceCheckUtils]: 13: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:20,941 INFO L290 TraceCheckUtils]: 14: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:20,942 INFO L272 TraceCheckUtils]: 15: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1868#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:47:20,942 INFO L290 TraceCheckUtils]: 16: Hoare triple {1868#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1869#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:47:20,943 INFO L290 TraceCheckUtils]: 17: Hoare triple {1869#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1862#false} is VALID [2022-04-27 16:47:20,943 INFO L290 TraceCheckUtils]: 18: Hoare triple {1862#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1862#false} is VALID [2022-04-27 16:47:20,943 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:47:20,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:47:20,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1822148343] [2022-04-27 16:47:20,943 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1822148343] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:47:20,943 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1602275567] [2022-04-27 16:47:20,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:47:20,943 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:47:20,943 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:47:20,944 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:47:20,945 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 16:47:20,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:47:20,979 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 16:47:20,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:47:20,988 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:47:21,811 INFO L272 TraceCheckUtils]: 0: Hoare triple {1861#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:21,812 INFO L290 TraceCheckUtils]: 1: Hoare triple {1861#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1861#true} is VALID [2022-04-27 16:47:21,812 INFO L290 TraceCheckUtils]: 2: Hoare triple {1861#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:21,812 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1861#true} {1861#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:21,812 INFO L272 TraceCheckUtils]: 4: Hoare triple {1861#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:47:21,812 INFO L290 TraceCheckUtils]: 5: Hoare triple {1861#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1861#true} is VALID [2022-04-27 16:47:21,813 INFO L290 TraceCheckUtils]: 6: Hoare triple {1861#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:21,813 INFO L290 TraceCheckUtils]: 7: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:21,814 INFO L290 TraceCheckUtils]: 8: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:21,814 INFO L290 TraceCheckUtils]: 9: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:21,816 INFO L290 TraceCheckUtils]: 10: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:21,816 INFO L290 TraceCheckUtils]: 11: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:47:21,817 INFO L290 TraceCheckUtils]: 12: Hoare triple {1867#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:21,818 INFO L290 TraceCheckUtils]: 13: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:21,818 INFO L290 TraceCheckUtils]: 14: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:21,819 INFO L272 TraceCheckUtils]: 15: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1919#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:47:21,820 INFO L290 TraceCheckUtils]: 16: Hoare triple {1919#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1923#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:47:21,820 INFO L290 TraceCheckUtils]: 17: Hoare triple {1923#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1862#false} is VALID [2022-04-27 16:47:21,820 INFO L290 TraceCheckUtils]: 18: Hoare triple {1862#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1862#false} is VALID [2022-04-27 16:47:21,820 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:47:21,820 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:47:57,188 INFO L290 TraceCheckUtils]: 18: Hoare triple {1862#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1862#false} is VALID [2022-04-27 16:47:57,189 INFO L290 TraceCheckUtils]: 17: Hoare triple {1923#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1862#false} is VALID [2022-04-27 16:47:57,189 INFO L290 TraceCheckUtils]: 16: Hoare triple {1919#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1923#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:47:57,190 INFO L272 TraceCheckUtils]: 15: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1919#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:47:57,191 INFO L290 TraceCheckUtils]: 14: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:57,191 INFO L290 TraceCheckUtils]: 13: Hoare triple {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:57,201 INFO L290 TraceCheckUtils]: 12: Hoare triple {1948#(forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {1866#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:47:58,302 INFO L290 TraceCheckUtils]: 11: Hoare triple {1948#(forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {1948#(forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))} is VALID [2022-04-27 16:48:00,310 WARN L290 TraceCheckUtils]: 10: Hoare triple {1955#(forall ((v_main_~x~0_44 Int) (main_~y~0 Int) (v_main_~y~0_32 Int) (|main_#t~post11| Int) (|v_main_#t~post12_7| Int) (|v_main_#t~post11_7| Int) (|main_#t~post12| Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (= v_main_~y~0_32 (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_44)))) (not (< v_main_~x~0_44 main_~x~0))) (or (not (= v_main_~y~0_32 main_~y~0)) (not (= |v_main_#t~post12_7| |main_#t~post12|)) (not (= |v_main_#t~post11_7| |main_#t~post11|)) (not (= v_main_~x~0_44 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)))) (forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {1948#(forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)) main_~x~0)) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))} is UNKNOWN [2022-04-27 16:48:02,337 WARN L290 TraceCheckUtils]: 9: Hoare triple {1955#(forall ((v_main_~x~0_44 Int) (main_~y~0 Int) (v_main_~y~0_32 Int) (|main_#t~post11| Int) (|v_main_#t~post12_7| Int) (|v_main_#t~post11_7| Int) (|main_#t~post12| Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (= v_main_~y~0_32 (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_44)))) (not (< v_main_~x~0_44 main_~x~0))) (or (not (= v_main_~y~0_32 main_~y~0)) (not (= |v_main_#t~post12_7| |main_#t~post12|)) (not (= |v_main_#t~post11_7| |main_#t~post11|)) (not (= v_main_~x~0_44 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)))) (forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {1955#(forall ((v_main_~x~0_44 Int) (main_~y~0 Int) (v_main_~y~0_32 Int) (|main_#t~post11| Int) (|v_main_#t~post12_7| Int) (|v_main_#t~post11_7| Int) (|main_#t~post12| Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (= v_main_~y~0_32 (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_44)))) (not (< v_main_~x~0_44 main_~x~0))) (or (not (= v_main_~y~0_32 main_~y~0)) (not (= |v_main_#t~post12_7| |main_#t~post12|)) (not (= |v_main_#t~post11_7| |main_#t~post11|)) (not (= v_main_~x~0_44 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)))) (forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))))} is UNKNOWN [2022-04-27 16:48:02,353 INFO L290 TraceCheckUtils]: 8: Hoare triple {1962#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {1955#(forall ((v_main_~x~0_44 Int) (main_~y~0 Int) (v_main_~y~0_32 Int) (|main_#t~post11| Int) (|v_main_#t~post12_7| Int) (|v_main_#t~post11_7| Int) (|main_#t~post12| Int)) (or (and (or (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (= v_main_~y~0_32 (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_44)))) (not (< v_main_~x~0_44 main_~x~0))) (or (not (= v_main_~y~0_32 main_~y~0)) (not (= |v_main_#t~post12_7| |main_#t~post12|)) (not (= |v_main_#t~post11_7| |main_#t~post11|)) (not (= v_main_~x~0_44 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)))) (forall ((aux_mod_v_main_~x~0_43_31 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_43_31) (and (or (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~x~0_44 v_it_5 1) (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (not (< 0 (mod main_~z~0 4294967296))) (not (< v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296))))) (or (not (= v_main_~x~0_44 (+ aux_mod_v_main_~x~0_43_31 (* aux_div_v_main_~x~0_43_31 4294967296)))) (< 0 (mod main_~z~0 4294967296)))) (<= aux_mod_v_main_~x~0_43_31 0)))))} is VALID [2022-04-27 16:48:02,355 INFO L290 TraceCheckUtils]: 7: Hoare triple {1962#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {1962#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} is VALID [2022-04-27 16:48:02,355 INFO L290 TraceCheckUtils]: 6: Hoare triple {1861#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1962#(forall ((v_main_~x~0_44 Int) (aux_div_v_main_~x~0_43_31 Int)) (or (<= v_main_~x~0_44 (* aux_div_v_main_~x~0_43_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_43_31 4294967296) 4294967296) v_main_~x~0_44) (not (< 0 (mod main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= (+ v_main_~x~0_44 v_it_4 1) main_~x~0) (<= 1 v_it_4))) (not (< v_main_~x~0_44 main_~x~0))))} is VALID [2022-04-27 16:48:02,356 INFO L290 TraceCheckUtils]: 5: Hoare triple {1861#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {1861#true} is VALID [2022-04-27 16:48:02,356 INFO L272 TraceCheckUtils]: 4: Hoare triple {1861#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:48:02,356 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1861#true} {1861#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:48:02,356 INFO L290 TraceCheckUtils]: 2: Hoare triple {1861#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:48:02,356 INFO L290 TraceCheckUtils]: 1: Hoare triple {1861#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1861#true} is VALID [2022-04-27 16:48:02,356 INFO L272 TraceCheckUtils]: 0: Hoare triple {1861#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1861#true} is VALID [2022-04-27 16:48:02,356 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 1 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:48:02,356 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1602275567] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:48:02,356 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:48:02,356 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 8] total 12 [2022-04-27 16:48:02,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1480971104] [2022-04-27 16:48:02,357 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:48:02,357 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:48:02,357 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:48:02,357 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:11,214 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 27 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:11,214 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-04-27 16:48:11,214 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:48:11,215 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-04-27 16:48:11,215 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=94, Unknown=10, NotChecked=0, Total=132 [2022-04-27 16:48:11,215 INFO L87 Difference]: Start difference. First operand 43 states and 68 transitions. Second operand has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:17,628 INFO L93 Difference]: Finished difference Result 58 states and 92 transitions. [2022-04-27 16:48:17,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-27 16:48:17,628 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:48:17,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:48:17,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 48 transitions. [2022-04-27 16:48:17,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 48 transitions. [2022-04-27 16:48:17,631 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 48 transitions. [2022-04-27 16:48:17,674 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 48 edges. 48 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:17,675 INFO L225 Difference]: With dead ends: 58 [2022-04-27 16:48:17,675 INFO L226 Difference]: Without dead ends: 55 [2022-04-27 16:48:17,675 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 32 SyntacticMatches, 7 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 28.8s TimeCoverageRelationStatistics Valid=55, Invalid=174, Unknown=11, NotChecked=0, Total=240 [2022-04-27 16:48:17,677 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 30 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 45 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 55 SdHoareTripleChecker+Invalid, 114 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 45 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 57 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:48:17,677 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [30 Valid, 55 Invalid, 114 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 45 Invalid, 0 Unknown, 57 Unchecked, 0.1s Time] [2022-04-27 16:48:17,678 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2022-04-27 16:48:17,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 45. [2022-04-27 16:48:17,683 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:48:17,683 INFO L82 GeneralOperation]: Start isEquivalent. First operand 55 states. Second operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,683 INFO L74 IsIncluded]: Start isIncluded. First operand 55 states. Second operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,683 INFO L87 Difference]: Start difference. First operand 55 states. Second operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:17,692 INFO L93 Difference]: Finished difference Result 55 states and 89 transitions. [2022-04-27 16:48:17,692 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 89 transitions. [2022-04-27 16:48:17,692 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:48:17,692 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:48:17,692 INFO L74 IsIncluded]: Start isIncluded. First operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 55 states. [2022-04-27 16:48:17,692 INFO L87 Difference]: Start difference. First operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 55 states. [2022-04-27 16:48:17,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:17,694 INFO L93 Difference]: Finished difference Result 55 states and 89 transitions. [2022-04-27 16:48:17,694 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 89 transitions. [2022-04-27 16:48:17,694 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:48:17,694 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:48:17,694 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:48:17,694 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:48:17,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 40 states have (on average 1.7) internal successors, (68), 40 states have internal predecessors, (68), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 72 transitions. [2022-04-27 16:48:17,695 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 72 transitions. Word has length 19 [2022-04-27 16:48:17,695 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:48:17,695 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 72 transitions. [2022-04-27 16:48:17,696 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 9 states have internal predecessors, (25), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:17,696 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 72 transitions. [2022-04-27 16:48:17,696 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:48:17,696 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:48:17,696 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:48:17,712 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 16:48:17,898 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:48:17,899 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:48:17,899 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:48:17,899 INFO L85 PathProgramCache]: Analyzing trace with hash 84699953, now seen corresponding path program 1 times [2022-04-27 16:48:17,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:48:17,899 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2028245491] [2022-04-27 16:48:17,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:48:17,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:48:17,908 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:17,909 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:17,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:17,919 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:17,922 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.4))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:18,022 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:48:18,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:18,029 INFO L290 TraceCheckUtils]: 0: Hoare triple {2224#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2212#true} is VALID [2022-04-27 16:48:18,029 INFO L290 TraceCheckUtils]: 1: Hoare triple {2212#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,030 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2212#true} {2212#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,031 INFO L272 TraceCheckUtils]: 0: Hoare triple {2212#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2224#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:48:18,032 INFO L290 TraceCheckUtils]: 1: Hoare triple {2224#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2212#true} is VALID [2022-04-27 16:48:18,032 INFO L290 TraceCheckUtils]: 2: Hoare triple {2212#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,032 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2212#true} {2212#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,032 INFO L272 TraceCheckUtils]: 4: Hoare triple {2212#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,032 INFO L290 TraceCheckUtils]: 5: Hoare triple {2212#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2217#(= main_~y~0 0)} is VALID [2022-04-27 16:48:18,033 INFO L290 TraceCheckUtils]: 6: Hoare triple {2217#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2218#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:18,033 INFO L290 TraceCheckUtils]: 7: Hoare triple {2218#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2219#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:18,034 INFO L290 TraceCheckUtils]: 8: Hoare triple {2219#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:18,035 INFO L290 TraceCheckUtils]: 9: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:18,035 INFO L290 TraceCheckUtils]: 10: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:18,036 INFO L290 TraceCheckUtils]: 11: Hoare triple {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:18,036 INFO L290 TraceCheckUtils]: 12: Hoare triple {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:18,037 INFO L290 TraceCheckUtils]: 13: Hoare triple {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:18,038 INFO L290 TraceCheckUtils]: 14: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:18,039 INFO L272 TraceCheckUtils]: 15: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2222#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:48:18,039 INFO L290 TraceCheckUtils]: 16: Hoare triple {2222#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2223#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:48:18,039 INFO L290 TraceCheckUtils]: 17: Hoare triple {2223#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2213#false} is VALID [2022-04-27 16:48:18,039 INFO L290 TraceCheckUtils]: 18: Hoare triple {2213#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2213#false} is VALID [2022-04-27 16:48:18,039 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:48:18,039 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:48:18,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2028245491] [2022-04-27 16:48:18,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2028245491] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:48:18,040 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [779205392] [2022-04-27 16:48:18,040 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:48:18,040 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:48:18,040 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:48:18,041 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:48:18,042 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 16:48:18,070 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:18,071 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:48:18,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:18,079 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:48:18,734 INFO L272 TraceCheckUtils]: 0: Hoare triple {2212#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 1: Hoare triple {2212#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 2: Hoare triple {2212#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2212#true} {2212#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L272 TraceCheckUtils]: 4: Hoare triple {2212#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 5: Hoare triple {2212#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 6: Hoare triple {2212#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 7: Hoare triple {2212#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 8: Hoare triple {2212#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2212#true} is VALID [2022-04-27 16:48:18,735 INFO L290 TraceCheckUtils]: 9: Hoare triple {2212#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:18,739 INFO L290 TraceCheckUtils]: 10: Hoare triple {2212#true} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2258#(not (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:48:18,740 INFO L290 TraceCheckUtils]: 11: Hoare triple {2258#(not (< 0 (mod main_~y~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:18,741 INFO L290 TraceCheckUtils]: 12: Hoare triple {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:18,742 INFO L290 TraceCheckUtils]: 13: Hoare triple {2221#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:18,743 INFO L290 TraceCheckUtils]: 14: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:18,743 INFO L272 TraceCheckUtils]: 15: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2274#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:48:18,744 INFO L290 TraceCheckUtils]: 16: Hoare triple {2274#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2278#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:48:18,744 INFO L290 TraceCheckUtils]: 17: Hoare triple {2278#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2213#false} is VALID [2022-04-27 16:48:18,744 INFO L290 TraceCheckUtils]: 18: Hoare triple {2213#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2213#false} is VALID [2022-04-27 16:48:18,744 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:48:18,744 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:48:23,481 INFO L290 TraceCheckUtils]: 18: Hoare triple {2213#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2213#false} is VALID [2022-04-27 16:48:23,482 INFO L290 TraceCheckUtils]: 17: Hoare triple {2278#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2213#false} is VALID [2022-04-27 16:48:23,482 INFO L290 TraceCheckUtils]: 16: Hoare triple {2274#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2278#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:48:23,483 INFO L272 TraceCheckUtils]: 15: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2274#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:48:23,483 INFO L290 TraceCheckUtils]: 14: Hoare triple {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:23,498 INFO L290 TraceCheckUtils]: 13: Hoare triple {2300#(forall ((aux_mod_v_main_~x~0_46_31 Int) (aux_div_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (and (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_46_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {2220#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:23,507 INFO L290 TraceCheckUtils]: 12: Hoare triple {2300#(forall ((aux_mod_v_main_~x~0_46_31 Int) (aux_div_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (and (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_46_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2300#(forall ((aux_mod_v_main_~x~0_46_31 Int) (aux_div_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (and (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_46_31)))} is VALID [2022-04-27 16:48:23,508 INFO L290 TraceCheckUtils]: 11: Hoare triple {2258#(not (< 0 (mod main_~y~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2300#(forall ((aux_mod_v_main_~x~0_46_31 Int) (aux_div_v_main_~x~0_46_31 Int)) (or (<= aux_mod_v_main_~x~0_46_31 0) (and (or (not (< (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)) main_~x~0)) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))) (<= (+ aux_mod_v_main_~x~0_46_31 v_it_6 (* aux_div_v_main_~x~0_46_31 4294967296) 1) main_~x~0)))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_46_31 (* aux_div_v_main_~x~0_46_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_46_31)))} is VALID [2022-04-27 16:48:23,508 INFO L290 TraceCheckUtils]: 10: Hoare triple {2212#true} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2258#(not (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:48:23,508 INFO L290 TraceCheckUtils]: 9: Hoare triple {2212#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L290 TraceCheckUtils]: 8: Hoare triple {2212#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L290 TraceCheckUtils]: 7: Hoare triple {2212#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L290 TraceCheckUtils]: 6: Hoare triple {2212#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L290 TraceCheckUtils]: 5: Hoare triple {2212#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L272 TraceCheckUtils]: 4: Hoare triple {2212#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2212#true} {2212#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L290 TraceCheckUtils]: 2: Hoare triple {2212#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L290 TraceCheckUtils]: 1: Hoare triple {2212#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L272 TraceCheckUtils]: 0: Hoare triple {2212#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2212#true} is VALID [2022-04-27 16:48:23,509 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:48:23,509 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [779205392] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:48:23,509 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:48:23,510 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 7] total 14 [2022-04-27 16:48:23,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400176748] [2022-04-27 16:48:23,510 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:48:23,510 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:48:23,510 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:48:23,510 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:25,565 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 33 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:25,566 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:48:25,566 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:48:25,566 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:48:25,566 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=144, Unknown=1, NotChecked=0, Total=182 [2022-04-27 16:48:25,566 INFO L87 Difference]: Start difference. First operand 45 states and 72 transitions. Second operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:25,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:25,999 INFO L93 Difference]: Finished difference Result 64 states and 101 transitions. [2022-04-27 16:48:25,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 16:48:25,999 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:48:25,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:48:25,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 58 transitions. [2022-04-27 16:48:26,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 58 transitions. [2022-04-27 16:48:26,001 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 58 transitions. [2022-04-27 16:48:26,058 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:26,059 INFO L225 Difference]: With dead ends: 64 [2022-04-27 16:48:26,059 INFO L226 Difference]: Without dead ends: 61 [2022-04-27 16:48:26,059 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 35 SyntacticMatches, 6 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 115 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=101, Invalid=360, Unknown=1, NotChecked=0, Total=462 [2022-04-27 16:48:26,060 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 36 mSDsluCounter, 58 mSDsCounter, 0 mSdLazyCounter, 87 mSolverCounterSat, 19 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 71 SdHoareTripleChecker+Invalid, 130 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 19 IncrementalHoareTripleChecker+Valid, 87 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 24 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:48:26,060 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [36 Valid, 71 Invalid, 130 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [19 Valid, 87 Invalid, 0 Unknown, 24 Unchecked, 0.1s Time] [2022-04-27 16:48:26,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2022-04-27 16:48:26,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 44. [2022-04-27 16:48:26,061 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:48:26,062 INFO L82 GeneralOperation]: Start isEquivalent. First operand 61 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,062 INFO L74 IsIncluded]: Start isIncluded. First operand 61 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,062 INFO L87 Difference]: Start difference. First operand 61 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:26,063 INFO L93 Difference]: Finished difference Result 61 states and 98 transitions. [2022-04-27 16:48:26,063 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 98 transitions. [2022-04-27 16:48:26,063 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:48:26,063 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:48:26,063 INFO L74 IsIncluded]: Start isIncluded. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-27 16:48:26,063 INFO L87 Difference]: Start difference. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-27 16:48:26,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:26,064 INFO L93 Difference]: Finished difference Result 61 states and 98 transitions. [2022-04-27 16:48:26,064 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 98 transitions. [2022-04-27 16:48:26,065 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:48:26,065 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:48:26,065 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:48:26,065 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:48:26,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 70 transitions. [2022-04-27 16:48:26,066 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 70 transitions. Word has length 19 [2022-04-27 16:48:26,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:48:26,066 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 70 transitions. [2022-04-27 16:48:26,066 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.0) internal successors, (28), 11 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:26,066 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 70 transitions. [2022-04-27 16:48:26,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2022-04-27 16:48:26,066 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:48:26,066 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:48:26,082 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-27 16:48:26,266 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:48:26,267 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:48:26,267 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:48:26,267 INFO L85 PathProgramCache]: Analyzing trace with hash 857687030, now seen corresponding path program 1 times [2022-04-27 16:48:26,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:48:26,267 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294107676] [2022-04-27 16:48:26,267 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:48:26,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:48:26,275 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:26,277 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:26,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:26,288 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_2.3))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:26,292 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.4))) (+ main_~z~0_8 .cse0 (* (- 4294967296) (div (+ main_~z~0_8 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:26,400 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:48:26,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:26,405 INFO L290 TraceCheckUtils]: 0: Hoare triple {2604#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2592#true} is VALID [2022-04-27 16:48:26,405 INFO L290 TraceCheckUtils]: 1: Hoare triple {2592#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:26,405 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2592#true} {2592#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:26,406 INFO L272 TraceCheckUtils]: 0: Hoare triple {2592#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2604#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:48:26,406 INFO L290 TraceCheckUtils]: 1: Hoare triple {2604#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2592#true} is VALID [2022-04-27 16:48:26,406 INFO L290 TraceCheckUtils]: 2: Hoare triple {2592#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:26,406 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2592#true} {2592#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:26,406 INFO L272 TraceCheckUtils]: 4: Hoare triple {2592#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:26,412 INFO L290 TraceCheckUtils]: 5: Hoare triple {2592#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2597#(= main_~y~0 0)} is VALID [2022-04-27 16:48:26,413 INFO L290 TraceCheckUtils]: 6: Hoare triple {2597#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2598#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:26,414 INFO L290 TraceCheckUtils]: 7: Hoare triple {2598#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2599#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:26,415 INFO L290 TraceCheckUtils]: 8: Hoare triple {2599#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:26,415 INFO L290 TraceCheckUtils]: 9: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:48:26,416 INFO L290 TraceCheckUtils]: 10: Hoare triple {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:48:26,416 INFO L290 TraceCheckUtils]: 11: Hoare triple {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:48:26,417 INFO L290 TraceCheckUtils]: 12: Hoare triple {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:26,418 INFO L290 TraceCheckUtils]: 13: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:26,418 INFO L290 TraceCheckUtils]: 14: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:26,419 INFO L272 TraceCheckUtils]: 15: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2602#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:48:26,419 INFO L290 TraceCheckUtils]: 16: Hoare triple {2602#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2603#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:48:26,420 INFO L290 TraceCheckUtils]: 17: Hoare triple {2603#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2593#false} is VALID [2022-04-27 16:48:26,420 INFO L290 TraceCheckUtils]: 18: Hoare triple {2593#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2593#false} is VALID [2022-04-27 16:48:26,420 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:48:26,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:48:26,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294107676] [2022-04-27 16:48:26,420 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294107676] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:48:26,420 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [289192165] [2022-04-27 16:48:26,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:48:26,420 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:48:26,420 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:48:26,421 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:48:26,422 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 16:48:26,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:26,449 INFO L263 TraceCheckSpWp]: Trace formula consists of 64 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 16:48:26,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:26,458 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:48:27,055 INFO L272 TraceCheckUtils]: 0: Hoare triple {2592#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:27,055 INFO L290 TraceCheckUtils]: 1: Hoare triple {2592#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2592#true} is VALID [2022-04-27 16:48:27,055 INFO L290 TraceCheckUtils]: 2: Hoare triple {2592#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:27,055 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2592#true} {2592#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:27,055 INFO L272 TraceCheckUtils]: 4: Hoare triple {2592#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:27,056 INFO L290 TraceCheckUtils]: 5: Hoare triple {2592#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2592#true} is VALID [2022-04-27 16:48:27,056 INFO L290 TraceCheckUtils]: 6: Hoare triple {2592#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:27,056 INFO L290 TraceCheckUtils]: 7: Hoare triple {2592#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2592#true} is VALID [2022-04-27 16:48:27,056 INFO L290 TraceCheckUtils]: 8: Hoare triple {2592#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2592#true} is VALID [2022-04-27 16:48:27,057 INFO L290 TraceCheckUtils]: 9: Hoare triple {2592#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2635#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:48:27,058 INFO L290 TraceCheckUtils]: 10: Hoare triple {2635#(not (< 0 (mod main_~z~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2635#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:48:27,058 INFO L290 TraceCheckUtils]: 11: Hoare triple {2635#(not (< 0 (mod main_~z~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} is VALID [2022-04-27 16:48:27,060 INFO L290 TraceCheckUtils]: 12: Hoare triple {2601#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:27,060 INFO L290 TraceCheckUtils]: 13: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:27,061 INFO L290 TraceCheckUtils]: 14: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:27,066 INFO L272 TraceCheckUtils]: 15: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2654#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:48:27,066 INFO L290 TraceCheckUtils]: 16: Hoare triple {2654#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2658#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:48:27,067 INFO L290 TraceCheckUtils]: 17: Hoare triple {2658#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2593#false} is VALID [2022-04-27 16:48:27,067 INFO L290 TraceCheckUtils]: 18: Hoare triple {2593#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2593#false} is VALID [2022-04-27 16:48:27,067 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:48:27,067 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:48:33,159 INFO L290 TraceCheckUtils]: 18: Hoare triple {2593#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2593#false} is VALID [2022-04-27 16:48:33,160 INFO L290 TraceCheckUtils]: 17: Hoare triple {2658#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2593#false} is VALID [2022-04-27 16:48:33,160 INFO L290 TraceCheckUtils]: 16: Hoare triple {2654#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2658#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:48:33,161 INFO L272 TraceCheckUtils]: 15: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2654#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:48:33,162 INFO L290 TraceCheckUtils]: 14: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:33,162 INFO L290 TraceCheckUtils]: 13: Hoare triple {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:33,191 INFO L290 TraceCheckUtils]: 12: Hoare triple {2683#(forall ((aux_div_v_main_~x~0_48_31 Int) (aux_mod_v_main_~x~0_48_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296))))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= aux_mod_v_main_~x~0_48_31 0) (<= 4294967296 aux_mod_v_main_~x~0_48_31)))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2600#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:33,192 INFO L290 TraceCheckUtils]: 11: Hoare triple {2635#(not (< 0 (mod main_~z~0 4294967296)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2683#(forall ((aux_div_v_main_~x~0_48_31 Int) (aux_mod_v_main_~x~0_48_31 Int)) (or (and (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296))))) (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_48_31 (* aux_div_v_main_~x~0_48_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))))) (<= aux_mod_v_main_~x~0_48_31 0) (<= 4294967296 aux_mod_v_main_~x~0_48_31)))} is VALID [2022-04-27 16:48:33,193 INFO L290 TraceCheckUtils]: 10: Hoare triple {2635#(not (< 0 (mod main_~z~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2635#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:48:33,193 INFO L290 TraceCheckUtils]: 9: Hoare triple {2592#true} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2635#(not (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:48:33,193 INFO L290 TraceCheckUtils]: 8: Hoare triple {2592#true} [109] L23-2-->L23-2: Formula: (let ((.cse0 (mod v_main_~z~0_8 4294967296))) (or (and (forall ((v_it_2 Int)) (or (< 0 (mod (+ v_main_~z~0_8 (* v_it_2 4294967295)) 4294967296)) (not (<= (+ v_main_~z~0_7 v_it_2 1) v_main_~z~0_8)) (not (<= 1 v_it_2)))) (= v_main_~x~0_11 (+ v_main_~x~0_12 v_main_~z~0_8 (* (- 1) v_main_~z~0_7))) (< 0 .cse0) (< v_main_~z~0_7 v_main_~z~0_8)) (and (<= .cse0 0) (= v_main_~z~0_8 v_main_~z~0_7) (= v_main_~x~0_12 v_main_~x~0_11) (= |v_main_#t~post7_3| |v_main_#t~post7_1|) (= |v_main_#t~post8_3| |v_main_#t~post8_1|)))) InVars {main_~x~0=v_main_~x~0_12, main_#t~post8=|v_main_#t~post8_3|, main_~z~0=v_main_~z~0_8, main_#t~post7=|v_main_#t~post7_3|} OutVars{main_~x~0=v_main_~x~0_11, main_#t~post8=|v_main_#t~post8_1|, main_~z~0=v_main_~z~0_7, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post8, main_#t~post7] {2592#true} is VALID [2022-04-27 16:48:33,193 INFO L290 TraceCheckUtils]: 7: Hoare triple {2592#true} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2592#true} is VALID [2022-04-27 16:48:33,193 INFO L290 TraceCheckUtils]: 6: Hoare triple {2592#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:33,193 INFO L290 TraceCheckUtils]: 5: Hoare triple {2592#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2592#true} is VALID [2022-04-27 16:48:33,193 INFO L272 TraceCheckUtils]: 4: Hoare triple {2592#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:33,194 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2592#true} {2592#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:33,194 INFO L290 TraceCheckUtils]: 2: Hoare triple {2592#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:33,194 INFO L290 TraceCheckUtils]: 1: Hoare triple {2592#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2592#true} is VALID [2022-04-27 16:48:33,194 INFO L272 TraceCheckUtils]: 0: Hoare triple {2592#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2592#true} is VALID [2022-04-27 16:48:33,194 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:48:33,194 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [289192165] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:48:33,194 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:48:33,194 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7, 7] total 14 [2022-04-27 16:48:33,194 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934356095] [2022-04-27 16:48:33,194 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:48:33,195 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:48:33,195 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:48:33,195 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,269 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 33 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:34,269 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:48:34,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:48:34,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:48:34,270 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=144, Unknown=2, NotChecked=0, Total=182 [2022-04-27 16:48:34,270 INFO L87 Difference]: Start difference. First operand 44 states and 70 transitions. Second operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:34,672 INFO L93 Difference]: Finished difference Result 61 states and 98 transitions. [2022-04-27 16:48:34,672 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 16:48:34,672 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 19 [2022-04-27 16:48:34,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:48:34,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 60 transitions. [2022-04-27 16:48:34,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 60 transitions. [2022-04-27 16:48:34,674 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 60 transitions. [2022-04-27 16:48:34,744 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 60 edges. 60 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:48:34,744 INFO L225 Difference]: With dead ends: 61 [2022-04-27 16:48:34,744 INFO L226 Difference]: Without dead ends: 58 [2022-04-27 16:48:34,745 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 35 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=93, Invalid=367, Unknown=2, NotChecked=0, Total=462 [2022-04-27 16:48:34,745 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 32 mSDsluCounter, 55 mSDsCounter, 0 mSdLazyCounter, 112 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 67 SdHoareTripleChecker+Invalid, 154 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 112 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 26 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:48:34,745 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 67 Invalid, 154 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 112 Invalid, 0 Unknown, 26 Unchecked, 0.1s Time] [2022-04-27 16:48:34,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2022-04-27 16:48:34,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 44. [2022-04-27 16:48:34,747 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:48:34,747 INFO L82 GeneralOperation]: Start isEquivalent. First operand 58 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,747 INFO L74 IsIncluded]: Start isIncluded. First operand 58 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,748 INFO L87 Difference]: Start difference. First operand 58 states. Second operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:34,755 INFO L93 Difference]: Finished difference Result 58 states and 95 transitions. [2022-04-27 16:48:34,755 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 95 transitions. [2022-04-27 16:48:34,756 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:48:34,756 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:48:34,756 INFO L74 IsIncluded]: Start isIncluded. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 58 states. [2022-04-27 16:48:34,756 INFO L87 Difference]: Start difference. First operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 58 states. [2022-04-27 16:48:34,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:48:34,757 INFO L93 Difference]: Finished difference Result 58 states and 95 transitions. [2022-04-27 16:48:34,757 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 95 transitions. [2022-04-27 16:48:34,757 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:48:34,757 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:48:34,757 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:48:34,757 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:48:34,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 39 states have (on average 1.6923076923076923) internal successors, (66), 39 states have internal predecessors, (66), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 70 transitions. [2022-04-27 16:48:34,758 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 70 transitions. Word has length 19 [2022-04-27 16:48:34,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:48:34,758 INFO L495 AbstractCegarLoop]: Abstraction has 44 states and 70 transitions. [2022-04-27 16:48:34,758 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.9285714285714286) internal successors, (27), 11 states have internal predecessors, (27), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:48:34,758 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 70 transitions. [2022-04-27 16:48:34,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:48:34,759 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:48:34,759 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:48:34,776 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-27 16:48:34,963 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:48:34,963 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:48:34,964 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:48:34,964 INFO L85 PathProgramCache]: Analyzing trace with hash 1145856883, now seen corresponding path program 2 times [2022-04-27 16:48:34,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:48:34,965 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [752408409] [2022-04-27 16:48:34,965 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:48:34,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:48:34,974 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:34,975 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.1))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:34,976 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_10 .cse0 (* (- 4294967296) (div (+ main_~z~0_10 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:34,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:34,991 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.3))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:34,993 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.4))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:34,996 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_10 .cse0 (* (- 4294967296) (div (+ main_~z~0_10 .cse0) 4294967296)))) 0)) [2022-04-27 16:48:35,127 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:48:35,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:35,130 INFO L290 TraceCheckUtils]: 0: Hoare triple {2974#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2962#true} is VALID [2022-04-27 16:48:35,131 INFO L290 TraceCheckUtils]: 1: Hoare triple {2962#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,131 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2962#true} {2962#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,131 INFO L272 TraceCheckUtils]: 0: Hoare triple {2962#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2974#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:48:35,131 INFO L290 TraceCheckUtils]: 1: Hoare triple {2974#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2962#true} is VALID [2022-04-27 16:48:35,131 INFO L290 TraceCheckUtils]: 2: Hoare triple {2962#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,131 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2962#true} {2962#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,132 INFO L272 TraceCheckUtils]: 4: Hoare triple {2962#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,132 INFO L290 TraceCheckUtils]: 5: Hoare triple {2962#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2967#(= main_~y~0 0)} is VALID [2022-04-27 16:48:35,133 INFO L290 TraceCheckUtils]: 6: Hoare triple {2967#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2968#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,133 INFO L290 TraceCheckUtils]: 7: Hoare triple {2968#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,133 INFO L290 TraceCheckUtils]: 8: Hoare triple {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,134 INFO L290 TraceCheckUtils]: 9: Hoare triple {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,135 INFO L290 TraceCheckUtils]: 10: Hoare triple {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:35,135 INFO L290 TraceCheckUtils]: 11: Hoare triple {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:35,136 INFO L290 TraceCheckUtils]: 12: Hoare triple {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:35,137 INFO L290 TraceCheckUtils]: 13: Hoare triple {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:35,137 INFO L290 TraceCheckUtils]: 14: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:35,137 INFO L290 TraceCheckUtils]: 15: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:35,138 INFO L272 TraceCheckUtils]: 16: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {2972#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:48:35,138 INFO L290 TraceCheckUtils]: 17: Hoare triple {2972#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2973#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:48:35,139 INFO L290 TraceCheckUtils]: 18: Hoare triple {2973#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2963#false} is VALID [2022-04-27 16:48:35,139 INFO L290 TraceCheckUtils]: 19: Hoare triple {2963#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2963#false} is VALID [2022-04-27 16:48:35,139 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:48:35,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:48:35,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [752408409] [2022-04-27 16:48:35,139 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [752408409] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:48:35,139 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1674884486] [2022-04-27 16:48:35,139 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:48:35,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:48:35,140 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:48:35,140 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:48:35,141 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 16:48:35,174 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:48:35,174 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:48:35,175 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 16:48:35,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:48:35,216 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:48:35,489 INFO L272 TraceCheckUtils]: 0: Hoare triple {2962#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,489 INFO L290 TraceCheckUtils]: 1: Hoare triple {2962#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2962#true} is VALID [2022-04-27 16:48:35,489 INFO L290 TraceCheckUtils]: 2: Hoare triple {2962#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,490 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2962#true} {2962#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,490 INFO L272 TraceCheckUtils]: 4: Hoare triple {2962#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:48:35,490 INFO L290 TraceCheckUtils]: 5: Hoare triple {2962#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2967#(= main_~y~0 0)} is VALID [2022-04-27 16:48:35,491 INFO L290 TraceCheckUtils]: 6: Hoare triple {2967#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2968#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,491 INFO L290 TraceCheckUtils]: 7: Hoare triple {2968#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,491 INFO L290 TraceCheckUtils]: 8: Hoare triple {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,492 INFO L290 TraceCheckUtils]: 9: Hoare triple {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:48:35,493 INFO L290 TraceCheckUtils]: 10: Hoare triple {2969#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:35,493 INFO L290 TraceCheckUtils]: 11: Hoare triple {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:35,494 INFO L290 TraceCheckUtils]: 12: Hoare triple {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:48:35,495 INFO L290 TraceCheckUtils]: 13: Hoare triple {2970#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:35,495 INFO L290 TraceCheckUtils]: 14: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:35,495 INFO L290 TraceCheckUtils]: 15: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:48:35,496 INFO L272 TraceCheckUtils]: 16: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3026#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:48:35,496 INFO L290 TraceCheckUtils]: 17: Hoare triple {3026#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3030#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:48:35,497 INFO L290 TraceCheckUtils]: 18: Hoare triple {3030#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2963#false} is VALID [2022-04-27 16:48:35,497 INFO L290 TraceCheckUtils]: 19: Hoare triple {2963#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2963#false} is VALID [2022-04-27 16:48:35,497 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:48:35,497 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:48:49,182 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (and (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int) (aux_div_v_main_~z~0_41_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296))) (.cse0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (and (or (not (< c_main_~z~0 .cse0)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))) (not .cse1)) (or .cse1 (not (= .cse0 c_main_~z~0))))) (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= 4294967296 aux_mod_v_main_~z~0_41_31))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))) (forall ((aux_mod_v_main_~z~0_41_31 Int) (aux_div_v_main_~z~0_41_31 Int)) (or (let ((.cse3 (< 0 (mod c_main_~y~0 4294967296))) (.cse2 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (and (or (not (< c_main_~z~0 .cse2)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))) (not .cse3)) (or .cse3 (not (= .cse2 c_main_~z~0))))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))))) (<= 4294967296 aux_mod_v_main_~x~0_50_31))) is different from false [2022-04-27 16:50:03,659 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (let ((.cse0 (< 0 (mod c_main_~y~0 4294967296))) (.cse1 (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))))) (and (or (not .cse0) (and (or .cse1 (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse2 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse2 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse2 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse3 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse3 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse3 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (<= 4294967296 aux_mod_v_main_~z~0_41_31))))) (or .cse0 (let ((.cse4 (* (- 1) c_main_~z~0))) (and (or (<= (div .cse4 (- 4294967296)) (+ (div (+ (- 4294967296) c_main_~z~0) 4294967296) 1)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5)))))) (or .cse1 (< (div (+ (- 1) .cse4) (- 4294967296)) (+ 2 (div (+ (- 1) c_main_~z~0) 4294967296))))))))))) is different from false [2022-04-27 16:50:58,341 INFO L290 TraceCheckUtils]: 19: Hoare triple {2963#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2963#false} is VALID [2022-04-27 16:50:58,342 INFO L290 TraceCheckUtils]: 18: Hoare triple {3030#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2963#false} is VALID [2022-04-27 16:50:58,342 INFO L290 TraceCheckUtils]: 17: Hoare triple {3026#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3030#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:50:58,343 INFO L272 TraceCheckUtils]: 16: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3026#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:50:58,343 INFO L290 TraceCheckUtils]: 15: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:58,344 INFO L290 TraceCheckUtils]: 14: Hoare triple {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:58,354 INFO L290 TraceCheckUtils]: 13: Hoare triple {3055#(forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {2971#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:50:58,391 INFO L290 TraceCheckUtils]: 12: Hoare triple {3055#(forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3055#(forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))))))} is VALID [2022-04-27 16:50:58,402 INFO L290 TraceCheckUtils]: 11: Hoare triple {3055#(forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3055#(forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))))))} is VALID [2022-04-27 16:51:00,420 WARN L290 TraceCheckUtils]: 10: Hoare triple {3065#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (forall ((aux_mod_v_main_~z~0_41_31 Int) (aux_div_v_main_~z~0_41_31 Int)) (or (< 0 aux_mod_v_main_~z~0_41_31) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int) (aux_div_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3055#(forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))))))} is UNKNOWN [2022-04-27 16:51:02,541 WARN L290 TraceCheckUtils]: 9: Hoare triple {3069#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)))) (< 0 (mod main_~y~0 4294967296))))))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3065#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (forall ((aux_mod_v_main_~z~0_41_31 Int) (aux_div_v_main_~z~0_41_31 Int)) (or (< 0 aux_mod_v_main_~z~0_41_31) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int) (aux_div_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))))} is UNKNOWN [2022-04-27 16:51:04,580 WARN L290 TraceCheckUtils]: 8: Hoare triple {3073#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_50_31))))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3069#(forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)))) (< 0 (mod main_~y~0 4294967296))))))} is UNKNOWN [2022-04-27 16:51:04,634 INFO L290 TraceCheckUtils]: 7: Hoare triple {3077#(or (<= (div (- main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3073#(or (< 0 (mod main_~z~0 4294967296)) (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0))) (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))))) (< 0 (mod (+ main_~z~0 main_~y~0 (* aux_mod_v_main_~z~0_41_31 4294967295)) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31) (+ main_~z~0 main_~y~0)) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 main_~y~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) main_~y~0) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (<= 4294967296 aux_mod_v_main_~z~0_41_31) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) main_~x~0))))) (or (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= 4294967296 aux_mod_v_main_~x~0_50_31))))} is VALID [2022-04-27 16:51:04,635 INFO L290 TraceCheckUtils]: 6: Hoare triple {2962#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3077#(or (<= (div (- main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:51:04,635 INFO L290 TraceCheckUtils]: 5: Hoare triple {2962#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {2962#true} is VALID [2022-04-27 16:51:04,636 INFO L272 TraceCheckUtils]: 4: Hoare triple {2962#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:51:04,636 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2962#true} {2962#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:51:04,636 INFO L290 TraceCheckUtils]: 2: Hoare triple {2962#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:51:04,636 INFO L290 TraceCheckUtils]: 1: Hoare triple {2962#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2962#true} is VALID [2022-04-27 16:51:04,636 INFO L272 TraceCheckUtils]: 0: Hoare triple {2962#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2962#true} is VALID [2022-04-27 16:51:04,636 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 3 not checked. [2022-04-27 16:51:04,636 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1674884486] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:51:04,636 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:51:04,636 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 10] total 17 [2022-04-27 16:51:04,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2130438489] [2022-04-27 16:51:04,637 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:51:04,637 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:51:04,638 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:51:04,638 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:11,127 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 31 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:51:11,128 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-27 16:51:11,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:51:11,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-27 16:51:11,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=164, Unknown=6, NotChecked=54, Total=272 [2022-04-27 16:51:11,128 INFO L87 Difference]: Start difference. First operand 44 states and 70 transitions. Second operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:23,896 WARN L232 SmtUtils]: Spent 8.24s on a formula simplification that was a NOOP. DAG size: 108 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:51:28,401 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (<= c_main_~x~0 (* (div c_main_~x~0 4294967296) 4294967296)) (or (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (let ((.cse3 (< 0 (mod c_main_~y~0 4294967296))) (.cse0 (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))))) (and (or (and (or .cse0 (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse1 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse1 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse1 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31)))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse2 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse2 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse2 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (<= 4294967296 aux_mod_v_main_~z~0_41_31)))) (not .cse3)) (or .cse3 .cse0))))) (< 0 (mod c_main_~z~0 4294967296))) (forall ((aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (<= 4294967296 aux_mod_v_main_~x~0_50_31) (let ((.cse4 (< 0 (mod c_main_~y~0 4294967296))) (.cse5 (forall ((aux_div_v_main_~x~0_50_31 Int)) (not (= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0))))) (and (or (not .cse4) (and (or .cse5 (forall ((aux_mod_v_main_~z~0_41_31 Int)) (or (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse6 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse6 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse6 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (< 0 aux_mod_v_main_~z~0_41_31) (< aux_mod_v_main_~z~0_41_31 0)))) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~z~0_41_31 Int)) (or (<= aux_mod_v_main_~z~0_41_31 0) (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_41_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5))) (and (or (forall ((aux_div_v_main_~z~0_41_31 Int)) (or (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31)))) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31))))))) (< 0 (mod (+ (* aux_mod_v_main_~z~0_41_31 4294967295) c_main_~y~0 c_main_~z~0) 4294967296))) (forall ((aux_div_v_main_~z~0_41_31 Int) (aux_div_v_main_~y~0_38_31 Int) (aux_mod_v_main_~y~0_38_31 Int)) (let ((.cse7 (* aux_div_v_main_~y~0_38_31 4294967296))) (or (<= aux_mod_v_main_~y~0_38_31 0) (<= c_main_~y~0 (+ .cse7 aux_mod_v_main_~y~0_38_31)) (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31 1) c_main_~y~0))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 c_main_~y~0 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) (* aux_div_v_main_~y~0_38_31 4294967296) aux_mod_v_main_~y~0_38_31)) (not (< 0 (mod (+ (* v_it_3 4294967295) aux_mod_v_main_~y~0_38_31) 4294967296))) (<= 1 v_it_3))) (<= (+ aux_mod_v_main_~z~0_41_31 (* 4294967296 aux_div_v_main_~z~0_41_31) .cse7 aux_mod_v_main_~y~0_38_31) (+ c_main_~y~0 c_main_~z~0)) (<= 4294967296 aux_mod_v_main_~y~0_38_31))))) (<= 4294967296 aux_mod_v_main_~z~0_41_31))))) (or .cse4 (let ((.cse8 (* (- 1) c_main_~z~0))) (and (or (<= (div .cse8 (- 4294967296)) (+ (div (+ (- 4294967296) c_main_~z~0) 4294967296) 1)) (forall ((aux_div_v_main_~x~0_50_31 Int)) (or (<= (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296)) c_main_~x~0) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5)))))) (or .cse5 (< (div (+ (- 1) .cse8) (- 4294967296)) (+ 2 (div (+ (- 1) c_main_~z~0) 4294967296))))))))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 16:51:32,693 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (forall ((aux_div_v_main_~x~0_50_31 Int) (aux_mod_v_main_~x~0_50_31 Int)) (or (<= aux_mod_v_main_~x~0_50_31 0) (let ((.cse0 (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (.cse1 (< 0 (mod c_main_~z~0 4294967296)))) (and (or (not (= .cse0 c_main_~x~0)) .cse1) (or (not (< c_main_~x~0 .cse0)) (not .cse1) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) (+ aux_mod_v_main_~x~0_50_31 (* aux_div_v_main_~x~0_50_31 4294967296))) (<= 1 v_it_5)))))) (<= 4294967296 aux_mod_v_main_~x~0_50_31))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 16:51:37,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:51:37,459 INFO L93 Difference]: Finished difference Result 66 states and 105 transitions. [2022-04-27 16:51:37,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2022-04-27 16:51:37,462 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:51:37,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:51:37,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:37,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 65 transitions. [2022-04-27 16:51:37,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:37,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 65 transitions. [2022-04-27 16:51:37,470 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 17 states and 65 transitions. [2022-04-27 16:51:46,256 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 61 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:51:46,256 INFO L225 Difference]: With dead ends: 66 [2022-04-27 16:51:46,257 INFO L226 Difference]: Without dead ends: 63 [2022-04-27 16:51:46,257 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 33 SyntacticMatches, 6 SemanticMatches, 25 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 36.0s TimeCoverageRelationStatistics Valid=115, Invalid=395, Unknown=12, NotChecked=180, Total=702 [2022-04-27 16:51:46,257 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 42 mSDsluCounter, 60 mSDsCounter, 0 mSdLazyCounter, 80 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 42 SdHoareTripleChecker+Valid, 71 SdHoareTripleChecker+Invalid, 217 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 80 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 121 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:51:46,257 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [42 Valid, 71 Invalid, 217 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 80 Invalid, 0 Unknown, 121 Unchecked, 0.2s Time] [2022-04-27 16:51:46,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2022-04-27 16:51:46,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 46. [2022-04-27 16:51:46,259 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:51:46,259 INFO L82 GeneralOperation]: Start isEquivalent. First operand 63 states. Second operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:46,259 INFO L74 IsIncluded]: Start isIncluded. First operand 63 states. Second operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:46,259 INFO L87 Difference]: Start difference. First operand 63 states. Second operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:46,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:51:46,260 INFO L93 Difference]: Finished difference Result 63 states and 102 transitions. [2022-04-27 16:51:46,260 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 102 transitions. [2022-04-27 16:51:46,260 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:51:46,260 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:51:46,260 INFO L74 IsIncluded]: Start isIncluded. First operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 63 states. [2022-04-27 16:51:46,261 INFO L87 Difference]: Start difference. First operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 63 states. [2022-04-27 16:51:46,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:51:46,261 INFO L93 Difference]: Finished difference Result 63 states and 102 transitions. [2022-04-27 16:51:46,261 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 102 transitions. [2022-04-27 16:51:46,262 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:51:46,262 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:51:46,262 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:51:46,262 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:51:46,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 41 states have (on average 1.7073170731707317) internal successors, (70), 41 states have internal predecessors, (70), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:46,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 74 transitions. [2022-04-27 16:51:46,262 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 74 transitions. Word has length 20 [2022-04-27 16:51:46,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:51:46,263 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 74 transitions. [2022-04-27 16:51:46,263 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.6470588235294117) internal successors, (28), 14 states have internal predecessors, (28), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:51:46,263 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 74 transitions. [2022-04-27 16:51:46,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:51:46,263 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:51:46,263 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:51:46,290 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-27 16:51:46,463 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-04-27 16:51:46,464 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:51:46,464 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:51:46,464 INFO L85 PathProgramCache]: Analyzing trace with hash -369501645, now seen corresponding path program 1 times [2022-04-27 16:51:46,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:51:46,464 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906980387] [2022-04-27 16:51:46,464 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:51:46,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:51:46,473 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:51:46,474 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:51:46,475 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_13 .cse0 (* (- 4294967296) (div (+ main_~y~0_13 .cse0) 4294967296)))) 0)) [2022-04-27 16:51:46,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:51:46,488 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:51:46,491 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.7))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:51:46,493 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.8))) (+ main_~y~0_13 .cse0 (* (- 4294967296) (div (+ main_~y~0_13 .cse0) 4294967296)))) 0)) [2022-04-27 16:51:46,778 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:51:46,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:51:46,782 INFO L290 TraceCheckUtils]: 0: Hoare triple {3372#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3362#true} is VALID [2022-04-27 16:51:46,782 INFO L290 TraceCheckUtils]: 1: Hoare triple {3362#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:46,782 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3362#true} {3362#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:46,783 INFO L272 TraceCheckUtils]: 0: Hoare triple {3362#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3372#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:51:46,783 INFO L290 TraceCheckUtils]: 1: Hoare triple {3372#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3362#true} is VALID [2022-04-27 16:51:46,783 INFO L290 TraceCheckUtils]: 2: Hoare triple {3362#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:46,783 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3362#true} {3362#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:46,783 INFO L272 TraceCheckUtils]: 4: Hoare triple {3362#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:46,784 INFO L290 TraceCheckUtils]: 5: Hoare triple {3362#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3367#(= main_~y~0 0)} is VALID [2022-04-27 16:51:46,784 INFO L290 TraceCheckUtils]: 6: Hoare triple {3367#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,785 INFO L290 TraceCheckUtils]: 7: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,785 INFO L290 TraceCheckUtils]: 8: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,786 INFO L290 TraceCheckUtils]: 9: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,786 INFO L290 TraceCheckUtils]: 10: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,786 INFO L290 TraceCheckUtils]: 11: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,787 INFO L290 TraceCheckUtils]: 12: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,788 INFO L290 TraceCheckUtils]: 13: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:51:46,789 INFO L290 TraceCheckUtils]: 14: Hoare triple {3368#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:46,789 INFO L290 TraceCheckUtils]: 15: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:46,790 INFO L272 TraceCheckUtils]: 16: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3370#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:51:46,790 INFO L290 TraceCheckUtils]: 17: Hoare triple {3370#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3371#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:51:46,790 INFO L290 TraceCheckUtils]: 18: Hoare triple {3371#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3363#false} is VALID [2022-04-27 16:51:46,790 INFO L290 TraceCheckUtils]: 19: Hoare triple {3363#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3363#false} is VALID [2022-04-27 16:51:46,790 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-27 16:51:46,791 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:51:46,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906980387] [2022-04-27 16:51:46,791 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906980387] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:51:46,791 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1513616529] [2022-04-27 16:51:46,791 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:51:46,791 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:51:46,791 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:51:46,792 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:51:46,792 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 16:51:46,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:51:46,823 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 16:51:46,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:51:46,834 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:51:47,434 INFO L272 TraceCheckUtils]: 0: Hoare triple {3362#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:47,434 INFO L290 TraceCheckUtils]: 1: Hoare triple {3362#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3362#true} is VALID [2022-04-27 16:51:47,434 INFO L290 TraceCheckUtils]: 2: Hoare triple {3362#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:47,434 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3362#true} {3362#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:47,434 INFO L272 TraceCheckUtils]: 4: Hoare triple {3362#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:51:47,434 INFO L290 TraceCheckUtils]: 5: Hoare triple {3362#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3362#true} is VALID [2022-04-27 16:51:47,435 INFO L290 TraceCheckUtils]: 6: Hoare triple {3362#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:47,435 INFO L290 TraceCheckUtils]: 7: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:47,436 INFO L290 TraceCheckUtils]: 8: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:47,436 INFO L290 TraceCheckUtils]: 9: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:47,437 INFO L290 TraceCheckUtils]: 10: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:51:47,437 INFO L290 TraceCheckUtils]: 11: Hoare triple {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:51:47,437 INFO L290 TraceCheckUtils]: 12: Hoare triple {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:51:47,439 INFO L290 TraceCheckUtils]: 13: Hoare triple {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:51:47,440 INFO L290 TraceCheckUtils]: 14: Hoare triple {3406#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:47,440 INFO L290 TraceCheckUtils]: 15: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:51:47,441 INFO L272 TraceCheckUtils]: 16: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3425#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:51:47,441 INFO L290 TraceCheckUtils]: 17: Hoare triple {3425#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3429#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:51:47,441 INFO L290 TraceCheckUtils]: 18: Hoare triple {3429#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3363#false} is VALID [2022-04-27 16:51:47,442 INFO L290 TraceCheckUtils]: 19: Hoare triple {3363#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3363#false} is VALID [2022-04-27 16:51:47,442 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-27 16:51:47,442 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:52:58,532 INFO L290 TraceCheckUtils]: 19: Hoare triple {3363#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3363#false} is VALID [2022-04-27 16:52:58,532 INFO L290 TraceCheckUtils]: 18: Hoare triple {3429#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3363#false} is VALID [2022-04-27 16:52:58,532 INFO L290 TraceCheckUtils]: 17: Hoare triple {3425#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3429#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:52:58,533 INFO L272 TraceCheckUtils]: 16: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3425#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:52:58,534 INFO L290 TraceCheckUtils]: 15: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:52:58,588 INFO L290 TraceCheckUtils]: 14: Hoare triple {3451#(forall ((aux_mod_v_main_~x~0_53_31 Int) (aux_div_v_main_~x~0_53_31 Int)) (or (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:00,623 WARN L290 TraceCheckUtils]: 13: Hoare triple {3455#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3451#(forall ((aux_mod_v_main_~x~0_53_31 Int) (aux_div_v_main_~x~0_53_31 Int)) (or (and (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is UNKNOWN [2022-04-27 16:53:02,635 WARN L290 TraceCheckUtils]: 12: Hoare triple {3455#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3455#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is UNKNOWN [2022-04-27 16:53:04,646 WARN L290 TraceCheckUtils]: 11: Hoare triple {3455#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3455#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is UNKNOWN [2022-04-27 16:53:04,669 INFO L290 TraceCheckUtils]: 10: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3455#(forall ((aux_mod_v_main_~x~0_53_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (and (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (or (not (< (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296)) main_~x~0)) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 (* aux_div_v_main_~x~0_53_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))))) (< 0 (mod (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* main_~x~0 4294967295)) 4294967296))) (forall ((aux_div_v_main_~x~0_53_31 Int) (aux_mod_v_main_~y~0_42_31 Int) (aux_div_v_main_~y~0_42_31 Int)) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ v_it_6 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31 1) main_~y~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~y~0_42_31) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_53_31 v_it_6 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296) 1) (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (not (< 0 (mod (+ aux_mod_v_main_~y~0_42_31 (* v_it_6 4294967295)) 4294967296))))) (<= aux_mod_v_main_~y~0_42_31 0) (<= main_~y~0 (+ (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31)) (<= (+ main_~x~0 (* aux_div_v_main_~y~0_42_31 4294967296) aux_mod_v_main_~y~0_42_31) (+ aux_mod_v_main_~x~0_53_31 main_~y~0 (* aux_div_v_main_~x~0_53_31 4294967296))))))) (or (forall ((aux_div_v_main_~x~0_53_31 Int)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_53_31 (* aux_div_v_main_~x~0_53_31 4294967296))))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_53_31 0) (<= 4294967296 aux_mod_v_main_~x~0_53_31)))} is VALID [2022-04-27 16:53:04,670 INFO L290 TraceCheckUtils]: 9: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:04,670 INFO L290 TraceCheckUtils]: 8: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:04,676 INFO L290 TraceCheckUtils]: 7: Hoare triple {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:04,677 INFO L290 TraceCheckUtils]: 6: Hoare triple {3362#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3369#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:04,677 INFO L290 TraceCheckUtils]: 5: Hoare triple {3362#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3362#true} is VALID [2022-04-27 16:53:04,677 INFO L272 TraceCheckUtils]: 4: Hoare triple {3362#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:53:04,677 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3362#true} {3362#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:53:04,677 INFO L290 TraceCheckUtils]: 2: Hoare triple {3362#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:53:04,677 INFO L290 TraceCheckUtils]: 1: Hoare triple {3362#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3362#true} is VALID [2022-04-27 16:53:04,677 INFO L272 TraceCheckUtils]: 0: Hoare triple {3362#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3362#true} is VALID [2022-04-27 16:53:04,678 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 1 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:53:04,678 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1513616529] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:53:04,678 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:53:04,678 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 7] total 13 [2022-04-27 16:53:04,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1135045400] [2022-04-27 16:53:04,678 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:53:04,679 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:53:04,679 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:53:04,679 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:10,863 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 37 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 16:53:10,863 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 13 states [2022-04-27 16:53:10,863 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:53:10,863 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2022-04-27 16:53:10,863 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=117, Unknown=6, NotChecked=0, Total=156 [2022-04-27 16:53:10,863 INFO L87 Difference]: Start difference. First operand 46 states and 74 transitions. Second operand has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:53:13,771 INFO L93 Difference]: Finished difference Result 71 states and 112 transitions. [2022-04-27 16:53:13,771 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 16:53:13,771 INFO L78 Accepts]: Start accepts. Automaton has has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:53:13,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:53:13,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 65 transitions. [2022-04-27 16:53:13,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 65 transitions. [2022-04-27 16:53:13,773 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 65 transitions. [2022-04-27 16:53:13,839 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:53:13,839 INFO L225 Difference]: With dead ends: 71 [2022-04-27 16:53:13,839 INFO L226 Difference]: Without dead ends: 61 [2022-04-27 16:53:13,840 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 37 SyntacticMatches, 5 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 17.3s TimeCoverageRelationStatistics Valid=74, Invalid=261, Unknown=7, NotChecked=0, Total=342 [2022-04-27 16:53:13,840 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 49 mSDsluCounter, 43 mSDsCounter, 0 mSdLazyCounter, 59 mSolverCounterSat, 12 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 49 SdHoareTripleChecker+Valid, 56 SdHoareTripleChecker+Invalid, 117 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 12 IncrementalHoareTripleChecker+Valid, 59 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 46 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:53:13,840 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [49 Valid, 56 Invalid, 117 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [12 Valid, 59 Invalid, 0 Unknown, 46 Unchecked, 0.2s Time] [2022-04-27 16:53:13,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2022-04-27 16:53:13,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 52. [2022-04-27 16:53:13,842 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:53:13,842 INFO L82 GeneralOperation]: Start isEquivalent. First operand 61 states. Second operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,842 INFO L74 IsIncluded]: Start isIncluded. First operand 61 states. Second operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,842 INFO L87 Difference]: Start difference. First operand 61 states. Second operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:53:13,843 INFO L93 Difference]: Finished difference Result 61 states and 96 transitions. [2022-04-27 16:53:13,843 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 96 transitions. [2022-04-27 16:53:13,843 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:53:13,843 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:53:13,843 INFO L74 IsIncluded]: Start isIncluded. First operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-27 16:53:13,843 INFO L87 Difference]: Start difference. First operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 61 states. [2022-04-27 16:53:13,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:53:13,844 INFO L93 Difference]: Finished difference Result 61 states and 96 transitions. [2022-04-27 16:53:13,844 INFO L276 IsEmpty]: Start isEmpty. Operand 61 states and 96 transitions. [2022-04-27 16:53:13,844 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:53:13,844 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:53:13,844 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:53:13,844 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:53:13,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 47 states have (on average 1.6808510638297873) internal successors, (79), 47 states have internal predecessors, (79), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 83 transitions. [2022-04-27 16:53:13,845 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 83 transitions. Word has length 20 [2022-04-27 16:53:13,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:53:13,845 INFO L495 AbstractCegarLoop]: Abstraction has 52 states and 83 transitions. [2022-04-27 16:53:13,845 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 13 states, 13 states have (on average 2.6153846153846154) internal successors, (34), 10 states have internal predecessors, (34), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:53:13,846 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 83 transitions. [2022-04-27 16:53:13,846 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:53:13,846 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:53:13,846 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:53:13,876 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-04-27 16:53:14,059 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-04-27 16:53:14,060 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:53:14,060 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:53:14,060 INFO L85 PathProgramCache]: Analyzing trace with hash 2118261262, now seen corresponding path program 1 times [2022-04-27 16:53:14,060 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:53:14,060 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518264572] [2022-04-27 16:53:14,060 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:53:14,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:53:14,069 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:53:14,070 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.1))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:53:14,071 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:53:14,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:53:14,082 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.4))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:53:14,085 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.5))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:53:14,088 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.6))) (+ main_~y~0_9 .cse0 (* (- 4294967296) (div (+ main_~y~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:53:14,524 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:53:14,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:53:14,528 INFO L290 TraceCheckUtils]: 0: Hoare triple {3770#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3756#true} is VALID [2022-04-27 16:53:14,528 INFO L290 TraceCheckUtils]: 1: Hoare triple {3756#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:14,528 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3756#true} {3756#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:14,529 INFO L272 TraceCheckUtils]: 0: Hoare triple {3756#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3770#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:53:14,529 INFO L290 TraceCheckUtils]: 1: Hoare triple {3770#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3756#true} is VALID [2022-04-27 16:53:14,529 INFO L290 TraceCheckUtils]: 2: Hoare triple {3756#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:14,529 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3756#true} {3756#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:14,529 INFO L272 TraceCheckUtils]: 4: Hoare triple {3756#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:14,529 INFO L290 TraceCheckUtils]: 5: Hoare triple {3756#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3761#(= main_~y~0 0)} is VALID [2022-04-27 16:53:14,530 INFO L290 TraceCheckUtils]: 6: Hoare triple {3761#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:14,530 INFO L290 TraceCheckUtils]: 7: Hoare triple {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:14,531 INFO L290 TraceCheckUtils]: 8: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:14,531 INFO L290 TraceCheckUtils]: 9: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3764#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:53:14,532 INFO L290 TraceCheckUtils]: 10: Hoare triple {3764#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3765#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:53:14,532 INFO L290 TraceCheckUtils]: 11: Hoare triple {3765#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3765#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:53:14,534 INFO L290 TraceCheckUtils]: 12: Hoare triple {3765#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {3765#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:53:14,534 INFO L290 TraceCheckUtils]: 13: Hoare triple {3765#(and (= main_~z~0 0) (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3766#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:53:14,535 INFO L290 TraceCheckUtils]: 14: Hoare triple {3766#(and (<= main_~y~0 (* (div main_~y~0 4294967296) 4294967296)) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:14,536 INFO L290 TraceCheckUtils]: 15: Hoare triple {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:14,536 INFO L272 TraceCheckUtils]: 16: Hoare triple {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3768#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:53:14,537 INFO L290 TraceCheckUtils]: 17: Hoare triple {3768#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3769#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:53:14,537 INFO L290 TraceCheckUtils]: 18: Hoare triple {3769#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3757#false} is VALID [2022-04-27 16:53:14,537 INFO L290 TraceCheckUtils]: 19: Hoare triple {3757#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3757#false} is VALID [2022-04-27 16:53:14,537 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:53:14,537 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:53:14,537 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518264572] [2022-04-27 16:53:14,537 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518264572] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:53:14,537 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2095502338] [2022-04-27 16:53:14,538 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:53:14,538 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:53:14,538 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:53:14,538 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:53:14,539 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-04-27 16:53:14,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:53:14,570 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-27 16:53:14,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:53:14,590 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:53:15,170 INFO L272 TraceCheckUtils]: 0: Hoare triple {3756#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:15,171 INFO L290 TraceCheckUtils]: 1: Hoare triple {3756#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3756#true} is VALID [2022-04-27 16:53:15,171 INFO L290 TraceCheckUtils]: 2: Hoare triple {3756#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:15,171 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3756#true} {3756#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:15,171 INFO L272 TraceCheckUtils]: 4: Hoare triple {3756#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:53:15,173 INFO L290 TraceCheckUtils]: 5: Hoare triple {3756#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3761#(= main_~y~0 0)} is VALID [2022-04-27 16:53:15,174 INFO L290 TraceCheckUtils]: 6: Hoare triple {3761#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,174 INFO L290 TraceCheckUtils]: 7: Hoare triple {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,174 INFO L290 TraceCheckUtils]: 8: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,175 INFO L290 TraceCheckUtils]: 9: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,176 INFO L290 TraceCheckUtils]: 10: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,176 INFO L290 TraceCheckUtils]: 11: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,177 INFO L290 TraceCheckUtils]: 12: Hoare triple {3763#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,177 INFO L290 TraceCheckUtils]: 13: Hoare triple {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:53:15,178 INFO L290 TraceCheckUtils]: 14: Hoare triple {3762#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:15,179 INFO L290 TraceCheckUtils]: 15: Hoare triple {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:53:15,179 INFO L272 TraceCheckUtils]: 16: Hoare triple {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3822#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:53:15,180 INFO L290 TraceCheckUtils]: 17: Hoare triple {3822#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3826#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:53:15,180 INFO L290 TraceCheckUtils]: 18: Hoare triple {3826#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3757#false} is VALID [2022-04-27 16:53:15,180 INFO L290 TraceCheckUtils]: 19: Hoare triple {3757#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3757#false} is VALID [2022-04-27 16:53:15,180 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:53:15,180 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:53:26,114 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296))) (.cse0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (and (or (not (= v_main_~x~0_58 .cse0)) .cse1) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ (* v_it_6 4294967295) c_main_~y~0) 4294967296))))) (not .cse1) (not (< .cse0 v_main_~x~0_58))))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (let ((.cse2 (mod c_main_~z~0 4294967296))) (and (or (not (= v_main_~z~0_48 c_main_~z~0)) (not (<= .cse2 0)) (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~x~0_58 c_main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))) (or (not (< v_main_~z~0_48 c_main_~z~0)) (not (< 0 .cse2)) (not (= v_main_~x~0_58 (+ (* (- 1) v_main_~z~0_48) c_main_~x~0 c_main_~z~0))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) c_main_~z~0)))))))) is different from false [2022-04-27 16:53:50,796 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (let ((.cse0 (* aux_div_v_main_~x~0_57_31 4294967296))) (or (<= (+ 4294967296 .cse0) v_main_~x~0_58) (<= v_main_~x~0_58 .cse0) (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (let ((.cse7 (not .cse1)) (.cse2 (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) c_main_~y~0)))) (.cse3 (* (- 1) c_main_~z~0))) (and (or (not (< c_main_~x~0 v_main_~x~0_58)) (and (or .cse1 (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) .cse2 (<= (div .cse3 (- 4294967296)) (+ (div (+ (- 4294967296) c_main_~z~0) 4294967296) 1))) (or (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (let ((.cse6 (+ c_main_~y~0 c_main_~z~0)) (.cse5 (* 4294967296 aux_div_v_main_~z~0_49_31)) (.cse4 (* aux_div_v_main_~y~0_47_31 4294967296))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) c_main_~y~0))) (<= (+ .cse4 aux_mod_v_main_~y~0_47_31 4294967296 .cse5) .cse6) (<= .cse6 (+ .cse4 aux_mod_v_main_~y~0_47_31 .cse5)) (not (< (+ .cse4 aux_mod_v_main_~y~0_47_31) c_main_~y~0))))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31) c_main_~y~0 c_main_~z~0) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) v_main_~x~0_58) (<= 1 v_it_5))) .cse7))) (or (not (= v_main_~x~0_58 c_main_~x~0)) (and (or .cse7 (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (let ((.cse10 (* aux_div_v_main_~y~0_47_31 4294967296))) (let ((.cse9 (+ c_main_~y~0 c_main_~z~0)) (.cse8 (+ .cse10 aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31)))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) c_main_~y~0))) (< .cse8 .cse9) (< .cse9 .cse8) (not (< (+ .cse10 aux_mod_v_main_~y~0_47_31) c_main_~y~0))))))) (or .cse1 .cse2 (< (div (+ (- 1) .cse3) (- 4294967296)) (+ 2 (div (+ (- 1) c_main_~z~0) 4294967296))))))))) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31)))) is different from false [2022-04-27 16:53:52,810 WARN L855 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (let ((.cse0 (* aux_div_v_main_~x~0_57_31 4294967296))) (or (<= (+ 4294967296 .cse0) v_main_~x~0_58) (<= v_main_~x~0_58 .cse0) (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (let ((.cse7 (not .cse1)) (.cse2 (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) c_main_~y~0)))) (.cse3 (* (- 1) c_main_~z~0))) (and (or (not (< c_main_~x~0 v_main_~x~0_58)) (and (or .cse1 (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) .cse2 (<= (div .cse3 (- 4294967296)) (+ (div (+ (- 4294967296) c_main_~z~0) 4294967296) 1))) (or (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (let ((.cse6 (+ c_main_~y~0 c_main_~z~0)) (.cse5 (* 4294967296 aux_div_v_main_~z~0_49_31)) (.cse4 (* aux_div_v_main_~y~0_47_31 4294967296))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) c_main_~y~0))) (<= (+ .cse4 aux_mod_v_main_~y~0_47_31 4294967296 .cse5) .cse6) (<= .cse6 (+ .cse4 aux_mod_v_main_~y~0_47_31 .cse5)) (not (< (+ .cse4 aux_mod_v_main_~y~0_47_31) c_main_~y~0))))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31) c_main_~y~0 c_main_~z~0) 4294967296))) (<= (+ v_it_5 c_main_~x~0 1) v_main_~x~0_58) (<= 1 v_it_5))) .cse7))) (or (not (= v_main_~x~0_58 c_main_~x~0)) (and (or .cse7 (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (let ((.cse10 (* aux_div_v_main_~y~0_47_31 4294967296))) (let ((.cse9 (+ c_main_~y~0 c_main_~z~0)) (.cse8 (+ .cse10 aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31)))) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) c_main_~y~0))) (< .cse8 .cse9) (< .cse9 .cse8) (not (< (+ .cse10 aux_mod_v_main_~y~0_47_31) c_main_~y~0))))))) (or .cse1 .cse2 (< (div (+ (- 1) .cse3) (- 4294967296)) (+ 2 (div (+ (- 1) c_main_~z~0) 4294967296))))))))) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31)))) is different from true [2022-04-27 16:54:14,634 INFO L290 TraceCheckUtils]: 19: Hoare triple {3757#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3757#false} is VALID [2022-04-27 16:54:14,635 INFO L290 TraceCheckUtils]: 18: Hoare triple {3826#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3757#false} is VALID [2022-04-27 16:54:14,635 INFO L290 TraceCheckUtils]: 17: Hoare triple {3822#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3826#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:54:14,636 INFO L272 TraceCheckUtils]: 16: Hoare triple {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {3822#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:54:14,636 INFO L290 TraceCheckUtils]: 15: Hoare triple {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:54:16,648 WARN L290 TraceCheckUtils]: 14: Hoare triple {3848#(forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {3767#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is UNKNOWN [2022-04-27 16:54:16,649 INFO L290 TraceCheckUtils]: 13: Hoare triple {3848#(forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {3848#(forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} is VALID [2022-04-27 16:54:18,697 WARN L290 TraceCheckUtils]: 12: Hoare triple {3855#(forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (and (or (not (< v_main_~z~0_48 main_~z~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) main_~z~0))) (not (= v_main_~x~0_58 (+ main_~z~0 main_~x~0 (* (- 1) v_main_~z~0_48)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~z~0_48 main_~z~0)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~x~0_58 main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {3848#(forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) main_~x~0) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) main_~x~0))) (or (not (= main_~x~0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31)))} is UNKNOWN [2022-04-27 16:54:20,704 WARN L290 TraceCheckUtils]: 11: Hoare triple {3855#(forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (and (or (not (< v_main_~z~0_48 main_~z~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) main_~z~0))) (not (= v_main_~x~0_58 (+ main_~z~0 main_~x~0 (* (- 1) v_main_~z~0_48)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~z~0_48 main_~z~0)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~x~0_58 main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {3855#(forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (and (or (not (< v_main_~z~0_48 main_~z~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) main_~z~0))) (not (= v_main_~x~0_58 (+ main_~z~0 main_~x~0 (* (- 1) v_main_~z~0_48)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~z~0_48 main_~z~0)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~x~0_58 main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))))))} is UNKNOWN [2022-04-27 16:54:20,793 INFO L290 TraceCheckUtils]: 10: Hoare triple {3862#(or (forall ((aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {3855#(forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (and (or (not (= v_main_~x~0_58 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296))) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~y~0 (* v_it_6 4294967295)) 4294967296))))) (not (< 0 (mod main_~y~0 4294967296))) (not (< (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58)))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (and (or (not (< v_main_~z~0_48 main_~z~0)) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) main_~z~0))) (not (= v_main_~x~0_58 (+ main_~z~0 main_~x~0 (* (- 1) v_main_~z~0_48)))) (not (< 0 (mod main_~z~0 4294967296)))) (or (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~z~0_48 main_~z~0)) (not (<= (mod main_~z~0 4294967296) 0)) (not (= v_main_~x~0_58 main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))))))} is VALID [2022-04-27 16:54:22,809 WARN L290 TraceCheckUtils]: 9: Hoare triple {3866#(forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0))))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (< 0 (mod main_~y~0 4294967296)))) (not (< main_~x~0 v_main_~x~0_58))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (< (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))))))) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31)))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {3862#(or (forall ((aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~z~0 4294967296))) (not (< main_~x~0 v_main_~x~0_58)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)))) (< 0 (mod main_~y~0 4294967296)))} is UNKNOWN [2022-04-27 16:54:24,822 WARN L290 TraceCheckUtils]: 8: Hoare triple {3870#(or (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)))) (not (< main_~x~0 v_main_~x~0_58))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (not (= v_main_~x~0_58 main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31))) (< 0 (mod main_~z~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {3866#(forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0))))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (<= (div (- main_~z~0) (- 4294967296)) (+ (div (+ main_~z~0 (- 4294967296)) 4294967296) 1)) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (< 0 (mod main_~y~0 4294967296)))) (not (< main_~x~0 v_main_~x~0_58))) (or (and (or (< (div (+ (- 1) (* (- 1) main_~z~0)) (- 4294967296)) (+ 2 (div (+ (- 1) main_~z~0) 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (< (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))))))) (not (= v_main_~x~0_58 main_~x~0)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31)))} is UNKNOWN [2022-04-27 16:54:24,825 INFO L290 TraceCheckUtils]: 7: Hoare triple {3874#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {3870#(or (forall ((aux_mod_v_main_~y~0_47_31 Int) (aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (or (and (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ main_~z~0 main_~y~0 (* v_it_5 4294967295) (* 4294967295 aux_mod_v_main_~y~0_47_31)) 4294967296))) (<= 1 v_it_5))) (forall ((aux_div_v_main_~y~0_47_31 Int) (aux_div_v_main_~z~0_49_31 Int)) (or (<= (+ main_~z~0 main_~y~0) (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 (* 4294967296 aux_div_v_main_~z~0_49_31))) (not (< (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31) main_~y~0)) (exists ((v_it_3 Int)) (and (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))) (<= (+ v_it_3 (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 1) main_~y~0))) (<= (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31 4294967296 (* 4294967296 aux_div_v_main_~z~0_49_31)) (+ main_~z~0 main_~y~0)))) (not (< main_~x~0 v_main_~x~0_58))) (or (forall ((aux_div_v_main_~y~0_47_31 Int)) (not (= main_~y~0 (+ (* aux_div_v_main_~y~0_47_31 4294967296) aux_mod_v_main_~y~0_47_31)))) (not (= v_main_~x~0_58 main_~x~0)) (< 0 (mod main_~y~0 4294967296)))) (<= (+ 4294967296 (* aux_div_v_main_~x~0_57_31 4294967296)) v_main_~x~0_58) (<= v_main_~x~0_58 (* aux_div_v_main_~x~0_57_31 4294967296)) (< aux_mod_v_main_~y~0_47_31 0) (< 0 aux_mod_v_main_~y~0_47_31))) (< 0 (mod main_~z~0 4294967296)))} is VALID [2022-04-27 16:54:24,826 INFO L290 TraceCheckUtils]: 6: Hoare triple {3756#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3874#(or (<= (div (* (- 1) main_~x~0) (- 4294967296)) (+ (div (+ main_~x~0 (- 4294967296)) 4294967296) 1)) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:54:24,826 INFO L290 TraceCheckUtils]: 5: Hoare triple {3756#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {3756#true} is VALID [2022-04-27 16:54:24,826 INFO L272 TraceCheckUtils]: 4: Hoare triple {3756#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:54:24,826 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3756#true} {3756#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:54:24,826 INFO L290 TraceCheckUtils]: 2: Hoare triple {3756#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:54:24,826 INFO L290 TraceCheckUtils]: 1: Hoare triple {3756#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3756#true} is VALID [2022-04-27 16:54:24,826 INFO L272 TraceCheckUtils]: 0: Hoare triple {3756#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3756#true} is VALID [2022-04-27 16:54:24,826 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 2 not checked. [2022-04-27 16:54:24,827 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2095502338] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:54:24,827 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:54:24,827 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 8, 11] total 20 [2022-04-27 16:54:24,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [543930760] [2022-04-27 16:54:24,827 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:54:24,827 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:54:24,827 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:24,827 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:33,191 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 37 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:33,191 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 20 states [2022-04-27 16:54:33,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:33,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2022-04-27 16:54:33,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=233, Unknown=10, NotChecked=66, Total=380 [2022-04-27 16:54:33,192 INFO L87 Difference]: Start difference. First operand 52 states and 83 transitions. Second operand has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:49,753 WARN L232 SmtUtils]: Spent 6.21s on a formula simplification that was a NOOP. DAG size: 81 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:55:03,012 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296))) (.cse0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (and (or (not (= v_main_~x~0_58 .cse0)) .cse1) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ (* v_it_6 4294967295) c_main_~y~0) 4294967296))))) (not .cse1) (not (< .cse0 v_main_~x~0_58))))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (let ((.cse2 (mod c_main_~z~0 4294967296))) (and (or (not (= v_main_~z~0_48 c_main_~z~0)) (not (<= .cse2 0)) (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~x~0_58 c_main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))) (or (not (< v_main_~z~0_48 c_main_~z~0)) (not (< 0 .cse2)) (not (= v_main_~x~0_58 (+ (* (- 1) v_main_~z~0_48) c_main_~x~0 c_main_~z~0))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) c_main_~z~0)))))))) (or (< 0 (mod c_main_~y~0 4294967296)) (forall ((aux_div_v_main_~x~0_57_31 Int) (v_main_~x~0_58 Int)) (let ((.cse3 (* aux_div_v_main_~x~0_57_31 4294967296))) (or (<= (+ 4294967296 .cse3) v_main_~x~0_58) (<= v_main_~x~0_58 .cse3) (let ((.cse4 (< 0 (mod c_main_~z~0 4294967296)))) (and (or (not (= v_main_~x~0_58 c_main_~x~0)) .cse4) (or (exists ((v_it_5 Int)) (and (<= (+ v_it_5 c_main_~x~0 1) v_main_~x~0_58) (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5))) (not .cse4) (not (< c_main_~x~0 v_main_~x~0_58))))))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 16:55:05,097 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (forall ((v_main_~z~0_48 Int) (|v_main_#t~post14_19| Int) (|v_main_#t~post13_19| Int) (|main_#t~post14| Int) (|main_#t~post13| Int) (v_main_~x~0_58 Int)) (or (forall ((aux_mod_v_main_~x~0_57_31 Int) (aux_div_v_main_~x~0_57_31 Int)) (or (let ((.cse1 (< 0 (mod c_main_~y~0 4294967296))) (.cse0 (+ aux_mod_v_main_~x~0_57_31 (* aux_div_v_main_~x~0_57_31 4294967296)))) (and (or (not (= v_main_~x~0_58 .cse0)) .cse1) (or (exists ((v_it_6 Int)) (and (<= 1 v_it_6) (<= (+ aux_mod_v_main_~x~0_57_31 v_it_6 (* aux_div_v_main_~x~0_57_31 4294967296) 1) v_main_~x~0_58) (not (< 0 (mod (+ (* v_it_6 4294967295) c_main_~y~0) 4294967296))))) (not .cse1) (not (< .cse0 v_main_~x~0_58))))) (<= aux_mod_v_main_~x~0_57_31 0) (<= 4294967296 aux_mod_v_main_~x~0_57_31))) (let ((.cse2 (mod c_main_~z~0 4294967296))) (and (or (not (= v_main_~z~0_48 c_main_~z~0)) (not (<= .cse2 0)) (not (= |v_main_#t~post14_19| |main_#t~post14|)) (not (= v_main_~x~0_58 c_main_~x~0)) (not (= |v_main_#t~post13_19| |main_#t~post13|))) (or (not (< v_main_~z~0_48 c_main_~z~0)) (not (< 0 .cse2)) (not (= v_main_~x~0_58 (+ (* (- 1) v_main_~z~0_48) c_main_~x~0 c_main_~z~0))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= 1 v_it_5) (<= (+ v_main_~z~0_48 v_it_5 1) c_main_~z~0)))))))) (<= c_main_~x~0 (* (div c_main_~x~0 4294967296) 4294967296)) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 16:55:28,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:55:28,395 INFO L93 Difference]: Finished difference Result 75 states and 115 transitions. [2022-04-27 16:55:28,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2022-04-27 16:55:28,395 INFO L78 Accepts]: Start accepts. Automaton has has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:55:28,395 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:55:28,395 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:28,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 68 transitions. [2022-04-27 16:55:28,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:28,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 68 transitions. [2022-04-27 16:55:28,397 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 19 states and 68 transitions. [2022-04-27 16:55:38,721 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 68 edges. 63 inductive. 0 not inductive. 5 times theorem prover too weak to decide inductivity. [2022-04-27 16:55:38,722 INFO L225 Difference]: With dead ends: 75 [2022-04-27 16:55:38,722 INFO L226 Difference]: Without dead ends: 71 [2022-04-27 16:55:38,722 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 31 SyntacticMatches, 9 SemanticMatches, 30 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 187 ImplicationChecksByTransitivity, 76.0s TimeCoverageRelationStatistics Valid=162, Invalid=584, Unknown=26, NotChecked=220, Total=992 [2022-04-27 16:55:38,723 INFO L413 NwaCegarLoop]: 14 mSDtfsCounter, 54 mSDsluCounter, 52 mSDsCounter, 0 mSdLazyCounter, 75 mSolverCounterSat, 17 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 54 SdHoareTripleChecker+Valid, 66 SdHoareTripleChecker+Invalid, 211 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 17 IncrementalHoareTripleChecker+Valid, 75 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 119 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:55:38,723 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [54 Valid, 66 Invalid, 211 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [17 Valid, 75 Invalid, 0 Unknown, 119 Unchecked, 0.2s Time] [2022-04-27 16:55:38,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2022-04-27 16:55:38,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 50. [2022-04-27 16:55:38,724 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:55:38,725 INFO L82 GeneralOperation]: Start isEquivalent. First operand 71 states. Second operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:38,725 INFO L74 IsIncluded]: Start isIncluded. First operand 71 states. Second operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:38,725 INFO L87 Difference]: Start difference. First operand 71 states. Second operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:38,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:55:38,726 INFO L93 Difference]: Finished difference Result 71 states and 110 transitions. [2022-04-27 16:55:38,726 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 110 transitions. [2022-04-27 16:55:38,726 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:55:38,726 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:55:38,726 INFO L74 IsIncluded]: Start isIncluded. First operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 71 states. [2022-04-27 16:55:38,726 INFO L87 Difference]: Start difference. First operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 71 states. [2022-04-27 16:55:38,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:55:38,727 INFO L93 Difference]: Finished difference Result 71 states and 110 transitions. [2022-04-27 16:55:38,727 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 110 transitions. [2022-04-27 16:55:38,727 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:55:38,727 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:55:38,727 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:55:38,727 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:55:38,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 45 states have (on average 1.6888888888888889) internal successors, (76), 45 states have internal predecessors, (76), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:38,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 80 transitions. [2022-04-27 16:55:38,728 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 80 transitions. Word has length 20 [2022-04-27 16:55:38,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:55:38,728 INFO L495 AbstractCegarLoop]: Abstraction has 50 states and 80 transitions. [2022-04-27 16:55:38,728 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 20 states, 20 states have (on average 1.75) internal successors, (35), 17 states have internal predecessors, (35), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:38,729 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 80 transitions. [2022-04-27 16:55:38,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:55:38,729 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:55:38,729 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:55:38,746 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-04-27 16:55:38,948 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-04-27 16:55:38,948 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:55:38,948 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:55:38,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1929500051, now seen corresponding path program 1 times [2022-04-27 16:55:38,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:55:38,949 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [790186939] [2022-04-27 16:55:38,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:55:38,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:55:38,957 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:38,958 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:55:38,959 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_11 .cse0 (* (- 4294967296) (div (+ main_~y~0_11 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:38,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:55:38,969 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:38,971 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.7))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:55:38,974 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.8))) (+ main_~y~0_11 .cse0 (* (- 4294967296) (div (+ main_~y~0_11 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:39,207 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:55:39,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:55:39,224 INFO L290 TraceCheckUtils]: 0: Hoare triple {4204#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4194#true} is VALID [2022-04-27 16:55:39,224 INFO L290 TraceCheckUtils]: 1: Hoare triple {4194#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4194#true} is VALID [2022-04-27 16:55:39,224 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4194#true} {4194#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4194#true} is VALID [2022-04-27 16:55:39,225 INFO L272 TraceCheckUtils]: 0: Hoare triple {4194#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4204#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:55:39,225 INFO L290 TraceCheckUtils]: 1: Hoare triple {4204#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4194#true} is VALID [2022-04-27 16:55:39,225 INFO L290 TraceCheckUtils]: 2: Hoare triple {4194#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4194#true} is VALID [2022-04-27 16:55:39,225 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4194#true} {4194#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4194#true} is VALID [2022-04-27 16:55:39,225 INFO L272 TraceCheckUtils]: 4: Hoare triple {4194#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4194#true} is VALID [2022-04-27 16:55:39,225 INFO L290 TraceCheckUtils]: 5: Hoare triple {4194#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4199#(= main_~y~0 0)} is VALID [2022-04-27 16:55:39,226 INFO L290 TraceCheckUtils]: 6: Hoare triple {4199#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,226 INFO L290 TraceCheckUtils]: 7: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,226 INFO L290 TraceCheckUtils]: 8: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,227 INFO L290 TraceCheckUtils]: 9: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,227 INFO L290 TraceCheckUtils]: 10: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,229 INFO L290 TraceCheckUtils]: 11: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,229 INFO L290 TraceCheckUtils]: 12: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,230 INFO L290 TraceCheckUtils]: 13: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,231 INFO L290 TraceCheckUtils]: 14: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:39,231 INFO L290 TraceCheckUtils]: 15: Hoare triple {4200#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4201#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:39,232 INFO L272 TraceCheckUtils]: 16: Hoare triple {4201#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4202#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:55:39,232 INFO L290 TraceCheckUtils]: 17: Hoare triple {4202#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4203#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:55:39,232 INFO L290 TraceCheckUtils]: 18: Hoare triple {4203#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4195#false} is VALID [2022-04-27 16:55:39,233 INFO L290 TraceCheckUtils]: 19: Hoare triple {4195#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4195#false} is VALID [2022-04-27 16:55:39,233 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-27 16:55:39,233 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:55:39,233 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [790186939] [2022-04-27 16:55:39,233 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [790186939] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:55:39,233 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:55:39,233 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2022-04-27 16:55:39,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1346756254] [2022-04-27 16:55:39,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:55:39,233 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:55:39,234 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:55:39,234 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,251 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 20 edges. 20 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:55:39,252 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:55:39,252 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:55:39,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:55:39,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2022-04-27 16:55:39,252 INFO L87 Difference]: Start difference. First operand 50 states and 80 transitions. Second operand has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:55:39,865 INFO L93 Difference]: Finished difference Result 62 states and 96 transitions. [2022-04-27 16:55:39,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-27 16:55:39,865 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:55:39,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:55:39,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 56 transitions. [2022-04-27 16:55:39,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 56 transitions. [2022-04-27 16:55:39,867 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 56 transitions. [2022-04-27 16:55:39,918 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:55:39,919 INFO L225 Difference]: With dead ends: 62 [2022-04-27 16:55:39,919 INFO L226 Difference]: Without dead ends: 57 [2022-04-27 16:55:39,919 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=41, Invalid=115, Unknown=0, NotChecked=0, Total=156 [2022-04-27 16:55:39,920 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 36 mSDsluCounter, 36 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 51 SdHoareTripleChecker+Invalid, 95 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 16 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:55:39,920 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [36 Valid, 51 Invalid, 95 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 65 Invalid, 0 Unknown, 16 Unchecked, 0.2s Time] [2022-04-27 16:55:39,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2022-04-27 16:55:39,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 51. [2022-04-27 16:55:39,921 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:55:39,921 INFO L82 GeneralOperation]: Start isEquivalent. First operand 57 states. Second operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,921 INFO L74 IsIncluded]: Start isIncluded. First operand 57 states. Second operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,921 INFO L87 Difference]: Start difference. First operand 57 states. Second operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:55:39,922 INFO L93 Difference]: Finished difference Result 57 states and 90 transitions. [2022-04-27 16:55:39,922 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 90 transitions. [2022-04-27 16:55:39,922 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:55:39,922 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:55:39,922 INFO L74 IsIncluded]: Start isIncluded. First operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-27 16:55:39,923 INFO L87 Difference]: Start difference. First operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-27 16:55:39,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:55:39,923 INFO L93 Difference]: Finished difference Result 57 states and 90 transitions. [2022-04-27 16:55:39,923 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 90 transitions. [2022-04-27 16:55:39,923 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:55:39,924 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:55:39,924 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:55:39,924 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:55:39,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51 states, 46 states have (on average 1.6956521739130435) internal successors, (78), 46 states have internal predecessors, (78), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 82 transitions. [2022-04-27 16:55:39,924 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 82 transitions. Word has length 20 [2022-04-27 16:55:39,924 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:55:39,924 INFO L495 AbstractCegarLoop]: Abstraction has 51 states and 82 transitions. [2022-04-27 16:55:39,925 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 7 states have (on average 2.2857142857142856) internal successors, (16), 6 states have internal predecessors, (16), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:55:39,925 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 82 transitions. [2022-04-27 16:55:39,925 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:55:39,925 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:55:39,925 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:55:39,925 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable14 [2022-04-27 16:55:39,925 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:55:39,925 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:55:39,925 INFO L85 PathProgramCache]: Analyzing trace with hash -1592480168, now seen corresponding path program 1 times [2022-04-27 16:55:39,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:55:39,925 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440498595] [2022-04-27 16:55:39,925 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:55:39,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:55:39,934 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.0))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:39,934 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.1))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:55:39,935 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.2))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:39,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:55:39,944 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_3.6))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:39,946 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_4.7))) (+ .cse0 main_~x~0_5 (* (- 4294967296) (div (+ .cse0 main_~x~0_5) 4294967296)))) 0)) [2022-04-27 16:55:39,947 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.8))) (+ main_~z~0_9 .cse0 (* (- 4294967296) (div (+ main_~z~0_9 .cse0) 4294967296)))) 0)) [2022-04-27 16:55:40,251 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:55:40,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:55:40,254 INFO L290 TraceCheckUtils]: 0: Hoare triple {4457#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4445#true} is VALID [2022-04-27 16:55:40,255 INFO L290 TraceCheckUtils]: 1: Hoare triple {4445#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:40,255 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4445#true} {4445#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:40,255 INFO L272 TraceCheckUtils]: 0: Hoare triple {4445#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4457#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:55:40,255 INFO L290 TraceCheckUtils]: 1: Hoare triple {4457#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4445#true} is VALID [2022-04-27 16:55:40,255 INFO L290 TraceCheckUtils]: 2: Hoare triple {4445#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:40,255 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4445#true} {4445#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:40,255 INFO L272 TraceCheckUtils]: 4: Hoare triple {4445#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:40,256 INFO L290 TraceCheckUtils]: 5: Hoare triple {4445#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4450#(= main_~y~0 0)} is VALID [2022-04-27 16:55:40,256 INFO L290 TraceCheckUtils]: 6: Hoare triple {4450#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4451#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:40,257 INFO L290 TraceCheckUtils]: 7: Hoare triple {4451#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:40,257 INFO L290 TraceCheckUtils]: 8: Hoare triple {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:40,258 INFO L290 TraceCheckUtils]: 9: Hoare triple {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:55:40,258 INFO L290 TraceCheckUtils]: 10: Hoare triple {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:55:40,259 INFO L290 TraceCheckUtils]: 11: Hoare triple {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:55:40,260 INFO L290 TraceCheckUtils]: 12: Hoare triple {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:55:40,261 INFO L290 TraceCheckUtils]: 13: Hoare triple {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:40,261 INFO L290 TraceCheckUtils]: 14: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:40,261 INFO L290 TraceCheckUtils]: 15: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:40,262 INFO L272 TraceCheckUtils]: 16: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4455#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:55:40,262 INFO L290 TraceCheckUtils]: 17: Hoare triple {4455#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4456#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:55:40,262 INFO L290 TraceCheckUtils]: 18: Hoare triple {4456#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4446#false} is VALID [2022-04-27 16:55:40,262 INFO L290 TraceCheckUtils]: 19: Hoare triple {4446#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4446#false} is VALID [2022-04-27 16:55:40,263 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:55:40,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:55:40,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440498595] [2022-04-27 16:55:40,263 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440498595] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:55:40,263 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [596465214] [2022-04-27 16:55:40,263 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:55:40,263 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:55:40,263 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:55:40,264 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:55:40,265 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-04-27 16:55:40,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:55:40,294 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 16:55:40,310 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:55:40,310 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:55:41,194 INFO L272 TraceCheckUtils]: 0: Hoare triple {4445#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:41,195 INFO L290 TraceCheckUtils]: 1: Hoare triple {4445#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4445#true} is VALID [2022-04-27 16:55:41,195 INFO L290 TraceCheckUtils]: 2: Hoare triple {4445#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:41,195 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4445#true} {4445#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:41,195 INFO L272 TraceCheckUtils]: 4: Hoare triple {4445#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:55:41,195 INFO L290 TraceCheckUtils]: 5: Hoare triple {4445#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4450#(= main_~y~0 0)} is VALID [2022-04-27 16:55:41,196 INFO L290 TraceCheckUtils]: 6: Hoare triple {4450#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4451#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:41,196 INFO L290 TraceCheckUtils]: 7: Hoare triple {4451#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:41,197 INFO L290 TraceCheckUtils]: 8: Hoare triple {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:41,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:41,198 INFO L290 TraceCheckUtils]: 10: Hoare triple {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:55:41,199 INFO L290 TraceCheckUtils]: 11: Hoare triple {4452#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:55:41,200 INFO L290 TraceCheckUtils]: 12: Hoare triple {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:55:41,201 INFO L290 TraceCheckUtils]: 13: Hoare triple {4453#(and (= main_~z~0 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:41,201 INFO L290 TraceCheckUtils]: 14: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:41,201 INFO L290 TraceCheckUtils]: 15: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:55:41,202 INFO L272 TraceCheckUtils]: 16: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4509#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:55:41,202 INFO L290 TraceCheckUtils]: 17: Hoare triple {4509#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4513#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:55:41,203 INFO L290 TraceCheckUtils]: 18: Hoare triple {4513#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4446#false} is VALID [2022-04-27 16:55:41,203 INFO L290 TraceCheckUtils]: 19: Hoare triple {4446#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4446#false} is VALID [2022-04-27 16:55:41,203 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:55:41,203 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:55:50,140 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~y~0_50 Int) (|main_#t~post11| Int) (v_main_~x~0_62 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (let ((.cse0 (mod c_main_~x~0 4294967296))) (and (or (not (= v_main_~x~0_62 c_main_~x~0)) (not (<= .cse0 0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (= v_main_~y~0_50 c_main_~y~0)) (not (= |v_main_#t~post12_9| |main_#t~post12|))) (or (not (= v_main_~y~0_50 (+ (* (- 1) v_main_~x~0_62) c_main_~x~0 c_main_~y~0))) (not (< 0 .cse0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) c_main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~x~0_62 c_main_~x~0))))) (forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (let ((.cse2 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (.cse1 (< 0 (mod c_main_~z~0 4294967296)))) (and (or .cse1 (not (= v_main_~x~0_62 .cse2))) (or (not (< v_main_~x~0_62 .cse2)) (not .cse1) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ (* v_it_5 4294967295) c_main_~z~0) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5)))))))))) is different from false [2022-04-27 16:56:45,051 WARN L833 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (and (or (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (< 0 aux_mod_v_main_~z~0_54_31) (let ((.cse0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse0 c_main_~z~0)) .cse1) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse0)) (not .cse1)))))) (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))) (let ((.cse2 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse3 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse2 c_main_~z~0)) .cse3) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse2)) (not .cse3))))))) (<= aux_mod_v_main_~x~0_61_31 0) (let ((.cse4 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (not (= v_main_~x~0_62 c_main_~x~0)) .cse4) (or (not .cse4) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) c_main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~x~0_62 c_main_~x~0))))))) is different from false [2022-04-27 16:56:47,072 WARN L855 $PredicateComparison]: unable to prove that (forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (and (or (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (< 0 aux_mod_v_main_~z~0_54_31) (let ((.cse0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse0 c_main_~z~0)) .cse1) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse0)) (not .cse1)))))) (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))) (let ((.cse2 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse3 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse2 c_main_~z~0)) .cse3) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse2)) (not .cse3))))))) (<= aux_mod_v_main_~x~0_61_31 0) (let ((.cse4 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (not (= v_main_~x~0_62 c_main_~x~0)) .cse4) (or (not .cse4) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) c_main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~x~0_62 c_main_~x~0))))))) is different from true [2022-04-27 16:57:05,983 WARN L855 $PredicateComparison]: unable to prove that (or (forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (and (or (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (< 0 aux_mod_v_main_~z~0_54_31) (let ((.cse0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse1 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse0 c_main_~z~0)) .cse1) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse0)) (not .cse1)))))) (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))) (or (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (<= aux_mod_v_main_~z~0_54_31 0) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))))) (not (< 0 (mod c_main_~y~0 4294967296))))) (<= aux_mod_v_main_~x~0_61_31 0) (let ((.cse2 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (not (= v_main_~x~0_62 c_main_~x~0)) .cse2) (or (not .cse2) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) c_main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~x~0_62 c_main_~x~0))))))) (< 0 (mod c_main_~z~0 4294967296))) is different from true [2022-04-27 16:57:08,526 INFO L290 TraceCheckUtils]: 19: Hoare triple {4446#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4446#false} is VALID [2022-04-27 16:57:08,527 INFO L290 TraceCheckUtils]: 18: Hoare triple {4513#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4446#false} is VALID [2022-04-27 16:57:08,527 INFO L290 TraceCheckUtils]: 17: Hoare triple {4509#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4513#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:57:08,528 INFO L272 TraceCheckUtils]: 16: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4509#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:57:08,528 INFO L290 TraceCheckUtils]: 15: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:08,528 INFO L290 TraceCheckUtils]: 14: Hoare triple {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:08,562 INFO L290 TraceCheckUtils]: 13: Hoare triple {4538#(forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4454#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:08,590 INFO L290 TraceCheckUtils]: 12: Hoare triple {4538#(forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4538#(forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))))))} is VALID [2022-04-27 16:57:10,602 WARN L290 TraceCheckUtils]: 11: Hoare triple {4545#(forall ((v_main_~y~0_50 Int) (|main_#t~post11| Int) (v_main_~x~0_62 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))))) (and (or (not (= v_main_~y~0_50 main_~y~0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (= v_main_~x~0_62 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)) (not (= |v_main_#t~post12_9| |main_#t~post12|))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (= (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_62)) v_main_~y~0_50)) (not (< 0 (mod main_~x~0 4294967296)))))))} [115] L35-1-->L35-1: Formula: (let ((.cse0 (mod v_main_~x~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post12_3| |v_main_#t~post12_1|) (= |v_main_#t~post11_3| |v_main_#t~post11_1|) (= v_main_~y~0_11 v_main_~y~0_10) (= v_main_~x~0_10 v_main_~x~0_9)) (and (= (+ v_main_~x~0_10 v_main_~y~0_11 (* (- 1) v_main_~x~0_9)) v_main_~y~0_10) (< 0 .cse0) (forall ((v_it_4 Int)) (or (< 0 (mod (+ (* v_it_4 4294967295) v_main_~x~0_10) 4294967296)) (not (<= (+ v_main_~x~0_9 v_it_4 1) v_main_~x~0_10)) (not (<= 1 v_it_4)))) (< v_main_~x~0_9 v_main_~x~0_10)))) InVars {main_~y~0=v_main_~y~0_11, main_~x~0=v_main_~x~0_10, main_#t~post11=|v_main_#t~post11_3|, main_#t~post12=|v_main_#t~post12_3|} OutVars{main_~y~0=v_main_~y~0_10, main_~x~0=v_main_~x~0_9, main_#t~post11=|v_main_#t~post11_1|, main_#t~post12=|v_main_#t~post12_1|} AuxVars[] AssignedVars[main_~x~0, main_~y~0, main_#t~post11, main_#t~post12] {4538#(forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (exists ((v_it_5 Int)) (and (<= (+ v_it_5 main_~x~0 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5))) (not (< 0 (mod main_~z~0 4294967296)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= main_~x~0 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))))))} is UNKNOWN [2022-04-27 16:57:12,621 WARN L290 TraceCheckUtils]: 10: Hoare triple {4545#(forall ((v_main_~y~0_50 Int) (|main_#t~post11| Int) (v_main_~x~0_62 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))))) (and (or (not (= v_main_~y~0_50 main_~y~0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (= v_main_~x~0_62 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)) (not (= |v_main_#t~post12_9| |main_#t~post12|))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (= (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_62)) v_main_~y~0_50)) (not (< 0 (mod main_~x~0 4294967296)))))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4545#(forall ((v_main_~y~0_50 Int) (|main_#t~post11| Int) (v_main_~x~0_62 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))))) (and (or (not (= v_main_~y~0_50 main_~y~0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (= v_main_~x~0_62 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)) (not (= |v_main_#t~post12_9| |main_#t~post12|))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (= (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_62)) v_main_~y~0_50)) (not (< 0 (mod main_~x~0 4294967296)))))))} is UNKNOWN [2022-04-27 16:57:14,629 WARN L290 TraceCheckUtils]: 9: Hoare triple {4552#(forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))) (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))))) (< 0 aux_mod_v_main_~z~0_54_31))))) (and (or (not (= v_main_~x~0_62 main_~x~0)) (< 0 (mod main_~x~0 4294967296))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296)))))))} [112] L29-1-->L29-1: Formula: (let ((.cse0 (mod v_main_~y~0_5 4294967296))) (or (and (= v_main_~y~0_4 v_main_~y~0_5) (= |v_main_#t~post10_3| |v_main_#t~post10_1|) (= v_main_~z~0_3 v_main_~z~0_2) (= |v_main_#t~post9_3| |v_main_#t~post9_1|) (<= .cse0 0)) (and (= v_main_~y~0_4 (+ v_main_~y~0_5 v_main_~z~0_3 (* (- 1) v_main_~z~0_2))) (< 0 .cse0) (forall ((v_it_3 Int)) (or (not (<= (+ v_main_~z~0_3 v_it_3 1) v_main_~z~0_2)) (not (<= 1 v_it_3)) (< 0 (mod (+ v_main_~y~0_5 (* v_it_3 4294967295)) 4294967296)))) (< v_main_~z~0_3 v_main_~z~0_2)))) InVars {main_~y~0=v_main_~y~0_5, main_#t~post10=|v_main_#t~post10_3|, main_#t~post9=|v_main_#t~post9_3|, main_~z~0=v_main_~z~0_3} OutVars{main_~y~0=v_main_~y~0_4, main_#t~post10=|v_main_#t~post10_1|, main_#t~post9=|v_main_#t~post9_1|, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_#t~post10, main_~z~0, main_~y~0, main_#t~post9] {4545#(forall ((v_main_~y~0_50 Int) (|main_#t~post11| Int) (v_main_~x~0_62 Int) (|main_#t~post12| Int) (|v_main_#t~post12_9| Int) (|v_main_#t~post11_9| Int)) (or (forall ((aux_mod_v_main_~x~0_61_31 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (not (< v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))) (not (< 0 (mod main_~z~0 4294967296))) (exists ((v_it_5 Int)) (and (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (not (< 0 (mod (+ main_~z~0 (* v_it_5 4294967295)) 4294967296))) (<= 1 v_it_5)))) (or (< 0 (mod main_~z~0 4294967296)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))))) (and (or (not (= v_main_~y~0_50 main_~y~0)) (not (= |v_main_#t~post11_9| |main_#t~post11|)) (not (= v_main_~x~0_62 main_~x~0)) (not (<= (mod main_~x~0 4294967296) 0)) (not (= |v_main_#t~post12_9| |main_#t~post12|))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (= (+ main_~y~0 main_~x~0 (* (- 1) v_main_~x~0_62)) v_main_~y~0_50)) (not (< 0 (mod main_~x~0 4294967296)))))))} is UNKNOWN [2022-04-27 16:57:16,646 WARN L290 TraceCheckUtils]: 8: Hoare triple {4556#(or (forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))) (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))))) (< 0 aux_mod_v_main_~z~0_54_31)))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))))))) (and (or (not (= v_main_~x~0_62 main_~x~0)) (< 0 (mod main_~x~0 4294967296))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))))) (< 0 (mod main_~z~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4552#(forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))))) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))))) (or (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))) (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))))) (< 0 aux_mod_v_main_~z~0_54_31))))) (and (or (not (= v_main_~x~0_62 main_~x~0)) (< 0 (mod main_~x~0 4294967296))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296)))))))} is UNKNOWN [2022-04-27 16:57:18,678 WARN L290 TraceCheckUtils]: 7: Hoare triple {4560#(or (forall ((v_main_~x~0_62 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= v_main_~x~0_62 (* aux_div_v_main_~x~0_61_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_61_31 4294967296) 4294967296) v_main_~x~0_62) (not (< 0 (mod main_~x~0 4294967296))))) (< 0 (mod main_~y~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4556#(or (forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (<= aux_mod_v_main_~x~0_61_31 0) (and (or (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))))) (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (and (or (not (= main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (< 0 (mod main_~y~0 4294967296))) (or (not (< 0 (mod main_~y~0 4294967296))) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))))) (< 0 aux_mod_v_main_~z~0_54_31)))) (or (not (< 0 (mod main_~y~0 4294967296))) (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (exists ((v_it_3 Int)) (and (<= (+ v_it_3 main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (<= 1 v_it_3) (not (< 0 (mod (+ main_~y~0 (* v_it_3 4294967295)) 4294967296))))) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (not (< main_~z~0 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31)))) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))))))) (and (or (not (= v_main_~x~0_62 main_~x~0)) (< 0 (mod main_~x~0 4294967296))) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< 0 (mod main_~x~0 4294967296))))))) (< 0 (mod main_~z~0 4294967296)))} is UNKNOWN [2022-04-27 16:57:18,680 INFO L290 TraceCheckUtils]: 6: Hoare triple {4445#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4560#(or (forall ((v_main_~x~0_62 Int) (aux_div_v_main_~x~0_61_31 Int)) (or (not (< v_main_~x~0_62 main_~x~0)) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= v_main_~x~0_62 (* aux_div_v_main_~x~0_61_31 4294967296)) (<= (+ (* aux_div_v_main_~x~0_61_31 4294967296) 4294967296) v_main_~x~0_62) (not (< 0 (mod main_~x~0 4294967296))))) (< 0 (mod main_~y~0 4294967296)))} is VALID [2022-04-27 16:57:18,680 INFO L290 TraceCheckUtils]: 5: Hoare triple {4445#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4445#true} is VALID [2022-04-27 16:57:18,680 INFO L272 TraceCheckUtils]: 4: Hoare triple {4445#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:57:18,680 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4445#true} {4445#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:57:18,680 INFO L290 TraceCheckUtils]: 2: Hoare triple {4445#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:57:18,680 INFO L290 TraceCheckUtils]: 1: Hoare triple {4445#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4445#true} is VALID [2022-04-27 16:57:18,680 INFO L272 TraceCheckUtils]: 0: Hoare triple {4445#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4445#true} is VALID [2022-04-27 16:57:18,680 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 2 not checked. [2022-04-27 16:57:18,680 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [596465214] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:57:18,681 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:57:18,681 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 10] total 17 [2022-04-27 16:57:18,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1544544287] [2022-04-27 16:57:18,681 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:57:18,681 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:57:18,681 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:57:18,681 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:27,687 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 33 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:57:27,687 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 17 states [2022-04-27 16:57:27,687 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:57:27,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2022-04-27 16:57:27,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=143, Unknown=5, NotChecked=78, Total=272 [2022-04-27 16:57:27,688 INFO L87 Difference]: Start difference. First operand 51 states and 82 transitions. Second operand has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:38,657 WARN L232 SmtUtils]: Spent 8.28s on a formula simplification that was a NOOP. DAG size: 101 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 16:57:40,799 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (or (forall ((v_main_~x~0_62 Int) (aux_div_v_main_~x~0_61_31 Int)) (let ((.cse0 (* aux_div_v_main_~x~0_61_31 4294967296))) (or (not (< 0 (mod c_main_~x~0 4294967296))) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) c_main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (<= v_main_~x~0_62 .cse0) (<= (+ .cse0 4294967296) v_main_~x~0_62) (not (< v_main_~x~0_62 c_main_~x~0))))) (< 0 (mod c_main_~y~0 4294967296))) (forall ((aux_mod_v_main_~x~0_61_31 Int) (v_main_~x~0_62 Int)) (or (<= 4294967296 aux_mod_v_main_~x~0_61_31) (and (or (forall ((aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (< aux_mod_v_main_~z~0_54_31 0) (< 0 aux_mod_v_main_~z~0_54_31) (let ((.cse1 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse2 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse1 c_main_~z~0)) .cse2) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse1)) (not .cse2)))))) (forall ((aux_div_v_main_~x~0_61_31 Int)) (not (= v_main_~x~0_62 (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)))))) (forall ((aux_div_v_main_~x~0_61_31 Int) (aux_div_v_main_~z~0_54_31 Int) (aux_mod_v_main_~z~0_54_31 Int)) (or (<= aux_mod_v_main_~z~0_54_31 0) (<= 4294967296 aux_mod_v_main_~z~0_54_31) (<= (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296)) v_main_~x~0_62) (exists ((v_it_5 Int)) (and (not (< 0 (mod (+ aux_mod_v_main_~z~0_54_31 (* v_it_5 4294967295)) 4294967296))) (<= (+ v_main_~x~0_62 v_it_5 1) (+ aux_mod_v_main_~x~0_61_31 (* aux_div_v_main_~x~0_61_31 4294967296))) (<= 1 v_it_5))) (let ((.cse3 (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))) (.cse4 (< 0 (mod c_main_~y~0 4294967296)))) (and (or (not (= .cse3 c_main_~z~0)) .cse4) (or (exists ((v_it_3 Int)) (and (not (< 0 (mod (+ (* v_it_3 4294967295) c_main_~y~0) 4294967296))) (<= 1 v_it_3) (<= (+ v_it_3 c_main_~z~0 1) (+ aux_mod_v_main_~z~0_54_31 (* 4294967296 aux_div_v_main_~z~0_54_31))))) (not (< c_main_~z~0 .cse3)) (not .cse4))))))) (<= aux_mod_v_main_~x~0_61_31 0) (let ((.cse5 (< 0 (mod c_main_~x~0 4294967296)))) (and (or (not (= v_main_~x~0_62 c_main_~x~0)) .cse5) (or (not .cse5) (exists ((v_it_4 Int)) (and (<= (+ v_main_~x~0_62 v_it_4 1) c_main_~x~0) (not (< 0 (mod (+ (* v_it_4 4294967295) c_main_~x~0) 4294967296))) (<= 1 v_it_4))) (not (< v_main_~x~0_62 c_main_~x~0))))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 16:57:44,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:57:44,136 INFO L93 Difference]: Finished difference Result 68 states and 107 transitions. [2022-04-27 16:57:44,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-04-27 16:57:44,136 INFO L78 Accepts]: Start accepts. Automaton has has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 16:57:44,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:57:44,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:44,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 65 transitions. [2022-04-27 16:57:44,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:44,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 65 transitions. [2022-04-27 16:57:44,138 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 18 states and 65 transitions. [2022-04-27 16:57:52,528 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 61 inductive. 0 not inductive. 4 times theorem prover too weak to decide inductivity. [2022-04-27 16:57:52,529 INFO L225 Difference]: With dead ends: 68 [2022-04-27 16:57:52,529 INFO L226 Difference]: Without dead ends: 65 [2022-04-27 16:57:52,529 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 33 SyntacticMatches, 8 SemanticMatches, 25 ConstructedPredicates, 4 IntricatePredicates, 0 DeprecatedPredicates, 118 ImplicationChecksByTransitivity, 26.8s TimeCoverageRelationStatistics Valid=118, Invalid=396, Unknown=8, NotChecked=180, Total=702 [2022-04-27 16:57:52,530 INFO L413 NwaCegarLoop]: 13 mSDtfsCounter, 38 mSDsluCounter, 39 mSDsCounter, 0 mSdLazyCounter, 50 mSolverCounterSat, 16 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 38 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 163 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 16 IncrementalHoareTripleChecker+Valid, 50 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 97 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:57:52,530 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [38 Valid, 52 Invalid, 163 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [16 Valid, 50 Invalid, 0 Unknown, 97 Unchecked, 0.1s Time] [2022-04-27 16:57:52,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2022-04-27 16:57:52,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 49. [2022-04-27 16:57:52,533 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:57:52,533 INFO L82 GeneralOperation]: Start isEquivalent. First operand 65 states. Second operand has 49 states, 44 states have (on average 1.6818181818181819) internal successors, (74), 44 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:52,533 INFO L74 IsIncluded]: Start isIncluded. First operand 65 states. Second operand has 49 states, 44 states have (on average 1.6818181818181819) internal successors, (74), 44 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:52,533 INFO L87 Difference]: Start difference. First operand 65 states. Second operand has 49 states, 44 states have (on average 1.6818181818181819) internal successors, (74), 44 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:52,534 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:57:52,534 INFO L93 Difference]: Finished difference Result 65 states and 104 transitions. [2022-04-27 16:57:52,534 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 104 transitions. [2022-04-27 16:57:52,534 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:57:52,534 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:57:52,535 INFO L74 IsIncluded]: Start isIncluded. First operand has 49 states, 44 states have (on average 1.6818181818181819) internal successors, (74), 44 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 65 states. [2022-04-27 16:57:52,535 INFO L87 Difference]: Start difference. First operand has 49 states, 44 states have (on average 1.6818181818181819) internal successors, (74), 44 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 65 states. [2022-04-27 16:57:52,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:57:52,536 INFO L93 Difference]: Finished difference Result 65 states and 104 transitions. [2022-04-27 16:57:52,536 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 104 transitions. [2022-04-27 16:57:52,536 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:57:52,536 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:57:52,536 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:57:52,536 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:57:52,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 49 states, 44 states have (on average 1.6818181818181819) internal successors, (74), 44 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:52,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 78 transitions. [2022-04-27 16:57:52,536 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 78 transitions. Word has length 20 [2022-04-27 16:57:52,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:57:52,537 INFO L495 AbstractCegarLoop]: Abstraction has 49 states and 78 transitions. [2022-04-27 16:57:52,537 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 17 states, 17 states have (on average 1.8235294117647058) internal successors, (31), 14 states have internal predecessors, (31), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:57:52,537 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 78 transitions. [2022-04-27 16:57:52,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 16:57:52,537 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:57:52,537 INFO L195 NwaCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:57:52,553 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-04-27 16:57:52,738 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-04-27 16:57:52,738 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:57:52,738 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:57:52,738 INFO L85 PathProgramCache]: Analyzing trace with hash -2096941357, now seen corresponding path program 2 times [2022-04-27 16:57:52,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:57:52,739 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108735694] [2022-04-27 16:57:52,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:57:52,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:57:52,755 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.0))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:57:52,755 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.1))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:57:52,756 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.2))) (+ main_~y~0_13 .cse0 (* (- 4294967296) (div (+ main_~y~0_13 .cse0) 4294967296)))) 0)) [2022-04-27 16:57:52,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:57:52,763 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_5.6))) (+ main_~z~0_7 .cse0 (* (- 4294967296) (div (+ main_~z~0_7 .cse0) 4294967296)))) 0)) [2022-04-27 16:57:52,765 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.7))) (+ main_~y~0_5 .cse0 (* (- 4294967296) (div (+ main_~y~0_5 .cse0) 4294967296)))) 0)) [2022-04-27 16:57:52,767 WARN L250 erpolLogProxyWrapper]: Quant: Clause contains literal that is not almost uninterpreted: (not (<= (let ((.cse0 (* 4294967295 .v_it_6.8))) (+ main_~y~0_13 .cse0 (* (- 4294967296) (div (+ main_~y~0_13 .cse0) 4294967296)))) 0)) [2022-04-27 16:57:53,056 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:57:53,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:57:53,060 INFO L290 TraceCheckUtils]: 0: Hoare triple {4867#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4856#true} is VALID [2022-04-27 16:57:53,060 INFO L290 TraceCheckUtils]: 1: Hoare triple {4856#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,060 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4856#true} {4856#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,060 INFO L272 TraceCheckUtils]: 0: Hoare triple {4856#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4867#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:57:53,061 INFO L290 TraceCheckUtils]: 1: Hoare triple {4867#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4856#true} is VALID [2022-04-27 16:57:53,061 INFO L290 TraceCheckUtils]: 2: Hoare triple {4856#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,061 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4856#true} {4856#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,061 INFO L272 TraceCheckUtils]: 4: Hoare triple {4856#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,061 INFO L290 TraceCheckUtils]: 5: Hoare triple {4856#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4861#(= main_~y~0 0)} is VALID [2022-04-27 16:57:53,062 INFO L290 TraceCheckUtils]: 6: Hoare triple {4861#(= main_~y~0 0)} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,062 INFO L290 TraceCheckUtils]: 7: Hoare triple {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,063 INFO L290 TraceCheckUtils]: 8: Hoare triple {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4863#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,063 INFO L290 TraceCheckUtils]: 9: Hoare triple {4863#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4863#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,063 INFO L290 TraceCheckUtils]: 10: Hoare triple {4863#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4863#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,065 INFO L290 TraceCheckUtils]: 11: Hoare triple {4863#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (<= main_~z~0 (* (div main_~z~0 4294967296) 4294967296)) (= main_~y~0 0))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,065 INFO L290 TraceCheckUtils]: 12: Hoare triple {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,066 INFO L290 TraceCheckUtils]: 13: Hoare triple {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} is VALID [2022-04-27 16:57:53,067 INFO L290 TraceCheckUtils]: 14: Hoare triple {4862#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (= main_~y~0 0))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:53,068 INFO L290 TraceCheckUtils]: 15: Hoare triple {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:53,068 INFO L272 TraceCheckUtils]: 16: Hoare triple {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4865#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 16:57:53,068 INFO L290 TraceCheckUtils]: 17: Hoare triple {4865#(not (= |__VERIFIER_assert_#in~cond| 0))} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4866#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 16:57:53,069 INFO L290 TraceCheckUtils]: 18: Hoare triple {4866#(not (= __VERIFIER_assert_~cond 0))} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4857#false} is VALID [2022-04-27 16:57:53,069 INFO L290 TraceCheckUtils]: 19: Hoare triple {4857#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4857#false} is VALID [2022-04-27 16:57:53,069 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:57:53,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:57:53,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108735694] [2022-04-27 16:57:53,069 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108735694] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:57:53,069 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1625107228] [2022-04-27 16:57:53,069 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:57:53,069 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:57:53,070 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:57:53,070 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:57:53,071 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-04-27 16:57:53,101 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:57:53,101 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:57:53,101 INFO L263 TraceCheckSpWp]: Trace formula consists of 65 conjuncts, 9 conjunts are in the unsatisfiable core [2022-04-27 16:57:53,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:57:53,113 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:57:53,973 INFO L272 TraceCheckUtils]: 0: Hoare triple {4856#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,973 INFO L290 TraceCheckUtils]: 1: Hoare triple {4856#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 10) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4856#true} is VALID [2022-04-27 16:57:53,973 INFO L290 TraceCheckUtils]: 2: Hoare triple {4856#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,974 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4856#true} {4856#true} [131] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,974 INFO L272 TraceCheckUtils]: 4: Hoare triple {4856#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4856#true} is VALID [2022-04-27 16:57:53,974 INFO L290 TraceCheckUtils]: 5: Hoare triple {4856#true} [101] mainENTRY-->L16-2: Formula: (and (= v_main_~n~0_1 v_main_~x~0_1) (= v_main_~n~0_1 |v_main_#t~nondet4_2|) (= v_main_~y~0_2 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~y~0=v_main_~y~0_2, main_~n~0=v_main_~n~0_1, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_1} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~z~0, main_~y~0, main_~n~0] {4856#true} is VALID [2022-04-27 16:57:53,974 INFO L290 TraceCheckUtils]: 6: Hoare triple {4856#true} [104] L16-2-->L16-3: Formula: (not (< 0 (mod v_main_~x~0_5 4294967296))) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:53,975 INFO L290 TraceCheckUtils]: 7: Hoare triple {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [106] L16-3-->L23-2: Formula: (= v_main_~y~0_12 v_main_~z~0_4) InVars {main_~y~0=v_main_~y~0_12} OutVars{main_~y~0=v_main_~y~0_12, main_~z~0=v_main_~z~0_4} AuxVars[] AssignedVars[main_~z~0] {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:53,975 INFO L290 TraceCheckUtils]: 8: Hoare triple {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [108] L23-2-->L29-1: Formula: (not (< 0 (mod v_main_~z~0_5 4294967296))) InVars {main_~z~0=v_main_~z~0_5} OutVars{main_~z~0=v_main_~z~0_5} AuxVars[] AssignedVars[] {4895#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:57:53,975 INFO L290 TraceCheckUtils]: 9: Hoare triple {4895#(and (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [111] L29-1-->L35-1: Formula: (not (< 0 (mod v_main_~y~0_1 4294967296))) InVars {main_~y~0=v_main_~y~0_1} OutVars{main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[] {4899#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:57:53,976 INFO L290 TraceCheckUtils]: 10: Hoare triple {4899#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [114] L35-1-->L41-1: Formula: (not (< 0 (mod v_main_~x~0_8 4294967296))) InVars {main_~x~0=v_main_~x~0_8} OutVars{main_~x~0=v_main_~x~0_8} AuxVars[] AssignedVars[] {4899#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} is VALID [2022-04-27 16:57:53,977 INFO L290 TraceCheckUtils]: 11: Hoare triple {4899#(and (not (< 0 (mod main_~y~0 4294967296))) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))) (not (< 0 (mod main_~z~0 4294967296))))} [118] L41-1-->L41-1: Formula: (let ((.cse0 (mod v_main_~z~0_10 4294967296))) (or (and (<= .cse0 0) (= |v_main_#t~post14_3| |v_main_#t~post14_1|) (= v_main_~z~0_10 v_main_~z~0_9) (= v_main_~x~0_14 v_main_~x~0_13) (= |v_main_#t~post13_3| |v_main_#t~post13_1|)) (and (< 0 .cse0) (forall ((v_it_5 Int)) (or (not (<= (+ v_main_~z~0_9 v_it_5 1) v_main_~z~0_10)) (< 0 (mod (+ v_main_~z~0_10 (* v_it_5 4294967295)) 4294967296)) (not (<= 1 v_it_5)))) (< v_main_~z~0_9 v_main_~z~0_10) (= v_main_~x~0_13 (+ v_main_~x~0_14 v_main_~z~0_10 (* (- 1) v_main_~z~0_9)))))) InVars {main_~x~0=v_main_~x~0_14, main_~z~0=v_main_~z~0_10, main_#t~post13=|v_main_#t~post13_3|, main_#t~post14=|v_main_#t~post14_3|} OutVars{main_~x~0=v_main_~x~0_13, main_~z~0=v_main_~z~0_9, main_#t~post13=|v_main_#t~post13_1|, main_#t~post14=|v_main_#t~post14_1|} AuxVars[] AssignedVars[main_~x~0, main_~z~0, main_#t~post13, main_#t~post14] {4906#(and (<= (mod main_~y~0 4294967296) 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:57:53,977 INFO L290 TraceCheckUtils]: 12: Hoare triple {4906#(and (<= (mod main_~y~0 4294967296) 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [117] L41-1-->L47-1: Formula: (not (< 0 (mod v_main_~z~0_6 4294967296))) InVars {main_~z~0=v_main_~z~0_6} OutVars{main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[] {4906#(and (<= (mod main_~y~0 4294967296) 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:57:53,978 INFO L290 TraceCheckUtils]: 13: Hoare triple {4906#(and (<= (mod main_~y~0 4294967296) 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {4906#(and (<= (mod main_~y~0 4294967296) 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} is VALID [2022-04-27 16:57:53,979 INFO L290 TraceCheckUtils]: 14: Hoare triple {4906#(and (<= (mod main_~y~0 4294967296) 0) (<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296))))} [121] L47-1-->L47-1: Formula: (let ((.cse0 (mod v_main_~y~0_7 4294967296))) (or (and (= |v_main_#t~post15_3| |v_main_#t~post15_1|) (= |v_main_#t~post16_3| |v_main_#t~post16_1|) (= v_main_~y~0_7 v_main_~y~0_6) (= v_main_~x~0_3 v_main_~x~0_2) (<= .cse0 0)) (and (< 0 .cse0) (= v_main_~y~0_6 (+ v_main_~x~0_2 v_main_~y~0_7 (* (- 1) v_main_~x~0_3))) (forall ((v_it_6 Int)) (or (not (<= (+ v_main_~x~0_2 v_it_6 1) v_main_~x~0_3)) (not (<= 1 v_it_6)) (< 0 (mod (+ v_main_~y~0_7 (* v_it_6 4294967295)) 4294967296)))) (< v_main_~x~0_2 v_main_~x~0_3)))) InVars {main_#t~post15=|v_main_#t~post15_3|, main_~y~0=v_main_~y~0_7, main_#t~post16=|v_main_#t~post16_3|, main_~x~0=v_main_~x~0_3} OutVars{main_#t~post15=|v_main_#t~post15_1|, main_#t~post16=|v_main_#t~post16_1|, main_~y~0=v_main_~y~0_6, main_~x~0=v_main_~x~0_2} AuxVars[] AssignedVars[main_~x~0, main_#t~post15, main_#t~post16, main_~y~0] {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:53,980 INFO L290 TraceCheckUtils]: 15: Hoare triple {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [120] L47-1-->L47-2: Formula: (not (< 0 (mod v_main_~y~0_3 4294967296))) InVars {main_~y~0=v_main_~y~0_3} OutVars{main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[] {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} is VALID [2022-04-27 16:57:53,980 INFO L272 TraceCheckUtils]: 16: Hoare triple {4864#(<= main_~x~0 (* 4294967296 (div main_~x~0 4294967296)))} [122] L47-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_15 4294967296) 0) 1 0)) InVars {main_~x~0=v_main_~x~0_15} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {4922#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 16:57:53,981 INFO L290 TraceCheckUtils]: 17: Hoare triple {4922#(<= 1 |__VERIFIER_assert_#in~cond|)} [124] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4926#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 16:57:53,981 INFO L290 TraceCheckUtils]: 18: Hoare triple {4926#(<= 1 __VERIFIER_assert_~cond)} [126] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4857#false} is VALID [2022-04-27 16:57:53,981 INFO L290 TraceCheckUtils]: 19: Hoare triple {4857#false} [128] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4857#false} is VALID [2022-04-27 16:57:53,981 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 16:57:53,981 INFO L328 TraceCheckSpWp]: Computing backward predicates...