/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops/insertion_sort-2.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 15:56:05,448 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 15:56:05,482 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 15:56:05,517 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 15:56:05,517 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 15:56:05,518 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 15:56:05,521 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 15:56:05,522 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 15:56:05,523 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 15:56:05,527 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 15:56:05,527 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 15:56:05,528 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 15:56:05,529 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 15:56:05,530 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 15:56:05,531 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 15:56:05,533 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 15:56:05,533 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 15:56:05,534 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 15:56:05,535 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 15:56:05,539 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 15:56:05,541 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 15:56:05,541 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 15:56:05,542 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 15:56:05,543 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 15:56:05,544 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 15:56:05,548 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 15:56:05,554 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 15:56:05,554 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 15:56:05,555 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 15:56:05,556 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 15:56:05,567 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 15:56:05,567 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 15:56:05,568 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 15:56:05,568 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 15:56:05,568 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 15:56:05,568 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 15:56:05,569 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 15:56:05,569 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 15:56:05,569 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 15:56:05,569 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 15:56:05,570 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 15:56:05,570 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 15:56:05,571 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 15:56:05,571 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 15:56:05,571 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 15:56:05,571 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 15:56:05,848 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 15:56:05,868 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 15:56:05,877 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 15:56:05,877 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 15:56:05,878 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 15:56:05,879 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops/insertion_sort-2.c [2022-04-27 15:56:05,944 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3ad5ab2a7/0d2bc6e834944570b857c45403254ed4/FLAGb509d7243 [2022-04-27 15:56:06,329 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 15:56:06,329 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-2.c [2022-04-27 15:56:06,334 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3ad5ab2a7/0d2bc6e834944570b857c45403254ed4/FLAGb509d7243 [2022-04-27 15:56:06,760 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/3ad5ab2a7/0d2bc6e834944570b857c45403254ed4 [2022-04-27 15:56:06,762 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 15:56:06,764 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 15:56:06,772 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 15:56:06,772 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 15:56:06,789 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 15:56:06,790 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 03:56:06" (1/1) ... [2022-04-27 15:56:06,791 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@21b28248 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:06, skipping insertion in model container [2022-04-27 15:56:06,791 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 03:56:06" (1/1) ... [2022-04-27 15:56:06,804 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 15:56:06,813 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 15:56:06,959 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-2.c[328,341] [2022-04-27 15:56:06,995 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 15:56:07,007 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 15:56:07,014 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-2.c[328,341] [2022-04-27 15:56:07,027 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 15:56:07,037 INFO L208 MainTranslator]: Completed translation [2022-04-27 15:56:07,037 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07 WrapperNode [2022-04-27 15:56:07,038 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 15:56:07,038 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 15:56:07,038 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 15:56:07,038 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 15:56:07,047 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,048 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,052 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,052 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,057 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,067 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,068 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,071 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 15:56:07,071 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 15:56:07,072 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 15:56:07,072 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 15:56:07,079 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,091 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 15:56:07,107 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:56:07,125 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 15:56:07,144 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 15:56:07,173 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 15:56:07,179 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 15:56:07,179 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 15:56:07,179 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 15:56:07,179 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 15:56:07,180 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 15:56:07,180 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 15:56:07,180 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 15:56:07,180 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 15:56:07,180 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 15:56:07,181 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 15:56:07,181 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2022-04-27 15:56:07,181 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 15:56:07,182 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-27 15:56:07,182 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 15:56:07,184 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 15:56:07,184 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 15:56:07,184 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 15:56:07,184 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 15:56:07,184 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 15:56:07,235 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 15:56:07,236 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 15:56:07,461 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 15:56:07,467 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 15:56:07,467 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-27 15:56:07,468 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 03:56:07 BoogieIcfgContainer [2022-04-27 15:56:07,468 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 15:56:07,469 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 15:56:07,469 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 15:56:07,470 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 15:56:07,472 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 03:56:07" (1/1) ... [2022-04-27 15:56:07,485 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 15:56:07,510 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 03:56:07 BasicIcfg [2022-04-27 15:56:07,511 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 15:56:07,512 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 15:56:07,512 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 15:56:07,520 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 15:56:07,520 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 03:56:06" (1/4) ... [2022-04-27 15:56:07,521 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39f5bb9d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 03:56:07, skipping insertion in model container [2022-04-27 15:56:07,521 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 03:56:07" (2/4) ... [2022-04-27 15:56:07,521 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39f5bb9d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 03:56:07, skipping insertion in model container [2022-04-27 15:56:07,521 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 03:56:07" (3/4) ... [2022-04-27 15:56:07,522 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@39f5bb9d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 03:56:07, skipping insertion in model container [2022-04-27 15:56:07,522 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 03:56:07" (4/4) ... [2022-04-27 15:56:07,522 INFO L111 eAbstractionObserver]: Analyzing ICFG insertion_sort-2.cJordan [2022-04-27 15:56:07,533 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 15:56:07,533 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 15:56:07,572 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 15:56:07,576 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@31af8d5c, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@46c8186 [2022-04-27 15:56:07,577 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 15:56:07,585 INFO L276 IsEmpty]: Start isEmpty. Operand has 31 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 24 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:56:07,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 15:56:07,592 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:07,592 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:07,594 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:07,599 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:07,599 INFO L85 PathProgramCache]: Analyzing trace with hash -189909079, now seen corresponding path program 1 times [2022-04-27 15:56:07,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:07,606 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687565399] [2022-04-27 15:56:07,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:07,607 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:07,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:07,799 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:07,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:07,811 INFO L290 TraceCheckUtils]: 0: Hoare triple {39#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {34#true} is VALID [2022-04-27 15:56:07,811 INFO L290 TraceCheckUtils]: 1: Hoare triple {34#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 15:56:07,812 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {34#true} {34#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 15:56:07,831 INFO L272 TraceCheckUtils]: 0: Hoare triple {34#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {39#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:07,831 INFO L290 TraceCheckUtils]: 1: Hoare triple {39#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {34#true} is VALID [2022-04-27 15:56:07,831 INFO L290 TraceCheckUtils]: 2: Hoare triple {34#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 15:56:07,832 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {34#true} {34#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 15:56:07,832 INFO L272 TraceCheckUtils]: 4: Hoare triple {34#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 15:56:07,832 INFO L290 TraceCheckUtils]: 5: Hoare triple {34#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {34#true} is VALID [2022-04-27 15:56:07,833 INFO L290 TraceCheckUtils]: 6: Hoare triple {34#true} [96] L17-3-->L17-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 15:56:07,833 INFO L290 TraceCheckUtils]: 7: Hoare triple {35#false} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {35#false} is VALID [2022-04-27 15:56:07,833 INFO L290 TraceCheckUtils]: 8: Hoare triple {35#false} [101] L19-3-->L19-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 15:56:07,833 INFO L290 TraceCheckUtils]: 9: Hoare triple {35#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {35#false} is VALID [2022-04-27 15:56:07,834 INFO L290 TraceCheckUtils]: 10: Hoare triple {35#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {35#false} is VALID [2022-04-27 15:56:07,834 INFO L272 TraceCheckUtils]: 11: Hoare triple {35#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {35#false} is VALID [2022-04-27 15:56:07,834 INFO L290 TraceCheckUtils]: 12: Hoare triple {35#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {35#false} is VALID [2022-04-27 15:56:07,834 INFO L290 TraceCheckUtils]: 13: Hoare triple {35#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 15:56:07,834 INFO L290 TraceCheckUtils]: 14: Hoare triple {35#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 15:56:07,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:07,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:07,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1687565399] [2022-04-27 15:56:07,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1687565399] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 15:56:07,836 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 15:56:07,836 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 15:56:07,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417792348] [2022-04-27 15:56:07,838 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 15:56:07,841 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 15:56:07,842 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:07,845 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:07,902 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:07,902 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 15:56:07,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:07,929 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 15:56:07,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 15:56:07,933 INFO L87 Difference]: Start difference. First operand has 31 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 24 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:08,033 INFO L93 Difference]: Finished difference Result 31 states and 35 transitions. [2022-04-27 15:56:08,033 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 15:56:08,034 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 15:56:08,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:56:08,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 40 transitions. [2022-04-27 15:56:08,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 40 transitions. [2022-04-27 15:56:08,069 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 40 transitions. [2022-04-27 15:56:08,132 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:08,141 INFO L225 Difference]: With dead ends: 31 [2022-04-27 15:56:08,142 INFO L226 Difference]: Without dead ends: 26 [2022-04-27 15:56:08,143 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 15:56:08,147 INFO L413 NwaCegarLoop]: 34 mSDtfsCounter, 26 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 37 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 15:56:08,148 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 37 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 15:56:08,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-04-27 15:56:08,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2022-04-27 15:56:08,172 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:56:08,173 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,173 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,174 INFO L87 Difference]: Start difference. First operand 26 states. Second operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:08,176 INFO L93 Difference]: Finished difference Result 26 states and 30 transitions. [2022-04-27 15:56:08,176 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 15:56:08,177 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:08,177 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:08,177 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 26 states. [2022-04-27 15:56:08,177 INFO L87 Difference]: Start difference. First operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 26 states. [2022-04-27 15:56:08,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:08,179 INFO L93 Difference]: Finished difference Result 26 states and 30 transitions. [2022-04-27 15:56:08,180 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 15:56:08,180 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:08,180 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:08,180 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:56:08,180 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:56:08,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,182 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 30 transitions. [2022-04-27 15:56:08,183 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 30 transitions. Word has length 15 [2022-04-27 15:56:08,183 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:56:08,183 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 30 transitions. [2022-04-27 15:56:08,183 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,183 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 15:56:08,184 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 15:56:08,184 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:08,184 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:08,184 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 15:56:08,184 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:08,185 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:08,185 INFO L85 PathProgramCache]: Analyzing trace with hash -1109859861, now seen corresponding path program 1 times [2022-04-27 15:56:08,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:08,185 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1005922115] [2022-04-27 15:56:08,185 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:08,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:08,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:08,292 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:08,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:08,302 INFO L290 TraceCheckUtils]: 0: Hoare triple {159#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {151#true} is VALID [2022-04-27 15:56:08,303 INFO L290 TraceCheckUtils]: 1: Hoare triple {151#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {151#true} is VALID [2022-04-27 15:56:08,303 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {151#true} {151#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {151#true} is VALID [2022-04-27 15:56:08,304 INFO L272 TraceCheckUtils]: 0: Hoare triple {151#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {159#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:08,304 INFO L290 TraceCheckUtils]: 1: Hoare triple {159#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {151#true} is VALID [2022-04-27 15:56:08,304 INFO L290 TraceCheckUtils]: 2: Hoare triple {151#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {151#true} is VALID [2022-04-27 15:56:08,304 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {151#true} {151#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {151#true} is VALID [2022-04-27 15:56:08,304 INFO L272 TraceCheckUtils]: 4: Hoare triple {151#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {151#true} is VALID [2022-04-27 15:56:08,305 INFO L290 TraceCheckUtils]: 5: Hoare triple {151#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {156#(= main_~j~0 0)} is VALID [2022-04-27 15:56:08,305 INFO L290 TraceCheckUtils]: 6: Hoare triple {156#(= main_~j~0 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {157#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 15:56:08,306 INFO L290 TraceCheckUtils]: 7: Hoare triple {157#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {157#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 15:56:08,306 INFO L290 TraceCheckUtils]: 8: Hoare triple {157#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {157#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 15:56:08,307 INFO L290 TraceCheckUtils]: 9: Hoare triple {157#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {158#(and (<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 15:56:08,308 INFO L290 TraceCheckUtils]: 10: Hoare triple {158#(and (<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {152#false} is VALID [2022-04-27 15:56:08,308 INFO L272 TraceCheckUtils]: 11: Hoare triple {152#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {152#false} is VALID [2022-04-27 15:56:08,308 INFO L290 TraceCheckUtils]: 12: Hoare triple {152#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {152#false} is VALID [2022-04-27 15:56:08,308 INFO L290 TraceCheckUtils]: 13: Hoare triple {152#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {152#false} is VALID [2022-04-27 15:56:08,308 INFO L290 TraceCheckUtils]: 14: Hoare triple {152#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {152#false} is VALID [2022-04-27 15:56:08,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:08,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:08,309 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1005922115] [2022-04-27 15:56:08,309 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1005922115] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 15:56:08,309 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 15:56:08,309 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 15:56:08,309 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917846829] [2022-04-27 15:56:08,309 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 15:56:08,310 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 15:56:08,311 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:08,311 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,322 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:08,323 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 15:56:08,323 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:08,323 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 15:56:08,323 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-04-27 15:56:08,324 INFO L87 Difference]: Start difference. First operand 26 states and 30 transitions. Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:08,537 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2022-04-27 15:56:08,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 15:56:08,537 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 15:56:08,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:56:08,537 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 38 transitions. [2022-04-27 15:56:08,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 38 transitions. [2022-04-27 15:56:08,540 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 38 transitions. [2022-04-27 15:56:08,572 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:08,573 INFO L225 Difference]: With dead ends: 32 [2022-04-27 15:56:08,573 INFO L226 Difference]: Without dead ends: 28 [2022-04-27 15:56:08,573 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-04-27 15:56:08,574 INFO L413 NwaCegarLoop]: 25 mSDtfsCounter, 31 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 37 SdHoareTripleChecker+Invalid, 62 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 15:56:08,575 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 37 Invalid, 62 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 15:56:08,575 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-27 15:56:08,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2022-04-27 15:56:08,577 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:56:08,577 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,577 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,578 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:08,579 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-04-27 15:56:08,579 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-04-27 15:56:08,579 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:08,579 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:08,580 INFO L74 IsIncluded]: Start isIncluded. First operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-27 15:56:08,580 INFO L87 Difference]: Start difference. First operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-27 15:56:08,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:08,581 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-04-27 15:56:08,581 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-04-27 15:56:08,581 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:08,581 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:08,581 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:56:08,582 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:56:08,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:08,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 31 transitions. [2022-04-27 15:56:08,583 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 31 transitions. Word has length 15 [2022-04-27 15:56:08,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:56:08,583 INFO L495 AbstractCegarLoop]: Abstraction has 27 states and 31 transitions. [2022-04-27 15:56:08,583 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:08,583 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2022-04-27 15:56:08,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 15:56:08,584 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:08,584 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:08,584 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 15:56:08,584 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:08,584 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:08,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1012960919, now seen corresponding path program 1 times [2022-04-27 15:56:08,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:08,585 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446177807] [2022-04-27 15:56:08,585 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:08,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:08,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:08,729 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:08,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:08,734 INFO L290 TraceCheckUtils]: 0: Hoare triple {295#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {285#true} is VALID [2022-04-27 15:56:08,735 INFO L290 TraceCheckUtils]: 1: Hoare triple {285#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:08,735 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {285#true} {285#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:08,735 INFO L272 TraceCheckUtils]: 0: Hoare triple {285#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {295#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:08,736 INFO L290 TraceCheckUtils]: 1: Hoare triple {295#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {285#true} is VALID [2022-04-27 15:56:08,736 INFO L290 TraceCheckUtils]: 2: Hoare triple {285#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:08,736 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {285#true} {285#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:08,736 INFO L272 TraceCheckUtils]: 4: Hoare triple {285#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:08,737 INFO L290 TraceCheckUtils]: 5: Hoare triple {285#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {290#(= main_~j~0 0)} is VALID [2022-04-27 15:56:08,737 INFO L290 TraceCheckUtils]: 6: Hoare triple {290#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {291#(and (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1) (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296)))) (= main_~j~0 0))} is VALID [2022-04-27 15:56:08,738 INFO L290 TraceCheckUtils]: 7: Hoare triple {291#(and (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1) (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296)))) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {292#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (+ main_~SIZE~0 (* (div (+ (* (- 1) main_~j~0) 1) 4294967296) 4294967296))))} is VALID [2022-04-27 15:56:08,739 INFO L290 TraceCheckUtils]: 8: Hoare triple {292#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (+ main_~SIZE~0 (* (div (+ (* (- 1) main_~j~0) 1) 4294967296) 4294967296))))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:08,739 INFO L290 TraceCheckUtils]: 9: Hoare triple {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:08,740 INFO L290 TraceCheckUtils]: 10: Hoare triple {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:08,740 INFO L290 TraceCheckUtils]: 11: Hoare triple {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {294#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 15:56:08,741 INFO L290 TraceCheckUtils]: 12: Hoare triple {294#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {286#false} is VALID [2022-04-27 15:56:08,742 INFO L272 TraceCheckUtils]: 13: Hoare triple {286#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {286#false} is VALID [2022-04-27 15:56:08,742 INFO L290 TraceCheckUtils]: 14: Hoare triple {286#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {286#false} is VALID [2022-04-27 15:56:08,742 INFO L290 TraceCheckUtils]: 15: Hoare triple {286#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {286#false} is VALID [2022-04-27 15:56:08,742 INFO L290 TraceCheckUtils]: 16: Hoare triple {286#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {286#false} is VALID [2022-04-27 15:56:08,742 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:08,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:08,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446177807] [2022-04-27 15:56:08,743 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [446177807] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:56:08,743 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1969324588] [2022-04-27 15:56:08,743 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:08,743 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:08,743 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:56:08,745 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:56:08,746 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 15:56:08,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:08,793 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 15:56:08,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:08,811 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:56:09,209 INFO L272 TraceCheckUtils]: 0: Hoare triple {285#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:09,209 INFO L290 TraceCheckUtils]: 1: Hoare triple {285#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {285#true} is VALID [2022-04-27 15:56:09,210 INFO L290 TraceCheckUtils]: 2: Hoare triple {285#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:09,210 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {285#true} {285#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:09,210 INFO L272 TraceCheckUtils]: 4: Hoare triple {285#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:09,210 INFO L290 TraceCheckUtils]: 5: Hoare triple {285#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {285#true} is VALID [2022-04-27 15:56:09,210 INFO L290 TraceCheckUtils]: 6: Hoare triple {285#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {285#true} is VALID [2022-04-27 15:56:09,211 INFO L290 TraceCheckUtils]: 7: Hoare triple {285#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {285#true} is VALID [2022-04-27 15:56:09,211 INFO L290 TraceCheckUtils]: 8: Hoare triple {285#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {285#true} is VALID [2022-04-27 15:56:09,211 INFO L290 TraceCheckUtils]: 9: Hoare triple {285#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {326#(= main_~j~0 1)} is VALID [2022-04-27 15:56:09,212 INFO L290 TraceCheckUtils]: 10: Hoare triple {326#(= main_~j~0 1)} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:09,213 INFO L290 TraceCheckUtils]: 11: Hoare triple {293#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {294#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 15:56:09,213 INFO L290 TraceCheckUtils]: 12: Hoare triple {294#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {286#false} is VALID [2022-04-27 15:56:09,214 INFO L272 TraceCheckUtils]: 13: Hoare triple {286#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {286#false} is VALID [2022-04-27 15:56:09,214 INFO L290 TraceCheckUtils]: 14: Hoare triple {286#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {286#false} is VALID [2022-04-27 15:56:09,214 INFO L290 TraceCheckUtils]: 15: Hoare triple {286#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {286#false} is VALID [2022-04-27 15:56:09,214 INFO L290 TraceCheckUtils]: 16: Hoare triple {286#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {286#false} is VALID [2022-04-27 15:56:09,214 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:56:09,214 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 15:56:09,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1969324588] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 15:56:09,215 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 15:56:09,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [8] total 9 [2022-04-27 15:56:09,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099089030] [2022-04-27 15:56:09,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 15:56:09,216 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 15:56:09,216 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:09,216 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,229 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:09,229 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-04-27 15:56:09,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:09,229 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-04-27 15:56:09,230 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2022-04-27 15:56:09,230 INFO L87 Difference]: Start difference. First operand 27 states and 31 transitions. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:09,345 INFO L93 Difference]: Finished difference Result 35 states and 41 transitions. [2022-04-27 15:56:09,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-04-27 15:56:09,345 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 15:56:09,346 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:56:09,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 41 transitions. [2022-04-27 15:56:09,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 41 transitions. [2022-04-27 15:56:09,348 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 5 states and 41 transitions. [2022-04-27 15:56:09,384 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:09,384 INFO L225 Difference]: With dead ends: 35 [2022-04-27 15:56:09,385 INFO L226 Difference]: Without dead ends: 33 [2022-04-27 15:56:09,385 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 16 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2022-04-27 15:56:09,386 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 10 mSDsluCounter, 66 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 93 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 15:56:09,386 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 93 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 15:56:09,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-27 15:56:09,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 28. [2022-04-27 15:56:09,388 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:56:09,388 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:09,388 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:09,388 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:09,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:09,390 INFO L93 Difference]: Finished difference Result 33 states and 39 transitions. [2022-04-27 15:56:09,390 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 39 transitions. [2022-04-27 15:56:09,390 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:09,390 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:09,390 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-27 15:56:09,390 INFO L87 Difference]: Start difference. First operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-27 15:56:09,392 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:09,392 INFO L93 Difference]: Finished difference Result 33 states and 39 transitions. [2022-04-27 15:56:09,392 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 39 transitions. [2022-04-27 15:56:09,392 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:09,392 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:09,392 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:56:09,392 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:56:09,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:09,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2022-04-27 15:56:09,393 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 17 [2022-04-27 15:56:09,393 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:56:09,393 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2022-04-27 15:56:09,394 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,394 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-04-27 15:56:09,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 15:56:09,394 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:09,394 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:09,420 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 15:56:09,594 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:09,595 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:09,595 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:09,595 INFO L85 PathProgramCache]: Analyzing trace with hash -768849603, now seen corresponding path program 1 times [2022-04-27 15:56:09,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:09,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191664355] [2022-04-27 15:56:09,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:09,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:09,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:09,696 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:09,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:09,705 INFO L290 TraceCheckUtils]: 0: Hoare triple {488#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {480#true} is VALID [2022-04-27 15:56:09,705 INFO L290 TraceCheckUtils]: 1: Hoare triple {480#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {480#true} is VALID [2022-04-27 15:56:09,705 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {480#true} {480#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {480#true} is VALID [2022-04-27 15:56:09,706 INFO L272 TraceCheckUtils]: 0: Hoare triple {480#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {488#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:09,706 INFO L290 TraceCheckUtils]: 1: Hoare triple {488#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {480#true} is VALID [2022-04-27 15:56:09,706 INFO L290 TraceCheckUtils]: 2: Hoare triple {480#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {480#true} is VALID [2022-04-27 15:56:09,706 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {480#true} {480#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {480#true} is VALID [2022-04-27 15:56:09,706 INFO L272 TraceCheckUtils]: 4: Hoare triple {480#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {480#true} is VALID [2022-04-27 15:56:09,707 INFO L290 TraceCheckUtils]: 5: Hoare triple {480#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {480#true} is VALID [2022-04-27 15:56:09,707 INFO L290 TraceCheckUtils]: 6: Hoare triple {480#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {480#true} is VALID [2022-04-27 15:56:09,708 INFO L290 TraceCheckUtils]: 7: Hoare triple {480#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {480#true} is VALID [2022-04-27 15:56:09,708 INFO L290 TraceCheckUtils]: 8: Hoare triple {480#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {480#true} is VALID [2022-04-27 15:56:09,708 INFO L290 TraceCheckUtils]: 9: Hoare triple {480#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {485#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:56:09,709 INFO L290 TraceCheckUtils]: 10: Hoare triple {485#(= (+ (- 1) main_~j~0) 0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {486#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 15:56:09,709 INFO L290 TraceCheckUtils]: 11: Hoare triple {486#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {487#(and (= (+ (- 1) main_~j~0) 0) |main_#t~short10|)} is VALID [2022-04-27 15:56:09,710 INFO L290 TraceCheckUtils]: 12: Hoare triple {487#(and (= (+ (- 1) main_~j~0) 0) |main_#t~short10|)} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {481#false} is VALID [2022-04-27 15:56:09,710 INFO L290 TraceCheckUtils]: 13: Hoare triple {481#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {481#false} is VALID [2022-04-27 15:56:09,710 INFO L290 TraceCheckUtils]: 14: Hoare triple {481#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {481#false} is VALID [2022-04-27 15:56:09,710 INFO L290 TraceCheckUtils]: 15: Hoare triple {481#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {481#false} is VALID [2022-04-27 15:56:09,711 INFO L290 TraceCheckUtils]: 16: Hoare triple {481#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {481#false} is VALID [2022-04-27 15:56:09,711 INFO L290 TraceCheckUtils]: 17: Hoare triple {481#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {481#false} is VALID [2022-04-27 15:56:09,711 INFO L290 TraceCheckUtils]: 18: Hoare triple {481#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {481#false} is VALID [2022-04-27 15:56:09,712 INFO L272 TraceCheckUtils]: 19: Hoare triple {481#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {481#false} is VALID [2022-04-27 15:56:09,712 INFO L290 TraceCheckUtils]: 20: Hoare triple {481#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {481#false} is VALID [2022-04-27 15:56:09,713 INFO L290 TraceCheckUtils]: 21: Hoare triple {481#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {481#false} is VALID [2022-04-27 15:56:09,713 INFO L290 TraceCheckUtils]: 22: Hoare triple {481#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {481#false} is VALID [2022-04-27 15:56:09,717 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:56:09,718 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:09,718 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [191664355] [2022-04-27 15:56:09,718 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [191664355] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 15:56:09,718 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 15:56:09,718 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 15:56:09,719 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961697626] [2022-04-27 15:56:09,719 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 15:56:09,721 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 15:56:09,722 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:09,722 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,742 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:09,743 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 15:56:09,743 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:09,744 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 15:56:09,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-04-27 15:56:09,745 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:09,950 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2022-04-27 15:56:09,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 15:56:09,950 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 15:56:09,950 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:56:09,951 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,952 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 45 transitions. [2022-04-27 15:56:09,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:09,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 45 transitions. [2022-04-27 15:56:09,954 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 45 transitions. [2022-04-27 15:56:09,994 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 45 edges. 45 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:09,996 INFO L225 Difference]: With dead ends: 38 [2022-04-27 15:56:09,996 INFO L226 Difference]: Without dead ends: 38 [2022-04-27 15:56:09,998 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2022-04-27 15:56:10,001 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 43 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 65 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 44 SdHoareTripleChecker+Valid, 35 SdHoareTripleChecker+Invalid, 73 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 65 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 15:56:10,002 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [44 Valid, 35 Invalid, 73 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 65 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 15:56:10,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2022-04-27 15:56:10,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 30. [2022-04-27 15:56:10,004 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:56:10,004 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:10,004 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:10,004 INFO L87 Difference]: Start difference. First operand 38 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:10,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:10,005 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2022-04-27 15:56:10,005 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 45 transitions. [2022-04-27 15:56:10,006 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:10,006 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:10,006 INFO L74 IsIncluded]: Start isIncluded. First operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 38 states. [2022-04-27 15:56:10,006 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 38 states. [2022-04-27 15:56:10,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:10,009 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2022-04-27 15:56:10,010 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 45 transitions. [2022-04-27 15:56:10,011 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:10,011 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:10,011 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:56:10,011 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:56:10,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:10,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2022-04-27 15:56:10,012 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 23 [2022-04-27 15:56:10,012 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:56:10,012 INFO L495 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2022-04-27 15:56:10,013 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:10,013 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2022-04-27 15:56:10,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 15:56:10,013 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:10,013 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:10,013 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-04-27 15:56:10,013 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:10,014 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:10,014 INFO L85 PathProgramCache]: Analyzing trace with hash 1028101756, now seen corresponding path program 1 times [2022-04-27 15:56:10,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:10,014 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947733560] [2022-04-27 15:56:10,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:10,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:10,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:10,294 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:10,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:10,322 INFO L290 TraceCheckUtils]: 0: Hoare triple {651#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {641#true} is VALID [2022-04-27 15:56:10,322 INFO L290 TraceCheckUtils]: 1: Hoare triple {641#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:10,322 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {641#true} {641#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:10,323 INFO L272 TraceCheckUtils]: 0: Hoare triple {641#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {651#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:10,324 INFO L290 TraceCheckUtils]: 1: Hoare triple {651#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {641#true} is VALID [2022-04-27 15:56:10,325 INFO L290 TraceCheckUtils]: 2: Hoare triple {641#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:10,325 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {641#true} {641#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:10,325 INFO L272 TraceCheckUtils]: 4: Hoare triple {641#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:10,325 INFO L290 TraceCheckUtils]: 5: Hoare triple {641#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {646#(= main_~j~0 0)} is VALID [2022-04-27 15:56:10,326 INFO L290 TraceCheckUtils]: 6: Hoare triple {646#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {647#(and (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1) (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296)))) (= main_~j~0 0))} is VALID [2022-04-27 15:56:10,327 INFO L290 TraceCheckUtils]: 7: Hoare triple {647#(and (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1) (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296)))) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {648#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (+ main_~SIZE~0 (* (div (+ (* (- 1) main_~j~0) 1) 4294967296) 4294967296))))} is VALID [2022-04-27 15:56:10,328 INFO L290 TraceCheckUtils]: 8: Hoare triple {648#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (+ main_~SIZE~0 (* (div (+ (* (- 1) main_~j~0) 1) 4294967296) 4294967296))))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {649#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:10,329 INFO L290 TraceCheckUtils]: 9: Hoare triple {649#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {650#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 15:56:10,329 INFO L290 TraceCheckUtils]: 10: Hoare triple {650#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {642#false} is VALID [2022-04-27 15:56:10,329 INFO L290 TraceCheckUtils]: 11: Hoare triple {642#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {642#false} is VALID [2022-04-27 15:56:10,330 INFO L290 TraceCheckUtils]: 12: Hoare triple {642#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {642#false} is VALID [2022-04-27 15:56:10,330 INFO L290 TraceCheckUtils]: 13: Hoare triple {642#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {642#false} is VALID [2022-04-27 15:56:10,330 INFO L290 TraceCheckUtils]: 14: Hoare triple {642#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {642#false} is VALID [2022-04-27 15:56:10,330 INFO L290 TraceCheckUtils]: 15: Hoare triple {642#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {642#false} is VALID [2022-04-27 15:56:10,331 INFO L290 TraceCheckUtils]: 16: Hoare triple {642#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:10,331 INFO L290 TraceCheckUtils]: 17: Hoare triple {642#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {642#false} is VALID [2022-04-27 15:56:10,332 INFO L290 TraceCheckUtils]: 18: Hoare triple {642#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {642#false} is VALID [2022-04-27 15:56:10,332 INFO L272 TraceCheckUtils]: 19: Hoare triple {642#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {642#false} is VALID [2022-04-27 15:56:10,338 INFO L290 TraceCheckUtils]: 20: Hoare triple {642#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {642#false} is VALID [2022-04-27 15:56:10,338 INFO L290 TraceCheckUtils]: 21: Hoare triple {642#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:10,339 INFO L290 TraceCheckUtils]: 22: Hoare triple {642#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:10,339 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:10,339 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:10,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1947733560] [2022-04-27 15:56:10,339 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1947733560] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:56:10,339 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2011473039] [2022-04-27 15:56:10,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:10,339 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:10,339 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:56:10,356 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:56:10,371 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 15:56:10,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:10,486 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 15:56:10,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:10,506 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:56:11,038 INFO L272 TraceCheckUtils]: 0: Hoare triple {641#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:11,038 INFO L290 TraceCheckUtils]: 1: Hoare triple {641#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {641#true} is VALID [2022-04-27 15:56:11,038 INFO L290 TraceCheckUtils]: 2: Hoare triple {641#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:11,038 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {641#true} {641#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:11,038 INFO L272 TraceCheckUtils]: 4: Hoare triple {641#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:11,039 INFO L290 TraceCheckUtils]: 5: Hoare triple {641#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {646#(= main_~j~0 0)} is VALID [2022-04-27 15:56:11,040 INFO L290 TraceCheckUtils]: 6: Hoare triple {646#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {646#(= main_~j~0 0)} is VALID [2022-04-27 15:56:11,040 INFO L290 TraceCheckUtils]: 7: Hoare triple {646#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {676#(= main_~j~0 1)} is VALID [2022-04-27 15:56:11,041 INFO L290 TraceCheckUtils]: 8: Hoare triple {676#(= main_~j~0 1)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {649#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:11,042 INFO L290 TraceCheckUtils]: 9: Hoare triple {649#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {650#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 15:56:11,042 INFO L290 TraceCheckUtils]: 10: Hoare triple {650#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {642#false} is VALID [2022-04-27 15:56:11,060 INFO L290 TraceCheckUtils]: 11: Hoare triple {642#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {642#false} is VALID [2022-04-27 15:56:11,060 INFO L290 TraceCheckUtils]: 12: Hoare triple {642#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {642#false} is VALID [2022-04-27 15:56:11,061 INFO L290 TraceCheckUtils]: 13: Hoare triple {642#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {642#false} is VALID [2022-04-27 15:56:11,061 INFO L290 TraceCheckUtils]: 14: Hoare triple {642#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {642#false} is VALID [2022-04-27 15:56:11,061 INFO L290 TraceCheckUtils]: 15: Hoare triple {642#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {642#false} is VALID [2022-04-27 15:56:11,061 INFO L290 TraceCheckUtils]: 16: Hoare triple {642#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:11,061 INFO L290 TraceCheckUtils]: 17: Hoare triple {642#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {642#false} is VALID [2022-04-27 15:56:11,062 INFO L290 TraceCheckUtils]: 18: Hoare triple {642#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {642#false} is VALID [2022-04-27 15:56:11,062 INFO L272 TraceCheckUtils]: 19: Hoare triple {642#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {642#false} is VALID [2022-04-27 15:56:11,062 INFO L290 TraceCheckUtils]: 20: Hoare triple {642#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {642#false} is VALID [2022-04-27 15:56:11,062 INFO L290 TraceCheckUtils]: 21: Hoare triple {642#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:11,062 INFO L290 TraceCheckUtils]: 22: Hoare triple {642#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:11,062 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:11,062 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:56:24,510 INFO L290 TraceCheckUtils]: 22: Hoare triple {642#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:24,510 INFO L290 TraceCheckUtils]: 21: Hoare triple {642#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:24,510 INFO L290 TraceCheckUtils]: 20: Hoare triple {642#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {642#false} is VALID [2022-04-27 15:56:24,510 INFO L272 TraceCheckUtils]: 19: Hoare triple {642#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 18: Hoare triple {642#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 17: Hoare triple {642#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 16: Hoare triple {642#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 15: Hoare triple {642#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 14: Hoare triple {642#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 13: Hoare triple {642#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 12: Hoare triple {642#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {642#false} is VALID [2022-04-27 15:56:24,511 INFO L290 TraceCheckUtils]: 11: Hoare triple {642#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {642#false} is VALID [2022-04-27 15:56:24,512 INFO L290 TraceCheckUtils]: 10: Hoare triple {758#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {642#false} is VALID [2022-04-27 15:56:24,513 INFO L290 TraceCheckUtils]: 9: Hoare triple {649#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {758#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 15:56:24,551 INFO L290 TraceCheckUtils]: 8: Hoare triple {765#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (< (mod main_~j~0 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296)) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56)))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {649#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 15:56:24,583 INFO L290 TraceCheckUtils]: 7: Hoare triple {769#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {765#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (< (mod main_~j~0 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296)) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56)))} is VALID [2022-04-27 15:56:24,584 INFO L290 TraceCheckUtils]: 6: Hoare triple {769#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {769#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} is VALID [2022-04-27 15:56:24,586 INFO L290 TraceCheckUtils]: 5: Hoare triple {641#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {769#(forall ((aux_div_aux_mod_main_~SIZE~0_29_56 Int) (aux_mod_aux_mod_main_~SIZE~0_29_56 Int)) (or (<= 0 aux_div_aux_mod_main_~SIZE~0_29_56) (<= (+ 4294967295 (* aux_div_aux_mod_main_~SIZE~0_29_56 4294967296) aux_mod_aux_mod_main_~SIZE~0_29_56) 0) (<= 4294967296 aux_mod_aux_mod_main_~SIZE~0_29_56) (< (mod (+ main_~j~0 1) 4294967296) (mod (+ (* 4294967295 aux_mod_aux_mod_main_~SIZE~0_29_56) 1) 4294967296))))} is VALID [2022-04-27 15:56:24,586 INFO L272 TraceCheckUtils]: 4: Hoare triple {641#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:24,586 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {641#true} {641#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:24,586 INFO L290 TraceCheckUtils]: 2: Hoare triple {641#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:24,586 INFO L290 TraceCheckUtils]: 1: Hoare triple {641#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {641#true} is VALID [2022-04-27 15:56:24,586 INFO L272 TraceCheckUtils]: 0: Hoare triple {641#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {641#true} is VALID [2022-04-27 15:56:24,587 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:24,587 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2011473039] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:56:24,587 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:56:24,587 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 6] total 12 [2022-04-27 15:56:24,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880498152] [2022-04-27 15:56:24,587 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:56:24,588 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 15:56:24,588 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:24,588 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:24,834 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:24,834 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-04-27 15:56:24,835 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:24,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-04-27 15:56:24,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=95, Unknown=3, NotChecked=0, Total=132 [2022-04-27 15:56:24,835 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:25,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:25,257 INFO L93 Difference]: Finished difference Result 35 states and 39 transitions. [2022-04-27 15:56:25,257 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2022-04-27 15:56:25,257 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 15:56:25,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:56:25,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:25,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 37 transitions. [2022-04-27 15:56:25,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:25,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8 states to 8 states and 37 transitions. [2022-04-27 15:56:25,260 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 8 states and 37 transitions. [2022-04-27 15:56:25,295 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:25,296 INFO L225 Difference]: With dead ends: 35 [2022-04-27 15:56:25,296 INFO L226 Difference]: Without dead ends: 33 [2022-04-27 15:56:25,296 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 42 SyntacticMatches, 3 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 48 ImplicationChecksByTransitivity, 11.9s TimeCoverageRelationStatistics Valid=71, Invalid=198, Unknown=3, NotChecked=0, Total=272 [2022-04-27 15:56:25,297 INFO L413 NwaCegarLoop]: 25 mSDtfsCounter, 36 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 91 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 36 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 155 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 91 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 51 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 15:56:25,297 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [36 Valid, 52 Invalid, 155 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 91 Invalid, 0 Unknown, 51 Unchecked, 0.1s Time] [2022-04-27 15:56:25,297 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-27 15:56:25,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 32. [2022-04-27 15:56:25,299 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:56:25,300 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:25,300 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:25,300 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:25,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:25,301 INFO L93 Difference]: Finished difference Result 33 states and 37 transitions. [2022-04-27 15:56:25,301 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2022-04-27 15:56:25,301 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:25,301 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:25,302 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-27 15:56:25,302 INFO L87 Difference]: Start difference. First operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-27 15:56:25,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:25,302 INFO L93 Difference]: Finished difference Result 33 states and 37 transitions. [2022-04-27 15:56:25,303 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 37 transitions. [2022-04-27 15:56:25,303 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:25,303 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:25,303 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:56:25,303 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:56:25,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 15:56:25,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2022-04-27 15:56:25,304 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 23 [2022-04-27 15:56:25,304 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:56:25,304 INFO L495 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2022-04-27 15:56:25,304 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 12 states have (on average 2.4166666666666665) internal successors, (29), 11 states have internal predecessors, (29), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:25,304 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2022-04-27 15:56:25,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-27 15:56:25,305 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:25,305 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:25,328 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2022-04-27 15:56:25,515 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:25,515 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:25,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:25,516 INFO L85 PathProgramCache]: Analyzing trace with hash 1354614778, now seen corresponding path program 2 times [2022-04-27 15:56:25,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:25,516 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367774867] [2022-04-27 15:56:25,516 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:25,516 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:25,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:25,964 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:25,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:25,969 INFO L290 TraceCheckUtils]: 0: Hoare triple {954#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {936#true} is VALID [2022-04-27 15:56:25,969 INFO L290 TraceCheckUtils]: 1: Hoare triple {936#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:25,969 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {936#true} {936#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:25,970 INFO L272 TraceCheckUtils]: 0: Hoare triple {936#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {954#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:25,970 INFO L290 TraceCheckUtils]: 1: Hoare triple {954#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {936#true} is VALID [2022-04-27 15:56:25,970 INFO L290 TraceCheckUtils]: 2: Hoare triple {936#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:25,970 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {936#true} {936#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:25,970 INFO L272 TraceCheckUtils]: 4: Hoare triple {936#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:25,971 INFO L290 TraceCheckUtils]: 5: Hoare triple {936#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {941#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:56:25,972 INFO L290 TraceCheckUtils]: 6: Hoare triple {941#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {941#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:56:25,972 INFO L290 TraceCheckUtils]: 7: Hoare triple {941#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {942#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:25,972 INFO L290 TraceCheckUtils]: 8: Hoare triple {942#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {942#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:25,973 INFO L290 TraceCheckUtils]: 9: Hoare triple {942#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:25,973 INFO L290 TraceCheckUtils]: 10: Hoare triple {943#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:25,973 INFO L290 TraceCheckUtils]: 11: Hoare triple {943#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {942#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:25,974 INFO L290 TraceCheckUtils]: 12: Hoare triple {942#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {944#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 15:56:25,974 INFO L290 TraceCheckUtils]: 13: Hoare triple {944#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {945#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-27 15:56:25,977 INFO L290 TraceCheckUtils]: 14: Hoare triple {945#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {946#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 15:56:25,978 INFO L290 TraceCheckUtils]: 15: Hoare triple {946#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {947#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 15:56:25,979 INFO L290 TraceCheckUtils]: 16: Hoare triple {947#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {948#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:25,979 INFO L290 TraceCheckUtils]: 17: Hoare triple {948#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:25,979 INFO L290 TraceCheckUtils]: 18: Hoare triple {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:25,980 INFO L290 TraceCheckUtils]: 19: Hoare triple {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {950#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:56:25,980 INFO L290 TraceCheckUtils]: 20: Hoare triple {950#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {951#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:56:25,981 INFO L272 TraceCheckUtils]: 21: Hoare triple {951#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {952#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 15:56:25,981 INFO L290 TraceCheckUtils]: 22: Hoare triple {952#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {953#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 15:56:25,981 INFO L290 TraceCheckUtils]: 23: Hoare triple {953#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {937#false} is VALID [2022-04-27 15:56:25,981 INFO L290 TraceCheckUtils]: 24: Hoare triple {937#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {937#false} is VALID [2022-04-27 15:56:25,982 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:25,982 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:25,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367774867] [2022-04-27 15:56:25,982 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367774867] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:56:25,982 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1688993596] [2022-04-27 15:56:25,982 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 15:56:25,982 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:25,982 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:56:25,983 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:56:25,984 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 15:56:26,033 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 15:56:26,033 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 15:56:26,034 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 19 conjunts are in the unsatisfiable core [2022-04-27 15:56:26,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:26,047 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:56:26,426 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 15:56:26,429 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 15:56:26,544 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 15:56:26,545 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 15:56:26,612 INFO L272 TraceCheckUtils]: 0: Hoare triple {936#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:26,612 INFO L290 TraceCheckUtils]: 1: Hoare triple {936#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {936#true} is VALID [2022-04-27 15:56:26,615 INFO L290 TraceCheckUtils]: 2: Hoare triple {936#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:26,615 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {936#true} {936#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:26,615 INFO L272 TraceCheckUtils]: 4: Hoare triple {936#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:26,616 INFO L290 TraceCheckUtils]: 5: Hoare triple {936#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:26,616 INFO L290 TraceCheckUtils]: 6: Hoare triple {943#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:26,616 INFO L290 TraceCheckUtils]: 7: Hoare triple {943#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:26,617 INFO L290 TraceCheckUtils]: 8: Hoare triple {943#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:26,617 INFO L290 TraceCheckUtils]: 9: Hoare triple {943#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:26,617 INFO L290 TraceCheckUtils]: 10: Hoare triple {943#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {943#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:26,618 INFO L290 TraceCheckUtils]: 11: Hoare triple {943#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {991#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:26,619 INFO L290 TraceCheckUtils]: 12: Hoare triple {991#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {995#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-27 15:56:26,619 INFO L290 TraceCheckUtils]: 13: Hoare triple {995#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {999#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 15:56:26,620 INFO L290 TraceCheckUtils]: 14: Hoare triple {999#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1003#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 15:56:26,620 INFO L290 TraceCheckUtils]: 15: Hoare triple {1003#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1007#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 15:56:26,621 INFO L290 TraceCheckUtils]: 16: Hoare triple {1007#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:26,622 INFO L290 TraceCheckUtils]: 17: Hoare triple {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:26,622 INFO L290 TraceCheckUtils]: 18: Hoare triple {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:26,623 INFO L290 TraceCheckUtils]: 19: Hoare triple {949#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {950#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:56:26,623 INFO L290 TraceCheckUtils]: 20: Hoare triple {950#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {951#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:56:26,625 INFO L272 TraceCheckUtils]: 21: Hoare triple {951#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1026#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:56:26,625 INFO L290 TraceCheckUtils]: 22: Hoare triple {1026#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1030#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:56:26,626 INFO L290 TraceCheckUtils]: 23: Hoare triple {1030#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {937#false} is VALID [2022-04-27 15:56:26,626 INFO L290 TraceCheckUtils]: 24: Hoare triple {937#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {937#false} is VALID [2022-04-27 15:56:26,626 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:56:26,626 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:56:26,995 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-27 15:56:27,031 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-27 15:56:27,031 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-27 15:56:27,214 INFO L290 TraceCheckUtils]: 24: Hoare triple {937#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {937#false} is VALID [2022-04-27 15:56:27,215 INFO L290 TraceCheckUtils]: 23: Hoare triple {1030#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {937#false} is VALID [2022-04-27 15:56:27,215 INFO L290 TraceCheckUtils]: 22: Hoare triple {1026#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1030#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:56:27,216 INFO L272 TraceCheckUtils]: 21: Hoare triple {951#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1026#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:56:27,216 INFO L290 TraceCheckUtils]: 20: Hoare triple {1049#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {951#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:56:27,217 INFO L290 TraceCheckUtils]: 19: Hoare triple {1053#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1049#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 15:56:27,217 INFO L290 TraceCheckUtils]: 18: Hoare triple {1053#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1053#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:56:27,217 INFO L290 TraceCheckUtils]: 17: Hoare triple {1053#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1053#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:56:27,218 INFO L290 TraceCheckUtils]: 16: Hoare triple {1063#(forall ((v_ArrVal_48 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_48))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1053#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:56:27,219 INFO L290 TraceCheckUtils]: 15: Hoare triple {1067#(or (forall ((v_ArrVal_48 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_48)))) |main_#t~short10|)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1063#(forall ((v_ArrVal_48 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_48))))} is VALID [2022-04-27 15:56:27,220 INFO L290 TraceCheckUtils]: 14: Hoare triple {1071#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1067#(or (forall ((v_ArrVal_48 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_48) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_48)))) |main_#t~short10|)} is VALID [2022-04-27 15:56:27,220 INFO L290 TraceCheckUtils]: 13: Hoare triple {1075#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1071#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:56:27,221 INFO L290 TraceCheckUtils]: 12: Hoare triple {1079#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1075#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:56:27,221 INFO L290 TraceCheckUtils]: 11: Hoare triple {936#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1079#(<= main_~j~0 1)} is VALID [2022-04-27 15:56:27,221 INFO L290 TraceCheckUtils]: 10: Hoare triple {936#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:27,221 INFO L290 TraceCheckUtils]: 9: Hoare triple {936#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {936#true} is VALID [2022-04-27 15:56:27,221 INFO L290 TraceCheckUtils]: 8: Hoare triple {936#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L290 TraceCheckUtils]: 7: Hoare triple {936#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L290 TraceCheckUtils]: 6: Hoare triple {936#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L290 TraceCheckUtils]: 5: Hoare triple {936#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L272 TraceCheckUtils]: 4: Hoare triple {936#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {936#true} {936#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L290 TraceCheckUtils]: 2: Hoare triple {936#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L290 TraceCheckUtils]: 1: Hoare triple {936#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {936#true} is VALID [2022-04-27 15:56:27,222 INFO L272 TraceCheckUtils]: 0: Hoare triple {936#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {936#true} is VALID [2022-04-27 15:56:27,223 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:56:27,223 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1688993596] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:56:27,223 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:56:27,223 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 13, 12] total 30 [2022-04-27 15:56:27,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374409292] [2022-04-27 15:56:27,223 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:56:27,224 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 15:56:27,224 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:27,224 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:27,265 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:27,266 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 30 states [2022-04-27 15:56:27,266 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:27,266 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2022-04-27 15:56:27,266 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=137, Invalid=733, Unknown=0, NotChecked=0, Total=870 [2022-04-27 15:56:27,267 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:30,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:30,051 INFO L93 Difference]: Finished difference Result 86 states and 109 transitions. [2022-04-27 15:56:30,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-04-27 15:56:30,051 INFO L78 Accepts]: Start accepts. Automaton has has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 15:56:30,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:56:30,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:30,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 110 transitions. [2022-04-27 15:56:30,071 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:30,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 110 transitions. [2022-04-27 15:56:30,073 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 32 states and 110 transitions. [2022-04-27 15:56:30,182 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 110 edges. 110 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:30,184 INFO L225 Difference]: With dead ends: 86 [2022-04-27 15:56:30,184 INFO L226 Difference]: Without dead ends: 86 [2022-04-27 15:56:30,185 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 105 GetRequests, 43 SyntacticMatches, 5 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 965 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=606, Invalid=2816, Unknown=0, NotChecked=0, Total=3422 [2022-04-27 15:56:30,186 INFO L413 NwaCegarLoop]: 18 mSDtfsCounter, 132 mSDsluCounter, 87 mSDsCounter, 0 mSdLazyCounter, 710 mSolverCounterSat, 112 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 132 SdHoareTripleChecker+Valid, 105 SdHoareTripleChecker+Invalid, 961 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 112 IncrementalHoareTripleChecker+Valid, 710 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 139 IncrementalHoareTripleChecker+Unchecked, 1.0s IncrementalHoareTripleChecker+Time [2022-04-27 15:56:30,186 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [132 Valid, 105 Invalid, 961 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [112 Valid, 710 Invalid, 0 Unknown, 139 Unchecked, 1.0s Time] [2022-04-27 15:56:30,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 86 states. [2022-04-27 15:56:30,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 86 to 46. [2022-04-27 15:56:30,190 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:56:30,190 INFO L82 GeneralOperation]: Start isEquivalent. First operand 86 states. Second operand has 46 states, 38 states have (on average 1.236842105263158) internal successors, (47), 39 states have internal predecessors, (47), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:56:30,190 INFO L74 IsIncluded]: Start isIncluded. First operand 86 states. Second operand has 46 states, 38 states have (on average 1.236842105263158) internal successors, (47), 39 states have internal predecessors, (47), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:56:30,190 INFO L87 Difference]: Start difference. First operand 86 states. Second operand has 46 states, 38 states have (on average 1.236842105263158) internal successors, (47), 39 states have internal predecessors, (47), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:56:30,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:30,193 INFO L93 Difference]: Finished difference Result 86 states and 109 transitions. [2022-04-27 15:56:30,193 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 109 transitions. [2022-04-27 15:56:30,193 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:30,193 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:30,194 INFO L74 IsIncluded]: Start isIncluded. First operand has 46 states, 38 states have (on average 1.236842105263158) internal successors, (47), 39 states have internal predecessors, (47), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 86 states. [2022-04-27 15:56:30,194 INFO L87 Difference]: Start difference. First operand has 46 states, 38 states have (on average 1.236842105263158) internal successors, (47), 39 states have internal predecessors, (47), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 86 states. [2022-04-27 15:56:30,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:56:30,196 INFO L93 Difference]: Finished difference Result 86 states and 109 transitions. [2022-04-27 15:56:30,196 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 109 transitions. [2022-04-27 15:56:30,196 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:56:30,197 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:56:30,197 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:56:30,197 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:56:30,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46 states, 38 states have (on average 1.236842105263158) internal successors, (47), 39 states have internal predecessors, (47), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:56:30,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 54 transitions. [2022-04-27 15:56:30,198 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 54 transitions. Word has length 25 [2022-04-27 15:56:30,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:56:30,198 INFO L495 AbstractCegarLoop]: Abstraction has 46 states and 54 transitions. [2022-04-27 15:56:30,198 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 30 states, 29 states have (on average 1.6551724137931034) internal successors, (48), 27 states have internal predecessors, (48), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:30,198 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 54 transitions. [2022-04-27 15:56:30,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-04-27 15:56:30,198 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:56:30,198 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:56:30,219 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 15:56:30,414 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:30,415 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:56:30,415 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:56:30,415 INFO L85 PathProgramCache]: Analyzing trace with hash -1272155915, now seen corresponding path program 1 times [2022-04-27 15:56:30,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:56:30,415 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818781862] [2022-04-27 15:56:30,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:30,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:56:30,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:30,802 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:56:30,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:30,812 INFO L290 TraceCheckUtils]: 0: Hoare triple {1506#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1487#true} is VALID [2022-04-27 15:56:30,812 INFO L290 TraceCheckUtils]: 1: Hoare triple {1487#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:30,812 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1487#true} {1487#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:30,814 INFO L272 TraceCheckUtils]: 0: Hoare triple {1487#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1506#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:56:30,814 INFO L290 TraceCheckUtils]: 1: Hoare triple {1506#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1487#true} is VALID [2022-04-27 15:56:30,814 INFO L290 TraceCheckUtils]: 2: Hoare triple {1487#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:30,814 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1487#true} {1487#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:30,814 INFO L272 TraceCheckUtils]: 4: Hoare triple {1487#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:30,816 INFO L290 TraceCheckUtils]: 5: Hoare triple {1487#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1492#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:56:30,816 INFO L290 TraceCheckUtils]: 6: Hoare triple {1492#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1492#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:56:30,816 INFO L290 TraceCheckUtils]: 7: Hoare triple {1492#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1493#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:30,817 INFO L290 TraceCheckUtils]: 8: Hoare triple {1493#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1493#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:30,817 INFO L290 TraceCheckUtils]: 9: Hoare triple {1493#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1494#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:30,817 INFO L290 TraceCheckUtils]: 10: Hoare triple {1494#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1494#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:56:30,818 INFO L290 TraceCheckUtils]: 11: Hoare triple {1494#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1493#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:56:30,818 INFO L290 TraceCheckUtils]: 12: Hoare triple {1493#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1495#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 15:56:30,819 INFO L290 TraceCheckUtils]: 13: Hoare triple {1495#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1496#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:30,820 INFO L290 TraceCheckUtils]: 14: Hoare triple {1496#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1497#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (<= 0 main_~i~0))} is VALID [2022-04-27 15:56:30,823 INFO L290 TraceCheckUtils]: 15: Hoare triple {1497#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (<= 0 main_~i~0))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {1498#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0))) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 15:56:30,824 INFO L290 TraceCheckUtils]: 16: Hoare triple {1498#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0))) (<= 0 (+ main_~i~0 1)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1499#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} is VALID [2022-04-27 15:56:30,824 INFO L290 TraceCheckUtils]: 17: Hoare triple {1499#(and (= |main_~#v~0.offset| 0) (or (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1500#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 15:56:30,825 INFO L290 TraceCheckUtils]: 18: Hoare triple {1500#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1500#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 15:56:30,825 INFO L290 TraceCheckUtils]: 19: Hoare triple {1500#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1501#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:30,827 INFO L290 TraceCheckUtils]: 20: Hoare triple {1501#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1501#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:30,827 INFO L290 TraceCheckUtils]: 21: Hoare triple {1501#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1501#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:56:30,827 INFO L290 TraceCheckUtils]: 22: Hoare triple {1501#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1502#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:56:30,828 INFO L290 TraceCheckUtils]: 23: Hoare triple {1502#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1503#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:56:30,828 INFO L272 TraceCheckUtils]: 24: Hoare triple {1503#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1504#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 15:56:30,829 INFO L290 TraceCheckUtils]: 25: Hoare triple {1504#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1505#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 15:56:30,836 INFO L290 TraceCheckUtils]: 26: Hoare triple {1505#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1488#false} is VALID [2022-04-27 15:56:30,837 INFO L290 TraceCheckUtils]: 27: Hoare triple {1488#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1488#false} is VALID [2022-04-27 15:56:30,837 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:56:30,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:56:30,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818781862] [2022-04-27 15:56:30,837 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818781862] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:56:30,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [429259589] [2022-04-27 15:56:30,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:56:30,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:56:30,838 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:56:30,840 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:56:30,841 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 15:56:30,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:30,912 INFO L263 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-27 15:56:30,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:56:30,927 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:56:31,260 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-27 15:56:31,261 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-27 15:56:31,929 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-27 15:56:31,929 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-27 15:56:32,961 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-27 15:56:32,961 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-27 15:56:33,118 INFO L272 TraceCheckUtils]: 0: Hoare triple {1487#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:33,118 INFO L290 TraceCheckUtils]: 1: Hoare triple {1487#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1487#true} is VALID [2022-04-27 15:56:33,118 INFO L290 TraceCheckUtils]: 2: Hoare triple {1487#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:33,118 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1487#true} {1487#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:33,118 INFO L272 TraceCheckUtils]: 4: Hoare triple {1487#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:33,118 INFO L290 TraceCheckUtils]: 5: Hoare triple {1487#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1487#true} is VALID [2022-04-27 15:56:33,118 INFO L290 TraceCheckUtils]: 6: Hoare triple {1487#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1487#true} is VALID [2022-04-27 15:56:33,119 INFO L290 TraceCheckUtils]: 7: Hoare triple {1487#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1487#true} is VALID [2022-04-27 15:56:33,119 INFO L290 TraceCheckUtils]: 8: Hoare triple {1487#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1487#true} is VALID [2022-04-27 15:56:33,119 INFO L290 TraceCheckUtils]: 9: Hoare triple {1487#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1487#true} is VALID [2022-04-27 15:56:33,119 INFO L290 TraceCheckUtils]: 10: Hoare triple {1487#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:33,119 INFO L290 TraceCheckUtils]: 11: Hoare triple {1487#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1543#(<= main_~j~0 1)} is VALID [2022-04-27 15:56:33,120 INFO L290 TraceCheckUtils]: 12: Hoare triple {1543#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1547#(<= main_~i~0 0)} is VALID [2022-04-27 15:56:33,120 INFO L290 TraceCheckUtils]: 13: Hoare triple {1547#(<= main_~i~0 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1551#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 15:56:33,121 INFO L290 TraceCheckUtils]: 14: Hoare triple {1551#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1555#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} is VALID [2022-04-27 15:56:33,124 INFO L290 TraceCheckUtils]: 15: Hoare triple {1555#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {1559#(exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))))))} is VALID [2022-04-27 15:56:33,125 INFO L290 TraceCheckUtils]: 16: Hoare triple {1559#(exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1563#(and (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 15:56:33,126 INFO L290 TraceCheckUtils]: 17: Hoare triple {1563#(and (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1567#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} is VALID [2022-04-27 15:56:33,127 INFO L290 TraceCheckUtils]: 18: Hoare triple {1567#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1567#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} is VALID [2022-04-27 15:56:33,130 INFO L290 TraceCheckUtils]: 19: Hoare triple {1567#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1574#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} is VALID [2022-04-27 15:56:33,131 INFO L290 TraceCheckUtils]: 20: Hoare triple {1574#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1574#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} is VALID [2022-04-27 15:56:33,132 INFO L290 TraceCheckUtils]: 21: Hoare triple {1574#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1574#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} is VALID [2022-04-27 15:56:33,133 INFO L290 TraceCheckUtils]: 22: Hoare triple {1574#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1584#(and (exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11))) (= main_~k~0 1))} is VALID [2022-04-27 15:56:33,134 INFO L290 TraceCheckUtils]: 23: Hoare triple {1584#(and (exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11))) (= main_~k~0 1))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1588#(< |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:56:33,135 INFO L272 TraceCheckUtils]: 24: Hoare triple {1588#(< |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1592#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:56:33,135 INFO L290 TraceCheckUtils]: 25: Hoare triple {1592#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1596#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:56:33,136 INFO L290 TraceCheckUtils]: 26: Hoare triple {1596#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1488#false} is VALID [2022-04-27 15:56:33,136 INFO L290 TraceCheckUtils]: 27: Hoare triple {1488#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1488#false} is VALID [2022-04-27 15:56:33,136 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:56:33,136 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:56:34,181 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 61 [2022-04-27 15:56:34,242 INFO L356 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-04-27 15:56:34,242 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 717 treesize of output 657 [2022-04-27 15:56:35,588 INFO L290 TraceCheckUtils]: 27: Hoare triple {1488#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1488#false} is VALID [2022-04-27 15:56:35,589 INFO L290 TraceCheckUtils]: 26: Hoare triple {1596#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1488#false} is VALID [2022-04-27 15:56:35,589 INFO L290 TraceCheckUtils]: 25: Hoare triple {1592#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1596#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:56:35,590 INFO L272 TraceCheckUtils]: 24: Hoare triple {1503#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1592#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:56:35,591 INFO L290 TraceCheckUtils]: 23: Hoare triple {1615#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1503#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:56:35,591 INFO L290 TraceCheckUtils]: 22: Hoare triple {1619#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1615#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 15:56:35,591 INFO L290 TraceCheckUtils]: 21: Hoare triple {1619#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1619#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:56:35,592 INFO L290 TraceCheckUtils]: 20: Hoare triple {1619#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1619#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:56:35,593 INFO L290 TraceCheckUtils]: 19: Hoare triple {1629#(forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4)))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1619#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:56:35,594 INFO L290 TraceCheckUtils]: 18: Hoare triple {1629#(forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4)))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1629#(forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 15:56:35,608 INFO L290 TraceCheckUtils]: 17: Hoare triple {1636#(or (forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1629#(forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 15:56:35,609 INFO L290 TraceCheckUtils]: 16: Hoare triple {1640#(or (forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1636#(or (forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 15:56:35,611 INFO L290 TraceCheckUtils]: 15: Hoare triple {1644#(or (not |main_#t~short10|) (forall ((v_ArrVal_70 Int) (v_main_~i~0_12 Int) (v_ArrVal_72 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_70) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_72) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_70) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_72) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_72 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_12 1))) (<= 0 v_main_~i~0_12) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_70)))))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {1640#(or (forall ((v_ArrVal_72 Int)) (or (not (<= v_ArrVal_72 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_72) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} is VALID [2022-04-27 15:56:35,612 INFO L290 TraceCheckUtils]: 14: Hoare triple {1648#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1644#(or (not |main_#t~short10|) (forall ((v_ArrVal_70 Int) (v_main_~i~0_12 Int) (v_ArrVal_72 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_70) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_72) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_70) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_72) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_72 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_12 1))) (<= 0 v_main_~i~0_12) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_70)))))} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 13: Hoare triple {1487#true} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1648#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 12: Hoare triple {1487#true} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1487#true} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 11: Hoare triple {1487#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1487#true} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 10: Hoare triple {1487#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 9: Hoare triple {1487#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1487#true} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 8: Hoare triple {1487#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1487#true} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 7: Hoare triple {1487#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1487#true} is VALID [2022-04-27 15:56:35,613 INFO L290 TraceCheckUtils]: 6: Hoare triple {1487#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L290 TraceCheckUtils]: 5: Hoare triple {1487#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L272 TraceCheckUtils]: 4: Hoare triple {1487#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1487#true} {1487#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L290 TraceCheckUtils]: 2: Hoare triple {1487#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L290 TraceCheckUtils]: 1: Hoare triple {1487#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L272 TraceCheckUtils]: 0: Hoare triple {1487#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1487#true} is VALID [2022-04-27 15:56:35,614 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:56:35,614 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [429259589] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:56:35,614 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:56:35,614 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 14, 12] total 36 [2022-04-27 15:56:35,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530646673] [2022-04-27 15:56:35,615 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:56:35,615 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2022-04-27 15:56:35,615 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:56:35,616 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:56:35,681 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:56:35,681 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-04-27 15:56:35,681 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:56:35,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-04-27 15:56:35,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=1124, Unknown=1, NotChecked=0, Total=1260 [2022-04-27 15:56:35,682 INFO L87 Difference]: Start difference. First operand 46 states and 54 transitions. Second operand has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:10,856 WARN L232 SmtUtils]: Spent 6.32s on a formula simplification that was a NOOP. DAG size: 37 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 15:57:31,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:31,746 INFO L93 Difference]: Finished difference Result 166 states and 220 transitions. [2022-04-27 15:57:31,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2022-04-27 15:57:31,746 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2022-04-27 15:57:31,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:57:31,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:31,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 191 transitions. [2022-04-27 15:57:31,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:31,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 61 states to 61 states and 191 transitions. [2022-04-27 15:57:31,765 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 61 states and 191 transitions. [2022-04-27 15:57:31,989 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 191 edges. 191 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:31,992 INFO L225 Difference]: With dead ends: 166 [2022-04-27 15:57:31,992 INFO L226 Difference]: Without dead ends: 166 [2022-04-27 15:57:31,994 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 45 SyntacticMatches, 3 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2488 ImplicationChecksByTransitivity, 55.4s TimeCoverageRelationStatistics Valid=923, Invalid=7256, Unknown=11, NotChecked=0, Total=8190 [2022-04-27 15:57:31,994 INFO L413 NwaCegarLoop]: 32 mSDtfsCounter, 140 mSDsluCounter, 106 mSDsCounter, 0 mSdLazyCounter, 845 mSolverCounterSat, 135 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 138 SdHoareTripleChecker+Invalid, 1526 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 135 IncrementalHoareTripleChecker+Valid, 845 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 546 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-04-27 15:57:31,994 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [141 Valid, 138 Invalid, 1526 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [135 Valid, 845 Invalid, 0 Unknown, 546 Unchecked, 1.1s Time] [2022-04-27 15:57:31,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2022-04-27 15:57:31,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 69. [2022-04-27 15:57:31,999 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:57:31,999 INFO L82 GeneralOperation]: Start isEquivalent. First operand 166 states. Second operand has 69 states, 61 states have (on average 1.360655737704918) internal successors, (83), 62 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:31,999 INFO L74 IsIncluded]: Start isIncluded. First operand 166 states. Second operand has 69 states, 61 states have (on average 1.360655737704918) internal successors, (83), 62 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:31,999 INFO L87 Difference]: Start difference. First operand 166 states. Second operand has 69 states, 61 states have (on average 1.360655737704918) internal successors, (83), 62 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:32,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:32,004 INFO L93 Difference]: Finished difference Result 166 states and 220 transitions. [2022-04-27 15:57:32,004 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 220 transitions. [2022-04-27 15:57:32,004 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:32,004 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:32,004 INFO L74 IsIncluded]: Start isIncluded. First operand has 69 states, 61 states have (on average 1.360655737704918) internal successors, (83), 62 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 166 states. [2022-04-27 15:57:32,004 INFO L87 Difference]: Start difference. First operand has 69 states, 61 states have (on average 1.360655737704918) internal successors, (83), 62 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 166 states. [2022-04-27 15:57:32,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:32,009 INFO L93 Difference]: Finished difference Result 166 states and 220 transitions. [2022-04-27 15:57:32,009 INFO L276 IsEmpty]: Start isEmpty. Operand 166 states and 220 transitions. [2022-04-27 15:57:32,009 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:32,009 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:32,009 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:57:32,009 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:57:32,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 69 states, 61 states have (on average 1.360655737704918) internal successors, (83), 62 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:32,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 90 transitions. [2022-04-27 15:57:32,011 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 90 transitions. Word has length 28 [2022-04-27 15:57:32,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:57:32,011 INFO L495 AbstractCegarLoop]: Abstraction has 69 states and 90 transitions. [2022-04-27 15:57:32,011 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:32,011 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 90 transitions. [2022-04-27 15:57:32,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-27 15:57:32,011 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:57:32,012 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:57:32,041 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 15:57:32,228 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:32,228 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:57:32,229 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:57:32,229 INFO L85 PathProgramCache]: Analyzing trace with hash -551964914, now seen corresponding path program 1 times [2022-04-27 15:57:32,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:57:32,229 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2102724141] [2022-04-27 15:57:32,229 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:32,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:57:32,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:32,297 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:57:32,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:32,302 INFO L290 TraceCheckUtils]: 0: Hoare triple {2386#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2377#true} is VALID [2022-04-27 15:57:32,303 INFO L290 TraceCheckUtils]: 1: Hoare triple {2377#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,303 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2377#true} {2377#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,303 INFO L272 TraceCheckUtils]: 0: Hoare triple {2377#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2386#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:57:32,303 INFO L290 TraceCheckUtils]: 1: Hoare triple {2386#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 2: Hoare triple {2377#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2377#true} {2377#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L272 TraceCheckUtils]: 4: Hoare triple {2377#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 5: Hoare triple {2377#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 6: Hoare triple {2377#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 7: Hoare triple {2377#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 8: Hoare triple {2377#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 9: Hoare triple {2377#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2377#true} is VALID [2022-04-27 15:57:32,304 INFO L290 TraceCheckUtils]: 10: Hoare triple {2377#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,305 INFO L290 TraceCheckUtils]: 11: Hoare triple {2377#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2382#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:57:32,305 INFO L290 TraceCheckUtils]: 12: Hoare triple {2382#(= (+ (- 1) main_~j~0) 0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2382#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:57:32,306 INFO L290 TraceCheckUtils]: 13: Hoare triple {2382#(= (+ (- 1) main_~j~0) 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2382#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:57:32,306 INFO L290 TraceCheckUtils]: 14: Hoare triple {2382#(= (+ (- 1) main_~j~0) 0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2382#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:57:32,307 INFO L290 TraceCheckUtils]: 15: Hoare triple {2382#(= (+ (- 1) main_~j~0) 0)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2382#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:57:32,307 INFO L290 TraceCheckUtils]: 16: Hoare triple {2382#(= (+ (- 1) main_~j~0) 0)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2382#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 15:57:32,307 INFO L290 TraceCheckUtils]: 17: Hoare triple {2382#(= (+ (- 1) main_~j~0) 0)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2383#(<= 2 main_~j~0)} is VALID [2022-04-27 15:57:32,308 INFO L290 TraceCheckUtils]: 18: Hoare triple {2383#(<= 2 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2384#(<= 1 main_~i~0)} is VALID [2022-04-27 15:57:32,309 INFO L290 TraceCheckUtils]: 19: Hoare triple {2384#(<= 1 main_~i~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2385#|main_#t~short10|} is VALID [2022-04-27 15:57:32,309 INFO L290 TraceCheckUtils]: 20: Hoare triple {2385#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,309 INFO L290 TraceCheckUtils]: 21: Hoare triple {2378#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2378#false} is VALID [2022-04-27 15:57:32,309 INFO L290 TraceCheckUtils]: 22: Hoare triple {2378#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2378#false} is VALID [2022-04-27 15:57:32,310 INFO L290 TraceCheckUtils]: 23: Hoare triple {2378#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2378#false} is VALID [2022-04-27 15:57:32,310 INFO L290 TraceCheckUtils]: 24: Hoare triple {2378#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,310 INFO L290 TraceCheckUtils]: 25: Hoare triple {2378#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2378#false} is VALID [2022-04-27 15:57:32,311 INFO L290 TraceCheckUtils]: 26: Hoare triple {2378#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2378#false} is VALID [2022-04-27 15:57:32,311 INFO L272 TraceCheckUtils]: 27: Hoare triple {2378#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2378#false} is VALID [2022-04-27 15:57:32,311 INFO L290 TraceCheckUtils]: 28: Hoare triple {2378#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2378#false} is VALID [2022-04-27 15:57:32,311 INFO L290 TraceCheckUtils]: 29: Hoare triple {2378#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,311 INFO L290 TraceCheckUtils]: 30: Hoare triple {2378#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,311 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:57:32,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:57:32,311 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2102724141] [2022-04-27 15:57:32,312 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2102724141] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:57:32,312 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1494796884] [2022-04-27 15:57:32,312 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:32,312 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:32,312 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:57:32,313 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:57:32,314 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 15:57:32,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:32,359 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 15:57:32,368 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:32,369 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:57:32,464 INFO L272 TraceCheckUtils]: 0: Hoare triple {2377#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,465 INFO L290 TraceCheckUtils]: 1: Hoare triple {2377#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2377#true} is VALID [2022-04-27 15:57:32,465 INFO L290 TraceCheckUtils]: 2: Hoare triple {2377#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,465 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2377#true} {2377#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,465 INFO L272 TraceCheckUtils]: 4: Hoare triple {2377#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,465 INFO L290 TraceCheckUtils]: 5: Hoare triple {2377#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2377#true} is VALID [2022-04-27 15:57:32,465 INFO L290 TraceCheckUtils]: 6: Hoare triple {2377#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2377#true} is VALID [2022-04-27 15:57:32,468 INFO L290 TraceCheckUtils]: 7: Hoare triple {2377#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2377#true} is VALID [2022-04-27 15:57:32,468 INFO L290 TraceCheckUtils]: 8: Hoare triple {2377#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2377#true} is VALID [2022-04-27 15:57:32,470 INFO L290 TraceCheckUtils]: 9: Hoare triple {2377#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2377#true} is VALID [2022-04-27 15:57:32,474 INFO L290 TraceCheckUtils]: 10: Hoare triple {2377#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,475 INFO L290 TraceCheckUtils]: 11: Hoare triple {2377#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,475 INFO L290 TraceCheckUtils]: 12: Hoare triple {2423#(<= 1 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,478 INFO L290 TraceCheckUtils]: 13: Hoare triple {2423#(<= 1 main_~j~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,479 INFO L290 TraceCheckUtils]: 14: Hoare triple {2423#(<= 1 main_~j~0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,479 INFO L290 TraceCheckUtils]: 15: Hoare triple {2423#(<= 1 main_~j~0)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,480 INFO L290 TraceCheckUtils]: 16: Hoare triple {2423#(<= 1 main_~j~0)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,480 INFO L290 TraceCheckUtils]: 17: Hoare triple {2423#(<= 1 main_~j~0)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2383#(<= 2 main_~j~0)} is VALID [2022-04-27 15:57:32,481 INFO L290 TraceCheckUtils]: 18: Hoare triple {2383#(<= 2 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2384#(<= 1 main_~i~0)} is VALID [2022-04-27 15:57:32,481 INFO L290 TraceCheckUtils]: 19: Hoare triple {2384#(<= 1 main_~i~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2385#|main_#t~short10|} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 20: Hoare triple {2385#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 21: Hoare triple {2378#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 22: Hoare triple {2378#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 23: Hoare triple {2378#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 24: Hoare triple {2378#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 25: Hoare triple {2378#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 26: Hoare triple {2378#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L272 TraceCheckUtils]: 27: Hoare triple {2378#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 28: Hoare triple {2378#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2378#false} is VALID [2022-04-27 15:57:32,482 INFO L290 TraceCheckUtils]: 29: Hoare triple {2378#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,483 INFO L290 TraceCheckUtils]: 30: Hoare triple {2378#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,483 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:57:32,483 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:57:32,596 INFO L290 TraceCheckUtils]: 30: Hoare triple {2378#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,600 INFO L290 TraceCheckUtils]: 29: Hoare triple {2378#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,600 INFO L290 TraceCheckUtils]: 28: Hoare triple {2378#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2378#false} is VALID [2022-04-27 15:57:32,600 INFO L272 TraceCheckUtils]: 27: Hoare triple {2378#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2378#false} is VALID [2022-04-27 15:57:32,600 INFO L290 TraceCheckUtils]: 26: Hoare triple {2378#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2378#false} is VALID [2022-04-27 15:57:32,600 INFO L290 TraceCheckUtils]: 25: Hoare triple {2378#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2378#false} is VALID [2022-04-27 15:57:32,600 INFO L290 TraceCheckUtils]: 24: Hoare triple {2378#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,601 INFO L290 TraceCheckUtils]: 23: Hoare triple {2378#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2378#false} is VALID [2022-04-27 15:57:32,601 INFO L290 TraceCheckUtils]: 22: Hoare triple {2378#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2378#false} is VALID [2022-04-27 15:57:32,601 INFO L290 TraceCheckUtils]: 21: Hoare triple {2378#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2378#false} is VALID [2022-04-27 15:57:32,604 INFO L290 TraceCheckUtils]: 20: Hoare triple {2385#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2378#false} is VALID [2022-04-27 15:57:32,604 INFO L290 TraceCheckUtils]: 19: Hoare triple {2514#(<= 0 main_~i~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2385#|main_#t~short10|} is VALID [2022-04-27 15:57:32,605 INFO L290 TraceCheckUtils]: 18: Hoare triple {2423#(<= 1 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2514#(<= 0 main_~i~0)} is VALID [2022-04-27 15:57:32,605 INFO L290 TraceCheckUtils]: 17: Hoare triple {2521#(<= 0 main_~j~0)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2423#(<= 1 main_~j~0)} is VALID [2022-04-27 15:57:32,606 INFO L290 TraceCheckUtils]: 16: Hoare triple {2521#(<= 0 main_~j~0)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2521#(<= 0 main_~j~0)} is VALID [2022-04-27 15:57:32,606 INFO L290 TraceCheckUtils]: 15: Hoare triple {2521#(<= 0 main_~j~0)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2521#(<= 0 main_~j~0)} is VALID [2022-04-27 15:57:32,606 INFO L290 TraceCheckUtils]: 14: Hoare triple {2521#(<= 0 main_~j~0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2521#(<= 0 main_~j~0)} is VALID [2022-04-27 15:57:32,606 INFO L290 TraceCheckUtils]: 13: Hoare triple {2521#(<= 0 main_~j~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2521#(<= 0 main_~j~0)} is VALID [2022-04-27 15:57:32,607 INFO L290 TraceCheckUtils]: 12: Hoare triple {2521#(<= 0 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2521#(<= 0 main_~j~0)} is VALID [2022-04-27 15:57:32,607 INFO L290 TraceCheckUtils]: 11: Hoare triple {2377#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2521#(<= 0 main_~j~0)} is VALID [2022-04-27 15:57:32,607 INFO L290 TraceCheckUtils]: 10: Hoare triple {2377#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,607 INFO L290 TraceCheckUtils]: 9: Hoare triple {2377#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2377#true} is VALID [2022-04-27 15:57:32,607 INFO L290 TraceCheckUtils]: 8: Hoare triple {2377#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2377#true} is VALID [2022-04-27 15:57:32,607 INFO L290 TraceCheckUtils]: 7: Hoare triple {2377#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L290 TraceCheckUtils]: 6: Hoare triple {2377#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L290 TraceCheckUtils]: 5: Hoare triple {2377#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L272 TraceCheckUtils]: 4: Hoare triple {2377#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2377#true} {2377#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L290 TraceCheckUtils]: 2: Hoare triple {2377#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L290 TraceCheckUtils]: 1: Hoare triple {2377#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L272 TraceCheckUtils]: 0: Hoare triple {2377#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2377#true} is VALID [2022-04-27 15:57:32,608 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 15:57:32,608 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1494796884] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:57:32,609 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:57:32,609 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 15:57:32,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [313148698] [2022-04-27 15:57:32,609 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:57:32,609 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 15:57:32,610 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:57:32,610 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:32,639 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:32,639 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 15:57:32,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:57:32,639 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 15:57:32,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-04-27 15:57:32,640 INFO L87 Difference]: Start difference. First operand 69 states and 90 transitions. Second operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:33,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:33,106 INFO L93 Difference]: Finished difference Result 101 states and 130 transitions. [2022-04-27 15:57:33,106 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 15:57:33,106 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 15:57:33,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:57:33,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:33,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 78 transitions. [2022-04-27 15:57:33,107 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:33,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 78 transitions. [2022-04-27 15:57:33,108 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 78 transitions. [2022-04-27 15:57:33,168 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:33,169 INFO L225 Difference]: With dead ends: 101 [2022-04-27 15:57:33,170 INFO L226 Difference]: Without dead ends: 101 [2022-04-27 15:57:33,170 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=260, Unknown=0, NotChecked=0, Total=380 [2022-04-27 15:57:33,170 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 97 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 183 mSolverCounterSat, 51 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 97 SdHoareTripleChecker+Valid, 48 SdHoareTripleChecker+Invalid, 234 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 51 IncrementalHoareTripleChecker+Valid, 183 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 15:57:33,170 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [97 Valid, 48 Invalid, 234 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [51 Valid, 183 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 15:57:33,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2022-04-27 15:57:33,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 60. [2022-04-27 15:57:33,173 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:57:33,173 INFO L82 GeneralOperation]: Start isEquivalent. First operand 101 states. Second operand has 60 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 53 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:33,173 INFO L74 IsIncluded]: Start isIncluded. First operand 101 states. Second operand has 60 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 53 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:33,174 INFO L87 Difference]: Start difference. First operand 101 states. Second operand has 60 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 53 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:33,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:33,176 INFO L93 Difference]: Finished difference Result 101 states and 130 transitions. [2022-04-27 15:57:33,176 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 130 transitions. [2022-04-27 15:57:33,176 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:33,176 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:33,176 INFO L74 IsIncluded]: Start isIncluded. First operand has 60 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 53 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 101 states. [2022-04-27 15:57:33,176 INFO L87 Difference]: Start difference. First operand has 60 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 53 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 101 states. [2022-04-27 15:57:33,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:33,178 INFO L93 Difference]: Finished difference Result 101 states and 130 transitions. [2022-04-27 15:57:33,178 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 130 transitions. [2022-04-27 15:57:33,179 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:33,179 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:33,179 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:57:33,179 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:57:33,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 52 states have (on average 1.3076923076923077) internal successors, (68), 53 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:33,180 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 75 transitions. [2022-04-27 15:57:33,180 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 75 transitions. Word has length 31 [2022-04-27 15:57:33,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:57:33,180 INFO L495 AbstractCegarLoop]: Abstraction has 60 states and 75 transitions. [2022-04-27 15:57:33,180 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:33,180 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 75 transitions. [2022-04-27 15:57:33,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-27 15:57:33,181 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:57:33,181 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:57:33,204 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 15:57:33,381 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:33,381 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:57:33,382 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:57:33,382 INFO L85 PathProgramCache]: Analyzing trace with hash 1244986445, now seen corresponding path program 3 times [2022-04-27 15:57:33,382 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:57:33,382 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1545689764] [2022-04-27 15:57:33,382 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:33,382 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:57:33,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:33,477 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:57:33,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:33,480 INFO L290 TraceCheckUtils]: 0: Hoare triple {2970#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2959#true} is VALID [2022-04-27 15:57:33,481 INFO L290 TraceCheckUtils]: 1: Hoare triple {2959#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,481 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2959#true} {2959#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,481 INFO L272 TraceCheckUtils]: 0: Hoare triple {2959#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2970#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:57:33,481 INFO L290 TraceCheckUtils]: 1: Hoare triple {2970#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2959#true} is VALID [2022-04-27 15:57:33,482 INFO L290 TraceCheckUtils]: 2: Hoare triple {2959#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,482 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2959#true} {2959#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,482 INFO L272 TraceCheckUtils]: 4: Hoare triple {2959#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,482 INFO L290 TraceCheckUtils]: 5: Hoare triple {2959#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2964#(= main_~j~0 0)} is VALID [2022-04-27 15:57:33,482 INFO L290 TraceCheckUtils]: 6: Hoare triple {2964#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2964#(= main_~j~0 0)} is VALID [2022-04-27 15:57:33,483 INFO L290 TraceCheckUtils]: 7: Hoare triple {2964#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:33,484 INFO L290 TraceCheckUtils]: 8: Hoare triple {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:33,484 INFO L290 TraceCheckUtils]: 9: Hoare triple {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2966#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} is VALID [2022-04-27 15:57:33,485 INFO L290 TraceCheckUtils]: 10: Hoare triple {2966#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2967#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:33,485 INFO L290 TraceCheckUtils]: 11: Hoare triple {2967#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,486 INFO L290 TraceCheckUtils]: 12: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,486 INFO L290 TraceCheckUtils]: 13: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,487 INFO L290 TraceCheckUtils]: 14: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,487 INFO L290 TraceCheckUtils]: 15: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,487 INFO L290 TraceCheckUtils]: 16: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,488 INFO L290 TraceCheckUtils]: 17: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2969#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 18: Hoare triple {2969#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 19: Hoare triple {2960#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 20: Hoare triple {2960#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 21: Hoare triple {2960#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 22: Hoare triple {2960#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 23: Hoare triple {2960#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 24: Hoare triple {2960#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 25: Hoare triple {2960#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 26: Hoare triple {2960#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L272 TraceCheckUtils]: 27: Hoare triple {2960#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 28: Hoare triple {2960#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 29: Hoare triple {2960#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:33,489 INFO L290 TraceCheckUtils]: 30: Hoare triple {2960#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:33,490 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:57:33,490 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:57:33,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1545689764] [2022-04-27 15:57:33,490 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1545689764] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:57:33,490 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1321158293] [2022-04-27 15:57:33,490 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 15:57:33,490 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:33,490 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:57:33,491 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:57:33,492 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 15:57:33,538 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2022-04-27 15:57:33,538 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 15:57:33,539 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 15:57:33,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:33,546 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:57:33,961 INFO L272 TraceCheckUtils]: 0: Hoare triple {2959#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,962 INFO L290 TraceCheckUtils]: 1: Hoare triple {2959#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2959#true} is VALID [2022-04-27 15:57:33,962 INFO L290 TraceCheckUtils]: 2: Hoare triple {2959#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,962 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2959#true} {2959#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,962 INFO L272 TraceCheckUtils]: 4: Hoare triple {2959#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:33,962 INFO L290 TraceCheckUtils]: 5: Hoare triple {2959#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2964#(= main_~j~0 0)} is VALID [2022-04-27 15:57:33,962 INFO L290 TraceCheckUtils]: 6: Hoare triple {2964#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2964#(= main_~j~0 0)} is VALID [2022-04-27 15:57:33,963 INFO L290 TraceCheckUtils]: 7: Hoare triple {2964#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:33,963 INFO L290 TraceCheckUtils]: 8: Hoare triple {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:33,964 INFO L290 TraceCheckUtils]: 9: Hoare triple {2965#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3001#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 15:57:33,965 INFO L290 TraceCheckUtils]: 10: Hoare triple {3001#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2967#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:33,965 INFO L290 TraceCheckUtils]: 11: Hoare triple {2967#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,965 INFO L290 TraceCheckUtils]: 12: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,966 INFO L290 TraceCheckUtils]: 13: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,966 INFO L290 TraceCheckUtils]: 14: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,967 INFO L290 TraceCheckUtils]: 15: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,967 INFO L290 TraceCheckUtils]: 16: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,967 INFO L290 TraceCheckUtils]: 17: Hoare triple {2968#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3026#(and (= (+ (- 2) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:33,968 INFO L290 TraceCheckUtils]: 18: Hoare triple {3026#(and (= (+ (- 2) main_~j~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2960#false} is VALID [2022-04-27 15:57:33,968 INFO L290 TraceCheckUtils]: 19: Hoare triple {2960#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2960#false} is VALID [2022-04-27 15:57:33,968 INFO L290 TraceCheckUtils]: 20: Hoare triple {2960#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2960#false} is VALID [2022-04-27 15:57:33,968 INFO L290 TraceCheckUtils]: 21: Hoare triple {2960#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2960#false} is VALID [2022-04-27 15:57:33,968 INFO L290 TraceCheckUtils]: 22: Hoare triple {2960#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2960#false} is VALID [2022-04-27 15:57:33,968 INFO L290 TraceCheckUtils]: 23: Hoare triple {2960#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L290 TraceCheckUtils]: 24: Hoare triple {2960#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L290 TraceCheckUtils]: 25: Hoare triple {2960#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L290 TraceCheckUtils]: 26: Hoare triple {2960#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L272 TraceCheckUtils]: 27: Hoare triple {2960#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L290 TraceCheckUtils]: 28: Hoare triple {2960#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L290 TraceCheckUtils]: 29: Hoare triple {2960#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L290 TraceCheckUtils]: 30: Hoare triple {2960#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:33,969 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:57:33,969 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:57:34,402 INFO L290 TraceCheckUtils]: 30: Hoare triple {2960#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:34,402 INFO L290 TraceCheckUtils]: 29: Hoare triple {2960#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:34,402 INFO L290 TraceCheckUtils]: 28: Hoare triple {2960#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2960#false} is VALID [2022-04-27 15:57:34,402 INFO L272 TraceCheckUtils]: 27: Hoare triple {2960#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 26: Hoare triple {2960#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 25: Hoare triple {2960#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 24: Hoare triple {2960#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 23: Hoare triple {2960#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 22: Hoare triple {2960#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 21: Hoare triple {2960#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 20: Hoare triple {2960#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2960#false} is VALID [2022-04-27 15:57:34,403 INFO L290 TraceCheckUtils]: 19: Hoare triple {2960#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2960#false} is VALID [2022-04-27 15:57:34,405 INFO L290 TraceCheckUtils]: 18: Hoare triple {2969#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2960#false} is VALID [2022-04-27 15:57:34,406 INFO L290 TraceCheckUtils]: 17: Hoare triple {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2969#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:34,406 INFO L290 TraceCheckUtils]: 16: Hoare triple {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 15:57:34,408 INFO L290 TraceCheckUtils]: 15: Hoare triple {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 15:57:34,408 INFO L290 TraceCheckUtils]: 14: Hoare triple {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 15:57:34,408 INFO L290 TraceCheckUtils]: 13: Hoare triple {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 15:57:34,409 INFO L290 TraceCheckUtils]: 12: Hoare triple {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 15:57:34,409 INFO L290 TraceCheckUtils]: 11: Hoare triple {2967#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3105#(<= (+ main_~SIZE~0 (* (div (+ main_~j~0 1) 4294967296) 4294967296)) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 15:57:34,410 INFO L290 TraceCheckUtils]: 10: Hoare triple {3127#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2967#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:34,411 INFO L290 TraceCheckUtils]: 9: Hoare triple {3131#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3127#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} is VALID [2022-04-27 15:57:34,411 INFO L290 TraceCheckUtils]: 8: Hoare triple {3131#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3131#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-27 15:57:34,412 INFO L290 TraceCheckUtils]: 7: Hoare triple {3138#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3131#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-27 15:57:34,412 INFO L290 TraceCheckUtils]: 6: Hoare triple {3138#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3138#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-27 15:57:34,412 INFO L290 TraceCheckUtils]: 5: Hoare triple {2959#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3138#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-27 15:57:34,413 INFO L272 TraceCheckUtils]: 4: Hoare triple {2959#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:34,413 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2959#true} {2959#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:34,413 INFO L290 TraceCheckUtils]: 2: Hoare triple {2959#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:34,413 INFO L290 TraceCheckUtils]: 1: Hoare triple {2959#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2959#true} is VALID [2022-04-27 15:57:34,413 INFO L272 TraceCheckUtils]: 0: Hoare triple {2959#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2959#true} is VALID [2022-04-27 15:57:34,413 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:57:34,413 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1321158293] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:57:34,413 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:57:34,413 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 15 [2022-04-27 15:57:34,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117356011] [2022-04-27 15:57:34,413 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:57:34,414 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 15:57:34,414 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:57:34,414 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:34,449 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:34,449 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 15 states [2022-04-27 15:57:34,449 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:57:34,449 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2022-04-27 15:57:34,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=161, Unknown=0, NotChecked=0, Total=210 [2022-04-27 15:57:34,450 INFO L87 Difference]: Start difference. First operand 60 states and 75 transitions. Second operand has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:35,123 INFO L93 Difference]: Finished difference Result 126 states and 168 transitions. [2022-04-27 15:57:35,123 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2022-04-27 15:57:35,124 INFO L78 Accepts]: Start accepts. Automaton has has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 15:57:35,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:57:35,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 71 transitions. [2022-04-27 15:57:35,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,126 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9 states to 9 states and 71 transitions. [2022-04-27 15:57:35,126 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 9 states and 71 transitions. [2022-04-27 15:57:35,195 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:35,197 INFO L225 Difference]: With dead ends: 126 [2022-04-27 15:57:35,197 INFO L226 Difference]: Without dead ends: 126 [2022-04-27 15:57:35,197 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 54 SyntacticMatches, 4 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=323, Unknown=0, NotChecked=0, Total=420 [2022-04-27 15:57:35,197 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 130 mSDsluCounter, 37 mSDsCounter, 0 mSdLazyCounter, 255 mSolverCounterSat, 35 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 130 SdHoareTripleChecker+Valid, 65 SdHoareTripleChecker+Invalid, 290 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 35 IncrementalHoareTripleChecker+Valid, 255 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 15:57:35,198 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [130 Valid, 65 Invalid, 290 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [35 Valid, 255 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 15:57:35,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2022-04-27 15:57:35,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 85. [2022-04-27 15:57:35,201 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:57:35,201 INFO L82 GeneralOperation]: Start isEquivalent. First operand 126 states. Second operand has 85 states, 77 states have (on average 1.3376623376623376) internal successors, (103), 78 states have internal predecessors, (103), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,201 INFO L74 IsIncluded]: Start isIncluded. First operand 126 states. Second operand has 85 states, 77 states have (on average 1.3376623376623376) internal successors, (103), 78 states have internal predecessors, (103), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,201 INFO L87 Difference]: Start difference. First operand 126 states. Second operand has 85 states, 77 states have (on average 1.3376623376623376) internal successors, (103), 78 states have internal predecessors, (103), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,204 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:35,204 INFO L93 Difference]: Finished difference Result 126 states and 168 transitions. [2022-04-27 15:57:35,204 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 168 transitions. [2022-04-27 15:57:35,204 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:35,204 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:35,204 INFO L74 IsIncluded]: Start isIncluded. First operand has 85 states, 77 states have (on average 1.3376623376623376) internal successors, (103), 78 states have internal predecessors, (103), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 126 states. [2022-04-27 15:57:35,204 INFO L87 Difference]: Start difference. First operand has 85 states, 77 states have (on average 1.3376623376623376) internal successors, (103), 78 states have internal predecessors, (103), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 126 states. [2022-04-27 15:57:35,207 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:35,207 INFO L93 Difference]: Finished difference Result 126 states and 168 transitions. [2022-04-27 15:57:35,207 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 168 transitions. [2022-04-27 15:57:35,207 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:35,207 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:35,207 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:57:35,207 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:57:35,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 85 states, 77 states have (on average 1.3376623376623376) internal successors, (103), 78 states have internal predecessors, (103), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 110 transitions. [2022-04-27 15:57:35,209 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 110 transitions. Word has length 31 [2022-04-27 15:57:35,209 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:57:35,209 INFO L495 AbstractCegarLoop]: Abstraction has 85 states and 110 transitions. [2022-04-27 15:57:35,209 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 15 states, 15 states have (on average 3.0) internal successors, (45), 14 states have internal predecessors, (45), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,209 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 110 transitions. [2022-04-27 15:57:35,209 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-27 15:57:35,209 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:57:35,209 INFO L195 NwaCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:57:35,225 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2022-04-27 15:57:35,424 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:35,425 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:57:35,425 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:57:35,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1093737958, now seen corresponding path program 2 times [2022-04-27 15:57:35,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:57:35,425 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [56727414] [2022-04-27 15:57:35,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:35,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:57:35,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,449 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:57:35,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,451 INFO L290 TraceCheckUtils]: 0: Hoare triple {3643#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L290 TraceCheckUtils]: 1: Hoare triple {3637#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3637#true} {3637#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L272 TraceCheckUtils]: 0: Hoare triple {3637#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3643#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:57:35,452 INFO L290 TraceCheckUtils]: 1: Hoare triple {3643#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L290 TraceCheckUtils]: 2: Hoare triple {3637#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3637#true} {3637#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L272 TraceCheckUtils]: 4: Hoare triple {3637#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L290 TraceCheckUtils]: 5: Hoare triple {3637#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3637#true} is VALID [2022-04-27 15:57:35,452 INFO L290 TraceCheckUtils]: 6: Hoare triple {3637#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 7: Hoare triple {3637#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 8: Hoare triple {3637#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 9: Hoare triple {3637#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 10: Hoare triple {3637#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 11: Hoare triple {3637#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 12: Hoare triple {3637#true} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 13: Hoare triple {3637#true} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 14: Hoare triple {3637#true} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 15: Hoare triple {3637#true} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 16: Hoare triple {3637#true} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3637#true} is VALID [2022-04-27 15:57:35,453 INFO L290 TraceCheckUtils]: 17: Hoare triple {3637#true} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3642#(not |main_#t~short10|)} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 18: Hoare triple {3642#(not |main_#t~short10|)} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 19: Hoare triple {3638#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 20: Hoare triple {3638#false} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 21: Hoare triple {3638#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 22: Hoare triple {3638#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 23: Hoare triple {3638#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 24: Hoare triple {3638#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 25: Hoare triple {3638#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 26: Hoare triple {3638#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L272 TraceCheckUtils]: 27: Hoare triple {3638#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3638#false} is VALID [2022-04-27 15:57:35,454 INFO L290 TraceCheckUtils]: 28: Hoare triple {3638#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3638#false} is VALID [2022-04-27 15:57:35,455 INFO L290 TraceCheckUtils]: 29: Hoare triple {3638#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3638#false} is VALID [2022-04-27 15:57:35,455 INFO L290 TraceCheckUtils]: 30: Hoare triple {3638#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3638#false} is VALID [2022-04-27 15:57:35,455 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2022-04-27 15:57:35,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:57:35,455 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [56727414] [2022-04-27 15:57:35,455 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [56727414] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 15:57:35,455 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 15:57:35,455 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 15:57:35,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1215189553] [2022-04-27 15:57:35,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 15:57:35,456 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 15:57:35,456 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:57:35,456 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,471 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 28 edges. 28 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:35,471 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 15:57:35,471 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:57:35,471 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 15:57:35,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 15:57:35,472 INFO L87 Difference]: Start difference. First operand 85 states and 110 transitions. Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:35,538 INFO L93 Difference]: Finished difference Result 72 states and 87 transitions. [2022-04-27 15:57:35,538 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 15:57:35,538 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 15:57:35,538 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:57:35,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,538 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 32 transitions. [2022-04-27 15:57:35,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 32 transitions. [2022-04-27 15:57:35,539 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 32 transitions. [2022-04-27 15:57:35,565 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:35,566 INFO L225 Difference]: With dead ends: 72 [2022-04-27 15:57:35,566 INFO L226 Difference]: Without dead ends: 72 [2022-04-27 15:57:35,566 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 15:57:35,567 INFO L413 NwaCegarLoop]: 29 mSDtfsCounter, 23 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 28 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 36 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 28 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 15:57:35,567 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 36 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 28 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 15:57:35,567 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2022-04-27 15:57:35,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 64. [2022-04-27 15:57:35,569 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:57:35,569 INFO L82 GeneralOperation]: Start isEquivalent. First operand 72 states. Second operand has 64 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 57 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,570 INFO L74 IsIncluded]: Start isIncluded. First operand 72 states. Second operand has 64 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 57 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,570 INFO L87 Difference]: Start difference. First operand 72 states. Second operand has 64 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 57 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:35,571 INFO L93 Difference]: Finished difference Result 72 states and 87 transitions. [2022-04-27 15:57:35,571 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 87 transitions. [2022-04-27 15:57:35,571 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:35,571 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:35,571 INFO L74 IsIncluded]: Start isIncluded. First operand has 64 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 57 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 72 states. [2022-04-27 15:57:35,571 INFO L87 Difference]: Start difference. First operand has 64 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 57 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 72 states. [2022-04-27 15:57:35,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:35,572 INFO L93 Difference]: Finished difference Result 72 states and 87 transitions. [2022-04-27 15:57:35,572 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 87 transitions. [2022-04-27 15:57:35,572 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:35,572 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:35,572 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:57:35,573 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:57:35,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 56 states have (on average 1.2142857142857142) internal successors, (68), 57 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:35,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 75 transitions. [2022-04-27 15:57:35,573 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 75 transitions. Word has length 31 [2022-04-27 15:57:35,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:57:35,574 INFO L495 AbstractCegarLoop]: Abstraction has 64 states and 75 transitions. [2022-04-27 15:57:35,574 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 6.0) internal successors, (24), 3 states have internal predecessors, (24), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:35,574 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 75 transitions. [2022-04-27 15:57:35,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-27 15:57:35,574 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:57:35,574 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:57:35,574 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9 [2022-04-27 15:57:35,574 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:57:35,574 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:57:35,575 INFO L85 PathProgramCache]: Analyzing trace with hash 567979469, now seen corresponding path program 1 times [2022-04-27 15:57:35,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:57:35,575 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019845503] [2022-04-27 15:57:35,575 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:35,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:57:35,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,670 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:57:35,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,673 INFO L290 TraceCheckUtils]: 0: Hoare triple {3943#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3928#true} is VALID [2022-04-27 15:57:35,673 INFO L290 TraceCheckUtils]: 1: Hoare triple {3928#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,673 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3928#true} {3928#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,673 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-04-27 15:57:35,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,675 INFO L290 TraceCheckUtils]: 0: Hoare triple {3928#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3928#true} is VALID [2022-04-27 15:57:35,676 INFO L290 TraceCheckUtils]: 1: Hoare triple {3928#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,676 INFO L290 TraceCheckUtils]: 2: Hoare triple {3928#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,676 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3928#true} {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:35,677 INFO L272 TraceCheckUtils]: 0: Hoare triple {3928#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3943#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:57:35,677 INFO L290 TraceCheckUtils]: 1: Hoare triple {3943#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3928#true} is VALID [2022-04-27 15:57:35,677 INFO L290 TraceCheckUtils]: 2: Hoare triple {3928#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,677 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3928#true} {3928#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,677 INFO L272 TraceCheckUtils]: 4: Hoare triple {3928#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,677 INFO L290 TraceCheckUtils]: 5: Hoare triple {3928#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3933#(= main_~j~0 0)} is VALID [2022-04-27 15:57:35,677 INFO L290 TraceCheckUtils]: 6: Hoare triple {3933#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3933#(= main_~j~0 0)} is VALID [2022-04-27 15:57:35,678 INFO L290 TraceCheckUtils]: 7: Hoare triple {3933#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:35,678 INFO L290 TraceCheckUtils]: 8: Hoare triple {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:35,679 INFO L290 TraceCheckUtils]: 9: Hoare triple {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3935#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} is VALID [2022-04-27 15:57:35,679 INFO L290 TraceCheckUtils]: 10: Hoare triple {3935#(and (<= main_~j~0 2) (not (<= (+ (div main_~j~0 4294967296) 1) 0)))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,680 INFO L290 TraceCheckUtils]: 11: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,680 INFO L290 TraceCheckUtils]: 12: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,680 INFO L290 TraceCheckUtils]: 13: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,681 INFO L290 TraceCheckUtils]: 14: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,681 INFO L290 TraceCheckUtils]: 15: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,681 INFO L290 TraceCheckUtils]: 16: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,682 INFO L290 TraceCheckUtils]: 17: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,682 INFO L290 TraceCheckUtils]: 18: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:35,682 INFO L290 TraceCheckUtils]: 19: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:35,683 INFO L290 TraceCheckUtils]: 20: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:35,683 INFO L272 TraceCheckUtils]: 21: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3928#true} is VALID [2022-04-27 15:57:35,683 INFO L290 TraceCheckUtils]: 22: Hoare triple {3928#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3928#true} is VALID [2022-04-27 15:57:35,683 INFO L290 TraceCheckUtils]: 23: Hoare triple {3928#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,683 INFO L290 TraceCheckUtils]: 24: Hoare triple {3928#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:35,683 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3928#true} {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:35,684 INFO L290 TraceCheckUtils]: 26: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [119] L29-1-->L28-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:35,684 INFO L290 TraceCheckUtils]: 27: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [121] L28-2-->L28-3: Formula: (= (+ v_main_~k~0_6 1) v_main_~k~0_5) InVars {main_~k~0=v_main_~k~0_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3942#(and (<= (div main_~k~0 4294967296) 0) (<= main_~SIZE~0 (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:35,685 INFO L290 TraceCheckUtils]: 28: Hoare triple {3942#(and (<= (div main_~k~0 4294967296) 0) (<= main_~SIZE~0 (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3929#false} is VALID [2022-04-27 15:57:35,685 INFO L272 TraceCheckUtils]: 29: Hoare triple {3929#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3929#false} is VALID [2022-04-27 15:57:35,685 INFO L290 TraceCheckUtils]: 30: Hoare triple {3929#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3929#false} is VALID [2022-04-27 15:57:35,685 INFO L290 TraceCheckUtils]: 31: Hoare triple {3929#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3929#false} is VALID [2022-04-27 15:57:35,685 INFO L290 TraceCheckUtils]: 32: Hoare triple {3929#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3929#false} is VALID [2022-04-27 15:57:35,685 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:57:35,685 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:57:35,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019845503] [2022-04-27 15:57:35,686 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019845503] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:57:35,686 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1155445737] [2022-04-27 15:57:35,686 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:35,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:35,686 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:57:35,687 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:57:35,688 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 15:57:35,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,726 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 15:57:35,732 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:35,733 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:57:36,288 INFO L272 TraceCheckUtils]: 0: Hoare triple {3928#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,288 INFO L290 TraceCheckUtils]: 1: Hoare triple {3928#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3928#true} is VALID [2022-04-27 15:57:36,288 INFO L290 TraceCheckUtils]: 2: Hoare triple {3928#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,288 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3928#true} {3928#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,288 INFO L272 TraceCheckUtils]: 4: Hoare triple {3928#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,289 INFO L290 TraceCheckUtils]: 5: Hoare triple {3928#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3933#(= main_~j~0 0)} is VALID [2022-04-27 15:57:36,289 INFO L290 TraceCheckUtils]: 6: Hoare triple {3933#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3933#(= main_~j~0 0)} is VALID [2022-04-27 15:57:36,289 INFO L290 TraceCheckUtils]: 7: Hoare triple {3933#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:36,290 INFO L290 TraceCheckUtils]: 8: Hoare triple {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:36,290 INFO L290 TraceCheckUtils]: 9: Hoare triple {3934#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3974#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 15:57:36,291 INFO L290 TraceCheckUtils]: 10: Hoare triple {3974#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,291 INFO L290 TraceCheckUtils]: 11: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,292 INFO L290 TraceCheckUtils]: 12: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,292 INFO L290 TraceCheckUtils]: 13: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,292 INFO L290 TraceCheckUtils]: 14: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,292 INFO L290 TraceCheckUtils]: 15: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,293 INFO L290 TraceCheckUtils]: 16: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,293 INFO L290 TraceCheckUtils]: 17: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,293 INFO L290 TraceCheckUtils]: 18: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,294 INFO L290 TraceCheckUtils]: 19: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:36,294 INFO L290 TraceCheckUtils]: 20: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:36,294 INFO L272 TraceCheckUtils]: 21: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3928#true} is VALID [2022-04-27 15:57:36,294 INFO L290 TraceCheckUtils]: 22: Hoare triple {3928#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3928#true} is VALID [2022-04-27 15:57:36,294 INFO L290 TraceCheckUtils]: 23: Hoare triple {3928#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,294 INFO L290 TraceCheckUtils]: 24: Hoare triple {3928#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,295 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3928#true} {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:36,295 INFO L290 TraceCheckUtils]: 26: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [119] L29-1-->L28-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:36,296 INFO L290 TraceCheckUtils]: 27: Hoare triple {3937#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [121] L28-2-->L28-3: Formula: (= (+ v_main_~k~0_6 1) v_main_~k~0_5) InVars {main_~k~0=v_main_~k~0_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {4029#(and (= main_~k~0 2) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} is VALID [2022-04-27 15:57:36,296 INFO L290 TraceCheckUtils]: 28: Hoare triple {4029#(and (= main_~k~0 2) (<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3929#false} is VALID [2022-04-27 15:57:36,296 INFO L272 TraceCheckUtils]: 29: Hoare triple {3929#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3929#false} is VALID [2022-04-27 15:57:36,296 INFO L290 TraceCheckUtils]: 30: Hoare triple {3929#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3929#false} is VALID [2022-04-27 15:57:36,296 INFO L290 TraceCheckUtils]: 31: Hoare triple {3929#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3929#false} is VALID [2022-04-27 15:57:36,297 INFO L290 TraceCheckUtils]: 32: Hoare triple {3929#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3929#false} is VALID [2022-04-27 15:57:36,297 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:57:36,297 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:57:36,758 INFO L290 TraceCheckUtils]: 32: Hoare triple {3929#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3929#false} is VALID [2022-04-27 15:57:36,758 INFO L290 TraceCheckUtils]: 31: Hoare triple {3929#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3929#false} is VALID [2022-04-27 15:57:36,758 INFO L290 TraceCheckUtils]: 30: Hoare triple {3929#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3929#false} is VALID [2022-04-27 15:57:36,758 INFO L272 TraceCheckUtils]: 29: Hoare triple {3929#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3929#false} is VALID [2022-04-27 15:57:36,759 INFO L290 TraceCheckUtils]: 28: Hoare triple {4057#(not (< (mod main_~k~0 4294967296) (mod main_~SIZE~0 4294967296)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3929#false} is VALID [2022-04-27 15:57:36,759 INFO L290 TraceCheckUtils]: 27: Hoare triple {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [121] L28-2-->L28-3: Formula: (= (+ v_main_~k~0_6 1) v_main_~k~0_5) InVars {main_~k~0=v_main_~k~0_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {4057#(not (< (mod main_~k~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 15:57:36,760 INFO L290 TraceCheckUtils]: 26: Hoare triple {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [119] L29-1-->L28-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 15:57:36,760 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3928#true} {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 15:57:36,760 INFO L290 TraceCheckUtils]: 24: Hoare triple {3928#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,760 INFO L290 TraceCheckUtils]: 23: Hoare triple {3928#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,761 INFO L290 TraceCheckUtils]: 22: Hoare triple {3928#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3928#true} is VALID [2022-04-27 15:57:36,761 INFO L272 TraceCheckUtils]: 21: Hoare triple {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3928#true} is VALID [2022-04-27 15:57:36,761 INFO L290 TraceCheckUtils]: 20: Hoare triple {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 15:57:36,761 INFO L290 TraceCheckUtils]: 19: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4061#(not (< (mod (+ main_~k~0 1) 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 15:57:36,762 INFO L290 TraceCheckUtils]: 18: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,762 INFO L290 TraceCheckUtils]: 17: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,763 INFO L290 TraceCheckUtils]: 16: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,763 INFO L290 TraceCheckUtils]: 15: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,768 INFO L290 TraceCheckUtils]: 14: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,768 INFO L290 TraceCheckUtils]: 13: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,768 INFO L290 TraceCheckUtils]: 12: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,769 INFO L290 TraceCheckUtils]: 11: Hoare triple {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,769 INFO L290 TraceCheckUtils]: 10: Hoare triple {4113#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3936#(<= main_~SIZE~0 (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 15:57:36,771 INFO L290 TraceCheckUtils]: 9: Hoare triple {4117#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4113#(<= 0 (div (+ 2 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} is VALID [2022-04-27 15:57:36,771 INFO L290 TraceCheckUtils]: 8: Hoare triple {4117#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4117#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-27 15:57:36,772 INFO L290 TraceCheckUtils]: 7: Hoare triple {4124#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4117#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 2) 4294967296))} is VALID [2022-04-27 15:57:36,772 INFO L290 TraceCheckUtils]: 6: Hoare triple {4124#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4124#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-27 15:57:36,773 INFO L290 TraceCheckUtils]: 5: Hoare triple {3928#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4124#(<= 0 (div (+ 2 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-27 15:57:36,773 INFO L272 TraceCheckUtils]: 4: Hoare triple {3928#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,773 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3928#true} {3928#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,773 INFO L290 TraceCheckUtils]: 2: Hoare triple {3928#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,773 INFO L290 TraceCheckUtils]: 1: Hoare triple {3928#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3928#true} is VALID [2022-04-27 15:57:36,773 INFO L272 TraceCheckUtils]: 0: Hoare triple {3928#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3928#true} is VALID [2022-04-27 15:57:36,773 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:57:36,773 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1155445737] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:57:36,774 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:57:36,774 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 16 [2022-04-27 15:57:36,774 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [529856210] [2022-04-27 15:57:36,774 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:57:36,774 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-27 15:57:36,774 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:57:36,775 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:36,813 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 52 edges. 52 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:36,813 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 15:57:36,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:57:36,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 15:57:36,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=194, Unknown=0, NotChecked=0, Total=240 [2022-04-27 15:57:36,814 INFO L87 Difference]: Start difference. First operand 64 states and 75 transitions. Second operand has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:37,652 INFO L93 Difference]: Finished difference Result 88 states and 103 transitions. [2022-04-27 15:57:37,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 15:57:37,652 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-27 15:57:37,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:57:37,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 71 transitions. [2022-04-27 15:57:37,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 71 transitions. [2022-04-27 15:57:37,654 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 71 transitions. [2022-04-27 15:57:37,714 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:37,715 INFO L225 Difference]: With dead ends: 88 [2022-04-27 15:57:37,715 INFO L226 Difference]: Without dead ends: 71 [2022-04-27 15:57:37,715 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 59 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 75 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=108, Invalid=398, Unknown=0, NotChecked=0, Total=506 [2022-04-27 15:57:37,715 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 89 mSDsluCounter, 47 mSDsCounter, 0 mSdLazyCounter, 293 mSolverCounterSat, 24 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 90 SdHoareTripleChecker+Valid, 74 SdHoareTripleChecker+Invalid, 317 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 24 IncrementalHoareTripleChecker+Valid, 293 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 15:57:37,716 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [90 Valid, 74 Invalid, 317 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [24 Valid, 293 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 15:57:37,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2022-04-27 15:57:37,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 57. [2022-04-27 15:57:37,718 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:57:37,718 INFO L82 GeneralOperation]: Start isEquivalent. First operand 71 states. Second operand has 57 states, 49 states have (on average 1.183673469387755) internal successors, (58), 50 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,718 INFO L74 IsIncluded]: Start isIncluded. First operand 71 states. Second operand has 57 states, 49 states have (on average 1.183673469387755) internal successors, (58), 50 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,718 INFO L87 Difference]: Start difference. First operand 71 states. Second operand has 57 states, 49 states have (on average 1.183673469387755) internal successors, (58), 50 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:37,720 INFO L93 Difference]: Finished difference Result 71 states and 82 transitions. [2022-04-27 15:57:37,720 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 82 transitions. [2022-04-27 15:57:37,720 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:37,720 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:37,720 INFO L74 IsIncluded]: Start isIncluded. First operand has 57 states, 49 states have (on average 1.183673469387755) internal successors, (58), 50 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 71 states. [2022-04-27 15:57:37,720 INFO L87 Difference]: Start difference. First operand has 57 states, 49 states have (on average 1.183673469387755) internal successors, (58), 50 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 71 states. [2022-04-27 15:57:37,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:57:37,721 INFO L93 Difference]: Finished difference Result 71 states and 82 transitions. [2022-04-27 15:57:37,721 INFO L276 IsEmpty]: Start isEmpty. Operand 71 states and 82 transitions. [2022-04-27 15:57:37,721 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:57:37,721 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:57:37,721 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:57:37,721 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:57:37,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 49 states have (on average 1.183673469387755) internal successors, (58), 50 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 65 transitions. [2022-04-27 15:57:37,722 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 65 transitions. Word has length 33 [2022-04-27 15:57:37,722 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:57:37,722 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 65 transitions. [2022-04-27 15:57:37,723 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.6875) internal successors, (43), 15 states have internal predecessors, (43), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:57:37,723 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 65 transitions. [2022-04-27 15:57:37,723 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-27 15:57:37,726 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:57:37,726 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:57:37,760 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-27 15:57:37,926 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:37,927 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:57:37,927 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:57:37,927 INFO L85 PathProgramCache]: Analyzing trace with hash -1701261365, now seen corresponding path program 4 times [2022-04-27 15:57:37,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:57:37,927 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332843742] [2022-04-27 15:57:37,927 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:57:37,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:57:37,976 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:38,396 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:57:38,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:38,402 INFO L290 TraceCheckUtils]: 0: Hoare triple {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4449#true} is VALID [2022-04-27 15:57:38,403 INFO L290 TraceCheckUtils]: 1: Hoare triple {4449#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:38,403 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4449#true} {4449#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:38,403 INFO L272 TraceCheckUtils]: 0: Hoare triple {4449#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:57:38,403 INFO L290 TraceCheckUtils]: 1: Hoare triple {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4449#true} is VALID [2022-04-27 15:57:38,403 INFO L290 TraceCheckUtils]: 2: Hoare triple {4449#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:38,403 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4449#true} {4449#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:38,403 INFO L272 TraceCheckUtils]: 4: Hoare triple {4449#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:38,404 INFO L290 TraceCheckUtils]: 5: Hoare triple {4449#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4454#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:57:38,405 INFO L290 TraceCheckUtils]: 6: Hoare triple {4454#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4454#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:57:38,405 INFO L290 TraceCheckUtils]: 7: Hoare triple {4454#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:38,406 INFO L290 TraceCheckUtils]: 8: Hoare triple {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:38,406 INFO L290 TraceCheckUtils]: 9: Hoare triple {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:38,406 INFO L290 TraceCheckUtils]: 10: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:38,407 INFO L290 TraceCheckUtils]: 11: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:38,407 INFO L290 TraceCheckUtils]: 12: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:38,407 INFO L290 TraceCheckUtils]: 13: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:38,408 INFO L290 TraceCheckUtils]: 14: Hoare triple {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4457#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 15:57:38,409 INFO L290 TraceCheckUtils]: 15: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4458#(and (= |main_~#v~0.offset| 0) (or (and (= main_~j~0 1) (= 0 (* main_~i~0 4))) (not |main_#t~short10|)))} is VALID [2022-04-27 15:57:38,409 INFO L290 TraceCheckUtils]: 16: Hoare triple {4458#(and (= |main_~#v~0.offset| 0) (or (and (= main_~j~0 1) (= 0 (* main_~i~0 4))) (not |main_#t~short10|)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4459#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:57:38,410 INFO L290 TraceCheckUtils]: 17: Hoare triple {4459#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|) (= 0 (* main_~i~0 4)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4460#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:57:38,410 INFO L290 TraceCheckUtils]: 18: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 0 (* main_~i~0 4)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4461#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,411 INFO L290 TraceCheckUtils]: 19: Hoare triple {4461#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4462#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,412 INFO L290 TraceCheckUtils]: 20: Hoare triple {4462#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,412 INFO L290 TraceCheckUtils]: 21: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,413 INFO L290 TraceCheckUtils]: 22: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,413 INFO L290 TraceCheckUtils]: 23: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,414 INFO L290 TraceCheckUtils]: 24: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,415 INFO L290 TraceCheckUtils]: 25: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,415 INFO L290 TraceCheckUtils]: 26: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:38,416 INFO L290 TraceCheckUtils]: 27: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:57:38,416 INFO L290 TraceCheckUtils]: 28: Hoare triple {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:57:38,417 INFO L272 TraceCheckUtils]: 29: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4467#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 15:57:38,417 INFO L290 TraceCheckUtils]: 30: Hoare triple {4467#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4468#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 15:57:38,417 INFO L290 TraceCheckUtils]: 31: Hoare triple {4468#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4450#false} is VALID [2022-04-27 15:57:38,417 INFO L290 TraceCheckUtils]: 32: Hoare triple {4450#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4450#false} is VALID [2022-04-27 15:57:38,418 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:57:38,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:57:38,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332843742] [2022-04-27 15:57:38,418 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332843742] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:57:38,418 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [933457155] [2022-04-27 15:57:38,418 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 15:57:38,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:57:38,418 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:57:38,419 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:57:38,420 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 15:57:38,465 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 15:57:38,465 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 15:57:38,466 INFO L263 TraceCheckSpWp]: Trace formula consists of 140 conjuncts, 28 conjunts are in the unsatisfiable core [2022-04-27 15:57:38,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:57:38,478 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:57:38,743 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 15:57:38,744 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2022-04-27 15:57:38,908 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 15:57:38,909 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 15:57:38,909 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 15:57:38,911 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 15:57:38,911 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 27 treesize of output 29 [2022-04-27 15:57:38,978 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 15:57:38,978 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 15:57:39,051 INFO L272 TraceCheckUtils]: 0: Hoare triple {4449#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:39,051 INFO L290 TraceCheckUtils]: 1: Hoare triple {4449#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4449#true} is VALID [2022-04-27 15:57:39,051 INFO L290 TraceCheckUtils]: 2: Hoare triple {4449#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:39,051 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4449#true} {4449#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:39,052 INFO L272 TraceCheckUtils]: 4: Hoare triple {4449#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:39,052 INFO L290 TraceCheckUtils]: 5: Hoare triple {4449#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,052 INFO L290 TraceCheckUtils]: 6: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,052 INFO L290 TraceCheckUtils]: 7: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,053 INFO L290 TraceCheckUtils]: 8: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,053 INFO L290 TraceCheckUtils]: 9: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,053 INFO L290 TraceCheckUtils]: 10: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,054 INFO L290 TraceCheckUtils]: 11: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,054 INFO L290 TraceCheckUtils]: 12: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4456#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:57:39,054 INFO L290 TraceCheckUtils]: 13: Hoare triple {4456#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:57:39,055 INFO L290 TraceCheckUtils]: 14: Hoare triple {4455#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4457#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 15:57:39,056 INFO L290 TraceCheckUtils]: 15: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4518#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 15:57:39,056 INFO L290 TraceCheckUtils]: 16: Hoare triple {4518#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4459#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:57:39,057 INFO L290 TraceCheckUtils]: 17: Hoare triple {4459#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|) (= 0 (* main_~i~0 4)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4460#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:57:39,058 INFO L290 TraceCheckUtils]: 18: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 0 (* main_~i~0 4)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4461#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,058 INFO L290 TraceCheckUtils]: 19: Hoare triple {4461#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4531#(and (= |main_~#v~0.offset| 0) (= main_~j~0 2) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,058 INFO L290 TraceCheckUtils]: 20: Hoare triple {4531#(and (= |main_~#v~0.offset| 0) (= main_~j~0 2) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4535#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,059 INFO L290 TraceCheckUtils]: 21: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4539#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) |main_#t~short10| (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,059 INFO L290 TraceCheckUtils]: 22: Hoare triple {4539#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) |main_#t~short10| (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4535#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,060 INFO L290 TraceCheckUtils]: 23: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4535#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,061 INFO L290 TraceCheckUtils]: 24: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (= 2 (+ main_~i~0 1)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,061 INFO L290 TraceCheckUtils]: 25: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,061 INFO L290 TraceCheckUtils]: 26: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:39,062 INFO L290 TraceCheckUtils]: 27: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:57:39,062 INFO L290 TraceCheckUtils]: 28: Hoare triple {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:57:39,063 INFO L272 TraceCheckUtils]: 29: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4564#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:57:39,063 INFO L290 TraceCheckUtils]: 30: Hoare triple {4564#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4568#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:57:39,064 INFO L290 TraceCheckUtils]: 31: Hoare triple {4568#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4450#false} is VALID [2022-04-27 15:57:39,064 INFO L290 TraceCheckUtils]: 32: Hoare triple {4450#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4450#false} is VALID [2022-04-27 15:57:39,064 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 15:57:39,064 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:57:49,989 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 51 [2022-04-27 15:57:50,053 INFO L356 Elim1Store]: treesize reduction 16, result has 56.8 percent of original size [2022-04-27 15:57:50,054 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 707 treesize of output 673 [2022-04-27 15:57:53,430 INFO L290 TraceCheckUtils]: 32: Hoare triple {4450#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4450#false} is VALID [2022-04-27 15:57:53,431 INFO L290 TraceCheckUtils]: 31: Hoare triple {4568#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4450#false} is VALID [2022-04-27 15:57:53,432 INFO L290 TraceCheckUtils]: 30: Hoare triple {4564#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4568#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:57:53,432 INFO L272 TraceCheckUtils]: 29: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4564#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:57:53,433 INFO L290 TraceCheckUtils]: 28: Hoare triple {4587#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:57:53,433 INFO L290 TraceCheckUtils]: 27: Hoare triple {4591#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4587#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 15:57:53,434 INFO L290 TraceCheckUtils]: 26: Hoare triple {4591#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4591#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:57:53,434 INFO L290 TraceCheckUtils]: 25: Hoare triple {4591#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4591#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:57:53,435 INFO L290 TraceCheckUtils]: 24: Hoare triple {4601#(forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4591#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:57:53,435 INFO L290 TraceCheckUtils]: 23: Hoare triple {4601#(forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4601#(forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:53,436 INFO L290 TraceCheckUtils]: 22: Hoare triple {4608#(or (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))) (not |main_#t~short10|))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4601#(forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:57:53,436 INFO L290 TraceCheckUtils]: 21: Hoare triple {4612#(or (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))) (not (<= 0 main_~i~0)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4608#(or (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))) (not |main_#t~short10|))} is VALID [2022-04-27 15:57:53,438 INFO L290 TraceCheckUtils]: 20: Hoare triple {4616#(or (not (<= 1 main_~j~0)) (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4612#(or (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))) (not (<= 0 main_~i~0)))} is VALID [2022-04-27 15:57:53,443 INFO L290 TraceCheckUtils]: 19: Hoare triple {4620#(or (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))) (not (<= 0 main_~j~0)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4616#(or (not (<= 1 main_~j~0)) (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 15:57:53,444 INFO L290 TraceCheckUtils]: 18: Hoare triple {4624#(or (forall ((v_ArrVal_167 Int) (v_ArrVal_166 Int)) (or (not (<= main_~key~0 v_ArrVal_166)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))) (not (<= 0 main_~j~0)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4620#(or (forall ((v_ArrVal_167 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) (+ |main_~#v~0.offset| 4)))) (not (<= 0 main_~j~0)))} is VALID [2022-04-27 15:57:53,445 INFO L290 TraceCheckUtils]: 17: Hoare triple {4628#(or (forall ((v_ArrVal_167 Int) (v_ArrVal_166 Int)) (or (not (<= main_~key~0 v_ArrVal_166)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))) (not (<= 0 main_~j~0)) |main_#t~short10|)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4624#(or (forall ((v_ArrVal_167 Int) (v_ArrVal_166 Int)) (or (not (<= main_~key~0 v_ArrVal_166)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))) (not (<= 0 main_~j~0)))} is VALID [2022-04-27 15:57:53,460 INFO L290 TraceCheckUtils]: 16: Hoare triple {4632#(or (not (<= 0 main_~j~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))) (not |main_#t~short10|))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4628#(or (forall ((v_ArrVal_167 Int) (v_ArrVal_166 Int)) (or (not (<= main_~key~0 v_ArrVal_166)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_166) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_167) (+ |main_~#v~0.offset| 4))))) (not (<= 0 main_~j~0)) |main_#t~short10|)} is VALID [2022-04-27 15:57:53,461 INFO L290 TraceCheckUtils]: 15: Hoare triple {4636#(or (not (<= 0 main_~j~0)) (not (<= 0 main_~i~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4632#(or (not (<= 0 main_~j~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))) (not |main_#t~short10|))} is VALID [2022-04-27 15:57:53,461 INFO L290 TraceCheckUtils]: 14: Hoare triple {4640#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4636#(or (not (<= 0 main_~j~0)) (not (<= 0 main_~i~0)) (and (not (= (* main_~j~0 4) 0)) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 13: Hoare triple {4449#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4640#(<= main_~j~0 1)} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 12: Hoare triple {4449#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 11: Hoare triple {4449#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 10: Hoare triple {4449#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 9: Hoare triple {4449#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 8: Hoare triple {4449#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 7: Hoare triple {4449#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 6: Hoare triple {4449#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4449#true} is VALID [2022-04-27 15:57:53,462 INFO L290 TraceCheckUtils]: 5: Hoare triple {4449#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4449#true} is VALID [2022-04-27 15:57:53,463 INFO L272 TraceCheckUtils]: 4: Hoare triple {4449#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:53,463 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4449#true} {4449#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:53,463 INFO L290 TraceCheckUtils]: 2: Hoare triple {4449#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:53,463 INFO L290 TraceCheckUtils]: 1: Hoare triple {4449#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4449#true} is VALID [2022-04-27 15:57:53,463 INFO L272 TraceCheckUtils]: 0: Hoare triple {4449#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4449#true} is VALID [2022-04-27 15:57:53,463 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 15:57:53,463 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [933457155] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:57:53,463 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:57:53,463 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17] total 36 [2022-04-27 15:57:53,464 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301773593] [2022-04-27 15:57:53,464 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:57:53,464 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-27 15:57:53,465 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:57:53,465 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:57:53,522 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:57:53,522 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-04-27 15:57:53,522 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:57:53,523 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-04-27 15:57:53,523 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=156, Invalid=1101, Unknown=3, NotChecked=0, Total=1260 [2022-04-27 15:57:53,523 INFO L87 Difference]: Start difference. First operand 57 states and 65 transitions. Second operand has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:02,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:58:02,243 INFO L93 Difference]: Finished difference Result 144 states and 173 transitions. [2022-04-27 15:58:02,243 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2022-04-27 15:58:02,243 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-27 15:58:02,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:58:02,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:02,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 142 transitions. [2022-04-27 15:58:02,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:02,247 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 142 transitions. [2022-04-27 15:58:02,247 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 39 states and 142 transitions. [2022-04-27 15:58:02,406 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 142 edges. 142 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:58:02,408 INFO L225 Difference]: With dead ends: 144 [2022-04-27 15:58:02,408 INFO L226 Difference]: Without dead ends: 144 [2022-04-27 15:58:02,409 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 128 GetRequests, 51 SyntacticMatches, 10 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1404 ImplicationChecksByTransitivity, 17.8s TimeCoverageRelationStatistics Valid=600, Invalid=4087, Unknown=5, NotChecked=0, Total=4692 [2022-04-27 15:58:02,409 INFO L413 NwaCegarLoop]: 16 mSDtfsCounter, 141 mSDsluCounter, 113 mSDsCounter, 0 mSdLazyCounter, 745 mSolverCounterSat, 104 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 142 SdHoareTripleChecker+Valid, 129 SdHoareTripleChecker+Invalid, 1261 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 104 IncrementalHoareTripleChecker+Valid, 745 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 412 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-04-27 15:58:02,409 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [142 Valid, 129 Invalid, 1261 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [104 Valid, 745 Invalid, 0 Unknown, 412 Unchecked, 0.9s Time] [2022-04-27 15:58:02,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2022-04-27 15:58:02,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 78. [2022-04-27 15:58:02,412 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:58:02,412 INFO L82 GeneralOperation]: Start isEquivalent. First operand 144 states. Second operand has 78 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 71 states have internal predecessors, (85), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:02,412 INFO L74 IsIncluded]: Start isIncluded. First operand 144 states. Second operand has 78 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 71 states have internal predecessors, (85), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:02,412 INFO L87 Difference]: Start difference. First operand 144 states. Second operand has 78 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 71 states have internal predecessors, (85), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:02,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:58:02,415 INFO L93 Difference]: Finished difference Result 144 states and 173 transitions. [2022-04-27 15:58:02,415 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 173 transitions. [2022-04-27 15:58:02,420 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:58:02,420 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:58:02,420 INFO L74 IsIncluded]: Start isIncluded. First operand has 78 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 71 states have internal predecessors, (85), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 144 states. [2022-04-27 15:58:02,420 INFO L87 Difference]: Start difference. First operand has 78 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 71 states have internal predecessors, (85), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 144 states. [2022-04-27 15:58:02,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:58:02,422 INFO L93 Difference]: Finished difference Result 144 states and 173 transitions. [2022-04-27 15:58:02,422 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 173 transitions. [2022-04-27 15:58:02,423 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:58:02,423 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:58:02,423 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:58:02,423 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:58:02,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78 states, 70 states have (on average 1.2142857142857142) internal successors, (85), 71 states have internal predecessors, (85), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:02,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 92 transitions. [2022-04-27 15:58:02,424 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 92 transitions. Word has length 33 [2022-04-27 15:58:02,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:58:02,424 INFO L495 AbstractCegarLoop]: Abstraction has 78 states and 92 transitions. [2022-04-27 15:58:02,424 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 35 states have (on average 1.7428571428571429) internal successors, (61), 33 states have internal predecessors, (61), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:02,424 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 92 transitions. [2022-04-27 15:58:02,424 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-04-27 15:58:02,424 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:58:02,424 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:58:02,445 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2022-04-27 15:58:02,643 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-04-27 15:58:02,643 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:58:02,648 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:58:02,648 INFO L85 PathProgramCache]: Analyzing trace with hash -954574653, now seen corresponding path program 1 times [2022-04-27 15:58:02,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:58:02,649 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1379866860] [2022-04-27 15:58:02,649 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:58:02,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:58:02,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:02,920 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:58:02,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:02,928 INFO L290 TraceCheckUtils]: 0: Hoare triple {5289#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5271#true} is VALID [2022-04-27 15:58:02,928 INFO L290 TraceCheckUtils]: 1: Hoare triple {5271#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:02,928 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {5271#true} {5271#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:02,928 INFO L272 TraceCheckUtils]: 0: Hoare triple {5271#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:58:02,928 INFO L290 TraceCheckUtils]: 1: Hoare triple {5289#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5271#true} is VALID [2022-04-27 15:58:02,929 INFO L290 TraceCheckUtils]: 2: Hoare triple {5271#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:02,929 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5271#true} {5271#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:02,929 INFO L272 TraceCheckUtils]: 4: Hoare triple {5271#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:02,929 INFO L290 TraceCheckUtils]: 5: Hoare triple {5271#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5276#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:58:02,929 INFO L290 TraceCheckUtils]: 6: Hoare triple {5276#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5276#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:58:02,930 INFO L290 TraceCheckUtils]: 7: Hoare triple {5276#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,930 INFO L290 TraceCheckUtils]: 8: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,930 INFO L290 TraceCheckUtils]: 9: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:02,930 INFO L290 TraceCheckUtils]: 10: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:02,931 INFO L290 TraceCheckUtils]: 11: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:02,931 INFO L290 TraceCheckUtils]: 12: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:02,931 INFO L290 TraceCheckUtils]: 13: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,931 INFO L290 TraceCheckUtils]: 14: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,932 INFO L290 TraceCheckUtils]: 15: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,932 INFO L290 TraceCheckUtils]: 16: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,932 INFO L290 TraceCheckUtils]: 17: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,932 INFO L290 TraceCheckUtils]: 18: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:02,933 INFO L290 TraceCheckUtils]: 19: Hoare triple {5277#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5279#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} is VALID [2022-04-27 15:58:02,933 INFO L290 TraceCheckUtils]: 20: Hoare triple {5279#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5280#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:02,934 INFO L290 TraceCheckUtils]: 21: Hoare triple {5280#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5280#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:02,934 INFO L290 TraceCheckUtils]: 22: Hoare triple {5280#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5280#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:02,934 INFO L290 TraceCheckUtils]: 23: Hoare triple {5280#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {5281#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:02,935 INFO L290 TraceCheckUtils]: 24: Hoare triple {5281#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5281#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:02,935 INFO L290 TraceCheckUtils]: 25: Hoare triple {5281#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5282#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 15:58:02,935 INFO L290 TraceCheckUtils]: 26: Hoare triple {5282#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5283#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 15:58:02,936 INFO L290 TraceCheckUtils]: 27: Hoare triple {5283#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:02,936 INFO L290 TraceCheckUtils]: 28: Hoare triple {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:02,937 INFO L290 TraceCheckUtils]: 29: Hoare triple {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:02,937 INFO L290 TraceCheckUtils]: 30: Hoare triple {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {5285#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:58:02,937 INFO L290 TraceCheckUtils]: 31: Hoare triple {5285#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5286#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:58:02,938 INFO L272 TraceCheckUtils]: 32: Hoare triple {5286#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5287#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 15:58:02,938 INFO L290 TraceCheckUtils]: 33: Hoare triple {5287#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5288#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 15:58:02,938 INFO L290 TraceCheckUtils]: 34: Hoare triple {5288#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5272#false} is VALID [2022-04-27 15:58:02,938 INFO L290 TraceCheckUtils]: 35: Hoare triple {5272#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5272#false} is VALID [2022-04-27 15:58:02,939 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 15:58:02,939 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:58:02,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1379866860] [2022-04-27 15:58:02,939 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1379866860] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:58:02,939 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [622434504] [2022-04-27 15:58:02,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:58:02,939 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:58:02,939 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:58:02,940 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:58:02,941 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 15:58:03,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:03,006 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 21 conjunts are in the unsatisfiable core [2022-04-27 15:58:03,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:03,014 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:58:03,396 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 15:58:03,397 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 15:58:03,546 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 15:58:03,546 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 15:58:03,618 INFO L272 TraceCheckUtils]: 0: Hoare triple {5271#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:03,618 INFO L290 TraceCheckUtils]: 1: Hoare triple {5271#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5271#true} is VALID [2022-04-27 15:58:03,618 INFO L290 TraceCheckUtils]: 2: Hoare triple {5271#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:03,618 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5271#true} {5271#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:03,618 INFO L272 TraceCheckUtils]: 4: Hoare triple {5271#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:03,628 INFO L290 TraceCheckUtils]: 5: Hoare triple {5271#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,628 INFO L290 TraceCheckUtils]: 6: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,628 INFO L290 TraceCheckUtils]: 7: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,629 INFO L290 TraceCheckUtils]: 8: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,629 INFO L290 TraceCheckUtils]: 9: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,629 INFO L290 TraceCheckUtils]: 10: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,629 INFO L290 TraceCheckUtils]: 11: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,630 INFO L290 TraceCheckUtils]: 12: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5278#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:03,630 INFO L290 TraceCheckUtils]: 13: Hoare triple {5278#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:03,631 INFO L290 TraceCheckUtils]: 14: Hoare triple {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:03,631 INFO L290 TraceCheckUtils]: 15: Hoare triple {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:03,631 INFO L290 TraceCheckUtils]: 16: Hoare triple {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:03,632 INFO L290 TraceCheckUtils]: 17: Hoare triple {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:03,632 INFO L290 TraceCheckUtils]: 18: Hoare triple {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:03,633 INFO L290 TraceCheckUtils]: 19: Hoare triple {5332#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5351#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} is VALID [2022-04-27 15:58:03,633 INFO L290 TraceCheckUtils]: 20: Hoare triple {5351#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5355#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 15:58:03,634 INFO L290 TraceCheckUtils]: 21: Hoare triple {5355#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5355#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 15:58:03,634 INFO L290 TraceCheckUtils]: 22: Hoare triple {5355#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5355#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 15:58:03,635 INFO L290 TraceCheckUtils]: 23: Hoare triple {5355#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {5365#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-27 15:58:03,635 INFO L290 TraceCheckUtils]: 24: Hoare triple {5365#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5369#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 15:58:03,636 INFO L290 TraceCheckUtils]: 25: Hoare triple {5369#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5282#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 15:58:03,636 INFO L290 TraceCheckUtils]: 26: Hoare triple {5282#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5283#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 15:58:03,637 INFO L290 TraceCheckUtils]: 27: Hoare triple {5283#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:03,638 INFO L290 TraceCheckUtils]: 28: Hoare triple {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:03,638 INFO L290 TraceCheckUtils]: 29: Hoare triple {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:03,638 INFO L290 TraceCheckUtils]: 30: Hoare triple {5284#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {5285#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:58:03,639 INFO L290 TraceCheckUtils]: 31: Hoare triple {5285#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5286#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:58:03,640 INFO L272 TraceCheckUtils]: 32: Hoare triple {5286#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5394#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:58:03,640 INFO L290 TraceCheckUtils]: 33: Hoare triple {5394#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5398#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:58:03,640 INFO L290 TraceCheckUtils]: 34: Hoare triple {5398#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5272#false} is VALID [2022-04-27 15:58:03,640 INFO L290 TraceCheckUtils]: 35: Hoare triple {5272#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5272#false} is VALID [2022-04-27 15:58:03,641 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 15:58:03,641 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:58:04,000 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-27 15:58:04,033 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-27 15:58:04,033 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-27 15:58:04,303 INFO L290 TraceCheckUtils]: 35: Hoare triple {5272#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5272#false} is VALID [2022-04-27 15:58:04,303 INFO L290 TraceCheckUtils]: 34: Hoare triple {5398#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5272#false} is VALID [2022-04-27 15:58:04,303 INFO L290 TraceCheckUtils]: 33: Hoare triple {5394#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5398#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:58:04,304 INFO L272 TraceCheckUtils]: 32: Hoare triple {5286#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5394#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:58:04,305 INFO L290 TraceCheckUtils]: 31: Hoare triple {5417#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5286#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 15:58:04,305 INFO L290 TraceCheckUtils]: 30: Hoare triple {5421#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {5417#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 15:58:04,305 INFO L290 TraceCheckUtils]: 29: Hoare triple {5421#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5421#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:58:04,306 INFO L290 TraceCheckUtils]: 28: Hoare triple {5421#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5421#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:58:04,306 INFO L290 TraceCheckUtils]: 27: Hoare triple {5431#(forall ((v_ArrVal_197 Int)) (or (not (<= main_~key~0 v_ArrVal_197)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) (+ |main_~#v~0.offset| 4)))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5421#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:58:04,307 INFO L290 TraceCheckUtils]: 26: Hoare triple {5435#(or (forall ((v_ArrVal_197 Int)) (or (not (<= main_~key~0 v_ArrVal_197)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5431#(forall ((v_ArrVal_197 Int)) (or (not (<= main_~key~0 v_ArrVal_197)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 15:58:04,308 INFO L290 TraceCheckUtils]: 25: Hoare triple {5439#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5435#(or (forall ((v_ArrVal_197 Int)) (or (not (<= main_~key~0 v_ArrVal_197)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_197) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 15:58:04,308 INFO L290 TraceCheckUtils]: 24: Hoare triple {5443#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5439#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:04,309 INFO L290 TraceCheckUtils]: 23: Hoare triple {5447#(<= main_~i~0 1)} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {5443#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:04,310 INFO L290 TraceCheckUtils]: 22: Hoare triple {5447#(<= main_~i~0 1)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5447#(<= main_~i~0 1)} is VALID [2022-04-27 15:58:04,311 INFO L290 TraceCheckUtils]: 21: Hoare triple {5447#(<= main_~i~0 1)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5447#(<= main_~i~0 1)} is VALID [2022-04-27 15:58:04,311 INFO L290 TraceCheckUtils]: 20: Hoare triple {5457#(<= main_~j~0 2)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5447#(<= main_~i~0 1)} is VALID [2022-04-27 15:58:04,312 INFO L290 TraceCheckUtils]: 19: Hoare triple {5461#(<= main_~j~0 1)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5457#(<= main_~j~0 2)} is VALID [2022-04-27 15:58:04,312 INFO L290 TraceCheckUtils]: 18: Hoare triple {5461#(<= main_~j~0 1)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5461#(<= main_~j~0 1)} is VALID [2022-04-27 15:58:04,312 INFO L290 TraceCheckUtils]: 17: Hoare triple {5461#(<= main_~j~0 1)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5461#(<= main_~j~0 1)} is VALID [2022-04-27 15:58:04,313 INFO L290 TraceCheckUtils]: 16: Hoare triple {5461#(<= main_~j~0 1)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5461#(<= main_~j~0 1)} is VALID [2022-04-27 15:58:04,313 INFO L290 TraceCheckUtils]: 15: Hoare triple {5461#(<= main_~j~0 1)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5461#(<= main_~j~0 1)} is VALID [2022-04-27 15:58:04,313 INFO L290 TraceCheckUtils]: 14: Hoare triple {5461#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5461#(<= main_~j~0 1)} is VALID [2022-04-27 15:58:04,313 INFO L290 TraceCheckUtils]: 13: Hoare triple {5271#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5461#(<= main_~j~0 1)} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 12: Hoare triple {5271#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 11: Hoare triple {5271#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 10: Hoare triple {5271#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 9: Hoare triple {5271#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 8: Hoare triple {5271#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 7: Hoare triple {5271#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 6: Hoare triple {5271#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 5: Hoare triple {5271#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L272 TraceCheckUtils]: 4: Hoare triple {5271#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5271#true} {5271#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 2: Hoare triple {5271#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:04,314 INFO L290 TraceCheckUtils]: 1: Hoare triple {5271#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5271#true} is VALID [2022-04-27 15:58:04,315 INFO L272 TraceCheckUtils]: 0: Hoare triple {5271#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5271#true} is VALID [2022-04-27 15:58:04,315 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 15:58:04,315 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [622434504] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 15:58:04,315 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 15:58:04,315 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 14] total 32 [2022-04-27 15:58:04,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1630376040] [2022-04-27 15:58:04,315 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 15:58:04,316 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 36 [2022-04-27 15:58:04,316 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 15:58:04,316 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:04,375 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:58:04,375 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-04-27 15:58:04,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 15:58:04,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-04-27 15:58:04,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=862, Unknown=0, NotChecked=0, Total=992 [2022-04-27 15:58:04,376 INFO L87 Difference]: Start difference. First operand 78 states and 92 transitions. Second operand has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:07,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:58:07,700 INFO L93 Difference]: Finished difference Result 151 states and 181 transitions. [2022-04-27 15:58:07,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-04-27 15:58:07,700 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 36 [2022-04-27 15:58:07,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 15:58:07,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:07,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 135 transitions. [2022-04-27 15:58:07,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:07,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 135 transitions. [2022-04-27 15:58:07,705 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 42 states and 135 transitions. [2022-04-27 15:58:07,851 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 135 edges. 135 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 15:58:07,852 INFO L225 Difference]: With dead ends: 151 [2022-04-27 15:58:07,852 INFO L226 Difference]: Without dead ends: 151 [2022-04-27 15:58:07,853 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 56 SyntacticMatches, 9 SemanticMatches, 69 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1360 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=829, Invalid=4141, Unknown=0, NotChecked=0, Total=4970 [2022-04-27 15:58:07,855 INFO L413 NwaCegarLoop]: 20 mSDtfsCounter, 225 mSDsluCounter, 92 mSDsCounter, 0 mSdLazyCounter, 1020 mSolverCounterSat, 221 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 225 SdHoareTripleChecker+Valid, 112 SdHoareTripleChecker+Invalid, 1329 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 221 IncrementalHoareTripleChecker+Valid, 1020 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 88 IncrementalHoareTripleChecker+Unchecked, 1.2s IncrementalHoareTripleChecker+Time [2022-04-27 15:58:07,855 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [225 Valid, 112 Invalid, 1329 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [221 Valid, 1020 Invalid, 0 Unknown, 88 Unchecked, 1.2s Time] [2022-04-27 15:58:07,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2022-04-27 15:58:07,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 86. [2022-04-27 15:58:07,866 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 15:58:07,867 INFO L82 GeneralOperation]: Start isEquivalent. First operand 151 states. Second operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:07,867 INFO L74 IsIncluded]: Start isIncluded. First operand 151 states. Second operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:07,868 INFO L87 Difference]: Start difference. First operand 151 states. Second operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:07,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:58:07,874 INFO L93 Difference]: Finished difference Result 151 states and 181 transitions. [2022-04-27 15:58:07,874 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 181 transitions. [2022-04-27 15:58:07,874 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:58:07,874 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:58:07,875 INFO L74 IsIncluded]: Start isIncluded. First operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 151 states. [2022-04-27 15:58:07,875 INFO L87 Difference]: Start difference. First operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 151 states. [2022-04-27 15:58:07,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 15:58:07,877 INFO L93 Difference]: Finished difference Result 151 states and 181 transitions. [2022-04-27 15:58:07,877 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 181 transitions. [2022-04-27 15:58:07,877 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 15:58:07,877 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 15:58:07,877 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 15:58:07,877 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 15:58:07,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 78 states have (on average 1.2307692307692308) internal successors, (96), 79 states have internal predecessors, (96), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 15:58:07,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 103 transitions. [2022-04-27 15:58:07,878 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 103 transitions. Word has length 36 [2022-04-27 15:58:07,878 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 15:58:07,878 INFO L495 AbstractCegarLoop]: Abstraction has 86 states and 103 transitions. [2022-04-27 15:58:07,879 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 15:58:07,879 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 103 transitions. [2022-04-27 15:58:07,879 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-04-27 15:58:07,879 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 15:58:07,879 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 15:58:07,895 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2022-04-27 15:58:08,080 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-04-27 15:58:08,080 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 15:58:08,081 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 15:58:08,082 INFO L85 PathProgramCache]: Analyzing trace with hash -392015670, now seen corresponding path program 3 times [2022-04-27 15:58:08,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 15:58:08,082 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2011455227] [2022-04-27 15:58:08,082 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 15:58:08,082 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 15:58:08,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:08,679 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 15:58:08,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:08,682 INFO L290 TraceCheckUtils]: 0: Hoare triple {6166#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6143#true} is VALID [2022-04-27 15:58:08,683 INFO L290 TraceCheckUtils]: 1: Hoare triple {6143#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:08,683 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {6143#true} {6143#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:08,683 INFO L272 TraceCheckUtils]: 0: Hoare triple {6143#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6166#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 15:58:08,683 INFO L290 TraceCheckUtils]: 1: Hoare triple {6166#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6143#true} is VALID [2022-04-27 15:58:08,683 INFO L290 TraceCheckUtils]: 2: Hoare triple {6143#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:08,683 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6143#true} {6143#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:08,683 INFO L272 TraceCheckUtils]: 4: Hoare triple {6143#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:08,684 INFO L290 TraceCheckUtils]: 5: Hoare triple {6143#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6148#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:58:08,685 INFO L290 TraceCheckUtils]: 6: Hoare triple {6148#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6148#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 15:58:08,685 INFO L290 TraceCheckUtils]: 7: Hoare triple {6148#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6149#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:08,685 INFO L290 TraceCheckUtils]: 8: Hoare triple {6149#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6149#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:08,686 INFO L290 TraceCheckUtils]: 9: Hoare triple {6149#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6150#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 15:58:08,686 INFO L290 TraceCheckUtils]: 10: Hoare triple {6150#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6150#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 15:58:08,687 INFO L290 TraceCheckUtils]: 11: Hoare triple {6150#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6151#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:08,687 INFO L290 TraceCheckUtils]: 12: Hoare triple {6151#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6151#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 15:58:08,687 INFO L290 TraceCheckUtils]: 13: Hoare triple {6151#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6149#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 15:58:08,688 INFO L290 TraceCheckUtils]: 14: Hoare triple {6149#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6152#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 15:58:08,689 INFO L290 TraceCheckUtils]: 15: Hoare triple {6152#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6153#(and (or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 15:58:08,690 INFO L290 TraceCheckUtils]: 16: Hoare triple {6153#(and (or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (= (+ (- 1) main_~j~0) 0))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6154#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 15:58:08,690 INFO L290 TraceCheckUtils]: 17: Hoare triple {6154#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {6155#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} is VALID [2022-04-27 15:58:08,691 INFO L290 TraceCheckUtils]: 18: Hoare triple {6155#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6156#(and (= |main_~#v~0.offset| 0) (or (and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 15:58:08,692 INFO L290 TraceCheckUtils]: 19: Hoare triple {6156#(and (= |main_~#v~0.offset| 0) (or (and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|) (= (+ (- 1) main_~j~0) 0))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {6157#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:08,692 INFO L290 TraceCheckUtils]: 20: Hoare triple {6157#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6157#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:08,693 INFO L290 TraceCheckUtils]: 21: Hoare triple {6157#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {6158#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:08,693 INFO L290 TraceCheckUtils]: 22: Hoare triple {6158#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6159#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-27 15:58:08,694 INFO L290 TraceCheckUtils]: 23: Hoare triple {6159#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:08,694 INFO L290 TraceCheckUtils]: 24: Hoare triple {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:08,695 INFO L290 TraceCheckUtils]: 25: Hoare triple {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:08,695 INFO L290 TraceCheckUtils]: 26: Hoare triple {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 15:58:08,696 INFO L290 TraceCheckUtils]: 27: Hoare triple {6160#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {6161#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:08,696 INFO L290 TraceCheckUtils]: 28: Hoare triple {6161#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6161#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:08,697 INFO L290 TraceCheckUtils]: 29: Hoare triple {6161#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6161#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 15:58:08,697 INFO L290 TraceCheckUtils]: 30: Hoare triple {6161#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {6162#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 15:58:08,698 INFO L290 TraceCheckUtils]: 31: Hoare triple {6162#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6163#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 15:58:08,698 INFO L272 TraceCheckUtils]: 32: Hoare triple {6163#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6164#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 15:58:08,699 INFO L290 TraceCheckUtils]: 33: Hoare triple {6164#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6165#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 15:58:08,699 INFO L290 TraceCheckUtils]: 34: Hoare triple {6165#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6144#false} is VALID [2022-04-27 15:58:08,699 INFO L290 TraceCheckUtils]: 35: Hoare triple {6144#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6144#false} is VALID [2022-04-27 15:58:08,700 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 15:58:08,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 15:58:08,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2011455227] [2022-04-27 15:58:08,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2011455227] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 15:58:08,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [670607441] [2022-04-27 15:58:08,700 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 15:58:08,700 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 15:58:08,700 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 15:58:08,702 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 15:58:08,704 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-04-27 15:58:08,774 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2022-04-27 15:58:08,775 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 15:58:08,776 INFO L263 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 27 conjunts are in the unsatisfiable core [2022-04-27 15:58:08,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 15:58:08,790 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 15:58:09,000 INFO L356 Elim1Store]: treesize reduction 40, result has 23.1 percent of original size [2022-04-27 15:58:09,000 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 30 [2022-04-27 15:58:09,326 INFO L356 Elim1Store]: treesize reduction 109, result has 9.2 percent of original size [2022-04-27 15:58:09,326 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 30 [2022-04-27 15:58:09,781 INFO L356 Elim1Store]: treesize reduction 88, result has 20.0 percent of original size [2022-04-27 15:58:09,781 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 37 [2022-04-27 15:58:10,147 INFO L356 Elim1Store]: treesize reduction 36, result has 7.7 percent of original size [2022-04-27 15:58:10,148 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2022-04-27 15:58:10,293 INFO L272 TraceCheckUtils]: 0: Hoare triple {6143#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:10,293 INFO L290 TraceCheckUtils]: 1: Hoare triple {6143#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6143#true} is VALID [2022-04-27 15:58:10,293 INFO L290 TraceCheckUtils]: 2: Hoare triple {6143#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:10,293 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6143#true} {6143#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L272 TraceCheckUtils]: 4: Hoare triple {6143#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 5: Hoare triple {6143#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (let ((.cse0 (mod v_main_~SIZE~0_1 4294967296))) (ite (<= .cse0 2147483647) .cse0 (+ .cse0 (- 4294967296)))) 4)) |v_#length_1|) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 6: Hoare triple {6143#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 7: Hoare triple {6143#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 8: Hoare triple {6143#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 9: Hoare triple {6143#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 10: Hoare triple {6143#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 11: Hoare triple {6143#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 12: Hoare triple {6143#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6143#true} is VALID [2022-04-27 15:58:10,294 INFO L290 TraceCheckUtils]: 13: Hoare triple {6143#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6209#(= main_~j~0 1)} is VALID [2022-04-27 15:58:10,295 INFO L290 TraceCheckUtils]: 14: Hoare triple {6209#(= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6213#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-27 15:58:10,295 INFO L290 TraceCheckUtils]: 15: Hoare triple {6213#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6213#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-27 15:58:10,296 INFO L290 TraceCheckUtils]: 16: Hoare triple {6213#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6220#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} is VALID [2022-04-27 15:58:10,297 INFO L290 TraceCheckUtils]: 17: Hoare triple {6220#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {6224#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 15:58:10,298 INFO L290 TraceCheckUtils]: 18: Hoare triple {6224#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6228#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 15:58:10,298 INFO L290 TraceCheckUtils]: 19: Hoare triple {6228#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {6232#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 15:58:10,299 INFO L290 TraceCheckUtils]: 20: Hoare triple {6232#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6232#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 15:58:10,301 INFO L290 TraceCheckUtils]: 21: Hoare triple {6232#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {6239#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} is VALID [2022-04-27 15:58:10,302 INFO L290 TraceCheckUtils]: 22: Hoare triple {6239#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6243#(and (<= 2 main_~j~0) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))))} is VALID [2022-04-27 15:58:10,303 INFO L290 TraceCheckUtils]: 23: Hoare triple {6243#(and (<= 2 main_~j~0) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-27 15:58:10,303 INFO L290 TraceCheckUtils]: 24: Hoare triple {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-27 15:58:10,304 INFO L290 TraceCheckUtils]: 25: Hoare triple {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-27 15:58:10,304 INFO L290 TraceCheckUtils]: 26: Hoare triple {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-27 15:58:10,305 INFO L290 TraceCheckUtils]: 27: Hoare triple {6247#(and (<= 1 main_~i~0) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {6260#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} is VALID [2022-04-27 15:58:10,305 INFO L290 TraceCheckUtils]: 28: Hoare triple {6260#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6260#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} is VALID [2022-04-27 15:58:10,306 INFO L290 TraceCheckUtils]: 29: Hoare triple {6260#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6260#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} is VALID [2022-04-27 15:58:10,306 INFO L290 TraceCheckUtils]: 30: Hoare triple {6260#(exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {6270#(and (= main_~k~0 1) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} is VALID [2022-04-27 15:58:10,307 INFO L290 TraceCheckUtils]: 31: Hoare triple {6270#(and (= main_~k~0 1) (exists ((v_main_~i~0_27 Int)) (and (< v_main_~i~0_27 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_27 1)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6163#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 15:58:10,307 INFO L272 TraceCheckUtils]: 32: Hoare triple {6163#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6277#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 15:58:10,308 INFO L290 TraceCheckUtils]: 33: Hoare triple {6277#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6281#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 15:58:10,308 INFO L290 TraceCheckUtils]: 34: Hoare triple {6281#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6144#false} is VALID [2022-04-27 15:58:10,308 INFO L290 TraceCheckUtils]: 35: Hoare triple {6144#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6144#false} is VALID [2022-04-27 15:58:10,308 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 15:58:10,308 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 15:58:16,728 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~i~0_28 Int)) (or (not (<= c_main_~j~0 (+ v_main_~i~0_28 1))) (forall ((v_ArrVal_231 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ (* v_main_~i~0_28 4) |c_main_~#v~0.offset| 4) v_ArrVal_231))) (<= (select .cse0 |c_main_~#v~0.offset|) (select .cse0 (+ |c_main_~#v~0.offset| 4))))))) is different from false [2022-04-27 15:58:29,071 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 77 [2022-04-27 15:58:29,206 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-27 15:58:29,206 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 85467 treesize of output 82393