/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf -i ../../../trunk/examples/svcomp/loops-crafted-1/nested5-2.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 16:54:11,843 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 16:54:11,844 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 16:54:11,882 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 16:54:11,882 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 16:54:11,883 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 16:54:11,886 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 16:54:11,890 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 16:54:11,892 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 16:54:11,896 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 16:54:11,897 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 16:54:11,898 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 16:54:11,898 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 16:54:11,900 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 16:54:11,901 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 16:54:11,904 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 16:54:11,904 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 16:54:11,905 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 16:54:11,907 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 16:54:11,912 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 16:54:11,913 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 16:54:11,914 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 16:54:11,915 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 16:54:11,916 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 16:54:11,917 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 16:54:11,923 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 16:54:11,931 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 16:54:11,931 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 16:54:11,933 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 16:54:11,933 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/automizer/LoopAccelerationJordanC.epf [2022-04-27 16:54:11,947 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 16:54:11,947 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 16:54:11,948 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 16:54:11,948 INFO L138 SettingsManager]: * sizeof long=4 [2022-04-27 16:54:11,949 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 16:54:11,949 INFO L138 SettingsManager]: * sizeof POINTER=4 [2022-04-27 16:54:11,949 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 16:54:11,949 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 16:54:11,949 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 16:54:11,950 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 16:54:11,950 INFO L138 SettingsManager]: * sizeof long double=12 [2022-04-27 16:54:11,950 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 16:54:11,950 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 16:54:11,950 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 16:54:11,951 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 16:54:11,951 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 16:54:11,951 INFO L138 SettingsManager]: * To the following directory=./dump/ [2022-04-27 16:54:11,951 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 16:54:11,951 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:54:11,951 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 16:54:11,951 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 16:54:11,952 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 16:54:11,952 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_JORDAN WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 16:54:12,186 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 16:54:12,207 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 16:54:12,209 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 16:54:12,210 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 16:54:12,211 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 16:54:12,212 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops-crafted-1/nested5-2.c [2022-04-27 16:54:12,273 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0c7040077/262d513f18184918bd6450fa28df48fc/FLAGf35716c13 [2022-04-27 16:54:12,604 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 16:54:12,604 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/nested5-2.c [2022-04-27 16:54:12,608 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0c7040077/262d513f18184918bd6450fa28df48fc/FLAGf35716c13 [2022-04-27 16:54:13,045 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0c7040077/262d513f18184918bd6450fa28df48fc [2022-04-27 16:54:13,047 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 16:54:13,048 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 16:54:13,056 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 16:54:13,056 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 16:54:13,058 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 16:54:13,059 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,060 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@440a8d60 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13, skipping insertion in model container [2022-04-27 16:54:13,060 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,066 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 16:54:13,075 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 16:54:13,216 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/nested5-2.c[321,334] [2022-04-27 16:54:13,232 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:54:13,239 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 16:54:13,249 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops-crafted-1/nested5-2.c[321,334] [2022-04-27 16:54:13,254 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 16:54:13,268 INFO L208 MainTranslator]: Completed translation [2022-04-27 16:54:13,268 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13 WrapperNode [2022-04-27 16:54:13,269 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 16:54:13,269 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 16:54:13,270 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 16:54:13,270 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 16:54:13,280 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,280 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,286 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,287 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,303 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,307 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,308 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,310 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 16:54:13,311 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 16:54:13,311 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 16:54:13,311 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 16:54:13,312 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,319 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 16:54:13,332 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:54:13,341 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 16:54:13,345 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 16:54:13,372 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 16:54:13,372 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 16:54:13,372 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 16:54:13,372 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 16:54:13,373 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 16:54:13,373 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 16:54:13,373 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 16:54:13,373 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 16:54:13,373 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 16:54:13,373 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 16:54:13,373 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 16:54:13,374 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 16:54:13,374 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 16:54:13,374 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 16:54:13,374 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 16:54:13,374 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 16:54:13,374 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 16:54:13,425 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 16:54:13,426 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 16:54:13,559 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 16:54:13,565 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 16:54:13,565 INFO L299 CfgBuilder]: Removed 5 assume(true) statements. [2022-04-27 16:54:13,566 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:54:13 BoogieIcfgContainer [2022-04-27 16:54:13,566 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 16:54:13,567 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 16:54:13,567 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 16:54:13,568 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 16:54:13,570 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:54:13" (1/1) ... [2022-04-27 16:54:13,572 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_JORDAN [2022-04-27 16:54:13,593 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:54:13 BasicIcfg [2022-04-27 16:54:13,593 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 16:54:13,595 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 16:54:13,595 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 16:54:13,598 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 16:54:13,598 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 04:54:13" (1/4) ... [2022-04-27 16:54:13,599 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@266c80ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:54:13, skipping insertion in model container [2022-04-27 16:54:13,599 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 04:54:13" (2/4) ... [2022-04-27 16:54:13,599 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@266c80ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 04:54:13, skipping insertion in model container [2022-04-27 16:54:13,600 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 04:54:13" (3/4) ... [2022-04-27 16:54:13,600 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@266c80ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 04:54:13, skipping insertion in model container [2022-04-27 16:54:13,600 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 04:54:13" (4/4) ... [2022-04-27 16:54:13,601 INFO L111 eAbstractionObserver]: Analyzing ICFG nested5-2.cJordan [2022-04-27 16:54:13,612 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:ForwardPredicates Determinization: PREDICATE_ABSTRACTION [2022-04-27 16:54:13,612 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 16:54:13,692 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 16:54:13,702 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=ForwardPredicates, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=false, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=All, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@4e0607dc, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@25b9e7ff [2022-04-27 16:54:13,702 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 16:54:13,713 INFO L276 IsEmpty]: Start isEmpty. Operand has 28 states, 20 states have (on average 1.6) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 16:54:13,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 16:54:13,720 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:54:13,720 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:54:13,721 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:54:13,741 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:54:13,741 INFO L85 PathProgramCache]: Analyzing trace with hash -1895308246, now seen corresponding path program 1 times [2022-04-27 16:54:13,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:54:13,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1497876974] [2022-04-27 16:54:13,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:13,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:54:13,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:13,979 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:54:13,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:13,999 INFO L290 TraceCheckUtils]: 0: Hoare triple {36#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {31#true} is VALID [2022-04-27 16:54:13,999 INFO L290 TraceCheckUtils]: 1: Hoare triple {31#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#true} is VALID [2022-04-27 16:54:14,000 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {31#true} {31#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#true} is VALID [2022-04-27 16:54:14,002 INFO L272 TraceCheckUtils]: 0: Hoare triple {31#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:54:14,005 INFO L290 TraceCheckUtils]: 1: Hoare triple {36#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {31#true} is VALID [2022-04-27 16:54:14,005 INFO L290 TraceCheckUtils]: 2: Hoare triple {31#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#true} is VALID [2022-04-27 16:54:14,006 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {31#true} {31#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#true} is VALID [2022-04-27 16:54:14,006 INFO L272 TraceCheckUtils]: 4: Hoare triple {31#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {31#true} is VALID [2022-04-27 16:54:14,007 INFO L290 TraceCheckUtils]: 5: Hoare triple {31#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {31#true} is VALID [2022-04-27 16:54:14,007 INFO L290 TraceCheckUtils]: 6: Hoare triple {31#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {31#true} is VALID [2022-04-27 16:54:14,008 INFO L290 TraceCheckUtils]: 7: Hoare triple {31#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {31#true} is VALID [2022-04-27 16:54:14,008 INFO L290 TraceCheckUtils]: 8: Hoare triple {31#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {31#true} is VALID [2022-04-27 16:54:14,009 INFO L290 TraceCheckUtils]: 9: Hoare triple {31#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {31#true} is VALID [2022-04-27 16:54:14,009 INFO L290 TraceCheckUtils]: 10: Hoare triple {31#true} [113] L24-3-->L24-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {32#false} is VALID [2022-04-27 16:54:14,010 INFO L272 TraceCheckUtils]: 11: Hoare triple {32#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {32#false} is VALID [2022-04-27 16:54:14,010 INFO L290 TraceCheckUtils]: 12: Hoare triple {32#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {32#false} is VALID [2022-04-27 16:54:14,010 INFO L290 TraceCheckUtils]: 13: Hoare triple {32#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {32#false} is VALID [2022-04-27 16:54:14,011 INFO L290 TraceCheckUtils]: 14: Hoare triple {32#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {32#false} is VALID [2022-04-27 16:54:14,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:14,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:54:14,013 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1497876974] [2022-04-27 16:54:14,014 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1497876974] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:54:14,014 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:54:14,014 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 16:54:14,016 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2134605558] [2022-04-27 16:54:14,016 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:54:14,021 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:54:14,022 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:14,024 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,051 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:14,051 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 16:54:14,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:14,069 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 16:54:14,070 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:54:14,072 INFO L87 Difference]: Start difference. First operand has 28 states, 20 states have (on average 1.6) internal successors, (32), 21 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:14,144 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-04-27 16:54:14,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 16:54:14,144 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:54:14,144 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:54:14,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 38 transitions. [2022-04-27 16:54:14,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 38 transitions. [2022-04-27 16:54:14,158 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 38 transitions. [2022-04-27 16:54:14,202 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:14,209 INFO L225 Difference]: With dead ends: 28 [2022-04-27 16:54:14,209 INFO L226 Difference]: Without dead ends: 23 [2022-04-27 16:54:14,211 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 16:54:14,214 INFO L413 NwaCegarLoop]: 31 mSDtfsCounter, 23 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 24 SdHoareTripleChecker+Valid, 34 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:54:14,214 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [24 Valid, 34 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:54:14,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2022-04-27 16:54:14,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2022-04-27 16:54:14,234 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:54:14,235 INFO L82 GeneralOperation]: Start isEquivalent. First operand 23 states. Second operand has 23 states, 17 states have (on average 1.2941176470588236) internal successors, (22), 17 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,236 INFO L74 IsIncluded]: Start isIncluded. First operand 23 states. Second operand has 23 states, 17 states have (on average 1.2941176470588236) internal successors, (22), 17 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,238 INFO L87 Difference]: Start difference. First operand 23 states. Second operand has 23 states, 17 states have (on average 1.2941176470588236) internal successors, (22), 17 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:14,242 INFO L93 Difference]: Finished difference Result 23 states and 27 transitions. [2022-04-27 16:54:14,242 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 27 transitions. [2022-04-27 16:54:14,243 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:14,243 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:14,243 INFO L74 IsIncluded]: Start isIncluded. First operand has 23 states, 17 states have (on average 1.2941176470588236) internal successors, (22), 17 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 23 states. [2022-04-27 16:54:14,244 INFO L87 Difference]: Start difference. First operand has 23 states, 17 states have (on average 1.2941176470588236) internal successors, (22), 17 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 23 states. [2022-04-27 16:54:14,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:14,246 INFO L93 Difference]: Finished difference Result 23 states and 27 transitions. [2022-04-27 16:54:14,246 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 27 transitions. [2022-04-27 16:54:14,246 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:14,246 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:14,246 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:54:14,246 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:54:14,247 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 17 states have (on average 1.2941176470588236) internal successors, (22), 17 states have internal predecessors, (22), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 27 transitions. [2022-04-27 16:54:14,249 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 27 transitions. Word has length 15 [2022-04-27 16:54:14,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:54:14,250 INFO L495 AbstractCegarLoop]: Abstraction has 23 states and 27 transitions. [2022-04-27 16:54:14,250 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,250 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 27 transitions. [2022-04-27 16:54:14,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 16:54:14,251 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:54:14,251 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:54:14,251 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 16:54:14,251 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:54:14,252 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:54:14,252 INFO L85 PathProgramCache]: Analyzing trace with hash -1894384725, now seen corresponding path program 1 times [2022-04-27 16:54:14,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:54:14,253 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1628280781] [2022-04-27 16:54:14,253 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:14,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:54:14,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:14,383 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:54:14,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:14,406 INFO L290 TraceCheckUtils]: 0: Hoare triple {142#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {136#true} is VALID [2022-04-27 16:54:14,407 INFO L290 TraceCheckUtils]: 1: Hoare triple {136#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {136#true} is VALID [2022-04-27 16:54:14,407 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {136#true} {136#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {136#true} is VALID [2022-04-27 16:54:14,408 INFO L272 TraceCheckUtils]: 0: Hoare triple {136#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {142#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:54:14,408 INFO L290 TraceCheckUtils]: 1: Hoare triple {142#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {136#true} is VALID [2022-04-27 16:54:14,408 INFO L290 TraceCheckUtils]: 2: Hoare triple {136#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {136#true} is VALID [2022-04-27 16:54:14,409 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {136#true} {136#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {136#true} is VALID [2022-04-27 16:54:14,409 INFO L272 TraceCheckUtils]: 4: Hoare triple {136#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {136#true} is VALID [2022-04-27 16:54:14,409 INFO L290 TraceCheckUtils]: 5: Hoare triple {136#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {136#true} is VALID [2022-04-27 16:54:14,409 INFO L290 TraceCheckUtils]: 6: Hoare triple {136#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {136#true} is VALID [2022-04-27 16:54:14,410 INFO L290 TraceCheckUtils]: 7: Hoare triple {136#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {136#true} is VALID [2022-04-27 16:54:14,410 INFO L290 TraceCheckUtils]: 8: Hoare triple {136#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {136#true} is VALID [2022-04-27 16:54:14,411 INFO L290 TraceCheckUtils]: 9: Hoare triple {136#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {141#(= main_~v~0 0)} is VALID [2022-04-27 16:54:14,411 INFO L290 TraceCheckUtils]: 10: Hoare triple {141#(= main_~v~0 0)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {137#false} is VALID [2022-04-27 16:54:14,411 INFO L272 TraceCheckUtils]: 11: Hoare triple {137#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {137#false} is VALID [2022-04-27 16:54:14,412 INFO L290 TraceCheckUtils]: 12: Hoare triple {137#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {137#false} is VALID [2022-04-27 16:54:14,412 INFO L290 TraceCheckUtils]: 13: Hoare triple {137#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {137#false} is VALID [2022-04-27 16:54:14,412 INFO L290 TraceCheckUtils]: 14: Hoare triple {137#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {137#false} is VALID [2022-04-27 16:54:14,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:14,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:54:14,413 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1628280781] [2022-04-27 16:54:14,413 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1628280781] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 16:54:14,413 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 16:54:14,413 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 16:54:14,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461972752] [2022-04-27 16:54:14,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 16:54:14,415 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:54:14,415 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:14,415 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,430 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:14,430 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 16:54:14,430 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:14,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 16:54:14,431 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 16:54:14,431 INFO L87 Difference]: Start difference. First operand 23 states and 27 transitions. Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:14,569 INFO L93 Difference]: Finished difference Result 32 states and 39 transitions. [2022-04-27 16:54:14,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 16:54:14,569 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 16:54:14,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:54:14,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 40 transitions. [2022-04-27 16:54:14,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 40 transitions. [2022-04-27 16:54:14,581 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 40 transitions. [2022-04-27 16:54:14,631 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 40 edges. 40 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:14,635 INFO L225 Difference]: With dead ends: 32 [2022-04-27 16:54:14,635 INFO L226 Difference]: Without dead ends: 32 [2022-04-27 16:54:14,637 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 5 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 16:54:14,640 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 41 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 24 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 42 SdHoareTripleChecker+Valid, 31 SdHoareTripleChecker+Invalid, 28 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 24 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 16:54:14,641 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [42 Valid, 31 Invalid, 28 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 24 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 16:54:14,642 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2022-04-27 16:54:14,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 24. [2022-04-27 16:54:14,647 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:54:14,649 INFO L82 GeneralOperation]: Start isEquivalent. First operand 32 states. Second operand has 24 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 18 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,649 INFO L74 IsIncluded]: Start isIncluded. First operand 32 states. Second operand has 24 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 18 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,650 INFO L87 Difference]: Start difference. First operand 32 states. Second operand has 24 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 18 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:14,653 INFO L93 Difference]: Finished difference Result 32 states and 39 transitions. [2022-04-27 16:54:14,653 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 39 transitions. [2022-04-27 16:54:14,654 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:14,654 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:14,656 INFO L74 IsIncluded]: Start isIncluded. First operand has 24 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 18 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 32 states. [2022-04-27 16:54:14,658 INFO L87 Difference]: Start difference. First operand has 24 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 18 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 32 states. [2022-04-27 16:54:14,662 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:14,662 INFO L93 Difference]: Finished difference Result 32 states and 39 transitions. [2022-04-27 16:54:14,662 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 39 transitions. [2022-04-27 16:54:14,663 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:14,663 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:14,664 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:54:14,664 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:54:14,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 18 states have (on average 1.2777777777777777) internal successors, (23), 18 states have internal predecessors, (23), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:14,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 28 transitions. [2022-04-27 16:54:14,666 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 28 transitions. Word has length 15 [2022-04-27 16:54:14,666 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:54:14,667 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 28 transitions. [2022-04-27 16:54:14,667 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:14,667 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 28 transitions. [2022-04-27 16:54:14,667 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 16:54:14,667 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:54:14,668 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:54:14,668 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 16:54:14,668 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:54:14,669 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:54:14,669 INFO L85 PathProgramCache]: Analyzing trace with hash 1473809801, now seen corresponding path program 1 times [2022-04-27 16:54:14,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:54:14,669 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [221950034] [2022-04-27 16:54:14,669 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:14,670 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:54:14,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:14,796 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:54:14,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:14,819 INFO L290 TraceCheckUtils]: 0: Hoare triple {275#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {268#true} is VALID [2022-04-27 16:54:14,820 INFO L290 TraceCheckUtils]: 1: Hoare triple {268#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:14,820 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {268#true} {268#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:14,821 INFO L272 TraceCheckUtils]: 0: Hoare triple {268#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {275#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:54:14,821 INFO L290 TraceCheckUtils]: 1: Hoare triple {275#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {268#true} is VALID [2022-04-27 16:54:14,822 INFO L290 TraceCheckUtils]: 2: Hoare triple {268#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:14,823 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {268#true} {268#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:14,823 INFO L272 TraceCheckUtils]: 4: Hoare triple {268#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:14,823 INFO L290 TraceCheckUtils]: 5: Hoare triple {268#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {268#true} is VALID [2022-04-27 16:54:14,823 INFO L290 TraceCheckUtils]: 6: Hoare triple {268#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {268#true} is VALID [2022-04-27 16:54:14,824 INFO L290 TraceCheckUtils]: 7: Hoare triple {268#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {268#true} is VALID [2022-04-27 16:54:14,824 INFO L290 TraceCheckUtils]: 8: Hoare triple {268#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {268#true} is VALID [2022-04-27 16:54:14,827 INFO L290 TraceCheckUtils]: 9: Hoare triple {268#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {273#(= main_~v~0 0)} is VALID [2022-04-27 16:54:14,827 INFO L290 TraceCheckUtils]: 10: Hoare triple {273#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {273#(= main_~v~0 0)} is VALID [2022-04-27 16:54:14,830 INFO L290 TraceCheckUtils]: 11: Hoare triple {273#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {274#(and (<= main_~v~0 1) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:54:14,831 INFO L290 TraceCheckUtils]: 12: Hoare triple {274#(and (<= main_~v~0 1) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:14,831 INFO L272 TraceCheckUtils]: 13: Hoare triple {269#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {269#false} is VALID [2022-04-27 16:54:14,832 INFO L290 TraceCheckUtils]: 14: Hoare triple {269#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {269#false} is VALID [2022-04-27 16:54:14,832 INFO L290 TraceCheckUtils]: 15: Hoare triple {269#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:14,833 INFO L290 TraceCheckUtils]: 16: Hoare triple {269#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:14,834 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:14,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:54:14,835 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [221950034] [2022-04-27 16:54:14,836 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [221950034] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:54:14,837 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [245588179] [2022-04-27 16:54:14,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:14,837 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:54:14,837 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:54:14,847 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:54:14,861 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 16:54:14,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:14,898 INFO L263 TraceCheckSpWp]: Trace formula consists of 74 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 16:54:14,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:14,909 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:54:15,004 INFO L272 TraceCheckUtils]: 0: Hoare triple {268#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,004 INFO L290 TraceCheckUtils]: 1: Hoare triple {268#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {268#true} is VALID [2022-04-27 16:54:15,004 INFO L290 TraceCheckUtils]: 2: Hoare triple {268#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,005 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {268#true} {268#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,005 INFO L272 TraceCheckUtils]: 4: Hoare triple {268#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,005 INFO L290 TraceCheckUtils]: 5: Hoare triple {268#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {268#true} is VALID [2022-04-27 16:54:15,005 INFO L290 TraceCheckUtils]: 6: Hoare triple {268#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {268#true} is VALID [2022-04-27 16:54:15,005 INFO L290 TraceCheckUtils]: 7: Hoare triple {268#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {268#true} is VALID [2022-04-27 16:54:15,005 INFO L290 TraceCheckUtils]: 8: Hoare triple {268#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {268#true} is VALID [2022-04-27 16:54:15,007 INFO L290 TraceCheckUtils]: 9: Hoare triple {268#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {273#(= main_~v~0 0)} is VALID [2022-04-27 16:54:15,007 INFO L290 TraceCheckUtils]: 10: Hoare triple {273#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {273#(= main_~v~0 0)} is VALID [2022-04-27 16:54:15,009 INFO L290 TraceCheckUtils]: 11: Hoare triple {273#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {312#(= main_~v~0 1)} is VALID [2022-04-27 16:54:15,009 INFO L290 TraceCheckUtils]: 12: Hoare triple {312#(= main_~v~0 1)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:15,010 INFO L272 TraceCheckUtils]: 13: Hoare triple {269#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {269#false} is VALID [2022-04-27 16:54:15,010 INFO L290 TraceCheckUtils]: 14: Hoare triple {269#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {269#false} is VALID [2022-04-27 16:54:15,011 INFO L290 TraceCheckUtils]: 15: Hoare triple {269#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:15,012 INFO L290 TraceCheckUtils]: 16: Hoare triple {269#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:15,012 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:15,012 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:54:15,103 INFO L290 TraceCheckUtils]: 16: Hoare triple {269#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:15,103 INFO L290 TraceCheckUtils]: 15: Hoare triple {269#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:15,103 INFO L290 TraceCheckUtils]: 14: Hoare triple {269#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {269#false} is VALID [2022-04-27 16:54:15,103 INFO L272 TraceCheckUtils]: 13: Hoare triple {269#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {269#false} is VALID [2022-04-27 16:54:15,104 INFO L290 TraceCheckUtils]: 12: Hoare triple {340#(< (mod main_~v~0 4294967296) 268435455)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {269#false} is VALID [2022-04-27 16:54:15,105 INFO L290 TraceCheckUtils]: 11: Hoare triple {344#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {340#(< (mod main_~v~0 4294967296) 268435455)} is VALID [2022-04-27 16:54:15,105 INFO L290 TraceCheckUtils]: 10: Hoare triple {344#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {344#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:15,106 INFO L290 TraceCheckUtils]: 9: Hoare triple {268#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {344#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:15,106 INFO L290 TraceCheckUtils]: 8: Hoare triple {268#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {268#true} is VALID [2022-04-27 16:54:15,106 INFO L290 TraceCheckUtils]: 7: Hoare triple {268#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {268#true} is VALID [2022-04-27 16:54:15,106 INFO L290 TraceCheckUtils]: 6: Hoare triple {268#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {268#true} is VALID [2022-04-27 16:54:15,107 INFO L290 TraceCheckUtils]: 5: Hoare triple {268#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {268#true} is VALID [2022-04-27 16:54:15,107 INFO L272 TraceCheckUtils]: 4: Hoare triple {268#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,107 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {268#true} {268#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,108 INFO L290 TraceCheckUtils]: 2: Hoare triple {268#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,108 INFO L290 TraceCheckUtils]: 1: Hoare triple {268#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {268#true} is VALID [2022-04-27 16:54:15,108 INFO L272 TraceCheckUtils]: 0: Hoare triple {268#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {268#true} is VALID [2022-04-27 16:54:15,108 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:15,112 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [245588179] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:54:15,112 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:54:15,112 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-27 16:54:15,113 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [694042126] [2022-04-27 16:54:15,113 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:54:15,114 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:54:15,114 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:15,115 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:15,137 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:15,137 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 16:54:15,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:15,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 16:54:15,140 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2022-04-27 16:54:15,140 INFO L87 Difference]: Start difference. First operand 24 states and 28 transitions. Second operand has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:15,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:15,424 INFO L93 Difference]: Finished difference Result 37 states and 44 transitions. [2022-04-27 16:54:15,424 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 16:54:15,425 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 16:54:15,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:54:15,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:15,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 47 transitions. [2022-04-27 16:54:15,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:15,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 47 transitions. [2022-04-27 16:54:15,429 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 47 transitions. [2022-04-27 16:54:15,481 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:15,482 INFO L225 Difference]: With dead ends: 37 [2022-04-27 16:54:15,482 INFO L226 Difference]: Without dead ends: 37 [2022-04-27 16:54:15,483 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-04-27 16:54:15,483 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 56 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 79 mSolverCounterSat, 13 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 57 SdHoareTripleChecker+Valid, 41 SdHoareTripleChecker+Invalid, 92 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 13 IncrementalHoareTripleChecker+Valid, 79 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 16:54:15,484 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [57 Valid, 41 Invalid, 92 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [13 Valid, 79 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 16:54:15,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-27 16:54:15,487 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 30. [2022-04-27 16:54:15,487 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:54:15,487 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:15,487 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:15,488 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:15,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:15,489 INFO L93 Difference]: Finished difference Result 37 states and 44 transitions. [2022-04-27 16:54:15,490 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 44 transitions. [2022-04-27 16:54:15,490 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:15,490 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:15,490 INFO L74 IsIncluded]: Start isIncluded. First operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-27 16:54:15,491 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-27 16:54:15,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:15,492 INFO L93 Difference]: Finished difference Result 37 states and 44 transitions. [2022-04-27 16:54:15,493 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 44 transitions. [2022-04-27 16:54:15,493 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:15,493 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:15,493 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:54:15,493 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:54:15,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:15,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2022-04-27 16:54:15,495 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 17 [2022-04-27 16:54:15,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:54:15,495 INFO L495 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2022-04-27 16:54:15,495 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 2.5) internal successors, (20), 7 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:15,495 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2022-04-27 16:54:15,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 16:54:15,496 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:54:15,496 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:54:15,513 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 16:54:15,703 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:54:15,704 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:54:15,704 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:54:15,704 INFO L85 PathProgramCache]: Analyzing trace with hash -1878931933, now seen corresponding path program 2 times [2022-04-27 16:54:15,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:54:15,704 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534472047] [2022-04-27 16:54:15,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:15,710 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:54:15,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:15,877 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:54:15,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:15,887 INFO L290 TraceCheckUtils]: 0: Hoare triple {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {530#true} is VALID [2022-04-27 16:54:15,888 INFO L290 TraceCheckUtils]: 1: Hoare triple {530#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:15,888 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {530#true} {530#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:15,889 INFO L272 TraceCheckUtils]: 0: Hoare triple {530#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:54:15,889 INFO L290 TraceCheckUtils]: 1: Hoare triple {540#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {530#true} is VALID [2022-04-27 16:54:15,889 INFO L290 TraceCheckUtils]: 2: Hoare triple {530#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:15,889 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {530#true} {530#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:15,890 INFO L272 TraceCheckUtils]: 4: Hoare triple {530#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:15,891 INFO L290 TraceCheckUtils]: 5: Hoare triple {530#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {530#true} is VALID [2022-04-27 16:54:15,892 INFO L290 TraceCheckUtils]: 6: Hoare triple {530#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {530#true} is VALID [2022-04-27 16:54:15,892 INFO L290 TraceCheckUtils]: 7: Hoare triple {530#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {530#true} is VALID [2022-04-27 16:54:15,892 INFO L290 TraceCheckUtils]: 8: Hoare triple {530#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {530#true} is VALID [2022-04-27 16:54:15,896 INFO L290 TraceCheckUtils]: 9: Hoare triple {530#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {535#(= main_~v~0 0)} is VALID [2022-04-27 16:54:15,896 INFO L290 TraceCheckUtils]: 10: Hoare triple {535#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {535#(= main_~v~0 0)} is VALID [2022-04-27 16:54:15,897 INFO L290 TraceCheckUtils]: 11: Hoare triple {535#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:15,897 INFO L290 TraceCheckUtils]: 12: Hoare triple {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:15,898 INFO L290 TraceCheckUtils]: 13: Hoare triple {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:15,898 INFO L290 TraceCheckUtils]: 14: Hoare triple {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:15,899 INFO L290 TraceCheckUtils]: 15: Hoare triple {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:15,899 INFO L290 TraceCheckUtils]: 16: Hoare triple {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:15,900 INFO L290 TraceCheckUtils]: 17: Hoare triple {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {539#(and (<= main_~v~0 4) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:54:15,901 INFO L290 TraceCheckUtils]: 18: Hoare triple {539#(and (<= main_~v~0 4) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:15,901 INFO L272 TraceCheckUtils]: 19: Hoare triple {531#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {531#false} is VALID [2022-04-27 16:54:15,901 INFO L290 TraceCheckUtils]: 20: Hoare triple {531#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {531#false} is VALID [2022-04-27 16:54:15,901 INFO L290 TraceCheckUtils]: 21: Hoare triple {531#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:15,901 INFO L290 TraceCheckUtils]: 22: Hoare triple {531#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:15,902 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:15,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:54:15,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534472047] [2022-04-27 16:54:15,902 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534472047] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:54:15,902 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [726076589] [2022-04-27 16:54:15,902 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 16:54:15,902 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:54:15,903 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:54:15,904 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:54:15,909 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 16:54:15,953 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 16:54:15,953 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:54:15,954 INFO L263 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-27 16:54:15,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:15,970 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:54:16,215 INFO L272 TraceCheckUtils]: 0: Hoare triple {530#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,216 INFO L290 TraceCheckUtils]: 1: Hoare triple {530#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {530#true} is VALID [2022-04-27 16:54:16,216 INFO L290 TraceCheckUtils]: 2: Hoare triple {530#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,216 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {530#true} {530#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,217 INFO L272 TraceCheckUtils]: 4: Hoare triple {530#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,217 INFO L290 TraceCheckUtils]: 5: Hoare triple {530#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {530#true} is VALID [2022-04-27 16:54:16,217 INFO L290 TraceCheckUtils]: 6: Hoare triple {530#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {530#true} is VALID [2022-04-27 16:54:16,217 INFO L290 TraceCheckUtils]: 7: Hoare triple {530#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {530#true} is VALID [2022-04-27 16:54:16,217 INFO L290 TraceCheckUtils]: 8: Hoare triple {530#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {530#true} is VALID [2022-04-27 16:54:16,225 INFO L290 TraceCheckUtils]: 9: Hoare triple {530#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {535#(= main_~v~0 0)} is VALID [2022-04-27 16:54:16,225 INFO L290 TraceCheckUtils]: 10: Hoare triple {535#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {535#(= main_~v~0 0)} is VALID [2022-04-27 16:54:16,226 INFO L290 TraceCheckUtils]: 11: Hoare triple {535#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:16,226 INFO L290 TraceCheckUtils]: 12: Hoare triple {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:16,227 INFO L290 TraceCheckUtils]: 13: Hoare triple {536#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:16,228 INFO L290 TraceCheckUtils]: 14: Hoare triple {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:16,228 INFO L290 TraceCheckUtils]: 15: Hoare triple {537#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:16,229 INFO L290 TraceCheckUtils]: 16: Hoare triple {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:16,229 INFO L290 TraceCheckUtils]: 17: Hoare triple {538#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {595#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:16,230 INFO L290 TraceCheckUtils]: 18: Hoare triple {595#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:16,230 INFO L272 TraceCheckUtils]: 19: Hoare triple {531#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {531#false} is VALID [2022-04-27 16:54:16,230 INFO L290 TraceCheckUtils]: 20: Hoare triple {531#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {531#false} is VALID [2022-04-27 16:54:16,231 INFO L290 TraceCheckUtils]: 21: Hoare triple {531#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:16,231 INFO L290 TraceCheckUtils]: 22: Hoare triple {531#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:16,231 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:16,231 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:54:16,392 INFO L290 TraceCheckUtils]: 22: Hoare triple {531#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:16,392 INFO L290 TraceCheckUtils]: 21: Hoare triple {531#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:16,392 INFO L290 TraceCheckUtils]: 20: Hoare triple {531#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {531#false} is VALID [2022-04-27 16:54:16,392 INFO L272 TraceCheckUtils]: 19: Hoare triple {531#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {531#false} is VALID [2022-04-27 16:54:16,393 INFO L290 TraceCheckUtils]: 18: Hoare triple {623#(< (mod main_~v~0 4294967296) 268435455)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {531#false} is VALID [2022-04-27 16:54:16,393 INFO L290 TraceCheckUtils]: 17: Hoare triple {627#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {623#(< (mod main_~v~0 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,394 INFO L290 TraceCheckUtils]: 16: Hoare triple {627#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {627#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,394 INFO L290 TraceCheckUtils]: 15: Hoare triple {634#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {627#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,395 INFO L290 TraceCheckUtils]: 14: Hoare triple {634#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {634#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,395 INFO L290 TraceCheckUtils]: 13: Hoare triple {641#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {634#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,396 INFO L290 TraceCheckUtils]: 12: Hoare triple {641#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {641#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,396 INFO L290 TraceCheckUtils]: 11: Hoare triple {648#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {641#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,397 INFO L290 TraceCheckUtils]: 10: Hoare triple {648#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {648#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,398 INFO L290 TraceCheckUtils]: 9: Hoare triple {530#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {648#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:54:16,398 INFO L290 TraceCheckUtils]: 8: Hoare triple {530#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {530#true} is VALID [2022-04-27 16:54:16,398 INFO L290 TraceCheckUtils]: 7: Hoare triple {530#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {530#true} is VALID [2022-04-27 16:54:16,398 INFO L290 TraceCheckUtils]: 6: Hoare triple {530#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {530#true} is VALID [2022-04-27 16:54:16,398 INFO L290 TraceCheckUtils]: 5: Hoare triple {530#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {530#true} is VALID [2022-04-27 16:54:16,398 INFO L272 TraceCheckUtils]: 4: Hoare triple {530#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,398 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {530#true} {530#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,398 INFO L290 TraceCheckUtils]: 2: Hoare triple {530#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,399 INFO L290 TraceCheckUtils]: 1: Hoare triple {530#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {530#true} is VALID [2022-04-27 16:54:16,399 INFO L272 TraceCheckUtils]: 0: Hoare triple {530#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {530#true} is VALID [2022-04-27 16:54:16,399 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:16,399 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [726076589] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:54:16,399 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:54:16,399 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 16:54:16,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48260045] [2022-04-27 16:54:16,401 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:54:16,401 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 16:54:16,402 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:16,402 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:16,438 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:16,438 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 16:54:16,438 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:16,439 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 16:54:16,440 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2022-04-27 16:54:16,440 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:17,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:17,235 INFO L93 Difference]: Finished difference Result 49 states and 56 transitions. [2022-04-27 16:54:17,235 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 16:54:17,235 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 16:54:17,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:54:17,236 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:17,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 62 transitions. [2022-04-27 16:54:17,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:17,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 62 transitions. [2022-04-27 16:54:17,240 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 62 transitions. [2022-04-27 16:54:17,356 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 62 edges. 62 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:17,358 INFO L225 Difference]: With dead ends: 49 [2022-04-27 16:54:17,358 INFO L226 Difference]: Without dead ends: 49 [2022-04-27 16:54:17,358 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=175, Invalid=377, Unknown=0, NotChecked=0, Total=552 [2022-04-27 16:54:17,359 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 100 mSDsluCounter, 37 mSDsCounter, 0 mSdLazyCounter, 215 mSolverCounterSat, 34 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 101 SdHoareTripleChecker+Valid, 61 SdHoareTripleChecker+Invalid, 249 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 34 IncrementalHoareTripleChecker+Valid, 215 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 16:54:17,359 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [101 Valid, 61 Invalid, 249 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [34 Valid, 215 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 16:54:17,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2022-04-27 16:54:17,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 42. [2022-04-27 16:54:17,362 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:54:17,362 INFO L82 GeneralOperation]: Start isEquivalent. First operand 49 states. Second operand has 42 states, 36 states have (on average 1.1388888888888888) internal successors, (41), 36 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:17,363 INFO L74 IsIncluded]: Start isIncluded. First operand 49 states. Second operand has 42 states, 36 states have (on average 1.1388888888888888) internal successors, (41), 36 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:17,363 INFO L87 Difference]: Start difference. First operand 49 states. Second operand has 42 states, 36 states have (on average 1.1388888888888888) internal successors, (41), 36 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:17,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:17,365 INFO L93 Difference]: Finished difference Result 49 states and 56 transitions. [2022-04-27 16:54:17,365 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 56 transitions. [2022-04-27 16:54:17,365 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:17,365 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:17,365 INFO L74 IsIncluded]: Start isIncluded. First operand has 42 states, 36 states have (on average 1.1388888888888888) internal successors, (41), 36 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 49 states. [2022-04-27 16:54:17,366 INFO L87 Difference]: Start difference. First operand has 42 states, 36 states have (on average 1.1388888888888888) internal successors, (41), 36 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 49 states. [2022-04-27 16:54:17,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:17,367 INFO L93 Difference]: Finished difference Result 49 states and 56 transitions. [2022-04-27 16:54:17,368 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 56 transitions. [2022-04-27 16:54:17,371 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:17,371 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:17,371 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:54:17,371 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:54:17,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 36 states have (on average 1.1388888888888888) internal successors, (41), 36 states have internal predecessors, (41), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:17,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 46 transitions. [2022-04-27 16:54:17,373 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 46 transitions. Word has length 23 [2022-04-27 16:54:17,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:54:17,373 INFO L495 AbstractCegarLoop]: Abstraction has 42 states and 46 transitions. [2022-04-27 16:54:17,373 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.2857142857142856) internal successors, (32), 13 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:17,373 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2022-04-27 16:54:17,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2022-04-27 16:54:17,374 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:54:17,374 INFO L195 NwaCegarLoop]: trace histogram [10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:54:17,399 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 16:54:17,574 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 16:54:17,575 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:54:17,575 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:54:17,575 INFO L85 PathProgramCache]: Analyzing trace with hash -607664937, now seen corresponding path program 3 times [2022-04-27 16:54:17,576 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:54:17,576 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [203905102] [2022-04-27 16:54:17,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:17,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:54:17,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:17,852 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:54:17,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:17,858 INFO L290 TraceCheckUtils]: 0: Hoare triple {910#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {894#true} is VALID [2022-04-27 16:54:17,858 INFO L290 TraceCheckUtils]: 1: Hoare triple {894#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:17,858 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {894#true} {894#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:17,859 INFO L272 TraceCheckUtils]: 0: Hoare triple {894#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {910#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:54:17,859 INFO L290 TraceCheckUtils]: 1: Hoare triple {910#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {894#true} is VALID [2022-04-27 16:54:17,859 INFO L290 TraceCheckUtils]: 2: Hoare triple {894#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:17,859 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {894#true} {894#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:17,859 INFO L272 TraceCheckUtils]: 4: Hoare triple {894#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:17,860 INFO L290 TraceCheckUtils]: 5: Hoare triple {894#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {894#true} is VALID [2022-04-27 16:54:17,860 INFO L290 TraceCheckUtils]: 6: Hoare triple {894#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {894#true} is VALID [2022-04-27 16:54:17,860 INFO L290 TraceCheckUtils]: 7: Hoare triple {894#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {894#true} is VALID [2022-04-27 16:54:17,860 INFO L290 TraceCheckUtils]: 8: Hoare triple {894#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {894#true} is VALID [2022-04-27 16:54:17,861 INFO L290 TraceCheckUtils]: 9: Hoare triple {894#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {899#(= main_~v~0 0)} is VALID [2022-04-27 16:54:17,861 INFO L290 TraceCheckUtils]: 10: Hoare triple {899#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {899#(= main_~v~0 0)} is VALID [2022-04-27 16:54:17,862 INFO L290 TraceCheckUtils]: 11: Hoare triple {899#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:17,862 INFO L290 TraceCheckUtils]: 12: Hoare triple {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:17,863 INFO L290 TraceCheckUtils]: 13: Hoare triple {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:17,863 INFO L290 TraceCheckUtils]: 14: Hoare triple {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:17,864 INFO L290 TraceCheckUtils]: 15: Hoare triple {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:17,864 INFO L290 TraceCheckUtils]: 16: Hoare triple {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:17,865 INFO L290 TraceCheckUtils]: 17: Hoare triple {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:17,866 INFO L290 TraceCheckUtils]: 18: Hoare triple {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:17,866 INFO L290 TraceCheckUtils]: 19: Hoare triple {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:17,872 INFO L290 TraceCheckUtils]: 20: Hoare triple {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:17,872 INFO L290 TraceCheckUtils]: 21: Hoare triple {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:17,873 INFO L290 TraceCheckUtils]: 22: Hoare triple {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:17,873 INFO L290 TraceCheckUtils]: 23: Hoare triple {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:17,874 INFO L290 TraceCheckUtils]: 24: Hoare triple {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:17,874 INFO L290 TraceCheckUtils]: 25: Hoare triple {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:17,875 INFO L290 TraceCheckUtils]: 26: Hoare triple {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:17,875 INFO L290 TraceCheckUtils]: 27: Hoare triple {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:17,876 INFO L290 TraceCheckUtils]: 28: Hoare triple {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:17,876 INFO L290 TraceCheckUtils]: 29: Hoare triple {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {909#(and (<= main_~v~0 10) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:54:17,877 INFO L290 TraceCheckUtils]: 30: Hoare triple {909#(and (<= main_~v~0 10) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:17,877 INFO L272 TraceCheckUtils]: 31: Hoare triple {895#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {895#false} is VALID [2022-04-27 16:54:17,877 INFO L290 TraceCheckUtils]: 32: Hoare triple {895#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {895#false} is VALID [2022-04-27 16:54:17,877 INFO L290 TraceCheckUtils]: 33: Hoare triple {895#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:17,878 INFO L290 TraceCheckUtils]: 34: Hoare triple {895#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:17,878 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:17,878 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:54:17,878 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [203905102] [2022-04-27 16:54:17,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [203905102] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:54:17,879 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1682350582] [2022-04-27 16:54:17,879 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 16:54:17,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:54:17,879 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:54:17,880 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:54:17,905 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 16:54:17,944 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-04-27 16:54:17,944 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:54:17,945 INFO L263 TraceCheckSpWp]: Trace formula consists of 101 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-27 16:54:17,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:17,957 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:54:18,334 INFO L272 TraceCheckUtils]: 0: Hoare triple {894#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,335 INFO L290 TraceCheckUtils]: 1: Hoare triple {894#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {894#true} is VALID [2022-04-27 16:54:18,335 INFO L290 TraceCheckUtils]: 2: Hoare triple {894#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,335 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {894#true} {894#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,335 INFO L272 TraceCheckUtils]: 4: Hoare triple {894#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,335 INFO L290 TraceCheckUtils]: 5: Hoare triple {894#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {894#true} is VALID [2022-04-27 16:54:18,335 INFO L290 TraceCheckUtils]: 6: Hoare triple {894#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {894#true} is VALID [2022-04-27 16:54:18,336 INFO L290 TraceCheckUtils]: 7: Hoare triple {894#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {894#true} is VALID [2022-04-27 16:54:18,336 INFO L290 TraceCheckUtils]: 8: Hoare triple {894#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {894#true} is VALID [2022-04-27 16:54:18,336 INFO L290 TraceCheckUtils]: 9: Hoare triple {894#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {899#(= main_~v~0 0)} is VALID [2022-04-27 16:54:18,336 INFO L290 TraceCheckUtils]: 10: Hoare triple {899#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {899#(= main_~v~0 0)} is VALID [2022-04-27 16:54:18,337 INFO L290 TraceCheckUtils]: 11: Hoare triple {899#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:18,337 INFO L290 TraceCheckUtils]: 12: Hoare triple {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:18,338 INFO L290 TraceCheckUtils]: 13: Hoare triple {900#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:18,339 INFO L290 TraceCheckUtils]: 14: Hoare triple {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:18,339 INFO L290 TraceCheckUtils]: 15: Hoare triple {901#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:18,340 INFO L290 TraceCheckUtils]: 16: Hoare triple {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:18,340 INFO L290 TraceCheckUtils]: 17: Hoare triple {902#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:18,341 INFO L290 TraceCheckUtils]: 18: Hoare triple {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:18,341 INFO L290 TraceCheckUtils]: 19: Hoare triple {903#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:18,342 INFO L290 TraceCheckUtils]: 20: Hoare triple {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:18,342 INFO L290 TraceCheckUtils]: 21: Hoare triple {904#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:18,343 INFO L290 TraceCheckUtils]: 22: Hoare triple {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:18,343 INFO L290 TraceCheckUtils]: 23: Hoare triple {905#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:18,344 INFO L290 TraceCheckUtils]: 24: Hoare triple {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:18,344 INFO L290 TraceCheckUtils]: 25: Hoare triple {906#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:18,345 INFO L290 TraceCheckUtils]: 26: Hoare triple {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:18,345 INFO L290 TraceCheckUtils]: 27: Hoare triple {907#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:18,346 INFO L290 TraceCheckUtils]: 28: Hoare triple {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:18,346 INFO L290 TraceCheckUtils]: 29: Hoare triple {908#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1001#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:54:18,347 INFO L290 TraceCheckUtils]: 30: Hoare triple {1001#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:18,347 INFO L272 TraceCheckUtils]: 31: Hoare triple {895#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {895#false} is VALID [2022-04-27 16:54:18,347 INFO L290 TraceCheckUtils]: 32: Hoare triple {895#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {895#false} is VALID [2022-04-27 16:54:18,348 INFO L290 TraceCheckUtils]: 33: Hoare triple {895#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:18,348 INFO L290 TraceCheckUtils]: 34: Hoare triple {895#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:18,349 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:18,349 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:54:18,748 INFO L290 TraceCheckUtils]: 34: Hoare triple {895#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:18,748 INFO L290 TraceCheckUtils]: 33: Hoare triple {895#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:18,748 INFO L290 TraceCheckUtils]: 32: Hoare triple {895#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {895#false} is VALID [2022-04-27 16:54:18,748 INFO L272 TraceCheckUtils]: 31: Hoare triple {895#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {895#false} is VALID [2022-04-27 16:54:18,748 INFO L290 TraceCheckUtils]: 30: Hoare triple {1029#(< (mod main_~v~0 4294967296) 268435455)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {895#false} is VALID [2022-04-27 16:54:18,749 INFO L290 TraceCheckUtils]: 29: Hoare triple {1033#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1029#(< (mod main_~v~0 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,749 INFO L290 TraceCheckUtils]: 28: Hoare triple {1033#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1033#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,750 INFO L290 TraceCheckUtils]: 27: Hoare triple {1040#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1033#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,751 INFO L290 TraceCheckUtils]: 26: Hoare triple {1040#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1040#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,751 INFO L290 TraceCheckUtils]: 25: Hoare triple {1047#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1040#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,752 INFO L290 TraceCheckUtils]: 24: Hoare triple {1047#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1047#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,752 INFO L290 TraceCheckUtils]: 23: Hoare triple {1054#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1047#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,753 INFO L290 TraceCheckUtils]: 22: Hoare triple {1054#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1054#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,754 INFO L290 TraceCheckUtils]: 21: Hoare triple {1061#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1054#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,754 INFO L290 TraceCheckUtils]: 20: Hoare triple {1061#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1061#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,755 INFO L290 TraceCheckUtils]: 19: Hoare triple {1068#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1061#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,755 INFO L290 TraceCheckUtils]: 18: Hoare triple {1068#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1068#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,756 INFO L290 TraceCheckUtils]: 17: Hoare triple {1075#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1068#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,756 INFO L290 TraceCheckUtils]: 16: Hoare triple {1075#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1075#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,757 INFO L290 TraceCheckUtils]: 15: Hoare triple {1082#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1075#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,757 INFO L290 TraceCheckUtils]: 14: Hoare triple {1082#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1082#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,758 INFO L290 TraceCheckUtils]: 13: Hoare triple {1089#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1082#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,758 INFO L290 TraceCheckUtils]: 12: Hoare triple {1089#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1089#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,759 INFO L290 TraceCheckUtils]: 11: Hoare triple {1096#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1089#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,759 INFO L290 TraceCheckUtils]: 10: Hoare triple {1096#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1096#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,760 INFO L290 TraceCheckUtils]: 9: Hoare triple {894#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {1096#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} is VALID [2022-04-27 16:54:18,760 INFO L290 TraceCheckUtils]: 8: Hoare triple {894#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {894#true} is VALID [2022-04-27 16:54:18,760 INFO L290 TraceCheckUtils]: 7: Hoare triple {894#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {894#true} is VALID [2022-04-27 16:54:18,760 INFO L290 TraceCheckUtils]: 6: Hoare triple {894#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {894#true} is VALID [2022-04-27 16:54:18,760 INFO L290 TraceCheckUtils]: 5: Hoare triple {894#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {894#true} is VALID [2022-04-27 16:54:18,761 INFO L272 TraceCheckUtils]: 4: Hoare triple {894#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,761 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {894#true} {894#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,761 INFO L290 TraceCheckUtils]: 2: Hoare triple {894#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,761 INFO L290 TraceCheckUtils]: 1: Hoare triple {894#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {894#true} is VALID [2022-04-27 16:54:18,761 INFO L272 TraceCheckUtils]: 0: Hoare triple {894#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {894#true} is VALID [2022-04-27 16:54:18,761 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:18,761 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1682350582] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:54:18,761 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:54:18,762 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2022-04-27 16:54:18,762 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1068847300] [2022-04-27 16:54:18,762 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:54:18,762 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-27 16:54:18,763 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:18,763 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:18,816 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:18,816 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-04-27 16:54:18,816 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:18,817 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-04-27 16:54:18,817 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=458, Unknown=0, NotChecked=0, Total=650 [2022-04-27 16:54:18,817 INFO L87 Difference]: Start difference. First operand 42 states and 46 transitions. Second operand has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:23,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:23,542 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2022-04-27 16:54:23,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-04-27 16:54:23,542 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-27 16:54:23,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:54:23,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:23,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 92 transitions. [2022-04-27 16:54:23,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:23,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 92 transitions. [2022-04-27 16:54:23,547 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 25 states and 92 transitions. [2022-04-27 16:54:23,639 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 92 edges. 92 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:23,640 INFO L225 Difference]: With dead ends: 73 [2022-04-27 16:54:23,640 INFO L226 Difference]: Without dead ends: 73 [2022-04-27 16:54:23,641 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 61 SyntacticMatches, 1 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=643, Invalid=1613, Unknown=0, NotChecked=0, Total=2256 [2022-04-27 16:54:23,642 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 92 mSDsluCounter, 62 mSDsCounter, 0 mSdLazyCounter, 583 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 93 SdHoareTripleChecker+Valid, 86 SdHoareTripleChecker+Invalid, 623 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 583 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-04-27 16:54:23,642 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [93 Valid, 86 Invalid, 623 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 583 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-04-27 16:54:23,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2022-04-27 16:54:23,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 66. [2022-04-27 16:54:23,646 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:54:23,646 INFO L82 GeneralOperation]: Start isEquivalent. First operand 73 states. Second operand has 66 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 60 states have internal predecessors, (65), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:23,647 INFO L74 IsIncluded]: Start isIncluded. First operand 73 states. Second operand has 66 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 60 states have internal predecessors, (65), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:23,647 INFO L87 Difference]: Start difference. First operand 73 states. Second operand has 66 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 60 states have internal predecessors, (65), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:23,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:23,649 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2022-04-27 16:54:23,649 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions. [2022-04-27 16:54:23,650 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:23,650 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:23,650 INFO L74 IsIncluded]: Start isIncluded. First operand has 66 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 60 states have internal predecessors, (65), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 73 states. [2022-04-27 16:54:23,650 INFO L87 Difference]: Start difference. First operand has 66 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 60 states have internal predecessors, (65), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 73 states. [2022-04-27 16:54:23,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:54:23,653 INFO L93 Difference]: Finished difference Result 73 states and 80 transitions. [2022-04-27 16:54:23,653 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 80 transitions. [2022-04-27 16:54:23,653 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:54:23,653 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:54:23,653 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:54:23,653 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:54:23,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 60 states have (on average 1.0833333333333333) internal successors, (65), 60 states have internal predecessors, (65), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:54:23,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 70 transitions. [2022-04-27 16:54:23,656 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 70 transitions. Word has length 35 [2022-04-27 16:54:23,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:54:23,656 INFO L495 AbstractCegarLoop]: Abstraction has 66 states and 70 transitions. [2022-04-27 16:54:23,656 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 2.1538461538461537) internal successors, (56), 25 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:23,656 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 70 transitions. [2022-04-27 16:54:23,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2022-04-27 16:54:23,657 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:54:23,657 INFO L195 NwaCegarLoop]: trace histogram [22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:54:23,677 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 16:54:23,875 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:54:23,876 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:54:23,876 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:54:23,876 INFO L85 PathProgramCache]: Analyzing trace with hash -943491009, now seen corresponding path program 4 times [2022-04-27 16:54:23,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:54:23,876 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1646964711] [2022-04-27 16:54:23,876 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:54:23,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:54:23,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:24,432 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:54:24,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:24,441 INFO L290 TraceCheckUtils]: 0: Hoare triple {1490#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1462#true} is VALID [2022-04-27 16:54:24,441 INFO L290 TraceCheckUtils]: 1: Hoare triple {1462#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:24,442 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1462#true} {1462#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:24,442 INFO L272 TraceCheckUtils]: 0: Hoare triple {1462#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1490#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:54:24,442 INFO L290 TraceCheckUtils]: 1: Hoare triple {1490#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L290 TraceCheckUtils]: 2: Hoare triple {1462#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1462#true} {1462#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L272 TraceCheckUtils]: 4: Hoare triple {1462#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L290 TraceCheckUtils]: 5: Hoare triple {1462#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L290 TraceCheckUtils]: 6: Hoare triple {1462#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L290 TraceCheckUtils]: 7: Hoare triple {1462#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {1462#true} is VALID [2022-04-27 16:54:24,443 INFO L290 TraceCheckUtils]: 8: Hoare triple {1462#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1462#true} is VALID [2022-04-27 16:54:24,444 INFO L290 TraceCheckUtils]: 9: Hoare triple {1462#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {1467#(= main_~v~0 0)} is VALID [2022-04-27 16:54:24,444 INFO L290 TraceCheckUtils]: 10: Hoare triple {1467#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1467#(= main_~v~0 0)} is VALID [2022-04-27 16:54:24,444 INFO L290 TraceCheckUtils]: 11: Hoare triple {1467#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:24,445 INFO L290 TraceCheckUtils]: 12: Hoare triple {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:24,445 INFO L290 TraceCheckUtils]: 13: Hoare triple {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:24,446 INFO L290 TraceCheckUtils]: 14: Hoare triple {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:24,446 INFO L290 TraceCheckUtils]: 15: Hoare triple {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:24,447 INFO L290 TraceCheckUtils]: 16: Hoare triple {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:24,447 INFO L290 TraceCheckUtils]: 17: Hoare triple {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:24,448 INFO L290 TraceCheckUtils]: 18: Hoare triple {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:24,448 INFO L290 TraceCheckUtils]: 19: Hoare triple {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:24,449 INFO L290 TraceCheckUtils]: 20: Hoare triple {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:24,449 INFO L290 TraceCheckUtils]: 21: Hoare triple {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:24,450 INFO L290 TraceCheckUtils]: 22: Hoare triple {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:24,450 INFO L290 TraceCheckUtils]: 23: Hoare triple {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:24,451 INFO L290 TraceCheckUtils]: 24: Hoare triple {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:24,451 INFO L290 TraceCheckUtils]: 25: Hoare triple {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:24,452 INFO L290 TraceCheckUtils]: 26: Hoare triple {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:24,452 INFO L290 TraceCheckUtils]: 27: Hoare triple {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:24,453 INFO L290 TraceCheckUtils]: 28: Hoare triple {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:24,453 INFO L290 TraceCheckUtils]: 29: Hoare triple {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:54:24,454 INFO L290 TraceCheckUtils]: 30: Hoare triple {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:54:24,455 INFO L290 TraceCheckUtils]: 31: Hoare triple {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:54:24,455 INFO L290 TraceCheckUtils]: 32: Hoare triple {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:54:24,456 INFO L290 TraceCheckUtils]: 33: Hoare triple {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:54:24,456 INFO L290 TraceCheckUtils]: 34: Hoare triple {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:54:24,457 INFO L290 TraceCheckUtils]: 35: Hoare triple {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:54:24,457 INFO L290 TraceCheckUtils]: 36: Hoare triple {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:54:24,458 INFO L290 TraceCheckUtils]: 37: Hoare triple {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:54:24,458 INFO L290 TraceCheckUtils]: 38: Hoare triple {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:54:24,459 INFO L290 TraceCheckUtils]: 39: Hoare triple {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:54:24,460 INFO L290 TraceCheckUtils]: 40: Hoare triple {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:54:24,460 INFO L290 TraceCheckUtils]: 41: Hoare triple {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:54:24,461 INFO L290 TraceCheckUtils]: 42: Hoare triple {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:54:24,461 INFO L290 TraceCheckUtils]: 43: Hoare triple {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:54:24,462 INFO L290 TraceCheckUtils]: 44: Hoare triple {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:54:24,462 INFO L290 TraceCheckUtils]: 45: Hoare triple {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:54:24,463 INFO L290 TraceCheckUtils]: 46: Hoare triple {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:54:24,463 INFO L290 TraceCheckUtils]: 47: Hoare triple {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:54:24,464 INFO L290 TraceCheckUtils]: 48: Hoare triple {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:54:24,464 INFO L290 TraceCheckUtils]: 49: Hoare triple {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:54:24,465 INFO L290 TraceCheckUtils]: 50: Hoare triple {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:54:24,465 INFO L290 TraceCheckUtils]: 51: Hoare triple {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:54:24,466 INFO L290 TraceCheckUtils]: 52: Hoare triple {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:54:24,466 INFO L290 TraceCheckUtils]: 53: Hoare triple {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1489#(and (<= main_~v~0 22) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} is VALID [2022-04-27 16:54:24,467 INFO L290 TraceCheckUtils]: 54: Hoare triple {1489#(and (<= main_~v~0 22) (not (<= (+ (div main_~v~0 4294967296) 1) 0)))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:24,467 INFO L272 TraceCheckUtils]: 55: Hoare triple {1463#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {1463#false} is VALID [2022-04-27 16:54:24,467 INFO L290 TraceCheckUtils]: 56: Hoare triple {1463#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1463#false} is VALID [2022-04-27 16:54:24,467 INFO L290 TraceCheckUtils]: 57: Hoare triple {1463#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:24,467 INFO L290 TraceCheckUtils]: 58: Hoare triple {1463#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:24,468 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:24,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:54:24,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1646964711] [2022-04-27 16:54:24,468 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1646964711] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:54:24,468 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [13405187] [2022-04-27 16:54:24,468 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 16:54:24,469 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:54:24,469 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:54:24,472 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:54:24,496 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 16:54:24,565 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 16:54:24,565 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:54:24,566 INFO L263 TraceCheckSpWp]: Trace formula consists of 137 conjuncts, 47 conjunts are in the unsatisfiable core [2022-04-27 16:54:24,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:54:24,583 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:54:25,229 INFO L272 TraceCheckUtils]: 0: Hoare triple {1462#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:25,229 INFO L290 TraceCheckUtils]: 1: Hoare triple {1462#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1462#true} is VALID [2022-04-27 16:54:25,229 INFO L290 TraceCheckUtils]: 2: Hoare triple {1462#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:25,229 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1462#true} {1462#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:25,230 INFO L272 TraceCheckUtils]: 4: Hoare triple {1462#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:25,230 INFO L290 TraceCheckUtils]: 5: Hoare triple {1462#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1462#true} is VALID [2022-04-27 16:54:25,230 INFO L290 TraceCheckUtils]: 6: Hoare triple {1462#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {1462#true} is VALID [2022-04-27 16:54:25,230 INFO L290 TraceCheckUtils]: 7: Hoare triple {1462#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {1462#true} is VALID [2022-04-27 16:54:25,230 INFO L290 TraceCheckUtils]: 8: Hoare triple {1462#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1462#true} is VALID [2022-04-27 16:54:25,232 INFO L290 TraceCheckUtils]: 9: Hoare triple {1462#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {1467#(= main_~v~0 0)} is VALID [2022-04-27 16:54:25,232 INFO L290 TraceCheckUtils]: 10: Hoare triple {1467#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1467#(= main_~v~0 0)} is VALID [2022-04-27 16:54:25,233 INFO L290 TraceCheckUtils]: 11: Hoare triple {1467#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:25,233 INFO L290 TraceCheckUtils]: 12: Hoare triple {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:54:25,234 INFO L290 TraceCheckUtils]: 13: Hoare triple {1468#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:25,234 INFO L290 TraceCheckUtils]: 14: Hoare triple {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:54:25,234 INFO L290 TraceCheckUtils]: 15: Hoare triple {1469#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:25,235 INFO L290 TraceCheckUtils]: 16: Hoare triple {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:54:25,235 INFO L290 TraceCheckUtils]: 17: Hoare triple {1470#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:25,236 INFO L290 TraceCheckUtils]: 18: Hoare triple {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:54:25,236 INFO L290 TraceCheckUtils]: 19: Hoare triple {1471#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:25,236 INFO L290 TraceCheckUtils]: 20: Hoare triple {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:54:25,237 INFO L290 TraceCheckUtils]: 21: Hoare triple {1472#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:25,237 INFO L290 TraceCheckUtils]: 22: Hoare triple {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:54:25,238 INFO L290 TraceCheckUtils]: 23: Hoare triple {1473#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:25,238 INFO L290 TraceCheckUtils]: 24: Hoare triple {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:54:25,238 INFO L290 TraceCheckUtils]: 25: Hoare triple {1474#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:25,239 INFO L290 TraceCheckUtils]: 26: Hoare triple {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:54:25,239 INFO L290 TraceCheckUtils]: 27: Hoare triple {1475#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:25,240 INFO L290 TraceCheckUtils]: 28: Hoare triple {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:54:25,240 INFO L290 TraceCheckUtils]: 29: Hoare triple {1476#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:54:25,240 INFO L290 TraceCheckUtils]: 30: Hoare triple {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:54:25,241 INFO L290 TraceCheckUtils]: 31: Hoare triple {1477#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:54:25,241 INFO L290 TraceCheckUtils]: 32: Hoare triple {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:54:25,242 INFO L290 TraceCheckUtils]: 33: Hoare triple {1478#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:54:25,242 INFO L290 TraceCheckUtils]: 34: Hoare triple {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:54:25,243 INFO L290 TraceCheckUtils]: 35: Hoare triple {1479#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:54:25,243 INFO L290 TraceCheckUtils]: 36: Hoare triple {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:54:25,243 INFO L290 TraceCheckUtils]: 37: Hoare triple {1480#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:54:25,244 INFO L290 TraceCheckUtils]: 38: Hoare triple {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:54:25,244 INFO L290 TraceCheckUtils]: 39: Hoare triple {1481#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:54:25,245 INFO L290 TraceCheckUtils]: 40: Hoare triple {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:54:25,245 INFO L290 TraceCheckUtils]: 41: Hoare triple {1482#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:54:25,245 INFO L290 TraceCheckUtils]: 42: Hoare triple {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:54:25,247 INFO L290 TraceCheckUtils]: 43: Hoare triple {1483#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:54:25,250 INFO L290 TraceCheckUtils]: 44: Hoare triple {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:54:25,255 INFO L290 TraceCheckUtils]: 45: Hoare triple {1484#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:54:25,256 INFO L290 TraceCheckUtils]: 46: Hoare triple {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:54:25,257 INFO L290 TraceCheckUtils]: 47: Hoare triple {1485#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:54:25,257 INFO L290 TraceCheckUtils]: 48: Hoare triple {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:54:25,258 INFO L290 TraceCheckUtils]: 49: Hoare triple {1486#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:54:25,263 INFO L290 TraceCheckUtils]: 50: Hoare triple {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:54:25,263 INFO L290 TraceCheckUtils]: 51: Hoare triple {1487#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:54:25,264 INFO L290 TraceCheckUtils]: 52: Hoare triple {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:54:25,265 INFO L290 TraceCheckUtils]: 53: Hoare triple {1488#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1653#(and (<= 22 main_~v~0) (<= main_~v~0 22))} is VALID [2022-04-27 16:54:25,265 INFO L290 TraceCheckUtils]: 54: Hoare triple {1653#(and (<= 22 main_~v~0) (<= main_~v~0 22))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:25,265 INFO L272 TraceCheckUtils]: 55: Hoare triple {1463#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {1463#false} is VALID [2022-04-27 16:54:25,265 INFO L290 TraceCheckUtils]: 56: Hoare triple {1463#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1463#false} is VALID [2022-04-27 16:54:25,266 INFO L290 TraceCheckUtils]: 57: Hoare triple {1463#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:25,266 INFO L290 TraceCheckUtils]: 58: Hoare triple {1463#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:25,266 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:25,266 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:54:26,379 INFO L290 TraceCheckUtils]: 58: Hoare triple {1463#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:26,380 INFO L290 TraceCheckUtils]: 57: Hoare triple {1463#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:26,380 INFO L290 TraceCheckUtils]: 56: Hoare triple {1463#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1463#false} is VALID [2022-04-27 16:54:26,380 INFO L272 TraceCheckUtils]: 55: Hoare triple {1463#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {1463#false} is VALID [2022-04-27 16:54:26,380 INFO L290 TraceCheckUtils]: 54: Hoare triple {1681#(< (mod main_~v~0 4294967296) 268435455)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {1463#false} is VALID [2022-04-27 16:54:26,381 INFO L290 TraceCheckUtils]: 53: Hoare triple {1685#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1681#(< (mod main_~v~0 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,381 INFO L290 TraceCheckUtils]: 52: Hoare triple {1685#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1685#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,382 INFO L290 TraceCheckUtils]: 51: Hoare triple {1692#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1685#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,382 INFO L290 TraceCheckUtils]: 50: Hoare triple {1692#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1692#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,382 INFO L290 TraceCheckUtils]: 49: Hoare triple {1699#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1692#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,383 INFO L290 TraceCheckUtils]: 48: Hoare triple {1699#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1699#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,383 INFO L290 TraceCheckUtils]: 47: Hoare triple {1706#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1699#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,384 INFO L290 TraceCheckUtils]: 46: Hoare triple {1706#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1706#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,384 INFO L290 TraceCheckUtils]: 45: Hoare triple {1713#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1706#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,387 INFO L290 TraceCheckUtils]: 44: Hoare triple {1713#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1713#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,388 INFO L290 TraceCheckUtils]: 43: Hoare triple {1720#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1713#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,388 INFO L290 TraceCheckUtils]: 42: Hoare triple {1720#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1720#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,388 INFO L290 TraceCheckUtils]: 41: Hoare triple {1727#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1720#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,389 INFO L290 TraceCheckUtils]: 40: Hoare triple {1727#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1727#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,389 INFO L290 TraceCheckUtils]: 39: Hoare triple {1734#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1727#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,390 INFO L290 TraceCheckUtils]: 38: Hoare triple {1734#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1734#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,391 INFO L290 TraceCheckUtils]: 37: Hoare triple {1741#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1734#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,391 INFO L290 TraceCheckUtils]: 36: Hoare triple {1741#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1741#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,392 INFO L290 TraceCheckUtils]: 35: Hoare triple {1748#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1741#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,393 INFO L290 TraceCheckUtils]: 34: Hoare triple {1748#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1748#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,393 INFO L290 TraceCheckUtils]: 33: Hoare triple {1755#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1748#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,393 INFO L290 TraceCheckUtils]: 32: Hoare triple {1755#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1755#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,402 INFO L290 TraceCheckUtils]: 31: Hoare triple {1762#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1755#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,402 INFO L290 TraceCheckUtils]: 30: Hoare triple {1762#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1762#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,403 INFO L290 TraceCheckUtils]: 29: Hoare triple {1769#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1762#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,403 INFO L290 TraceCheckUtils]: 28: Hoare triple {1769#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1769#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,404 INFO L290 TraceCheckUtils]: 27: Hoare triple {1776#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1769#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,404 INFO L290 TraceCheckUtils]: 26: Hoare triple {1776#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1776#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,405 INFO L290 TraceCheckUtils]: 25: Hoare triple {1783#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1776#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,405 INFO L290 TraceCheckUtils]: 24: Hoare triple {1783#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1783#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,406 INFO L290 TraceCheckUtils]: 23: Hoare triple {1790#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1783#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,406 INFO L290 TraceCheckUtils]: 22: Hoare triple {1790#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1790#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,407 INFO L290 TraceCheckUtils]: 21: Hoare triple {1797#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1790#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,407 INFO L290 TraceCheckUtils]: 20: Hoare triple {1797#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1797#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,408 INFO L290 TraceCheckUtils]: 19: Hoare triple {1804#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1797#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,408 INFO L290 TraceCheckUtils]: 18: Hoare triple {1804#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1804#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,409 INFO L290 TraceCheckUtils]: 17: Hoare triple {1811#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1804#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,409 INFO L290 TraceCheckUtils]: 16: Hoare triple {1811#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1811#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,410 INFO L290 TraceCheckUtils]: 15: Hoare triple {1818#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1811#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,410 INFO L290 TraceCheckUtils]: 14: Hoare triple {1818#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1818#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,411 INFO L290 TraceCheckUtils]: 13: Hoare triple {1825#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1818#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,412 INFO L290 TraceCheckUtils]: 12: Hoare triple {1825#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1825#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,413 INFO L290 TraceCheckUtils]: 11: Hoare triple {1832#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {1825#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,413 INFO L290 TraceCheckUtils]: 10: Hoare triple {1832#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {1832#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 9: Hoare triple {1462#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {1832#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 8: Hoare triple {1462#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 7: Hoare triple {1462#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 6: Hoare triple {1462#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 5: Hoare triple {1462#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L272 TraceCheckUtils]: 4: Hoare triple {1462#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1462#true} {1462#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 2: Hoare triple {1462#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:26,414 INFO L290 TraceCheckUtils]: 1: Hoare triple {1462#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1462#true} is VALID [2022-04-27 16:54:26,415 INFO L272 TraceCheckUtils]: 0: Hoare triple {1462#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1462#true} is VALID [2022-04-27 16:54:26,415 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:54:26,415 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [13405187] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:54:26,415 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:54:26,415 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 50 [2022-04-27 16:54:26,416 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [940709382] [2022-04-27 16:54:26,416 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:54:26,417 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 59 [2022-04-27 16:54:26,417 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:54:26,417 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:54:26,503 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 109 edges. 109 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:54:26,504 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-04-27 16:54:26,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:54:26,504 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-04-27 16:54:26,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=672, Invalid=1778, Unknown=0, NotChecked=0, Total=2450 [2022-04-27 16:54:26,506 INFO L87 Difference]: Start difference. First operand 66 states and 70 transitions. Second operand has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:56:24,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:56:24,388 INFO L93 Difference]: Finished difference Result 121 states and 128 transitions. [2022-04-27 16:56:24,388 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-27 16:56:24,388 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 59 [2022-04-27 16:56:24,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 16:56:24,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:56:24,391 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 152 transitions. [2022-04-27 16:56:24,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:56:24,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 152 transitions. [2022-04-27 16:56:24,395 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 152 transitions. [2022-04-27 16:56:24,633 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 152 edges. 152 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:56:24,640 INFO L225 Difference]: With dead ends: 121 [2022-04-27 16:56:24,640 INFO L226 Difference]: Without dead ends: 121 [2022-04-27 16:56:24,643 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 192 GetRequests, 97 SyntacticMatches, 1 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1111 ImplicationChecksByTransitivity, 116.1s TimeCoverageRelationStatistics Valid=2438, Invalid=6677, Unknown=5, NotChecked=0, Total=9120 [2022-04-27 16:56:24,644 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 341 mSDsluCounter, 122 mSDsCounter, 0 mSdLazyCounter, 1782 mSolverCounterSat, 161 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 342 SdHoareTripleChecker+Valid, 146 SdHoareTripleChecker+Invalid, 1943 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 161 IncrementalHoareTripleChecker+Valid, 1782 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 1.4s IncrementalHoareTripleChecker+Time [2022-04-27 16:56:24,644 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [342 Valid, 146 Invalid, 1943 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [161 Valid, 1782 Invalid, 0 Unknown, 0 Unchecked, 1.4s Time] [2022-04-27 16:56:24,646 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2022-04-27 16:56:24,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 114. [2022-04-27 16:56:24,661 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 16:56:24,661 INFO L82 GeneralOperation]: Start isEquivalent. First operand 121 states. Second operand has 114 states, 108 states have (on average 1.0462962962962963) internal successors, (113), 108 states have internal predecessors, (113), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:56:24,661 INFO L74 IsIncluded]: Start isIncluded. First operand 121 states. Second operand has 114 states, 108 states have (on average 1.0462962962962963) internal successors, (113), 108 states have internal predecessors, (113), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:56:24,662 INFO L87 Difference]: Start difference. First operand 121 states. Second operand has 114 states, 108 states have (on average 1.0462962962962963) internal successors, (113), 108 states have internal predecessors, (113), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:56:24,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:56:24,665 INFO L93 Difference]: Finished difference Result 121 states and 128 transitions. [2022-04-27 16:56:24,665 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 128 transitions. [2022-04-27 16:56:24,666 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:56:24,666 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:56:24,666 INFO L74 IsIncluded]: Start isIncluded. First operand has 114 states, 108 states have (on average 1.0462962962962963) internal successors, (113), 108 states have internal predecessors, (113), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 121 states. [2022-04-27 16:56:24,666 INFO L87 Difference]: Start difference. First operand has 114 states, 108 states have (on average 1.0462962962962963) internal successors, (113), 108 states have internal predecessors, (113), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 121 states. [2022-04-27 16:56:24,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 16:56:24,670 INFO L93 Difference]: Finished difference Result 121 states and 128 transitions. [2022-04-27 16:56:24,670 INFO L276 IsEmpty]: Start isEmpty. Operand 121 states and 128 transitions. [2022-04-27 16:56:24,670 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 16:56:24,670 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 16:56:24,670 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 16:56:24,670 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 16:56:24,671 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114 states, 108 states have (on average 1.0462962962962963) internal successors, (113), 108 states have internal predecessors, (113), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 16:56:24,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 118 transitions. [2022-04-27 16:56:24,679 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 118 transitions. Word has length 59 [2022-04-27 16:56:24,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 16:56:24,679 INFO L495 AbstractCegarLoop]: Abstraction has 114 states and 118 transitions. [2022-04-27 16:56:24,679 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 2.08) internal successors, (104), 49 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:56:24,680 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 118 transitions. [2022-04-27 16:56:24,685 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2022-04-27 16:56:24,686 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 16:56:24,686 INFO L195 NwaCegarLoop]: trace histogram [46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 16:56:24,711 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 16:56:24,899 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:56:24,899 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 16:56:24,900 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 16:56:24,900 INFO L85 PathProgramCache]: Analyzing trace with hash -1664764145, now seen corresponding path program 5 times [2022-04-27 16:56:24,900 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 16:56:24,900 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141688720] [2022-04-27 16:56:24,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 16:56:24,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 16:56:24,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:56:26,359 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 16:56:26,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:56:26,370 INFO L290 TraceCheckUtils]: 0: Hoare triple {2490#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2438#true} is VALID [2022-04-27 16:56:26,370 INFO L290 TraceCheckUtils]: 1: Hoare triple {2438#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:56:26,370 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2438#true} {2438#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L272 TraceCheckUtils]: 0: Hoare triple {2438#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2490#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 16:56:26,371 INFO L290 TraceCheckUtils]: 1: Hoare triple {2490#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L290 TraceCheckUtils]: 2: Hoare triple {2438#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2438#true} {2438#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L272 TraceCheckUtils]: 4: Hoare triple {2438#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L290 TraceCheckUtils]: 5: Hoare triple {2438#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L290 TraceCheckUtils]: 6: Hoare triple {2438#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L290 TraceCheckUtils]: 7: Hoare triple {2438#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {2438#true} is VALID [2022-04-27 16:56:26,371 INFO L290 TraceCheckUtils]: 8: Hoare triple {2438#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {2438#true} is VALID [2022-04-27 16:56:26,372 INFO L290 TraceCheckUtils]: 9: Hoare triple {2438#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {2443#(= main_~v~0 0)} is VALID [2022-04-27 16:56:26,372 INFO L290 TraceCheckUtils]: 10: Hoare triple {2443#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2443#(= main_~v~0 0)} is VALID [2022-04-27 16:56:26,372 INFO L290 TraceCheckUtils]: 11: Hoare triple {2443#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:56:26,373 INFO L290 TraceCheckUtils]: 12: Hoare triple {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:56:26,373 INFO L290 TraceCheckUtils]: 13: Hoare triple {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:56:26,375 INFO L290 TraceCheckUtils]: 14: Hoare triple {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:56:26,375 INFO L290 TraceCheckUtils]: 15: Hoare triple {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:56:26,375 INFO L290 TraceCheckUtils]: 16: Hoare triple {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:56:26,376 INFO L290 TraceCheckUtils]: 17: Hoare triple {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:56:26,376 INFO L290 TraceCheckUtils]: 18: Hoare triple {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:56:26,383 INFO L290 TraceCheckUtils]: 19: Hoare triple {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:56:26,384 INFO L290 TraceCheckUtils]: 20: Hoare triple {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:56:26,385 INFO L290 TraceCheckUtils]: 21: Hoare triple {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:56:26,385 INFO L290 TraceCheckUtils]: 22: Hoare triple {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:56:26,386 INFO L290 TraceCheckUtils]: 23: Hoare triple {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:56:26,386 INFO L290 TraceCheckUtils]: 24: Hoare triple {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:56:26,387 INFO L290 TraceCheckUtils]: 25: Hoare triple {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:56:26,387 INFO L290 TraceCheckUtils]: 26: Hoare triple {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:56:26,388 INFO L290 TraceCheckUtils]: 27: Hoare triple {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:56:26,388 INFO L290 TraceCheckUtils]: 28: Hoare triple {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:56:26,388 INFO L290 TraceCheckUtils]: 29: Hoare triple {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:56:26,389 INFO L290 TraceCheckUtils]: 30: Hoare triple {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:56:26,389 INFO L290 TraceCheckUtils]: 31: Hoare triple {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:56:26,390 INFO L290 TraceCheckUtils]: 32: Hoare triple {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:56:26,390 INFO L290 TraceCheckUtils]: 33: Hoare triple {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:56:26,390 INFO L290 TraceCheckUtils]: 34: Hoare triple {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:56:26,391 INFO L290 TraceCheckUtils]: 35: Hoare triple {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:56:26,391 INFO L290 TraceCheckUtils]: 36: Hoare triple {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:56:26,392 INFO L290 TraceCheckUtils]: 37: Hoare triple {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:56:26,392 INFO L290 TraceCheckUtils]: 38: Hoare triple {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:56:26,392 INFO L290 TraceCheckUtils]: 39: Hoare triple {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:56:26,393 INFO L290 TraceCheckUtils]: 40: Hoare triple {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:56:26,393 INFO L290 TraceCheckUtils]: 41: Hoare triple {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:56:26,393 INFO L290 TraceCheckUtils]: 42: Hoare triple {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:56:26,394 INFO L290 TraceCheckUtils]: 43: Hoare triple {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:56:26,394 INFO L290 TraceCheckUtils]: 44: Hoare triple {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:56:26,395 INFO L290 TraceCheckUtils]: 45: Hoare triple {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:56:26,395 INFO L290 TraceCheckUtils]: 46: Hoare triple {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:56:26,396 INFO L290 TraceCheckUtils]: 47: Hoare triple {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:56:26,396 INFO L290 TraceCheckUtils]: 48: Hoare triple {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:56:26,397 INFO L290 TraceCheckUtils]: 49: Hoare triple {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:56:26,397 INFO L290 TraceCheckUtils]: 50: Hoare triple {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:56:26,399 INFO L290 TraceCheckUtils]: 51: Hoare triple {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:56:26,400 INFO L290 TraceCheckUtils]: 52: Hoare triple {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:56:26,400 INFO L290 TraceCheckUtils]: 53: Hoare triple {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} is VALID [2022-04-27 16:56:26,401 INFO L290 TraceCheckUtils]: 54: Hoare triple {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} is VALID [2022-04-27 16:56:26,401 INFO L290 TraceCheckUtils]: 55: Hoare triple {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} is VALID [2022-04-27 16:56:26,401 INFO L290 TraceCheckUtils]: 56: Hoare triple {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} is VALID [2022-04-27 16:56:26,402 INFO L290 TraceCheckUtils]: 57: Hoare triple {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} is VALID [2022-04-27 16:56:26,402 INFO L290 TraceCheckUtils]: 58: Hoare triple {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} is VALID [2022-04-27 16:56:26,403 INFO L290 TraceCheckUtils]: 59: Hoare triple {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} is VALID [2022-04-27 16:56:26,404 INFO L290 TraceCheckUtils]: 60: Hoare triple {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} is VALID [2022-04-27 16:56:26,404 INFO L290 TraceCheckUtils]: 61: Hoare triple {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} is VALID [2022-04-27 16:56:26,404 INFO L290 TraceCheckUtils]: 62: Hoare triple {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} is VALID [2022-04-27 16:56:26,405 INFO L290 TraceCheckUtils]: 63: Hoare triple {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} is VALID [2022-04-27 16:56:26,405 INFO L290 TraceCheckUtils]: 64: Hoare triple {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} is VALID [2022-04-27 16:56:26,406 INFO L290 TraceCheckUtils]: 65: Hoare triple {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} is VALID [2022-04-27 16:56:26,406 INFO L290 TraceCheckUtils]: 66: Hoare triple {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} is VALID [2022-04-27 16:56:26,406 INFO L290 TraceCheckUtils]: 67: Hoare triple {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} is VALID [2022-04-27 16:56:26,407 INFO L290 TraceCheckUtils]: 68: Hoare triple {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} is VALID [2022-04-27 16:56:26,407 INFO L290 TraceCheckUtils]: 69: Hoare triple {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} is VALID [2022-04-27 16:56:26,408 INFO L290 TraceCheckUtils]: 70: Hoare triple {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} is VALID [2022-04-27 16:56:26,408 INFO L290 TraceCheckUtils]: 71: Hoare triple {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} is VALID [2022-04-27 16:56:26,408 INFO L290 TraceCheckUtils]: 72: Hoare triple {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} is VALID [2022-04-27 16:56:26,409 INFO L290 TraceCheckUtils]: 73: Hoare triple {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} is VALID [2022-04-27 16:56:26,409 INFO L290 TraceCheckUtils]: 74: Hoare triple {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} is VALID [2022-04-27 16:56:26,410 INFO L290 TraceCheckUtils]: 75: Hoare triple {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} is VALID [2022-04-27 16:56:26,410 INFO L290 TraceCheckUtils]: 76: Hoare triple {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} is VALID [2022-04-27 16:56:26,410 INFO L290 TraceCheckUtils]: 77: Hoare triple {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} is VALID [2022-04-27 16:56:26,411 INFO L290 TraceCheckUtils]: 78: Hoare triple {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} is VALID [2022-04-27 16:56:26,411 INFO L290 TraceCheckUtils]: 79: Hoare triple {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} is VALID [2022-04-27 16:56:26,411 INFO L290 TraceCheckUtils]: 80: Hoare triple {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} is VALID [2022-04-27 16:56:26,412 INFO L290 TraceCheckUtils]: 81: Hoare triple {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} is VALID [2022-04-27 16:56:26,412 INFO L290 TraceCheckUtils]: 82: Hoare triple {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} is VALID [2022-04-27 16:56:26,413 INFO L290 TraceCheckUtils]: 83: Hoare triple {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} is VALID [2022-04-27 16:56:26,413 INFO L290 TraceCheckUtils]: 84: Hoare triple {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} is VALID [2022-04-27 16:56:26,413 INFO L290 TraceCheckUtils]: 85: Hoare triple {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} is VALID [2022-04-27 16:56:26,414 INFO L290 TraceCheckUtils]: 86: Hoare triple {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} is VALID [2022-04-27 16:56:26,414 INFO L290 TraceCheckUtils]: 87: Hoare triple {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} is VALID [2022-04-27 16:56:26,415 INFO L290 TraceCheckUtils]: 88: Hoare triple {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} is VALID [2022-04-27 16:56:26,415 INFO L290 TraceCheckUtils]: 89: Hoare triple {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} is VALID [2022-04-27 16:56:26,415 INFO L290 TraceCheckUtils]: 90: Hoare triple {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} is VALID [2022-04-27 16:56:26,416 INFO L290 TraceCheckUtils]: 91: Hoare triple {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} is VALID [2022-04-27 16:56:26,416 INFO L290 TraceCheckUtils]: 92: Hoare triple {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} is VALID [2022-04-27 16:56:26,416 INFO L290 TraceCheckUtils]: 93: Hoare triple {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} is VALID [2022-04-27 16:56:26,417 INFO L290 TraceCheckUtils]: 94: Hoare triple {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} is VALID [2022-04-27 16:56:26,417 INFO L290 TraceCheckUtils]: 95: Hoare triple {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} is VALID [2022-04-27 16:56:26,418 INFO L290 TraceCheckUtils]: 96: Hoare triple {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} is VALID [2022-04-27 16:56:26,418 INFO L290 TraceCheckUtils]: 97: Hoare triple {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} is VALID [2022-04-27 16:56:26,418 INFO L290 TraceCheckUtils]: 98: Hoare triple {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} is VALID [2022-04-27 16:56:26,419 INFO L290 TraceCheckUtils]: 99: Hoare triple {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} is VALID [2022-04-27 16:56:26,419 INFO L290 TraceCheckUtils]: 100: Hoare triple {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} is VALID [2022-04-27 16:56:26,420 INFO L290 TraceCheckUtils]: 101: Hoare triple {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2489#(and (not (<= (+ (div main_~v~0 4294967296) 1) 0)) (<= main_~v~0 46))} is VALID [2022-04-27 16:56:26,420 INFO L290 TraceCheckUtils]: 102: Hoare triple {2489#(and (not (<= (+ (div main_~v~0 4294967296) 1) 0)) (<= main_~v~0 46))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:56:26,420 INFO L272 TraceCheckUtils]: 103: Hoare triple {2439#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {2439#false} is VALID [2022-04-27 16:56:26,420 INFO L290 TraceCheckUtils]: 104: Hoare triple {2439#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2439#false} is VALID [2022-04-27 16:56:26,420 INFO L290 TraceCheckUtils]: 105: Hoare triple {2439#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:56:26,420 INFO L290 TraceCheckUtils]: 106: Hoare triple {2439#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:56:26,421 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:56:26,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 16:56:26,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141688720] [2022-04-27 16:56:26,422 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141688720] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 16:56:26,422 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1176135498] [2022-04-27 16:56:26,422 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-27 16:56:26,422 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 16:56:26,422 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 16:56:26,424 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 16:56:26,427 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 16:58:31,404 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-04-27 16:58:31,404 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 16:58:31,447 INFO L263 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 95 conjunts are in the unsatisfiable core [2022-04-27 16:58:31,470 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 16:58:31,472 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 16:58:32,609 INFO L272 TraceCheckUtils]: 0: Hoare triple {2438#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L290 TraceCheckUtils]: 1: Hoare triple {2438#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L290 TraceCheckUtils]: 2: Hoare triple {2438#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2438#true} {2438#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L272 TraceCheckUtils]: 4: Hoare triple {2438#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L290 TraceCheckUtils]: 5: Hoare triple {2438#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L290 TraceCheckUtils]: 6: Hoare triple {2438#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L290 TraceCheckUtils]: 7: Hoare triple {2438#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {2438#true} is VALID [2022-04-27 16:58:32,610 INFO L290 TraceCheckUtils]: 8: Hoare triple {2438#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {2438#true} is VALID [2022-04-27 16:58:32,611 INFO L290 TraceCheckUtils]: 9: Hoare triple {2438#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {2443#(= main_~v~0 0)} is VALID [2022-04-27 16:58:32,611 INFO L290 TraceCheckUtils]: 10: Hoare triple {2443#(= main_~v~0 0)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2443#(= main_~v~0 0)} is VALID [2022-04-27 16:58:32,611 INFO L290 TraceCheckUtils]: 11: Hoare triple {2443#(= main_~v~0 0)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:58:32,612 INFO L290 TraceCheckUtils]: 12: Hoare triple {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} is VALID [2022-04-27 16:58:32,612 INFO L290 TraceCheckUtils]: 13: Hoare triple {2444#(and (<= main_~v~0 1) (<= 1 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:58:32,613 INFO L290 TraceCheckUtils]: 14: Hoare triple {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} is VALID [2022-04-27 16:58:32,613 INFO L290 TraceCheckUtils]: 15: Hoare triple {2445#(and (<= 2 main_~v~0) (<= main_~v~0 2))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:58:32,614 INFO L290 TraceCheckUtils]: 16: Hoare triple {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} is VALID [2022-04-27 16:58:32,614 INFO L290 TraceCheckUtils]: 17: Hoare triple {2446#(and (<= main_~v~0 3) (<= 3 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:58:32,615 INFO L290 TraceCheckUtils]: 18: Hoare triple {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} is VALID [2022-04-27 16:58:32,615 INFO L290 TraceCheckUtils]: 19: Hoare triple {2447#(and (<= main_~v~0 4) (<= 4 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:58:32,616 INFO L290 TraceCheckUtils]: 20: Hoare triple {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} is VALID [2022-04-27 16:58:32,616 INFO L290 TraceCheckUtils]: 21: Hoare triple {2448#(and (<= main_~v~0 5) (<= 5 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:58:32,617 INFO L290 TraceCheckUtils]: 22: Hoare triple {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} is VALID [2022-04-27 16:58:32,617 INFO L290 TraceCheckUtils]: 23: Hoare triple {2449#(and (<= 6 main_~v~0) (<= main_~v~0 6))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:58:32,618 INFO L290 TraceCheckUtils]: 24: Hoare triple {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} is VALID [2022-04-27 16:58:32,618 INFO L290 TraceCheckUtils]: 25: Hoare triple {2450#(and (<= main_~v~0 7) (<= 7 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:58:32,619 INFO L290 TraceCheckUtils]: 26: Hoare triple {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} is VALID [2022-04-27 16:58:32,619 INFO L290 TraceCheckUtils]: 27: Hoare triple {2451#(and (<= main_~v~0 8) (<= 8 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:58:32,620 INFO L290 TraceCheckUtils]: 28: Hoare triple {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} is VALID [2022-04-27 16:58:32,620 INFO L290 TraceCheckUtils]: 29: Hoare triple {2452#(and (<= 9 main_~v~0) (<= main_~v~0 9))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:58:32,621 INFO L290 TraceCheckUtils]: 30: Hoare triple {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} is VALID [2022-04-27 16:58:32,621 INFO L290 TraceCheckUtils]: 31: Hoare triple {2453#(and (<= 10 main_~v~0) (<= main_~v~0 10))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:58:32,622 INFO L290 TraceCheckUtils]: 32: Hoare triple {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} is VALID [2022-04-27 16:58:32,622 INFO L290 TraceCheckUtils]: 33: Hoare triple {2454#(and (<= main_~v~0 11) (<= 11 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:58:32,623 INFO L290 TraceCheckUtils]: 34: Hoare triple {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} is VALID [2022-04-27 16:58:32,623 INFO L290 TraceCheckUtils]: 35: Hoare triple {2455#(and (<= 12 main_~v~0) (<= main_~v~0 12))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:58:32,623 INFO L290 TraceCheckUtils]: 36: Hoare triple {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} is VALID [2022-04-27 16:58:32,624 INFO L290 TraceCheckUtils]: 37: Hoare triple {2456#(and (<= 13 main_~v~0) (<= main_~v~0 13))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:58:32,624 INFO L290 TraceCheckUtils]: 38: Hoare triple {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} is VALID [2022-04-27 16:58:32,625 INFO L290 TraceCheckUtils]: 39: Hoare triple {2457#(and (<= main_~v~0 14) (<= 14 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:58:32,625 INFO L290 TraceCheckUtils]: 40: Hoare triple {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} is VALID [2022-04-27 16:58:32,626 INFO L290 TraceCheckUtils]: 41: Hoare triple {2458#(and (<= 15 main_~v~0) (<= main_~v~0 15))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:58:32,626 INFO L290 TraceCheckUtils]: 42: Hoare triple {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} is VALID [2022-04-27 16:58:32,627 INFO L290 TraceCheckUtils]: 43: Hoare triple {2459#(and (<= main_~v~0 16) (<= 16 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:58:32,627 INFO L290 TraceCheckUtils]: 44: Hoare triple {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} is VALID [2022-04-27 16:58:32,628 INFO L290 TraceCheckUtils]: 45: Hoare triple {2460#(and (<= main_~v~0 17) (<= 17 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:58:32,628 INFO L290 TraceCheckUtils]: 46: Hoare triple {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} is VALID [2022-04-27 16:58:32,629 INFO L290 TraceCheckUtils]: 47: Hoare triple {2461#(and (<= main_~v~0 18) (<= 18 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:58:32,629 INFO L290 TraceCheckUtils]: 48: Hoare triple {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} is VALID [2022-04-27 16:58:32,630 INFO L290 TraceCheckUtils]: 49: Hoare triple {2462#(and (<= 19 main_~v~0) (<= main_~v~0 19))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:58:32,630 INFO L290 TraceCheckUtils]: 50: Hoare triple {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} is VALID [2022-04-27 16:58:32,631 INFO L290 TraceCheckUtils]: 51: Hoare triple {2463#(and (<= main_~v~0 20) (<= 20 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:58:32,631 INFO L290 TraceCheckUtils]: 52: Hoare triple {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} is VALID [2022-04-27 16:58:32,632 INFO L290 TraceCheckUtils]: 53: Hoare triple {2464#(and (<= main_~v~0 21) (<= 21 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} is VALID [2022-04-27 16:58:32,632 INFO L290 TraceCheckUtils]: 54: Hoare triple {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} is VALID [2022-04-27 16:58:32,633 INFO L290 TraceCheckUtils]: 55: Hoare triple {2465#(and (<= 22 main_~v~0) (<= main_~v~0 22))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} is VALID [2022-04-27 16:58:32,633 INFO L290 TraceCheckUtils]: 56: Hoare triple {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} is VALID [2022-04-27 16:58:32,634 INFO L290 TraceCheckUtils]: 57: Hoare triple {2466#(and (<= 23 main_~v~0) (<= main_~v~0 23))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} is VALID [2022-04-27 16:58:32,634 INFO L290 TraceCheckUtils]: 58: Hoare triple {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} is VALID [2022-04-27 16:58:32,635 INFO L290 TraceCheckUtils]: 59: Hoare triple {2467#(and (<= main_~v~0 24) (<= 24 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} is VALID [2022-04-27 16:58:32,635 INFO L290 TraceCheckUtils]: 60: Hoare triple {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} is VALID [2022-04-27 16:58:32,636 INFO L290 TraceCheckUtils]: 61: Hoare triple {2468#(and (<= 25 main_~v~0) (<= main_~v~0 25))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} is VALID [2022-04-27 16:58:32,636 INFO L290 TraceCheckUtils]: 62: Hoare triple {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} is VALID [2022-04-27 16:58:32,636 INFO L290 TraceCheckUtils]: 63: Hoare triple {2469#(and (<= 26 main_~v~0) (<= main_~v~0 26))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} is VALID [2022-04-27 16:58:32,637 INFO L290 TraceCheckUtils]: 64: Hoare triple {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} is VALID [2022-04-27 16:58:32,637 INFO L290 TraceCheckUtils]: 65: Hoare triple {2470#(and (<= 27 main_~v~0) (<= main_~v~0 27))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} is VALID [2022-04-27 16:58:32,638 INFO L290 TraceCheckUtils]: 66: Hoare triple {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} is VALID [2022-04-27 16:58:32,638 INFO L290 TraceCheckUtils]: 67: Hoare triple {2471#(and (<= main_~v~0 28) (<= 28 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} is VALID [2022-04-27 16:58:32,639 INFO L290 TraceCheckUtils]: 68: Hoare triple {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} is VALID [2022-04-27 16:58:32,639 INFO L290 TraceCheckUtils]: 69: Hoare triple {2472#(and (<= main_~v~0 29) (<= 29 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} is VALID [2022-04-27 16:58:32,640 INFO L290 TraceCheckUtils]: 70: Hoare triple {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} is VALID [2022-04-27 16:58:32,640 INFO L290 TraceCheckUtils]: 71: Hoare triple {2473#(and (<= 30 main_~v~0) (<= main_~v~0 30))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} is VALID [2022-04-27 16:58:32,641 INFO L290 TraceCheckUtils]: 72: Hoare triple {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} is VALID [2022-04-27 16:58:32,641 INFO L290 TraceCheckUtils]: 73: Hoare triple {2474#(and (<= 31 main_~v~0) (<= main_~v~0 31))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} is VALID [2022-04-27 16:58:32,642 INFO L290 TraceCheckUtils]: 74: Hoare triple {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} is VALID [2022-04-27 16:58:32,642 INFO L290 TraceCheckUtils]: 75: Hoare triple {2475#(and (<= main_~v~0 32) (<= 32 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} is VALID [2022-04-27 16:58:32,643 INFO L290 TraceCheckUtils]: 76: Hoare triple {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} is VALID [2022-04-27 16:58:32,643 INFO L290 TraceCheckUtils]: 77: Hoare triple {2476#(and (<= main_~v~0 33) (<= 33 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} is VALID [2022-04-27 16:58:32,645 INFO L290 TraceCheckUtils]: 78: Hoare triple {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} is VALID [2022-04-27 16:58:32,646 INFO L290 TraceCheckUtils]: 79: Hoare triple {2477#(and (<= 34 main_~v~0) (<= main_~v~0 34))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} is VALID [2022-04-27 16:58:32,646 INFO L290 TraceCheckUtils]: 80: Hoare triple {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} is VALID [2022-04-27 16:58:32,647 INFO L290 TraceCheckUtils]: 81: Hoare triple {2478#(and (<= 35 main_~v~0) (<= main_~v~0 35))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} is VALID [2022-04-27 16:58:32,647 INFO L290 TraceCheckUtils]: 82: Hoare triple {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} is VALID [2022-04-27 16:58:32,648 INFO L290 TraceCheckUtils]: 83: Hoare triple {2479#(and (<= 36 main_~v~0) (<= main_~v~0 36))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} is VALID [2022-04-27 16:58:32,648 INFO L290 TraceCheckUtils]: 84: Hoare triple {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} is VALID [2022-04-27 16:58:32,649 INFO L290 TraceCheckUtils]: 85: Hoare triple {2480#(and (<= main_~v~0 37) (<= 37 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} is VALID [2022-04-27 16:58:32,649 INFO L290 TraceCheckUtils]: 86: Hoare triple {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} is VALID [2022-04-27 16:58:32,649 INFO L290 TraceCheckUtils]: 87: Hoare triple {2481#(and (<= 38 main_~v~0) (<= main_~v~0 38))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} is VALID [2022-04-27 16:58:32,650 INFO L290 TraceCheckUtils]: 88: Hoare triple {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} is VALID [2022-04-27 16:58:32,650 INFO L290 TraceCheckUtils]: 89: Hoare triple {2482#(and (<= main_~v~0 39) (<= 39 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} is VALID [2022-04-27 16:58:32,651 INFO L290 TraceCheckUtils]: 90: Hoare triple {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} is VALID [2022-04-27 16:58:32,651 INFO L290 TraceCheckUtils]: 91: Hoare triple {2483#(and (<= main_~v~0 40) (<= 40 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} is VALID [2022-04-27 16:58:32,652 INFO L290 TraceCheckUtils]: 92: Hoare triple {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} is VALID [2022-04-27 16:58:32,652 INFO L290 TraceCheckUtils]: 93: Hoare triple {2484#(and (<= main_~v~0 41) (<= 41 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} is VALID [2022-04-27 16:58:32,653 INFO L290 TraceCheckUtils]: 94: Hoare triple {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} is VALID [2022-04-27 16:58:32,653 INFO L290 TraceCheckUtils]: 95: Hoare triple {2485#(and (<= main_~v~0 42) (<= 42 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} is VALID [2022-04-27 16:58:32,654 INFO L290 TraceCheckUtils]: 96: Hoare triple {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} is VALID [2022-04-27 16:58:32,654 INFO L290 TraceCheckUtils]: 97: Hoare triple {2486#(and (<= main_~v~0 43) (<= 43 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} is VALID [2022-04-27 16:58:32,655 INFO L290 TraceCheckUtils]: 98: Hoare triple {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} is VALID [2022-04-27 16:58:32,655 INFO L290 TraceCheckUtils]: 99: Hoare triple {2487#(and (<= 44 main_~v~0) (<= main_~v~0 44))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} is VALID [2022-04-27 16:58:32,656 INFO L290 TraceCheckUtils]: 100: Hoare triple {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} is VALID [2022-04-27 16:58:32,656 INFO L290 TraceCheckUtils]: 101: Hoare triple {2488#(and (<= main_~v~0 45) (<= 45 main_~v~0))} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2797#(and (<= 46 main_~v~0) (<= main_~v~0 46))} is VALID [2022-04-27 16:58:32,657 INFO L290 TraceCheckUtils]: 102: Hoare triple {2797#(and (<= 46 main_~v~0) (<= main_~v~0 46))} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:58:32,657 INFO L272 TraceCheckUtils]: 103: Hoare triple {2439#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {2439#false} is VALID [2022-04-27 16:58:32,657 INFO L290 TraceCheckUtils]: 104: Hoare triple {2439#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2439#false} is VALID [2022-04-27 16:58:32,657 INFO L290 TraceCheckUtils]: 105: Hoare triple {2439#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:58:32,657 INFO L290 TraceCheckUtils]: 106: Hoare triple {2439#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:58:32,659 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:58:32,659 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 16:58:36,273 INFO L290 TraceCheckUtils]: 106: Hoare triple {2439#false} [122] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:58:36,273 INFO L290 TraceCheckUtils]: 105: Hoare triple {2439#false} [120] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:58:36,273 INFO L290 TraceCheckUtils]: 104: Hoare triple {2439#false} [119] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2439#false} is VALID [2022-04-27 16:58:36,273 INFO L272 TraceCheckUtils]: 103: Hoare triple {2439#false} [116] L24-4-->__VERIFIER_assertENTRY: Formula: (= (ite (= 0 (mod v_main_~v~0_8 4)) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_~v~0=v_main_~v~0_8} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~v~0] {2439#false} is VALID [2022-04-27 16:58:36,274 INFO L290 TraceCheckUtils]: 102: Hoare triple {2825#(< (mod main_~v~0 4294967296) 268435455)} [114] L24-3-->L24-4: Formula: (not (< (mod v_main_~v~0_3 4294967296) 268435455)) InVars {main_~v~0=v_main_~v~0_3} OutVars{main_~v~0=v_main_~v~0_3} AuxVars[] AssignedVars[] {2439#false} is VALID [2022-04-27 16:58:36,274 INFO L290 TraceCheckUtils]: 101: Hoare triple {2829#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2825#(< (mod main_~v~0 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,275 INFO L290 TraceCheckUtils]: 100: Hoare triple {2829#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2829#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,275 INFO L290 TraceCheckUtils]: 99: Hoare triple {2836#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2829#(< (mod (+ main_~v~0 1) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,275 INFO L290 TraceCheckUtils]: 98: Hoare triple {2836#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2836#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,276 INFO L290 TraceCheckUtils]: 97: Hoare triple {2843#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2836#(< (mod (+ main_~v~0 2) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,276 INFO L290 TraceCheckUtils]: 96: Hoare triple {2843#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2843#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,277 INFO L290 TraceCheckUtils]: 95: Hoare triple {2850#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2843#(< (mod (+ main_~v~0 3) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,279 INFO L290 TraceCheckUtils]: 94: Hoare triple {2850#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2850#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,280 INFO L290 TraceCheckUtils]: 93: Hoare triple {2857#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2850#(< (mod (+ main_~v~0 4) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,280 INFO L290 TraceCheckUtils]: 92: Hoare triple {2857#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2857#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,281 INFO L290 TraceCheckUtils]: 91: Hoare triple {2864#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2857#(< (mod (+ 5 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,281 INFO L290 TraceCheckUtils]: 90: Hoare triple {2864#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2864#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,281 INFO L290 TraceCheckUtils]: 89: Hoare triple {2871#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2864#(< (mod (+ main_~v~0 6) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,282 INFO L290 TraceCheckUtils]: 88: Hoare triple {2871#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2871#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,282 INFO L290 TraceCheckUtils]: 87: Hoare triple {2878#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2871#(< (mod (+ 7 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,283 INFO L290 TraceCheckUtils]: 86: Hoare triple {2878#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2878#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,283 INFO L290 TraceCheckUtils]: 85: Hoare triple {2885#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2878#(< (mod (+ main_~v~0 8) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,283 INFO L290 TraceCheckUtils]: 84: Hoare triple {2885#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2885#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,284 INFO L290 TraceCheckUtils]: 83: Hoare triple {2892#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2885#(< (mod (+ main_~v~0 9) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,284 INFO L290 TraceCheckUtils]: 82: Hoare triple {2892#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2892#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,285 INFO L290 TraceCheckUtils]: 81: Hoare triple {2899#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2892#(< (mod (+ main_~v~0 10) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,285 INFO L290 TraceCheckUtils]: 80: Hoare triple {2899#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2899#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,286 INFO L290 TraceCheckUtils]: 79: Hoare triple {2906#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2899#(< (mod (+ main_~v~0 11) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,286 INFO L290 TraceCheckUtils]: 78: Hoare triple {2906#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2906#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,286 INFO L290 TraceCheckUtils]: 77: Hoare triple {2913#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2906#(< (mod (+ main_~v~0 12) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,287 INFO L290 TraceCheckUtils]: 76: Hoare triple {2913#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2913#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,287 INFO L290 TraceCheckUtils]: 75: Hoare triple {2920#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2913#(< (mod (+ main_~v~0 13) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,288 INFO L290 TraceCheckUtils]: 74: Hoare triple {2920#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2920#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,288 INFO L290 TraceCheckUtils]: 73: Hoare triple {2927#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2920#(< (mod (+ main_~v~0 14) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,288 INFO L290 TraceCheckUtils]: 72: Hoare triple {2927#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2927#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,289 INFO L290 TraceCheckUtils]: 71: Hoare triple {2934#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2927#(< (mod (+ main_~v~0 15) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,289 INFO L290 TraceCheckUtils]: 70: Hoare triple {2934#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2934#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,290 INFO L290 TraceCheckUtils]: 69: Hoare triple {2941#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2934#(< (mod (+ main_~v~0 16) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,290 INFO L290 TraceCheckUtils]: 68: Hoare triple {2941#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2941#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,299 INFO L290 TraceCheckUtils]: 67: Hoare triple {2948#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2941#(< (mod (+ main_~v~0 17) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,300 INFO L290 TraceCheckUtils]: 66: Hoare triple {2948#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2948#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,301 INFO L290 TraceCheckUtils]: 65: Hoare triple {2955#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2948#(< (mod (+ main_~v~0 18) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,301 INFO L290 TraceCheckUtils]: 64: Hoare triple {2955#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2955#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,302 INFO L290 TraceCheckUtils]: 63: Hoare triple {2962#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2955#(< (mod (+ 19 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,302 INFO L290 TraceCheckUtils]: 62: Hoare triple {2962#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2962#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,303 INFO L290 TraceCheckUtils]: 61: Hoare triple {2969#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2962#(< (mod (+ main_~v~0 20) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,303 INFO L290 TraceCheckUtils]: 60: Hoare triple {2969#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2969#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,304 INFO L290 TraceCheckUtils]: 59: Hoare triple {2976#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2969#(< (mod (+ main_~v~0 21) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,304 INFO L290 TraceCheckUtils]: 58: Hoare triple {2976#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2976#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,305 INFO L290 TraceCheckUtils]: 57: Hoare triple {2983#(< (mod (+ 23 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2976#(< (mod (+ main_~v~0 22) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,305 INFO L290 TraceCheckUtils]: 56: Hoare triple {2983#(< (mod (+ 23 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2983#(< (mod (+ 23 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,305 INFO L290 TraceCheckUtils]: 55: Hoare triple {2990#(< (mod (+ main_~v~0 24) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2983#(< (mod (+ 23 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,306 INFO L290 TraceCheckUtils]: 54: Hoare triple {2990#(< (mod (+ main_~v~0 24) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2990#(< (mod (+ main_~v~0 24) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,306 INFO L290 TraceCheckUtils]: 53: Hoare triple {2997#(< (mod (+ main_~v~0 25) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2990#(< (mod (+ main_~v~0 24) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,307 INFO L290 TraceCheckUtils]: 52: Hoare triple {2997#(< (mod (+ main_~v~0 25) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {2997#(< (mod (+ main_~v~0 25) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,307 INFO L290 TraceCheckUtils]: 51: Hoare triple {3004#(< (mod (+ main_~v~0 26) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {2997#(< (mod (+ main_~v~0 25) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,307 INFO L290 TraceCheckUtils]: 50: Hoare triple {3004#(< (mod (+ main_~v~0 26) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3004#(< (mod (+ main_~v~0 26) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,308 INFO L290 TraceCheckUtils]: 49: Hoare triple {3011#(< (mod (+ main_~v~0 27) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3004#(< (mod (+ main_~v~0 26) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,308 INFO L290 TraceCheckUtils]: 48: Hoare triple {3011#(< (mod (+ main_~v~0 27) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3011#(< (mod (+ main_~v~0 27) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,309 INFO L290 TraceCheckUtils]: 47: Hoare triple {3018#(< (mod (+ main_~v~0 28) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3011#(< (mod (+ main_~v~0 27) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,309 INFO L290 TraceCheckUtils]: 46: Hoare triple {3018#(< (mod (+ main_~v~0 28) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3018#(< (mod (+ main_~v~0 28) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,310 INFO L290 TraceCheckUtils]: 45: Hoare triple {3025#(< (mod (+ 29 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3018#(< (mod (+ main_~v~0 28) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,310 INFO L290 TraceCheckUtils]: 44: Hoare triple {3025#(< (mod (+ 29 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3025#(< (mod (+ 29 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,310 INFO L290 TraceCheckUtils]: 43: Hoare triple {3032#(< (mod (+ 30 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3025#(< (mod (+ 29 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,311 INFO L290 TraceCheckUtils]: 42: Hoare triple {3032#(< (mod (+ 30 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3032#(< (mod (+ 30 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,311 INFO L290 TraceCheckUtils]: 41: Hoare triple {3039#(< (mod (+ main_~v~0 31) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3032#(< (mod (+ 30 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,312 INFO L290 TraceCheckUtils]: 40: Hoare triple {3039#(< (mod (+ main_~v~0 31) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3039#(< (mod (+ main_~v~0 31) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,312 INFO L290 TraceCheckUtils]: 39: Hoare triple {3046#(< (mod (+ 32 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3039#(< (mod (+ main_~v~0 31) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,313 INFO L290 TraceCheckUtils]: 38: Hoare triple {3046#(< (mod (+ 32 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3046#(< (mod (+ 32 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,313 INFO L290 TraceCheckUtils]: 37: Hoare triple {3053#(< (mod (+ main_~v~0 33) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3046#(< (mod (+ 32 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,313 INFO L290 TraceCheckUtils]: 36: Hoare triple {3053#(< (mod (+ main_~v~0 33) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3053#(< (mod (+ main_~v~0 33) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,314 INFO L290 TraceCheckUtils]: 35: Hoare triple {3060#(< (mod (+ main_~v~0 34) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3053#(< (mod (+ main_~v~0 33) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,314 INFO L290 TraceCheckUtils]: 34: Hoare triple {3060#(< (mod (+ main_~v~0 34) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3060#(< (mod (+ main_~v~0 34) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,315 INFO L290 TraceCheckUtils]: 33: Hoare triple {3067#(< (mod (+ 35 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3060#(< (mod (+ main_~v~0 34) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,315 INFO L290 TraceCheckUtils]: 32: Hoare triple {3067#(< (mod (+ 35 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3067#(< (mod (+ 35 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,316 INFO L290 TraceCheckUtils]: 31: Hoare triple {3074#(< (mod (+ main_~v~0 36) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3067#(< (mod (+ 35 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,316 INFO L290 TraceCheckUtils]: 30: Hoare triple {3074#(< (mod (+ main_~v~0 36) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3074#(< (mod (+ main_~v~0 36) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,316 INFO L290 TraceCheckUtils]: 29: Hoare triple {3081#(< (mod (+ main_~v~0 37) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3074#(< (mod (+ main_~v~0 36) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,317 INFO L290 TraceCheckUtils]: 28: Hoare triple {3081#(< (mod (+ main_~v~0 37) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3081#(< (mod (+ main_~v~0 37) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,317 INFO L290 TraceCheckUtils]: 27: Hoare triple {3088#(< (mod (+ main_~v~0 38) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3081#(< (mod (+ main_~v~0 37) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,318 INFO L290 TraceCheckUtils]: 26: Hoare triple {3088#(< (mod (+ main_~v~0 38) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3088#(< (mod (+ main_~v~0 38) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,318 INFO L290 TraceCheckUtils]: 25: Hoare triple {3095#(< (mod (+ main_~v~0 39) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3088#(< (mod (+ main_~v~0 38) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,318 INFO L290 TraceCheckUtils]: 24: Hoare triple {3095#(< (mod (+ main_~v~0 39) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3095#(< (mod (+ main_~v~0 39) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,319 INFO L290 TraceCheckUtils]: 23: Hoare triple {3102#(< (mod (+ 40 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3095#(< (mod (+ main_~v~0 39) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,319 INFO L290 TraceCheckUtils]: 22: Hoare triple {3102#(< (mod (+ 40 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3102#(< (mod (+ 40 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,320 INFO L290 TraceCheckUtils]: 21: Hoare triple {3109#(< (mod (+ 41 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3102#(< (mod (+ 40 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,320 INFO L290 TraceCheckUtils]: 20: Hoare triple {3109#(< (mod (+ 41 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3109#(< (mod (+ 41 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,321 INFO L290 TraceCheckUtils]: 19: Hoare triple {3116#(< (mod (+ 42 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3109#(< (mod (+ 41 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,321 INFO L290 TraceCheckUtils]: 18: Hoare triple {3116#(< (mod (+ 42 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3116#(< (mod (+ 42 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,321 INFO L290 TraceCheckUtils]: 17: Hoare triple {3123#(< (mod (+ main_~v~0 43) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3116#(< (mod (+ 42 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,322 INFO L290 TraceCheckUtils]: 16: Hoare triple {3123#(< (mod (+ main_~v~0 43) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3123#(< (mod (+ main_~v~0 43) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,322 INFO L290 TraceCheckUtils]: 15: Hoare triple {3130#(< (mod (+ 44 main_~v~0) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3123#(< (mod (+ main_~v~0 43) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,322 INFO L290 TraceCheckUtils]: 14: Hoare triple {3130#(< (mod (+ 44 main_~v~0) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3130#(< (mod (+ 44 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,323 INFO L290 TraceCheckUtils]: 13: Hoare triple {3137#(< (mod (+ main_~v~0 45) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3130#(< (mod (+ 44 main_~v~0) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,323 INFO L290 TraceCheckUtils]: 12: Hoare triple {3137#(< (mod (+ main_~v~0 45) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3137#(< (mod (+ main_~v~0 45) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,324 INFO L290 TraceCheckUtils]: 11: Hoare triple {3144#(< (mod (+ main_~v~0 46) 4294967296) 268435455)} [117] L24-2-->L24-3: Formula: (= v_main_~v~0_5 (+ v_main_~v~0_6 1)) InVars {main_~v~0=v_main_~v~0_6} OutVars{main_#t~post8=|v_main_#t~post8_1|, main_~v~0=v_main_~v~0_5} AuxVars[] AssignedVars[main_~v~0, main_#t~post8] {3137#(< (mod (+ main_~v~0 45) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,324 INFO L290 TraceCheckUtils]: 10: Hoare triple {3144#(< (mod (+ main_~v~0 46) 4294967296) 268435455)} [115] L24-3-->L24-2: Formula: (< (mod v_main_~v~0_4 4294967296) 268435455) InVars {main_~v~0=v_main_~v~0_4} OutVars{main_~v~0=v_main_~v~0_4} AuxVars[] AssignedVars[] {3144#(< (mod (+ main_~v~0 46) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,324 INFO L290 TraceCheckUtils]: 9: Hoare triple {2438#true} [111] L23-2-->L24-3: Formula: (and (= v_main_~v~0_2 0) (< (mod v_main_~z~0_3 4294967296) 10)) InVars {main_~z~0=v_main_~z~0_3} OutVars{main_~v~0=v_main_~v~0_2, main_~z~0=v_main_~z~0_3} AuxVars[] AssignedVars[main_~v~0] {3144#(< (mod (+ main_~v~0 46) 4294967296) 268435455)} is VALID [2022-04-27 16:58:36,325 INFO L290 TraceCheckUtils]: 8: Hoare triple {2438#true} [107] L22-3-->L23-2: Formula: (and (< (mod v_main_~y~0_6 4294967296) 10) (= v_main_~z~0_6 0)) InVars {main_~y~0=v_main_~y~0_6} OutVars{main_~y~0=v_main_~y~0_6, main_~z~0=v_main_~z~0_6} AuxVars[] AssignedVars[main_~z~0] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L290 TraceCheckUtils]: 7: Hoare triple {2438#true} [102] L21-3-->L22-3: Formula: (and (< (mod v_main_~x~0_4 4294967296) 10) (= v_main_~y~0_2 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{main_~x~0=v_main_~x~0_4, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_~y~0] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L290 TraceCheckUtils]: 6: Hoare triple {2438#true} [98] L19-3-->L21-3: Formula: (and (= v_main_~x~0_2 0) (< (mod v_main_~w~0_6 4294967296) 268435455)) InVars {main_~w~0=v_main_~w~0_6} OutVars{main_~x~0=v_main_~x~0_2, main_~w~0=v_main_~w~0_6} AuxVars[] AssignedVars[main_~x~0] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L290 TraceCheckUtils]: 5: Hoare triple {2438#true} [94] mainENTRY-->L19-3: Formula: (and (= v_main_~x~0_1 0) (= v_main_~w~0_3 0) (= v_main_~v~0_1 0) (= v_main_~z~0_2 0) (= v_main_~y~0_1 0)) InVars {} OutVars{main_~y~0=v_main_~y~0_1, main_~v~0=v_main_~v~0_1, main_~w~0=v_main_~w~0_3, main_~x~0=v_main_~x~0_1, main_~z~0=v_main_~z~0_2} AuxVars[] AssignedVars[main_~v~0, main_~w~0, main_~x~0, main_~z~0, main_~y~0] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L272 TraceCheckUtils]: 4: Hoare triple {2438#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2438#true} {2438#true} [125] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L290 TraceCheckUtils]: 2: Hoare triple {2438#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L290 TraceCheckUtils]: 1: Hoare triple {2438#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2438#true} is VALID [2022-04-27 16:58:36,325 INFO L272 TraceCheckUtils]: 0: Hoare triple {2438#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2438#true} is VALID [2022-04-27 16:58:36,327 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 16:58:36,327 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1176135498] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 16:58:36,327 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 16:58:36,327 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49, 49] total 98 [2022-04-27 16:58:36,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1977549814] [2022-04-27 16:58:36,328 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 16:58:36,329 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 2.0408163265306123) internal successors, (200), 97 states have internal predecessors, (200), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 107 [2022-04-27 16:58:36,329 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 16:58:36,330 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 98 states, 98 states have (on average 2.0408163265306123) internal successors, (200), 97 states have internal predecessors, (200), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:58:36,483 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 205 edges. 205 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 16:58:36,483 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-04-27 16:58:36,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 16:58:36,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-04-27 16:58:36,487 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2496, Invalid=7010, Unknown=0, NotChecked=0, Total=9506 [2022-04-27 16:58:36,487 INFO L87 Difference]: Start difference. First operand 114 states and 118 transitions. Second operand has 98 states, 98 states have (on average 2.0408163265306123) internal successors, (200), 97 states have internal predecessors, (200), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 16:59:31,453 WARN L232 SmtUtils]: Spent 9.85s on a formula simplification. DAG size of input: 196 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:00:21,287 WARN L232 SmtUtils]: Spent 7.66s on a formula simplification. DAG size of input: 192 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:00:23,336 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ c_main_~v~0 39) 4294967296) 268435455) (< (mod (+ 7 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 24) 4294967296) 268435455) (< (mod (+ c_main_~v~0 36) 4294967296) 268435455) (< (mod (+ 44 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 6) 4294967296) 268435455) (< (mod (+ c_main_~v~0 17) 4294967296) 268435455) (< (mod (+ c_main_~v~0 13) 4294967296) 268435455) (< (mod (+ c_main_~v~0 18) 4294967296) 268435455) (< (mod (+ 32 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 28) 4294967296) 268435455) (< (mod (+ c_main_~v~0 20) 4294967296) 268435455) (< (mod (+ 29 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 22 c_main_~v~0) 4294967296) 268435455) (< (mod c_main_~v~0 4294967296) 268435455) (< (mod (+ c_main_~v~0 38) 4294967296) 268435455) (< (mod (+ 9 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 4) 4294967296) 268435455) (< (mod (+ c_main_~v~0 26) 4294967296) 268435455) (< (mod (+ 30 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 10) 4294967296) 268435455) (< (mod (+ 19 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 40 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 35 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 25) 4294967296) 268435455) (< (mod (+ 42 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 34) 4294967296) 268435455) (< (mod (+ c_main_~v~0 43) 4294967296) 268435455) (< (mod (+ c_main_~v~0 31) 4294967296) 268435455) (< (mod (+ 23 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 1) 4294967296) 268435455) (< (mod (+ 14 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 37) 4294967296) 268435455) (< (mod (+ c_main_~v~0 12) 4294967296) 268435455) (< (mod (+ c_main_~v~0 33) 4294967296) 268435455) (< (mod (+ 16 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 2 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 11) 4294967296) 268435455) (< (mod (+ c_main_~v~0 15) 4294967296) 268435455) (< (mod (+ 5 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 8) 4294967296) 268435455) (< (mod (+ 41 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 27) 4294967296) 268435455) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 3 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 21 c_main_~v~0) 4294967296) 268435455)) is different from false [2022-04-27 17:01:24,896 WARN L232 SmtUtils]: Spent 9.88s on a formula simplification. DAG size of input: 180 DAG size of output: 12 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:02:31,269 WARN L232 SmtUtils]: Spent 13.77s on a formula simplification. DAG size of input: 184 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:03:23,213 WARN L232 SmtUtils]: Spent 9.01s on a formula simplification. DAG size of input: 180 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:04:28,142 WARN L232 SmtUtils]: Spent 9.32s on a formula simplification. DAG size of input: 176 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:05:37,259 WARN L232 SmtUtils]: Spent 15.80s on a formula simplification. DAG size of input: 172 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:06:40,366 WARN L232 SmtUtils]: Spent 8.83s on a formula simplification. DAG size of input: 168 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 17:06:42,421 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ 7 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 24) 4294967296) 268435455) (< (mod (+ c_main_~v~0 36) 4294967296) 268435455) (< (mod (+ c_main_~v~0 6) 4294967296) 268435455) (< (mod (+ c_main_~v~0 17) 4294967296) 268435455) (< (mod (+ c_main_~v~0 13) 4294967296) 268435455) (< (mod (+ c_main_~v~0 18) 4294967296) 268435455) (< (mod (+ 32 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 28) 4294967296) 268435455) (< (mod (+ c_main_~v~0 20) 4294967296) 268435455) (< (mod (+ 29 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 22 c_main_~v~0) 4294967296) 268435455) (< (mod c_main_~v~0 4294967296) 268435455) (< (mod (+ c_main_~v~0 38) 4294967296) 268435455) (< (mod (+ 9 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 4) 4294967296) 268435455) (< (mod (+ c_main_~v~0 26) 4294967296) 268435455) (< (mod (+ 30 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 10) 4294967296) 268435455) (< (mod (+ 19 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 35 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 25) 4294967296) 268435455) (< (mod (+ c_main_~v~0 34) 4294967296) 268435455) (< (mod (+ c_main_~v~0 31) 4294967296) 268435455) (< (mod (+ 23 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 1) 4294967296) 268435455) (< (mod (+ 14 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 37) 4294967296) 268435455) (< (mod (+ c_main_~v~0 12) 4294967296) 268435455) (< (mod (+ c_main_~v~0 33) 4294967296) 268435455) (< (mod (+ 16 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 2 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 11) 4294967296) 268435455) (< (mod (+ c_main_~v~0 15) 4294967296) 268435455) (< (mod (+ 5 c_main_~v~0) 4294967296) 268435455) (< (mod (+ c_main_~v~0 8) 4294967296) 268435455) (< (mod (+ c_main_~v~0 27) 4294967296) 268435455) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 3 c_main_~v~0) 4294967296) 268435455) (< (mod (+ 21 c_main_~v~0) 4294967296) 268435455)) is different from false [2022-04-27 17:07:56,681 WARN L232 SmtUtils]: Spent 15.29s on a formula simplification. DAG size of input: 156 DAG size of output: 12 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate)