/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array_1-1.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 21:11:53,119 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 21:11:53,121 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 21:11:53,163 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2022-04-27 21:11:53,177 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 21:11:53,179 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 21:11:53,180 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 21:11:53,182 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 21:11:53,183 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 21:11:53,183 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 21:11:53,185 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 21:11:53,190 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 21:11:53,192 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 21:11:53,193 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 21:11:53,193 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 21:11:53,194 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 21:11:53,195 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 21:11:53,201 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 21:11:53,207 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 21:11:53,208 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 21:11:53,209 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 21:11:53,209 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-27 21:11:53,235 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 21:11:53,235 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 21:11:53,236 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-27 21:11:53,236 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-27 21:11:53,237 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-27 21:11:53,237 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-27 21:11:53,237 INFO L138 SettingsManager]: * Use SBE=true [2022-04-27 21:11:53,237 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 21:11:53,237 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 21:11:53,238 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 21:11:53,238 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 21:11:53,238 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 21:11:53,238 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 21:11:53,239 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 21:11:53,239 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 21:11:53,239 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 21:11:53,239 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 21:11:53,239 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 21:11:53,239 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 21:11:53,239 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:11:53,239 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 21:11:53,240 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-27 21:11:53,240 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-27 21:11:53,240 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 21:11:53,240 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-27 21:11:53,240 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-27 21:11:53,240 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-27 21:11:53,241 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-27 21:11:53,241 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 21:11:53,241 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 21:11:53,432 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 21:11:53,458 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 21:11:53,460 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 21:11:53,460 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 21:11:53,461 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 21:11:53,462 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array_1-1.c [2022-04-27 21:11:53,532 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/af4cc88a6/f79bfa49b27f45bf969a5b4c9fbef874/FLAG3bcc550e1 [2022-04-27 21:11:53,882 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 21:11:53,883 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_1-1.c [2022-04-27 21:11:53,888 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/af4cc88a6/f79bfa49b27f45bf969a5b4c9fbef874/FLAG3bcc550e1 [2022-04-27 21:11:54,296 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/af4cc88a6/f79bfa49b27f45bf969a5b4c9fbef874 [2022-04-27 21:11:54,298 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 21:11:54,299 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 21:11:54,301 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 21:11:54,301 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 21:11:54,304 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 21:11:54,305 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,306 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4266844e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54, skipping insertion in model container [2022-04-27 21:11:54,306 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,311 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 21:11:54,321 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 21:11:54,455 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_1-1.c[321,334] [2022-04-27 21:11:54,465 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:11:54,472 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 21:11:54,482 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_1-1.c[321,334] [2022-04-27 21:11:54,485 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:11:54,495 INFO L208 MainTranslator]: Completed translation [2022-04-27 21:11:54,496 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54 WrapperNode [2022-04-27 21:11:54,496 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 21:11:54,497 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 21:11:54,497 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 21:11:54,497 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 21:11:54,505 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,505 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,510 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,510 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,515 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,518 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,519 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,520 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 21:11:54,521 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 21:11:54,521 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 21:11:54,521 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 21:11:54,523 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,532 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:11:54,541 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:11:54,551 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 21:11:54,561 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 21:11:54,586 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 21:11:54,586 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 21:11:54,586 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 21:11:54,586 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 21:11:54,586 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 21:11:54,586 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 21:11:54,587 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 21:11:54,588 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 21:11:54,588 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 21:11:54,588 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 21:11:54,588 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 21:11:54,633 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 21:11:54,634 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 21:11:54,773 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 21:11:54,779 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 21:11:54,779 INFO L299 CfgBuilder]: Removed 1 assume(true) statements. [2022-04-27 21:11:54,780 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:11:54 BoogieIcfgContainer [2022-04-27 21:11:54,780 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 21:11:54,781 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 21:11:54,781 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 21:11:54,782 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 21:11:54,785 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:11:54" (1/1) ... [2022-04-27 21:11:54,786 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-27 21:11:54,800 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:11:54 BasicIcfg [2022-04-27 21:11:54,800 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 21:11:54,802 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 21:11:54,802 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 21:11:54,804 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 21:11:54,805 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 09:11:54" (1/4) ... [2022-04-27 21:11:54,805 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a82ed4f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:11:54, skipping insertion in model container [2022-04-27 21:11:54,805 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:11:54" (2/4) ... [2022-04-27 21:11:54,806 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a82ed4f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:11:54, skipping insertion in model container [2022-04-27 21:11:54,806 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:11:54" (3/4) ... [2022-04-27 21:11:54,806 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4a82ed4f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 09:11:54, skipping insertion in model container [2022-04-27 21:11:54,806 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:11:54" (4/4) ... [2022-04-27 21:11:54,807 INFO L111 eAbstractionObserver]: Analyzing ICFG array_1-1.cqvasr [2022-04-27 21:11:54,819 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-27 21:11:54,819 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 21:11:54,853 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 21:11:54,858 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@6a112702, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@b120f85 [2022-04-27 21:11:54,859 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 21:11:54,865 INFO L276 IsEmpty]: Start isEmpty. Operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:11:54,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-04-27 21:11:54,870 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:11:54,871 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:11:54,871 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:11:54,875 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:11:54,876 INFO L85 PathProgramCache]: Analyzing trace with hash -737742564, now seen corresponding path program 1 times [2022-04-27 21:11:54,883 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:11:54,884 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599377321] [2022-04-27 21:11:54,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:54,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:11:54,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,033 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:11:55,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,052 INFO L290 TraceCheckUtils]: 0: Hoare triple {29#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {24#true} is VALID [2022-04-27 21:11:55,052 INFO L290 TraceCheckUtils]: 1: Hoare triple {24#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 21:11:55,052 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {24#true} {24#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 21:11:55,054 INFO L272 TraceCheckUtils]: 0: Hoare triple {24#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {29#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:11:55,055 INFO L290 TraceCheckUtils]: 1: Hoare triple {29#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {24#true} is VALID [2022-04-27 21:11:55,055 INFO L290 TraceCheckUtils]: 2: Hoare triple {24#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 21:11:55,055 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {24#true} {24#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 21:11:55,055 INFO L272 TraceCheckUtils]: 4: Hoare triple {24#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {24#true} is VALID [2022-04-27 21:11:55,056 INFO L290 TraceCheckUtils]: 5: Hoare triple {24#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {24#true} is VALID [2022-04-27 21:11:55,056 INFO L290 TraceCheckUtils]: 6: Hoare triple {24#true} [48] L16-3-->L16-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {25#false} is VALID [2022-04-27 21:11:55,057 INFO L290 TraceCheckUtils]: 7: Hoare triple {25#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {25#false} is VALID [2022-04-27 21:11:55,057 INFO L272 TraceCheckUtils]: 8: Hoare triple {25#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {25#false} is VALID [2022-04-27 21:11:55,057 INFO L290 TraceCheckUtils]: 9: Hoare triple {25#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {25#false} is VALID [2022-04-27 21:11:55,058 INFO L290 TraceCheckUtils]: 10: Hoare triple {25#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {25#false} is VALID [2022-04-27 21:11:55,058 INFO L290 TraceCheckUtils]: 11: Hoare triple {25#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {25#false} is VALID [2022-04-27 21:11:55,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:55,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:11:55,059 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599377321] [2022-04-27 21:11:55,060 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599377321] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:11:55,060 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:11:55,060 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 21:11:55,062 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455904399] [2022-04-27 21:11:55,062 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:11:55,066 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 21:11:55,068 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:11:55,070 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,086 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 12 edges. 12 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:55,086 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 21:11:55,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:11:55,108 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 21:11:55,108 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:11:55,111 INFO L87 Difference]: Start difference. First operand has 21 states, 13 states have (on average 1.3076923076923077) internal successors, (17), 14 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:55,213 INFO L93 Difference]: Finished difference Result 34 states and 37 transitions. [2022-04-27 21:11:55,213 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 21:11:55,215 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 21:11:55,215 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:11:55,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2022-04-27 21:11:55,227 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 37 transitions. [2022-04-27 21:11:55,234 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 37 transitions. [2022-04-27 21:11:55,301 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:55,307 INFO L225 Difference]: With dead ends: 34 [2022-04-27 21:11:55,308 INFO L226 Difference]: Without dead ends: 14 [2022-04-27 21:11:55,310 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:11:55,313 INFO L413 NwaCegarLoop]: 20 mSDtfsCounter, 12 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 23 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:11:55,313 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 23 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:11:55,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2022-04-27 21:11:55,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2022-04-27 21:11:55,347 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:11:55,348 INFO L82 GeneralOperation]: Start isEquivalent. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,349 INFO L74 IsIncluded]: Start isIncluded. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,349 INFO L87 Difference]: Start difference. First operand 14 states. Second operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,355 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:55,355 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2022-04-27 21:11:55,355 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-27 21:11:55,355 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:55,356 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:55,356 INFO L74 IsIncluded]: Start isIncluded. First operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 14 states. [2022-04-27 21:11:55,357 INFO L87 Difference]: Start difference. First operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 14 states. [2022-04-27 21:11:55,359 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:55,359 INFO L93 Difference]: Finished difference Result 14 states and 14 transitions. [2022-04-27 21:11:55,359 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-27 21:11:55,360 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:55,360 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:55,360 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:11:55,360 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:11:55,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 9 states have (on average 1.1111111111111112) internal successors, (10), 9 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2022-04-27 21:11:55,362 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 12 [2022-04-27 21:11:55,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:11:55,362 INFO L495 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2022-04-27 21:11:55,362 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 2 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,363 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2022-04-27 21:11:55,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-04-27 21:11:55,363 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:11:55,363 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:11:55,363 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 21:11:55,364 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:11:55,365 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:11:55,365 INFO L85 PathProgramCache]: Analyzing trace with hash -709113413, now seen corresponding path program 1 times [2022-04-27 21:11:55,365 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:11:55,365 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280677940] [2022-04-27 21:11:55,365 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:55,365 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:11:55,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,434 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:11:55,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,444 INFO L290 TraceCheckUtils]: 0: Hoare triple {130#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {124#true} is VALID [2022-04-27 21:11:55,444 INFO L290 TraceCheckUtils]: 1: Hoare triple {124#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {124#true} is VALID [2022-04-27 21:11:55,445 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {124#true} {124#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {124#true} is VALID [2022-04-27 21:11:55,445 INFO L272 TraceCheckUtils]: 0: Hoare triple {124#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {130#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:11:55,446 INFO L290 TraceCheckUtils]: 1: Hoare triple {130#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {124#true} is VALID [2022-04-27 21:11:55,446 INFO L290 TraceCheckUtils]: 2: Hoare triple {124#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {124#true} is VALID [2022-04-27 21:11:55,446 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {124#true} {124#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {124#true} is VALID [2022-04-27 21:11:55,447 INFO L272 TraceCheckUtils]: 4: Hoare triple {124#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {124#true} is VALID [2022-04-27 21:11:55,447 INFO L290 TraceCheckUtils]: 5: Hoare triple {124#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {129#(= main_~i~0 0)} is VALID [2022-04-27 21:11:55,448 INFO L290 TraceCheckUtils]: 6: Hoare triple {129#(= main_~i~0 0)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {125#false} is VALID [2022-04-27 21:11:55,448 INFO L290 TraceCheckUtils]: 7: Hoare triple {125#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {125#false} is VALID [2022-04-27 21:11:55,448 INFO L272 TraceCheckUtils]: 8: Hoare triple {125#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {125#false} is VALID [2022-04-27 21:11:55,449 INFO L290 TraceCheckUtils]: 9: Hoare triple {125#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {125#false} is VALID [2022-04-27 21:11:55,449 INFO L290 TraceCheckUtils]: 10: Hoare triple {125#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {125#false} is VALID [2022-04-27 21:11:55,449 INFO L290 TraceCheckUtils]: 11: Hoare triple {125#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {125#false} is VALID [2022-04-27 21:11:55,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:55,450 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:11:55,450 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280677940] [2022-04-27 21:11:55,450 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280677940] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:11:55,450 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:11:55,450 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 21:11:55,451 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [632696038] [2022-04-27 21:11:55,451 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:11:55,452 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 21:11:55,452 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:11:55,452 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,463 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 12 edges. 12 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:55,464 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 21:11:55,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:11:55,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 21:11:55,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 21:11:55,465 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:55,512 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2022-04-27 21:11:55,512 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 21:11:55,512 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 21:11:55,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:11:55,513 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,514 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 22 transitions. [2022-04-27 21:11:55,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 22 transitions. [2022-04-27 21:11:55,515 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 22 transitions. [2022-04-27 21:11:55,540 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 22 edges. 22 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:55,543 INFO L225 Difference]: With dead ends: 22 [2022-04-27 21:11:55,543 INFO L226 Difference]: Without dead ends: 16 [2022-04-27 21:11:55,544 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 21:11:55,545 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 10 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 19 SdHoareTripleChecker+Invalid, 14 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:11:55,546 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 19 Invalid, 14 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:11:55,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2022-04-27 21:11:55,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2022-04-27 21:11:55,554 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:11:55,554 INFO L82 GeneralOperation]: Start isEquivalent. First operand 16 states. Second operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,555 INFO L74 IsIncluded]: Start isIncluded. First operand 16 states. Second operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,555 INFO L87 Difference]: Start difference. First operand 16 states. Second operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:55,556 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 21:11:55,556 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 21:11:55,557 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:55,557 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:55,557 INFO L74 IsIncluded]: Start isIncluded. First operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 21:11:55,557 INFO L87 Difference]: Start difference. First operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 21:11:55,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:55,558 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 21:11:55,559 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 21:11:55,559 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:55,559 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:55,559 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:11:55,559 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:11:55,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 10 states have (on average 1.1) internal successors, (11), 10 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2022-04-27 21:11:55,561 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 12 [2022-04-27 21:11:55,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:11:55,561 INFO L495 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2022-04-27 21:11:55,561 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 2.0) internal successors, (8), 3 states have internal predecessors, (8), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:55,561 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2022-04-27 21:11:55,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2022-04-27 21:11:55,562 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:11:55,562 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:11:55,562 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 21:11:55,562 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:11:55,563 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:11:55,563 INFO L85 PathProgramCache]: Analyzing trace with hash -341174979, now seen corresponding path program 1 times [2022-04-27 21:11:55,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:11:55,563 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86110982] [2022-04-27 21:11:55,564 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:55,564 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:11:55,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,652 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:11:55,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,676 INFO L290 TraceCheckUtils]: 0: Hoare triple {229#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 21:11:55,676 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,676 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {222#true} {222#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,677 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {229#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:11:55,677 INFO L290 TraceCheckUtils]: 1: Hoare triple {229#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 21:11:55,678 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,678 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,678 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,679 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {227#(= main_~i~0 0)} is VALID [2022-04-27 21:11:55,679 INFO L290 TraceCheckUtils]: 6: Hoare triple {227#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {227#(= main_~i~0 0)} is VALID [2022-04-27 21:11:55,680 INFO L290 TraceCheckUtils]: 7: Hoare triple {227#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {228#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:55,680 INFO L290 TraceCheckUtils]: 8: Hoare triple {228#(<= main_~i~0 1)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,681 INFO L290 TraceCheckUtils]: 9: Hoare triple {223#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {223#false} is VALID [2022-04-27 21:11:55,681 INFO L272 TraceCheckUtils]: 10: Hoare triple {223#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {223#false} is VALID [2022-04-27 21:11:55,681 INFO L290 TraceCheckUtils]: 11: Hoare triple {223#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {223#false} is VALID [2022-04-27 21:11:55,681 INFO L290 TraceCheckUtils]: 12: Hoare triple {223#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,682 INFO L290 TraceCheckUtils]: 13: Hoare triple {223#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,682 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:55,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:11:55,682 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86110982] [2022-04-27 21:11:55,682 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86110982] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:11:55,683 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [721176129] [2022-04-27 21:11:55,683 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:55,683 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:11:55,683 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:11:55,685 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:11:55,719 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 21:11:55,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,742 INFO L263 TraceCheckSpWp]: Trace formula consists of 76 conjuncts, 3 conjunts are in the unsatisfiable core [2022-04-27 21:11:55,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:55,774 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:11:55,874 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,878 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 21:11:55,878 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,880 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,880 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,881 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {248#(<= main_~i~0 0)} is VALID [2022-04-27 21:11:55,881 INFO L290 TraceCheckUtils]: 6: Hoare triple {248#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {248#(<= main_~i~0 0)} is VALID [2022-04-27 21:11:55,882 INFO L290 TraceCheckUtils]: 7: Hoare triple {248#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {228#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:55,884 INFO L290 TraceCheckUtils]: 8: Hoare triple {228#(<= main_~i~0 1)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,885 INFO L290 TraceCheckUtils]: 9: Hoare triple {223#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {223#false} is VALID [2022-04-27 21:11:55,886 INFO L272 TraceCheckUtils]: 10: Hoare triple {223#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {223#false} is VALID [2022-04-27 21:11:55,886 INFO L290 TraceCheckUtils]: 11: Hoare triple {223#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {223#false} is VALID [2022-04-27 21:11:55,886 INFO L290 TraceCheckUtils]: 12: Hoare triple {223#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,886 INFO L290 TraceCheckUtils]: 13: Hoare triple {223#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,887 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:55,887 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:11:55,973 INFO L290 TraceCheckUtils]: 13: Hoare triple {223#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,973 INFO L290 TraceCheckUtils]: 12: Hoare triple {223#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,974 INFO L290 TraceCheckUtils]: 11: Hoare triple {223#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {223#false} is VALID [2022-04-27 21:11:55,974 INFO L272 TraceCheckUtils]: 10: Hoare triple {223#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {223#false} is VALID [2022-04-27 21:11:55,974 INFO L290 TraceCheckUtils]: 9: Hoare triple {223#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {223#false} is VALID [2022-04-27 21:11:55,975 INFO L290 TraceCheckUtils]: 8: Hoare triple {288#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {223#false} is VALID [2022-04-27 21:11:55,975 INFO L290 TraceCheckUtils]: 7: Hoare triple {292#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {288#(< main_~i~0 1024)} is VALID [2022-04-27 21:11:55,976 INFO L290 TraceCheckUtils]: 6: Hoare triple {292#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {292#(< main_~i~0 1023)} is VALID [2022-04-27 21:11:55,977 INFO L290 TraceCheckUtils]: 5: Hoare triple {222#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {292#(< main_~i~0 1023)} is VALID [2022-04-27 21:11:55,977 INFO L272 TraceCheckUtils]: 4: Hoare triple {222#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,977 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {222#true} {222#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,977 INFO L290 TraceCheckUtils]: 2: Hoare triple {222#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,978 INFO L290 TraceCheckUtils]: 1: Hoare triple {222#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {222#true} is VALID [2022-04-27 21:11:55,978 INFO L272 TraceCheckUtils]: 0: Hoare triple {222#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {222#true} is VALID [2022-04-27 21:11:55,978 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:55,981 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [721176129] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:11:55,982 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:11:55,982 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-27 21:11:55,982 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [898224341] [2022-04-27 21:11:55,982 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:11:55,984 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-27 21:11:55,985 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:11:55,985 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,003 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:56,003 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 21:11:56,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:11:56,004 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 21:11:56,004 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2022-04-27 21:11:56,005 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:56,115 INFO L93 Difference]: Finished difference Result 27 states and 29 transitions. [2022-04-27 21:11:56,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:11:56,116 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 14 [2022-04-27 21:11:56,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:11:56,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 29 transitions. [2022-04-27 21:11:56,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 29 transitions. [2022-04-27 21:11:56,123 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 29 transitions. [2022-04-27 21:11:56,147 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 29 edges. 29 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:56,148 INFO L225 Difference]: With dead ends: 27 [2022-04-27 21:11:56,149 INFO L226 Difference]: Without dead ends: 21 [2022-04-27 21:11:56,149 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=52, Invalid=80, Unknown=0, NotChecked=0, Total=132 [2022-04-27 21:11:56,154 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 17 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 22 mSolverCounterSat, 11 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 17 SdHoareTripleChecker+Valid, 24 SdHoareTripleChecker+Invalid, 33 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 11 IncrementalHoareTripleChecker+Valid, 22 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:11:56,156 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [17 Valid, 24 Invalid, 33 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [11 Valid, 22 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:11:56,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2022-04-27 21:11:56,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2022-04-27 21:11:56,163 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:11:56,163 INFO L82 GeneralOperation]: Start isEquivalent. First operand 21 states. Second operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,166 INFO L74 IsIncluded]: Start isIncluded. First operand 21 states. Second operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,167 INFO L87 Difference]: Start difference. First operand 21 states. Second operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:56,169 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-27 21:11:56,169 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-04-27 21:11:56,170 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:56,170 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:56,170 INFO L74 IsIncluded]: Start isIncluded. First operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 21 states. [2022-04-27 21:11:56,170 INFO L87 Difference]: Start difference. First operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 21 states. [2022-04-27 21:11:56,172 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:56,172 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2022-04-27 21:11:56,172 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-04-27 21:11:56,173 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:56,173 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:56,173 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:11:56,173 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:11:56,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21 states, 16 states have (on average 1.0625) internal successors, (17), 16 states have internal predecessors, (17), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2022-04-27 21:11:56,179 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 14 [2022-04-27 21:11:56,179 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:11:56,180 INFO L495 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2022-04-27 21:11:56,180 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 2.25) internal successors, (18), 7 states have internal predecessors, (18), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,180 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2022-04-27 21:11:56,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2022-04-27 21:11:56,181 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:11:56,181 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:11:56,204 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 21:11:56,395 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:11:56,396 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:11:56,396 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:11:56,396 INFO L85 PathProgramCache]: Analyzing trace with hash -1847565117, now seen corresponding path program 2 times [2022-04-27 21:11:56,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:11:56,397 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1675832469] [2022-04-27 21:11:56,397 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:56,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:11:56,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:56,518 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:11:56,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:56,541 INFO L290 TraceCheckUtils]: 0: Hoare triple {448#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {438#true} is VALID [2022-04-27 21:11:56,541 INFO L290 TraceCheckUtils]: 1: Hoare triple {438#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,542 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {438#true} {438#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,542 INFO L272 TraceCheckUtils]: 0: Hoare triple {438#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {448#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:11:56,543 INFO L290 TraceCheckUtils]: 1: Hoare triple {448#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {438#true} is VALID [2022-04-27 21:11:56,543 INFO L290 TraceCheckUtils]: 2: Hoare triple {438#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,543 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {438#true} {438#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,543 INFO L272 TraceCheckUtils]: 4: Hoare triple {438#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,544 INFO L290 TraceCheckUtils]: 5: Hoare triple {438#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {443#(= main_~i~0 0)} is VALID [2022-04-27 21:11:56,545 INFO L290 TraceCheckUtils]: 6: Hoare triple {443#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {443#(= main_~i~0 0)} is VALID [2022-04-27 21:11:56,545 INFO L290 TraceCheckUtils]: 7: Hoare triple {443#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {444#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:56,546 INFO L290 TraceCheckUtils]: 8: Hoare triple {444#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {444#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:56,546 INFO L290 TraceCheckUtils]: 9: Hoare triple {444#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {445#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:56,547 INFO L290 TraceCheckUtils]: 10: Hoare triple {445#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {445#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:56,548 INFO L290 TraceCheckUtils]: 11: Hoare triple {445#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {446#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:56,550 INFO L290 TraceCheckUtils]: 12: Hoare triple {446#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {446#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:56,552 INFO L290 TraceCheckUtils]: 13: Hoare triple {446#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {447#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:56,552 INFO L290 TraceCheckUtils]: 14: Hoare triple {447#(<= main_~i~0 4)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,553 INFO L290 TraceCheckUtils]: 15: Hoare triple {439#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {439#false} is VALID [2022-04-27 21:11:56,553 INFO L272 TraceCheckUtils]: 16: Hoare triple {439#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {439#false} is VALID [2022-04-27 21:11:56,553 INFO L290 TraceCheckUtils]: 17: Hoare triple {439#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {439#false} is VALID [2022-04-27 21:11:56,554 INFO L290 TraceCheckUtils]: 18: Hoare triple {439#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,554 INFO L290 TraceCheckUtils]: 19: Hoare triple {439#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,554 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:56,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:11:56,554 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1675832469] [2022-04-27 21:11:56,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1675832469] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:11:56,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1814011730] [2022-04-27 21:11:56,555 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:11:56,555 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:11:56,555 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:11:56,560 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:11:56,561 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 21:11:56,604 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:11:56,604 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:11:56,605 INFO L263 TraceCheckSpWp]: Trace formula consists of 97 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 21:11:56,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:56,617 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:11:56,748 INFO L272 TraceCheckUtils]: 0: Hoare triple {438#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,748 INFO L290 TraceCheckUtils]: 1: Hoare triple {438#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {438#true} is VALID [2022-04-27 21:11:56,749 INFO L290 TraceCheckUtils]: 2: Hoare triple {438#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,750 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {438#true} {438#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,752 INFO L272 TraceCheckUtils]: 4: Hoare triple {438#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,753 INFO L290 TraceCheckUtils]: 5: Hoare triple {438#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {467#(<= main_~i~0 0)} is VALID [2022-04-27 21:11:56,753 INFO L290 TraceCheckUtils]: 6: Hoare triple {467#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {467#(<= main_~i~0 0)} is VALID [2022-04-27 21:11:56,754 INFO L290 TraceCheckUtils]: 7: Hoare triple {467#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {444#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:56,754 INFO L290 TraceCheckUtils]: 8: Hoare triple {444#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {444#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:56,755 INFO L290 TraceCheckUtils]: 9: Hoare triple {444#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {445#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:56,755 INFO L290 TraceCheckUtils]: 10: Hoare triple {445#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {445#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:56,756 INFO L290 TraceCheckUtils]: 11: Hoare triple {445#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {446#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:56,757 INFO L290 TraceCheckUtils]: 12: Hoare triple {446#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {446#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:56,758 INFO L290 TraceCheckUtils]: 13: Hoare triple {446#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {447#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:56,759 INFO L290 TraceCheckUtils]: 14: Hoare triple {447#(<= main_~i~0 4)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,760 INFO L290 TraceCheckUtils]: 15: Hoare triple {439#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {439#false} is VALID [2022-04-27 21:11:56,760 INFO L272 TraceCheckUtils]: 16: Hoare triple {439#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {439#false} is VALID [2022-04-27 21:11:56,761 INFO L290 TraceCheckUtils]: 17: Hoare triple {439#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {439#false} is VALID [2022-04-27 21:11:56,761 INFO L290 TraceCheckUtils]: 18: Hoare triple {439#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,762 INFO L290 TraceCheckUtils]: 19: Hoare triple {439#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,763 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:56,763 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:11:56,927 INFO L290 TraceCheckUtils]: 19: Hoare triple {439#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,928 INFO L290 TraceCheckUtils]: 18: Hoare triple {439#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,928 INFO L290 TraceCheckUtils]: 17: Hoare triple {439#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {439#false} is VALID [2022-04-27 21:11:56,928 INFO L272 TraceCheckUtils]: 16: Hoare triple {439#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {439#false} is VALID [2022-04-27 21:11:56,929 INFO L290 TraceCheckUtils]: 15: Hoare triple {439#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {439#false} is VALID [2022-04-27 21:11:56,939 INFO L290 TraceCheckUtils]: 14: Hoare triple {525#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {439#false} is VALID [2022-04-27 21:11:56,940 INFO L290 TraceCheckUtils]: 13: Hoare triple {529#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {525#(< main_~i~0 1024)} is VALID [2022-04-27 21:11:56,941 INFO L290 TraceCheckUtils]: 12: Hoare triple {529#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {529#(< main_~i~0 1023)} is VALID [2022-04-27 21:11:56,941 INFO L290 TraceCheckUtils]: 11: Hoare triple {536#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {529#(< main_~i~0 1023)} is VALID [2022-04-27 21:11:56,942 INFO L290 TraceCheckUtils]: 10: Hoare triple {536#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {536#(< main_~i~0 1022)} is VALID [2022-04-27 21:11:56,942 INFO L290 TraceCheckUtils]: 9: Hoare triple {543#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {536#(< main_~i~0 1022)} is VALID [2022-04-27 21:11:56,943 INFO L290 TraceCheckUtils]: 8: Hoare triple {543#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {543#(< main_~i~0 1021)} is VALID [2022-04-27 21:11:56,943 INFO L290 TraceCheckUtils]: 7: Hoare triple {550#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {543#(< main_~i~0 1021)} is VALID [2022-04-27 21:11:56,944 INFO L290 TraceCheckUtils]: 6: Hoare triple {550#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {550#(< main_~i~0 1020)} is VALID [2022-04-27 21:11:56,945 INFO L290 TraceCheckUtils]: 5: Hoare triple {438#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {550#(< main_~i~0 1020)} is VALID [2022-04-27 21:11:56,945 INFO L272 TraceCheckUtils]: 4: Hoare triple {438#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,945 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {438#true} {438#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,945 INFO L290 TraceCheckUtils]: 2: Hoare triple {438#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,946 INFO L290 TraceCheckUtils]: 1: Hoare triple {438#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {438#true} is VALID [2022-04-27 21:11:56,946 INFO L272 TraceCheckUtils]: 0: Hoare triple {438#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {438#true} is VALID [2022-04-27 21:11:56,946 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:56,946 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1814011730] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:11:56,946 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:11:56,946 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 21:11:56,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [925558500] [2022-04-27 21:11:56,947 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:11:56,947 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 21:11:56,948 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:11:56,948 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:56,979 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:56,980 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 21:11:56,980 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:11:56,981 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 21:11:56,981 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2022-04-27 21:11:56,982 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:57,239 INFO L93 Difference]: Finished difference Result 39 states and 44 transitions. [2022-04-27 21:11:57,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 21:11:57,240 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 20 [2022-04-27 21:11:57,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:11:57,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 44 transitions. [2022-04-27 21:11:57,242 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 44 transitions. [2022-04-27 21:11:57,244 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 44 transitions. [2022-04-27 21:11:57,281 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 44 edges. 44 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:57,282 INFO L225 Difference]: With dead ends: 39 [2022-04-27 21:11:57,282 INFO L226 Difference]: Without dead ends: 33 [2022-04-27 21:11:57,282 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 79 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=211, Invalid=341, Unknown=0, NotChecked=0, Total=552 [2022-04-27 21:11:57,283 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 32 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 42 mSolverCounterSat, 21 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 63 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 21 IncrementalHoareTripleChecker+Valid, 42 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:11:57,284 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 29 Invalid, 63 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [21 Valid, 42 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:11:57,284 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-27 21:11:57,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2022-04-27 21:11:57,295 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:11:57,295 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,295 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,295 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,297 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:57,297 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2022-04-27 21:11:57,298 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2022-04-27 21:11:57,298 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:57,298 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:57,298 INFO L74 IsIncluded]: Start isIncluded. First operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 33 states. [2022-04-27 21:11:57,298 INFO L87 Difference]: Start difference. First operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 33 states. [2022-04-27 21:11:57,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:57,300 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2022-04-27 21:11:57,300 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2022-04-27 21:11:57,300 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:57,300 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:57,301 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:11:57,301 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:11:57,301 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 28 states have (on average 1.0357142857142858) internal successors, (29), 28 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2022-04-27 21:11:57,302 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 20 [2022-04-27 21:11:57,302 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:11:57,302 INFO L495 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2022-04-27 21:11:57,303 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.142857142857143) internal successors, (30), 13 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:57,303 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2022-04-27 21:11:57,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2022-04-27 21:11:57,303 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:11:57,303 INFO L195 NwaCegarLoop]: trace histogram [10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:11:57,321 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2022-04-27 21:11:57,515 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 21:11:57,516 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:11:57,516 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:11:57,516 INFO L85 PathProgramCache]: Analyzing trace with hash 1093643855, now seen corresponding path program 3 times [2022-04-27 21:11:57,516 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:11:57,517 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080534641] [2022-04-27 21:11:57,517 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:57,517 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:11:57,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:57,681 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:11:57,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:57,689 INFO L290 TraceCheckUtils]: 0: Hoare triple {784#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {768#true} is VALID [2022-04-27 21:11:57,689 INFO L290 TraceCheckUtils]: 1: Hoare triple {768#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:57,689 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {768#true} {768#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:57,690 INFO L272 TraceCheckUtils]: 0: Hoare triple {768#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {784#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:11:57,690 INFO L290 TraceCheckUtils]: 1: Hoare triple {784#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {768#true} is VALID [2022-04-27 21:11:57,690 INFO L290 TraceCheckUtils]: 2: Hoare triple {768#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:57,690 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {768#true} {768#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:57,691 INFO L272 TraceCheckUtils]: 4: Hoare triple {768#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:57,691 INFO L290 TraceCheckUtils]: 5: Hoare triple {768#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {773#(= main_~i~0 0)} is VALID [2022-04-27 21:11:57,692 INFO L290 TraceCheckUtils]: 6: Hoare triple {773#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {773#(= main_~i~0 0)} is VALID [2022-04-27 21:11:57,692 INFO L290 TraceCheckUtils]: 7: Hoare triple {773#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {774#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:57,692 INFO L290 TraceCheckUtils]: 8: Hoare triple {774#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {774#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:57,693 INFO L290 TraceCheckUtils]: 9: Hoare triple {774#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {775#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:57,693 INFO L290 TraceCheckUtils]: 10: Hoare triple {775#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {775#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:57,694 INFO L290 TraceCheckUtils]: 11: Hoare triple {775#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {776#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:57,694 INFO L290 TraceCheckUtils]: 12: Hoare triple {776#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {776#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:57,695 INFO L290 TraceCheckUtils]: 13: Hoare triple {776#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {777#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:57,695 INFO L290 TraceCheckUtils]: 14: Hoare triple {777#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {777#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:57,695 INFO L290 TraceCheckUtils]: 15: Hoare triple {777#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {778#(<= main_~i~0 5)} is VALID [2022-04-27 21:11:57,696 INFO L290 TraceCheckUtils]: 16: Hoare triple {778#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {778#(<= main_~i~0 5)} is VALID [2022-04-27 21:11:57,696 INFO L290 TraceCheckUtils]: 17: Hoare triple {778#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {779#(<= main_~i~0 6)} is VALID [2022-04-27 21:11:57,697 INFO L290 TraceCheckUtils]: 18: Hoare triple {779#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {779#(<= main_~i~0 6)} is VALID [2022-04-27 21:11:57,697 INFO L290 TraceCheckUtils]: 19: Hoare triple {779#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {780#(<= main_~i~0 7)} is VALID [2022-04-27 21:11:57,697 INFO L290 TraceCheckUtils]: 20: Hoare triple {780#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {780#(<= main_~i~0 7)} is VALID [2022-04-27 21:11:57,698 INFO L290 TraceCheckUtils]: 21: Hoare triple {780#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {781#(<= main_~i~0 8)} is VALID [2022-04-27 21:11:57,698 INFO L290 TraceCheckUtils]: 22: Hoare triple {781#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {781#(<= main_~i~0 8)} is VALID [2022-04-27 21:11:57,699 INFO L290 TraceCheckUtils]: 23: Hoare triple {781#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {782#(<= main_~i~0 9)} is VALID [2022-04-27 21:11:57,699 INFO L290 TraceCheckUtils]: 24: Hoare triple {782#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {782#(<= main_~i~0 9)} is VALID [2022-04-27 21:11:57,700 INFO L290 TraceCheckUtils]: 25: Hoare triple {782#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {783#(<= main_~i~0 10)} is VALID [2022-04-27 21:11:57,700 INFO L290 TraceCheckUtils]: 26: Hoare triple {783#(<= main_~i~0 10)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:57,700 INFO L290 TraceCheckUtils]: 27: Hoare triple {769#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {769#false} is VALID [2022-04-27 21:11:57,700 INFO L272 TraceCheckUtils]: 28: Hoare triple {769#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {769#false} is VALID [2022-04-27 21:11:57,701 INFO L290 TraceCheckUtils]: 29: Hoare triple {769#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {769#false} is VALID [2022-04-27 21:11:57,701 INFO L290 TraceCheckUtils]: 30: Hoare triple {769#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:57,701 INFO L290 TraceCheckUtils]: 31: Hoare triple {769#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:57,701 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:57,701 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:11:57,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2080534641] [2022-04-27 21:11:57,702 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2080534641] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:11:57,702 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [487324838] [2022-04-27 21:11:57,702 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 21:11:57,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:11:57,702 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:11:57,703 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:11:57,722 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 21:11:57,822 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2022-04-27 21:11:57,823 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:11:57,824 INFO L263 TraceCheckSpWp]: Trace formula consists of 139 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 21:11:57,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:57,836 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:11:58,032 INFO L272 TraceCheckUtils]: 0: Hoare triple {768#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,032 INFO L290 TraceCheckUtils]: 1: Hoare triple {768#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {768#true} is VALID [2022-04-27 21:11:58,033 INFO L290 TraceCheckUtils]: 2: Hoare triple {768#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,033 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {768#true} {768#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,033 INFO L272 TraceCheckUtils]: 4: Hoare triple {768#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,034 INFO L290 TraceCheckUtils]: 5: Hoare triple {768#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {803#(<= main_~i~0 0)} is VALID [2022-04-27 21:11:58,034 INFO L290 TraceCheckUtils]: 6: Hoare triple {803#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {803#(<= main_~i~0 0)} is VALID [2022-04-27 21:11:58,035 INFO L290 TraceCheckUtils]: 7: Hoare triple {803#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {774#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:58,035 INFO L290 TraceCheckUtils]: 8: Hoare triple {774#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {774#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:58,036 INFO L290 TraceCheckUtils]: 9: Hoare triple {774#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {775#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:58,036 INFO L290 TraceCheckUtils]: 10: Hoare triple {775#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {775#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:58,037 INFO L290 TraceCheckUtils]: 11: Hoare triple {775#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {776#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:58,037 INFO L290 TraceCheckUtils]: 12: Hoare triple {776#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {776#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:58,038 INFO L290 TraceCheckUtils]: 13: Hoare triple {776#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {777#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:58,038 INFO L290 TraceCheckUtils]: 14: Hoare triple {777#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {777#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:58,039 INFO L290 TraceCheckUtils]: 15: Hoare triple {777#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {778#(<= main_~i~0 5)} is VALID [2022-04-27 21:11:58,039 INFO L290 TraceCheckUtils]: 16: Hoare triple {778#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {778#(<= main_~i~0 5)} is VALID [2022-04-27 21:11:58,040 INFO L290 TraceCheckUtils]: 17: Hoare triple {778#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {779#(<= main_~i~0 6)} is VALID [2022-04-27 21:11:58,040 INFO L290 TraceCheckUtils]: 18: Hoare triple {779#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {779#(<= main_~i~0 6)} is VALID [2022-04-27 21:11:58,041 INFO L290 TraceCheckUtils]: 19: Hoare triple {779#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {780#(<= main_~i~0 7)} is VALID [2022-04-27 21:11:58,041 INFO L290 TraceCheckUtils]: 20: Hoare triple {780#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {780#(<= main_~i~0 7)} is VALID [2022-04-27 21:11:58,042 INFO L290 TraceCheckUtils]: 21: Hoare triple {780#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {781#(<= main_~i~0 8)} is VALID [2022-04-27 21:11:58,042 INFO L290 TraceCheckUtils]: 22: Hoare triple {781#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {781#(<= main_~i~0 8)} is VALID [2022-04-27 21:11:58,043 INFO L290 TraceCheckUtils]: 23: Hoare triple {781#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {782#(<= main_~i~0 9)} is VALID [2022-04-27 21:11:58,043 INFO L290 TraceCheckUtils]: 24: Hoare triple {782#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {782#(<= main_~i~0 9)} is VALID [2022-04-27 21:11:58,044 INFO L290 TraceCheckUtils]: 25: Hoare triple {782#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {783#(<= main_~i~0 10)} is VALID [2022-04-27 21:11:58,045 INFO L290 TraceCheckUtils]: 26: Hoare triple {783#(<= main_~i~0 10)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:58,045 INFO L290 TraceCheckUtils]: 27: Hoare triple {769#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {769#false} is VALID [2022-04-27 21:11:58,045 INFO L272 TraceCheckUtils]: 28: Hoare triple {769#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {769#false} is VALID [2022-04-27 21:11:58,045 INFO L290 TraceCheckUtils]: 29: Hoare triple {769#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {769#false} is VALID [2022-04-27 21:11:58,045 INFO L290 TraceCheckUtils]: 30: Hoare triple {769#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:58,046 INFO L290 TraceCheckUtils]: 31: Hoare triple {769#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:58,046 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:58,046 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:11:58,410 INFO L290 TraceCheckUtils]: 31: Hoare triple {769#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:58,410 INFO L290 TraceCheckUtils]: 30: Hoare triple {769#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:58,410 INFO L290 TraceCheckUtils]: 29: Hoare triple {769#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {769#false} is VALID [2022-04-27 21:11:58,411 INFO L272 TraceCheckUtils]: 28: Hoare triple {769#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {769#false} is VALID [2022-04-27 21:11:58,411 INFO L290 TraceCheckUtils]: 27: Hoare triple {769#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {769#false} is VALID [2022-04-27 21:11:58,411 INFO L290 TraceCheckUtils]: 26: Hoare triple {897#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {769#false} is VALID [2022-04-27 21:11:58,412 INFO L290 TraceCheckUtils]: 25: Hoare triple {901#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {897#(< main_~i~0 1024)} is VALID [2022-04-27 21:11:58,412 INFO L290 TraceCheckUtils]: 24: Hoare triple {901#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {901#(< main_~i~0 1023)} is VALID [2022-04-27 21:11:58,413 INFO L290 TraceCheckUtils]: 23: Hoare triple {908#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {901#(< main_~i~0 1023)} is VALID [2022-04-27 21:11:58,413 INFO L290 TraceCheckUtils]: 22: Hoare triple {908#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {908#(< main_~i~0 1022)} is VALID [2022-04-27 21:11:58,414 INFO L290 TraceCheckUtils]: 21: Hoare triple {915#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {908#(< main_~i~0 1022)} is VALID [2022-04-27 21:11:58,414 INFO L290 TraceCheckUtils]: 20: Hoare triple {915#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {915#(< main_~i~0 1021)} is VALID [2022-04-27 21:11:58,415 INFO L290 TraceCheckUtils]: 19: Hoare triple {922#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {915#(< main_~i~0 1021)} is VALID [2022-04-27 21:11:58,415 INFO L290 TraceCheckUtils]: 18: Hoare triple {922#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {922#(< main_~i~0 1020)} is VALID [2022-04-27 21:11:58,415 INFO L290 TraceCheckUtils]: 17: Hoare triple {929#(< main_~i~0 1019)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {922#(< main_~i~0 1020)} is VALID [2022-04-27 21:11:58,416 INFO L290 TraceCheckUtils]: 16: Hoare triple {929#(< main_~i~0 1019)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {929#(< main_~i~0 1019)} is VALID [2022-04-27 21:11:58,416 INFO L290 TraceCheckUtils]: 15: Hoare triple {936#(< main_~i~0 1018)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {929#(< main_~i~0 1019)} is VALID [2022-04-27 21:11:58,417 INFO L290 TraceCheckUtils]: 14: Hoare triple {936#(< main_~i~0 1018)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {936#(< main_~i~0 1018)} is VALID [2022-04-27 21:11:58,417 INFO L290 TraceCheckUtils]: 13: Hoare triple {943#(< main_~i~0 1017)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {936#(< main_~i~0 1018)} is VALID [2022-04-27 21:11:58,418 INFO L290 TraceCheckUtils]: 12: Hoare triple {943#(< main_~i~0 1017)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {943#(< main_~i~0 1017)} is VALID [2022-04-27 21:11:58,418 INFO L290 TraceCheckUtils]: 11: Hoare triple {950#(< main_~i~0 1016)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {943#(< main_~i~0 1017)} is VALID [2022-04-27 21:11:58,419 INFO L290 TraceCheckUtils]: 10: Hoare triple {950#(< main_~i~0 1016)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {950#(< main_~i~0 1016)} is VALID [2022-04-27 21:11:58,419 INFO L290 TraceCheckUtils]: 9: Hoare triple {957#(< main_~i~0 1015)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {950#(< main_~i~0 1016)} is VALID [2022-04-27 21:11:58,420 INFO L290 TraceCheckUtils]: 8: Hoare triple {957#(< main_~i~0 1015)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {957#(< main_~i~0 1015)} is VALID [2022-04-27 21:11:58,420 INFO L290 TraceCheckUtils]: 7: Hoare triple {964#(< main_~i~0 1014)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {957#(< main_~i~0 1015)} is VALID [2022-04-27 21:11:58,421 INFO L290 TraceCheckUtils]: 6: Hoare triple {964#(< main_~i~0 1014)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {964#(< main_~i~0 1014)} is VALID [2022-04-27 21:11:58,421 INFO L290 TraceCheckUtils]: 5: Hoare triple {768#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {964#(< main_~i~0 1014)} is VALID [2022-04-27 21:11:58,421 INFO L272 TraceCheckUtils]: 4: Hoare triple {768#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,421 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {768#true} {768#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,422 INFO L290 TraceCheckUtils]: 2: Hoare triple {768#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,422 INFO L290 TraceCheckUtils]: 1: Hoare triple {768#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {768#true} is VALID [2022-04-27 21:11:58,422 INFO L272 TraceCheckUtils]: 0: Hoare triple {768#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {768#true} is VALID [2022-04-27 21:11:58,424 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:58,424 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [487324838] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:11:58,424 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:11:58,424 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2022-04-27 21:11:58,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1147082265] [2022-04-27 21:11:58,425 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:11:58,427 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 32 [2022-04-27 21:11:58,430 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:11:58,430 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:58,479 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 59 edges. 59 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:58,479 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-04-27 21:11:58,479 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:11:58,480 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-04-27 21:11:58,480 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=302, Invalid=348, Unknown=0, NotChecked=0, Total=650 [2022-04-27 21:11:58,480 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:58,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:58,999 INFO L93 Difference]: Finished difference Result 63 states and 74 transitions. [2022-04-27 21:11:58,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-04-27 21:11:59,000 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 32 [2022-04-27 21:11:59,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:11:59,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2022-04-27 21:11:59,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 74 transitions. [2022-04-27 21:11:59,004 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 25 states and 74 transitions. [2022-04-27 21:11:59,106 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 74 edges. 74 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:11:59,108 INFO L225 Difference]: With dead ends: 63 [2022-04-27 21:11:59,108 INFO L226 Difference]: Without dead ends: 57 [2022-04-27 21:11:59,110 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 346 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=853, Invalid=1403, Unknown=0, NotChecked=0, Total=2256 [2022-04-27 21:11:59,110 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 62 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 72 mSolverCounterSat, 40 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 62 SdHoareTripleChecker+Valid, 34 SdHoareTripleChecker+Invalid, 112 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 40 IncrementalHoareTripleChecker+Valid, 72 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:11:59,111 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [62 Valid, 34 Invalid, 112 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [40 Valid, 72 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:11:59,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2022-04-27 21:11:59,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2022-04-27 21:11:59,133 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:11:59,134 INFO L82 GeneralOperation]: Start isEquivalent. First operand 57 states. Second operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,134 INFO L74 IsIncluded]: Start isIncluded. First operand 57 states. Second operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,134 INFO L87 Difference]: Start difference. First operand 57 states. Second operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:59,136 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2022-04-27 21:11:59,136 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2022-04-27 21:11:59,136 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:59,137 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:59,137 INFO L74 IsIncluded]: Start isIncluded. First operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-27 21:11:59,137 INFO L87 Difference]: Start difference. First operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 57 states. [2022-04-27 21:11:59,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:11:59,139 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2022-04-27 21:11:59,139 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2022-04-27 21:11:59,140 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:11:59,140 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:11:59,140 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:11:59,140 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:11:59,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 52 states have (on average 1.0192307692307692) internal successors, (53), 52 states have internal predecessors, (53), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2022-04-27 21:11:59,142 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 32 [2022-04-27 21:11:59,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:11:59,142 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2022-04-27 21:11:59,142 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 2.076923076923077) internal successors, (54), 25 states have internal predecessors, (54), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:11:59,142 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2022-04-27 21:11:59,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2022-04-27 21:11:59,143 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:11:59,144 INFO L195 NwaCegarLoop]: trace histogram [22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:11:59,171 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 21:11:59,365 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:11:59,366 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:11:59,366 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:11:59,366 INFO L85 PathProgramCache]: Analyzing trace with hash -1053856921, now seen corresponding path program 4 times [2022-04-27 21:11:59,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:11:59,367 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2026386315] [2022-04-27 21:11:59,367 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:11:59,367 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:11:59,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:59,793 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:11:59,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:59,804 INFO L290 TraceCheckUtils]: 0: Hoare triple {1354#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1326#true} is VALID [2022-04-27 21:11:59,805 INFO L290 TraceCheckUtils]: 1: Hoare triple {1326#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:11:59,805 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1326#true} {1326#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:11:59,806 INFO L272 TraceCheckUtils]: 0: Hoare triple {1326#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1354#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:11:59,806 INFO L290 TraceCheckUtils]: 1: Hoare triple {1354#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1326#true} is VALID [2022-04-27 21:11:59,806 INFO L290 TraceCheckUtils]: 2: Hoare triple {1326#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:11:59,806 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1326#true} {1326#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:11:59,807 INFO L272 TraceCheckUtils]: 4: Hoare triple {1326#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:11:59,807 INFO L290 TraceCheckUtils]: 5: Hoare triple {1326#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {1331#(= main_~i~0 0)} is VALID [2022-04-27 21:11:59,811 INFO L290 TraceCheckUtils]: 6: Hoare triple {1331#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1331#(= main_~i~0 0)} is VALID [2022-04-27 21:11:59,813 INFO L290 TraceCheckUtils]: 7: Hoare triple {1331#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1332#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:59,819 INFO L290 TraceCheckUtils]: 8: Hoare triple {1332#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1332#(<= main_~i~0 1)} is VALID [2022-04-27 21:11:59,820 INFO L290 TraceCheckUtils]: 9: Hoare triple {1332#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1333#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:59,821 INFO L290 TraceCheckUtils]: 10: Hoare triple {1333#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1333#(<= main_~i~0 2)} is VALID [2022-04-27 21:11:59,822 INFO L290 TraceCheckUtils]: 11: Hoare triple {1333#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1334#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:59,823 INFO L290 TraceCheckUtils]: 12: Hoare triple {1334#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1334#(<= main_~i~0 3)} is VALID [2022-04-27 21:11:59,823 INFO L290 TraceCheckUtils]: 13: Hoare triple {1334#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1335#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:59,824 INFO L290 TraceCheckUtils]: 14: Hoare triple {1335#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1335#(<= main_~i~0 4)} is VALID [2022-04-27 21:11:59,827 INFO L290 TraceCheckUtils]: 15: Hoare triple {1335#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1336#(<= main_~i~0 5)} is VALID [2022-04-27 21:11:59,829 INFO L290 TraceCheckUtils]: 16: Hoare triple {1336#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1336#(<= main_~i~0 5)} is VALID [2022-04-27 21:11:59,829 INFO L290 TraceCheckUtils]: 17: Hoare triple {1336#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1337#(<= main_~i~0 6)} is VALID [2022-04-27 21:11:59,830 INFO L290 TraceCheckUtils]: 18: Hoare triple {1337#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1337#(<= main_~i~0 6)} is VALID [2022-04-27 21:11:59,830 INFO L290 TraceCheckUtils]: 19: Hoare triple {1337#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1338#(<= main_~i~0 7)} is VALID [2022-04-27 21:11:59,831 INFO L290 TraceCheckUtils]: 20: Hoare triple {1338#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1338#(<= main_~i~0 7)} is VALID [2022-04-27 21:11:59,831 INFO L290 TraceCheckUtils]: 21: Hoare triple {1338#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1339#(<= main_~i~0 8)} is VALID [2022-04-27 21:11:59,831 INFO L290 TraceCheckUtils]: 22: Hoare triple {1339#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1339#(<= main_~i~0 8)} is VALID [2022-04-27 21:11:59,832 INFO L290 TraceCheckUtils]: 23: Hoare triple {1339#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1340#(<= main_~i~0 9)} is VALID [2022-04-27 21:11:59,832 INFO L290 TraceCheckUtils]: 24: Hoare triple {1340#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1340#(<= main_~i~0 9)} is VALID [2022-04-27 21:11:59,833 INFO L290 TraceCheckUtils]: 25: Hoare triple {1340#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1341#(<= main_~i~0 10)} is VALID [2022-04-27 21:11:59,833 INFO L290 TraceCheckUtils]: 26: Hoare triple {1341#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1341#(<= main_~i~0 10)} is VALID [2022-04-27 21:11:59,834 INFO L290 TraceCheckUtils]: 27: Hoare triple {1341#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1342#(<= main_~i~0 11)} is VALID [2022-04-27 21:11:59,834 INFO L290 TraceCheckUtils]: 28: Hoare triple {1342#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1342#(<= main_~i~0 11)} is VALID [2022-04-27 21:11:59,835 INFO L290 TraceCheckUtils]: 29: Hoare triple {1342#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1343#(<= main_~i~0 12)} is VALID [2022-04-27 21:11:59,835 INFO L290 TraceCheckUtils]: 30: Hoare triple {1343#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1343#(<= main_~i~0 12)} is VALID [2022-04-27 21:11:59,836 INFO L290 TraceCheckUtils]: 31: Hoare triple {1343#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1344#(<= main_~i~0 13)} is VALID [2022-04-27 21:11:59,836 INFO L290 TraceCheckUtils]: 32: Hoare triple {1344#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1344#(<= main_~i~0 13)} is VALID [2022-04-27 21:11:59,837 INFO L290 TraceCheckUtils]: 33: Hoare triple {1344#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1345#(<= main_~i~0 14)} is VALID [2022-04-27 21:11:59,837 INFO L290 TraceCheckUtils]: 34: Hoare triple {1345#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1345#(<= main_~i~0 14)} is VALID [2022-04-27 21:11:59,838 INFO L290 TraceCheckUtils]: 35: Hoare triple {1345#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1346#(<= main_~i~0 15)} is VALID [2022-04-27 21:11:59,838 INFO L290 TraceCheckUtils]: 36: Hoare triple {1346#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1346#(<= main_~i~0 15)} is VALID [2022-04-27 21:11:59,838 INFO L290 TraceCheckUtils]: 37: Hoare triple {1346#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1347#(<= main_~i~0 16)} is VALID [2022-04-27 21:11:59,839 INFO L290 TraceCheckUtils]: 38: Hoare triple {1347#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1347#(<= main_~i~0 16)} is VALID [2022-04-27 21:11:59,839 INFO L290 TraceCheckUtils]: 39: Hoare triple {1347#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1348#(<= main_~i~0 17)} is VALID [2022-04-27 21:11:59,840 INFO L290 TraceCheckUtils]: 40: Hoare triple {1348#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1348#(<= main_~i~0 17)} is VALID [2022-04-27 21:11:59,841 INFO L290 TraceCheckUtils]: 41: Hoare triple {1348#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1349#(<= main_~i~0 18)} is VALID [2022-04-27 21:11:59,841 INFO L290 TraceCheckUtils]: 42: Hoare triple {1349#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1349#(<= main_~i~0 18)} is VALID [2022-04-27 21:11:59,842 INFO L290 TraceCheckUtils]: 43: Hoare triple {1349#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1350#(<= main_~i~0 19)} is VALID [2022-04-27 21:11:59,842 INFO L290 TraceCheckUtils]: 44: Hoare triple {1350#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1350#(<= main_~i~0 19)} is VALID [2022-04-27 21:11:59,843 INFO L290 TraceCheckUtils]: 45: Hoare triple {1350#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1351#(<= main_~i~0 20)} is VALID [2022-04-27 21:11:59,843 INFO L290 TraceCheckUtils]: 46: Hoare triple {1351#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1351#(<= main_~i~0 20)} is VALID [2022-04-27 21:11:59,844 INFO L290 TraceCheckUtils]: 47: Hoare triple {1351#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1352#(<= main_~i~0 21)} is VALID [2022-04-27 21:11:59,844 INFO L290 TraceCheckUtils]: 48: Hoare triple {1352#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1352#(<= main_~i~0 21)} is VALID [2022-04-27 21:11:59,845 INFO L290 TraceCheckUtils]: 49: Hoare triple {1352#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1353#(<= main_~i~0 22)} is VALID [2022-04-27 21:11:59,845 INFO L290 TraceCheckUtils]: 50: Hoare triple {1353#(<= main_~i~0 22)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:11:59,845 INFO L290 TraceCheckUtils]: 51: Hoare triple {1327#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {1327#false} is VALID [2022-04-27 21:11:59,846 INFO L272 TraceCheckUtils]: 52: Hoare triple {1327#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {1327#false} is VALID [2022-04-27 21:11:59,846 INFO L290 TraceCheckUtils]: 53: Hoare triple {1327#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1327#false} is VALID [2022-04-27 21:11:59,846 INFO L290 TraceCheckUtils]: 54: Hoare triple {1327#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:11:59,846 INFO L290 TraceCheckUtils]: 55: Hoare triple {1327#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:11:59,848 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:11:59,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:11:59,849 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2026386315] [2022-04-27 21:11:59,849 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2026386315] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:11:59,850 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [327620179] [2022-04-27 21:11:59,851 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 21:11:59,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:11:59,851 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:11:59,852 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:11:59,853 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 21:11:59,931 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 21:11:59,932 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:11:59,933 INFO L263 TraceCheckSpWp]: Trace formula consists of 223 conjuncts, 24 conjunts are in the unsatisfiable core [2022-04-27 21:11:59,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:11:59,954 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:12:00,308 INFO L272 TraceCheckUtils]: 0: Hoare triple {1326#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:00,309 INFO L290 TraceCheckUtils]: 1: Hoare triple {1326#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1326#true} is VALID [2022-04-27 21:12:00,309 INFO L290 TraceCheckUtils]: 2: Hoare triple {1326#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:00,309 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1326#true} {1326#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:00,309 INFO L272 TraceCheckUtils]: 4: Hoare triple {1326#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:00,310 INFO L290 TraceCheckUtils]: 5: Hoare triple {1326#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {1373#(<= main_~i~0 0)} is VALID [2022-04-27 21:12:00,310 INFO L290 TraceCheckUtils]: 6: Hoare triple {1373#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1373#(<= main_~i~0 0)} is VALID [2022-04-27 21:12:00,310 INFO L290 TraceCheckUtils]: 7: Hoare triple {1373#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1332#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:00,315 INFO L290 TraceCheckUtils]: 8: Hoare triple {1332#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1332#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:00,316 INFO L290 TraceCheckUtils]: 9: Hoare triple {1332#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1333#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:00,316 INFO L290 TraceCheckUtils]: 10: Hoare triple {1333#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1333#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:00,316 INFO L290 TraceCheckUtils]: 11: Hoare triple {1333#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1334#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:00,317 INFO L290 TraceCheckUtils]: 12: Hoare triple {1334#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1334#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:00,317 INFO L290 TraceCheckUtils]: 13: Hoare triple {1334#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1335#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:00,318 INFO L290 TraceCheckUtils]: 14: Hoare triple {1335#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1335#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:00,318 INFO L290 TraceCheckUtils]: 15: Hoare triple {1335#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1336#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:00,319 INFO L290 TraceCheckUtils]: 16: Hoare triple {1336#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1336#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:00,319 INFO L290 TraceCheckUtils]: 17: Hoare triple {1336#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1337#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:00,320 INFO L290 TraceCheckUtils]: 18: Hoare triple {1337#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1337#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:00,320 INFO L290 TraceCheckUtils]: 19: Hoare triple {1337#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1338#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:00,321 INFO L290 TraceCheckUtils]: 20: Hoare triple {1338#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1338#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:00,321 INFO L290 TraceCheckUtils]: 21: Hoare triple {1338#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1339#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:00,322 INFO L290 TraceCheckUtils]: 22: Hoare triple {1339#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1339#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:00,322 INFO L290 TraceCheckUtils]: 23: Hoare triple {1339#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1340#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:00,323 INFO L290 TraceCheckUtils]: 24: Hoare triple {1340#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1340#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:00,323 INFO L290 TraceCheckUtils]: 25: Hoare triple {1340#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1341#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:00,324 INFO L290 TraceCheckUtils]: 26: Hoare triple {1341#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1341#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:00,324 INFO L290 TraceCheckUtils]: 27: Hoare triple {1341#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1342#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:00,324 INFO L290 TraceCheckUtils]: 28: Hoare triple {1342#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1342#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:00,325 INFO L290 TraceCheckUtils]: 29: Hoare triple {1342#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1343#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:00,325 INFO L290 TraceCheckUtils]: 30: Hoare triple {1343#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1343#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:00,326 INFO L290 TraceCheckUtils]: 31: Hoare triple {1343#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1344#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:00,326 INFO L290 TraceCheckUtils]: 32: Hoare triple {1344#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1344#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:00,326 INFO L290 TraceCheckUtils]: 33: Hoare triple {1344#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1345#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:00,327 INFO L290 TraceCheckUtils]: 34: Hoare triple {1345#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1345#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:00,327 INFO L290 TraceCheckUtils]: 35: Hoare triple {1345#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1346#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:00,327 INFO L290 TraceCheckUtils]: 36: Hoare triple {1346#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1346#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:00,328 INFO L290 TraceCheckUtils]: 37: Hoare triple {1346#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1347#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:00,328 INFO L290 TraceCheckUtils]: 38: Hoare triple {1347#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1347#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:00,329 INFO L290 TraceCheckUtils]: 39: Hoare triple {1347#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1348#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:00,329 INFO L290 TraceCheckUtils]: 40: Hoare triple {1348#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1348#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:00,329 INFO L290 TraceCheckUtils]: 41: Hoare triple {1348#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1349#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:00,330 INFO L290 TraceCheckUtils]: 42: Hoare triple {1349#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1349#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:00,330 INFO L290 TraceCheckUtils]: 43: Hoare triple {1349#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1350#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:00,330 INFO L290 TraceCheckUtils]: 44: Hoare triple {1350#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1350#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:00,331 INFO L290 TraceCheckUtils]: 45: Hoare triple {1350#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1351#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:00,331 INFO L290 TraceCheckUtils]: 46: Hoare triple {1351#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1351#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:00,331 INFO L290 TraceCheckUtils]: 47: Hoare triple {1351#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1352#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:00,332 INFO L290 TraceCheckUtils]: 48: Hoare triple {1352#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1352#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:00,332 INFO L290 TraceCheckUtils]: 49: Hoare triple {1352#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1353#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:00,332 INFO L290 TraceCheckUtils]: 50: Hoare triple {1353#(<= main_~i~0 22)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:12:00,333 INFO L290 TraceCheckUtils]: 51: Hoare triple {1327#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {1327#false} is VALID [2022-04-27 21:12:00,333 INFO L272 TraceCheckUtils]: 52: Hoare triple {1327#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {1327#false} is VALID [2022-04-27 21:12:00,333 INFO L290 TraceCheckUtils]: 53: Hoare triple {1327#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1327#false} is VALID [2022-04-27 21:12:00,333 INFO L290 TraceCheckUtils]: 54: Hoare triple {1327#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:12:00,333 INFO L290 TraceCheckUtils]: 55: Hoare triple {1327#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:12:00,333 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:00,334 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:12:01,347 INFO L290 TraceCheckUtils]: 55: Hoare triple {1327#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:12:01,348 INFO L290 TraceCheckUtils]: 54: Hoare triple {1327#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:12:01,348 INFO L290 TraceCheckUtils]: 53: Hoare triple {1327#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1327#false} is VALID [2022-04-27 21:12:01,348 INFO L272 TraceCheckUtils]: 52: Hoare triple {1327#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {1327#false} is VALID [2022-04-27 21:12:01,348 INFO L290 TraceCheckUtils]: 51: Hoare triple {1327#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {1327#false} is VALID [2022-04-27 21:12:01,348 INFO L290 TraceCheckUtils]: 50: Hoare triple {1539#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {1327#false} is VALID [2022-04-27 21:12:01,349 INFO L290 TraceCheckUtils]: 49: Hoare triple {1543#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1539#(< main_~i~0 1024)} is VALID [2022-04-27 21:12:01,349 INFO L290 TraceCheckUtils]: 48: Hoare triple {1543#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1543#(< main_~i~0 1023)} is VALID [2022-04-27 21:12:01,350 INFO L290 TraceCheckUtils]: 47: Hoare triple {1550#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1543#(< main_~i~0 1023)} is VALID [2022-04-27 21:12:01,350 INFO L290 TraceCheckUtils]: 46: Hoare triple {1550#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1550#(< main_~i~0 1022)} is VALID [2022-04-27 21:12:01,350 INFO L290 TraceCheckUtils]: 45: Hoare triple {1557#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1550#(< main_~i~0 1022)} is VALID [2022-04-27 21:12:01,351 INFO L290 TraceCheckUtils]: 44: Hoare triple {1557#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1557#(< main_~i~0 1021)} is VALID [2022-04-27 21:12:01,353 INFO L290 TraceCheckUtils]: 43: Hoare triple {1564#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1557#(< main_~i~0 1021)} is VALID [2022-04-27 21:12:01,353 INFO L290 TraceCheckUtils]: 42: Hoare triple {1564#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1564#(< main_~i~0 1020)} is VALID [2022-04-27 21:12:01,353 INFO L290 TraceCheckUtils]: 41: Hoare triple {1571#(< main_~i~0 1019)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1564#(< main_~i~0 1020)} is VALID [2022-04-27 21:12:01,354 INFO L290 TraceCheckUtils]: 40: Hoare triple {1571#(< main_~i~0 1019)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1571#(< main_~i~0 1019)} is VALID [2022-04-27 21:12:01,354 INFO L290 TraceCheckUtils]: 39: Hoare triple {1578#(< main_~i~0 1018)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1571#(< main_~i~0 1019)} is VALID [2022-04-27 21:12:01,354 INFO L290 TraceCheckUtils]: 38: Hoare triple {1578#(< main_~i~0 1018)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1578#(< main_~i~0 1018)} is VALID [2022-04-27 21:12:01,355 INFO L290 TraceCheckUtils]: 37: Hoare triple {1585#(< main_~i~0 1017)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1578#(< main_~i~0 1018)} is VALID [2022-04-27 21:12:01,355 INFO L290 TraceCheckUtils]: 36: Hoare triple {1585#(< main_~i~0 1017)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1585#(< main_~i~0 1017)} is VALID [2022-04-27 21:12:01,356 INFO L290 TraceCheckUtils]: 35: Hoare triple {1592#(< main_~i~0 1016)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1585#(< main_~i~0 1017)} is VALID [2022-04-27 21:12:01,356 INFO L290 TraceCheckUtils]: 34: Hoare triple {1592#(< main_~i~0 1016)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1592#(< main_~i~0 1016)} is VALID [2022-04-27 21:12:01,359 INFO L290 TraceCheckUtils]: 33: Hoare triple {1599#(< main_~i~0 1015)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1592#(< main_~i~0 1016)} is VALID [2022-04-27 21:12:01,360 INFO L290 TraceCheckUtils]: 32: Hoare triple {1599#(< main_~i~0 1015)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1599#(< main_~i~0 1015)} is VALID [2022-04-27 21:12:01,361 INFO L290 TraceCheckUtils]: 31: Hoare triple {1606#(< main_~i~0 1014)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1599#(< main_~i~0 1015)} is VALID [2022-04-27 21:12:01,362 INFO L290 TraceCheckUtils]: 30: Hoare triple {1606#(< main_~i~0 1014)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1606#(< main_~i~0 1014)} is VALID [2022-04-27 21:12:01,362 INFO L290 TraceCheckUtils]: 29: Hoare triple {1613#(< main_~i~0 1013)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1606#(< main_~i~0 1014)} is VALID [2022-04-27 21:12:01,364 INFO L290 TraceCheckUtils]: 28: Hoare triple {1613#(< main_~i~0 1013)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1613#(< main_~i~0 1013)} is VALID [2022-04-27 21:12:01,364 INFO L290 TraceCheckUtils]: 27: Hoare triple {1620#(< main_~i~0 1012)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1613#(< main_~i~0 1013)} is VALID [2022-04-27 21:12:01,364 INFO L290 TraceCheckUtils]: 26: Hoare triple {1620#(< main_~i~0 1012)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1620#(< main_~i~0 1012)} is VALID [2022-04-27 21:12:01,365 INFO L290 TraceCheckUtils]: 25: Hoare triple {1627#(< main_~i~0 1011)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1620#(< main_~i~0 1012)} is VALID [2022-04-27 21:12:01,365 INFO L290 TraceCheckUtils]: 24: Hoare triple {1627#(< main_~i~0 1011)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1627#(< main_~i~0 1011)} is VALID [2022-04-27 21:12:01,366 INFO L290 TraceCheckUtils]: 23: Hoare triple {1634#(< main_~i~0 1010)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1627#(< main_~i~0 1011)} is VALID [2022-04-27 21:12:01,366 INFO L290 TraceCheckUtils]: 22: Hoare triple {1634#(< main_~i~0 1010)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1634#(< main_~i~0 1010)} is VALID [2022-04-27 21:12:01,366 INFO L290 TraceCheckUtils]: 21: Hoare triple {1641#(< main_~i~0 1009)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1634#(< main_~i~0 1010)} is VALID [2022-04-27 21:12:01,367 INFO L290 TraceCheckUtils]: 20: Hoare triple {1641#(< main_~i~0 1009)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1641#(< main_~i~0 1009)} is VALID [2022-04-27 21:12:01,367 INFO L290 TraceCheckUtils]: 19: Hoare triple {1648#(< main_~i~0 1008)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1641#(< main_~i~0 1009)} is VALID [2022-04-27 21:12:01,367 INFO L290 TraceCheckUtils]: 18: Hoare triple {1648#(< main_~i~0 1008)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1648#(< main_~i~0 1008)} is VALID [2022-04-27 21:12:01,368 INFO L290 TraceCheckUtils]: 17: Hoare triple {1655#(< main_~i~0 1007)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1648#(< main_~i~0 1008)} is VALID [2022-04-27 21:12:01,368 INFO L290 TraceCheckUtils]: 16: Hoare triple {1655#(< main_~i~0 1007)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1655#(< main_~i~0 1007)} is VALID [2022-04-27 21:12:01,369 INFO L290 TraceCheckUtils]: 15: Hoare triple {1662#(< main_~i~0 1006)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1655#(< main_~i~0 1007)} is VALID [2022-04-27 21:12:01,369 INFO L290 TraceCheckUtils]: 14: Hoare triple {1662#(< main_~i~0 1006)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1662#(< main_~i~0 1006)} is VALID [2022-04-27 21:12:01,369 INFO L290 TraceCheckUtils]: 13: Hoare triple {1669#(< main_~i~0 1005)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1662#(< main_~i~0 1006)} is VALID [2022-04-27 21:12:01,370 INFO L290 TraceCheckUtils]: 12: Hoare triple {1669#(< main_~i~0 1005)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1669#(< main_~i~0 1005)} is VALID [2022-04-27 21:12:01,370 INFO L290 TraceCheckUtils]: 11: Hoare triple {1676#(< main_~i~0 1004)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1669#(< main_~i~0 1005)} is VALID [2022-04-27 21:12:01,370 INFO L290 TraceCheckUtils]: 10: Hoare triple {1676#(< main_~i~0 1004)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1676#(< main_~i~0 1004)} is VALID [2022-04-27 21:12:01,371 INFO L290 TraceCheckUtils]: 9: Hoare triple {1683#(< main_~i~0 1003)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1676#(< main_~i~0 1004)} is VALID [2022-04-27 21:12:01,371 INFO L290 TraceCheckUtils]: 8: Hoare triple {1683#(< main_~i~0 1003)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1683#(< main_~i~0 1003)} is VALID [2022-04-27 21:12:01,372 INFO L290 TraceCheckUtils]: 7: Hoare triple {1690#(< main_~i~0 1002)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {1683#(< main_~i~0 1003)} is VALID [2022-04-27 21:12:01,372 INFO L290 TraceCheckUtils]: 6: Hoare triple {1690#(< main_~i~0 1002)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {1690#(< main_~i~0 1002)} is VALID [2022-04-27 21:12:01,373 INFO L290 TraceCheckUtils]: 5: Hoare triple {1326#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {1690#(< main_~i~0 1002)} is VALID [2022-04-27 21:12:01,373 INFO L272 TraceCheckUtils]: 4: Hoare triple {1326#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:01,373 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1326#true} {1326#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:01,373 INFO L290 TraceCheckUtils]: 2: Hoare triple {1326#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:01,373 INFO L290 TraceCheckUtils]: 1: Hoare triple {1326#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1326#true} is VALID [2022-04-27 21:12:01,384 INFO L272 TraceCheckUtils]: 0: Hoare triple {1326#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1326#true} is VALID [2022-04-27 21:12:01,385 INFO L134 CoverageAnalysis]: Checked inductivity of 484 backedges. 0 proven. 484 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:01,385 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [327620179] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:12:01,385 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:12:01,385 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 50 [2022-04-27 21:12:01,385 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [976384636] [2022-04-27 21:12:01,385 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:12:01,386 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 56 [2022-04-27 21:12:01,387 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:12:01,387 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:01,473 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 107 edges. 107 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:12:01,473 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-04-27 21:12:01,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:12:01,474 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-04-27 21:12:01,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1178, Invalid=1272, Unknown=0, NotChecked=0, Total=2450 [2022-04-27 21:12:01,475 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:02,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:02,883 INFO L93 Difference]: Finished difference Result 111 states and 134 transitions. [2022-04-27 21:12:02,883 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-27 21:12:02,883 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 56 [2022-04-27 21:12:02,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:12:02,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:02,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 134 transitions. [2022-04-27 21:12:02,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:02,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 134 transitions. [2022-04-27 21:12:02,890 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 134 transitions. [2022-04-27 21:12:03,011 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 134 edges. 134 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:12:03,013 INFO L225 Difference]: With dead ends: 111 [2022-04-27 21:12:03,014 INFO L226 Difference]: Without dead ends: 105 [2022-04-27 21:12:03,017 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 184 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1420 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3433, Invalid=5687, Unknown=0, NotChecked=0, Total=9120 [2022-04-27 21:12:03,017 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 122 mSDsluCounter, 42 mSDsCounter, 0 mSdLazyCounter, 142 mSolverCounterSat, 73 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 122 SdHoareTripleChecker+Valid, 54 SdHoareTripleChecker+Invalid, 215 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 73 IncrementalHoareTripleChecker+Valid, 142 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 21:12:03,018 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [122 Valid, 54 Invalid, 215 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [73 Valid, 142 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 21:12:03,018 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2022-04-27 21:12:03,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2022-04-27 21:12:03,058 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:12:03,059 INFO L82 GeneralOperation]: Start isEquivalent. First operand 105 states. Second operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:03,059 INFO L74 IsIncluded]: Start isIncluded. First operand 105 states. Second operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:03,059 INFO L87 Difference]: Start difference. First operand 105 states. Second operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:03,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:03,063 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2022-04-27 21:12:03,063 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2022-04-27 21:12:03,063 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:12:03,063 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:12:03,064 INFO L74 IsIncluded]: Start isIncluded. First operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 105 states. [2022-04-27 21:12:03,064 INFO L87 Difference]: Start difference. First operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 105 states. [2022-04-27 21:12:03,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:03,067 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2022-04-27 21:12:03,067 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2022-04-27 21:12:03,067 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:12:03,068 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:12:03,068 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:12:03,068 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:12:03,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 100 states have (on average 1.01) internal successors, (101), 100 states have internal predecessors, (101), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:03,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2022-04-27 21:12:03,071 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 56 [2022-04-27 21:12:03,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:12:03,071 INFO L495 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2022-04-27 21:12:03,072 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 2.04) internal successors, (102), 49 states have internal predecessors, (102), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:03,072 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2022-04-27 21:12:03,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2022-04-27 21:12:03,073 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:12:03,074 INFO L195 NwaCegarLoop]: trace histogram [46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:12:03,100 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 21:12:03,292 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:12:03,292 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:12:03,293 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:12:03,293 INFO L85 PathProgramCache]: Analyzing trace with hash 1931971991, now seen corresponding path program 5 times [2022-04-27 21:12:03,293 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:12:03,293 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1067125673] [2022-04-27 21:12:03,293 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:12:03,293 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:12:03,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:04,342 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:12:04,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:04,350 INFO L290 TraceCheckUtils]: 0: Hoare triple {2392#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2340#true} is VALID [2022-04-27 21:12:04,350 INFO L290 TraceCheckUtils]: 1: Hoare triple {2340#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:04,350 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2340#true} {2340#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:04,350 INFO L272 TraceCheckUtils]: 0: Hoare triple {2340#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2392#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:12:04,350 INFO L290 TraceCheckUtils]: 1: Hoare triple {2392#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2340#true} is VALID [2022-04-27 21:12:04,350 INFO L290 TraceCheckUtils]: 2: Hoare triple {2340#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:04,351 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2340#true} {2340#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:04,351 INFO L272 TraceCheckUtils]: 4: Hoare triple {2340#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:04,351 INFO L290 TraceCheckUtils]: 5: Hoare triple {2340#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {2345#(= main_~i~0 0)} is VALID [2022-04-27 21:12:04,351 INFO L290 TraceCheckUtils]: 6: Hoare triple {2345#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2345#(= main_~i~0 0)} is VALID [2022-04-27 21:12:04,352 INFO L290 TraceCheckUtils]: 7: Hoare triple {2345#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2346#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:04,352 INFO L290 TraceCheckUtils]: 8: Hoare triple {2346#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2346#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:04,352 INFO L290 TraceCheckUtils]: 9: Hoare triple {2346#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2347#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:04,353 INFO L290 TraceCheckUtils]: 10: Hoare triple {2347#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2347#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:04,353 INFO L290 TraceCheckUtils]: 11: Hoare triple {2347#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2348#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:04,353 INFO L290 TraceCheckUtils]: 12: Hoare triple {2348#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2348#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:04,354 INFO L290 TraceCheckUtils]: 13: Hoare triple {2348#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2349#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:04,354 INFO L290 TraceCheckUtils]: 14: Hoare triple {2349#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2349#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:04,354 INFO L290 TraceCheckUtils]: 15: Hoare triple {2349#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2350#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:04,355 INFO L290 TraceCheckUtils]: 16: Hoare triple {2350#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2350#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:04,356 INFO L290 TraceCheckUtils]: 17: Hoare triple {2350#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2351#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:04,356 INFO L290 TraceCheckUtils]: 18: Hoare triple {2351#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2351#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:04,356 INFO L290 TraceCheckUtils]: 19: Hoare triple {2351#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2352#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:04,357 INFO L290 TraceCheckUtils]: 20: Hoare triple {2352#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2352#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:04,357 INFO L290 TraceCheckUtils]: 21: Hoare triple {2352#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2353#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:04,357 INFO L290 TraceCheckUtils]: 22: Hoare triple {2353#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2353#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:04,358 INFO L290 TraceCheckUtils]: 23: Hoare triple {2353#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2354#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:04,358 INFO L290 TraceCheckUtils]: 24: Hoare triple {2354#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2354#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:04,359 INFO L290 TraceCheckUtils]: 25: Hoare triple {2354#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2355#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:04,359 INFO L290 TraceCheckUtils]: 26: Hoare triple {2355#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2355#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:04,360 INFO L290 TraceCheckUtils]: 27: Hoare triple {2355#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2356#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:04,360 INFO L290 TraceCheckUtils]: 28: Hoare triple {2356#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2356#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:04,360 INFO L290 TraceCheckUtils]: 29: Hoare triple {2356#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2357#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:04,361 INFO L290 TraceCheckUtils]: 30: Hoare triple {2357#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2357#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:04,361 INFO L290 TraceCheckUtils]: 31: Hoare triple {2357#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2358#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:04,361 INFO L290 TraceCheckUtils]: 32: Hoare triple {2358#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2358#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:04,362 INFO L290 TraceCheckUtils]: 33: Hoare triple {2358#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2359#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:04,362 INFO L290 TraceCheckUtils]: 34: Hoare triple {2359#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2359#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:04,362 INFO L290 TraceCheckUtils]: 35: Hoare triple {2359#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2360#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:04,363 INFO L290 TraceCheckUtils]: 36: Hoare triple {2360#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2360#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:04,363 INFO L290 TraceCheckUtils]: 37: Hoare triple {2360#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2361#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:04,363 INFO L290 TraceCheckUtils]: 38: Hoare triple {2361#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2361#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:04,364 INFO L290 TraceCheckUtils]: 39: Hoare triple {2361#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2362#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:04,364 INFO L290 TraceCheckUtils]: 40: Hoare triple {2362#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2362#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:04,364 INFO L290 TraceCheckUtils]: 41: Hoare triple {2362#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2363#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:04,365 INFO L290 TraceCheckUtils]: 42: Hoare triple {2363#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2363#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:04,365 INFO L290 TraceCheckUtils]: 43: Hoare triple {2363#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2364#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:04,365 INFO L290 TraceCheckUtils]: 44: Hoare triple {2364#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2364#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:04,366 INFO L290 TraceCheckUtils]: 45: Hoare triple {2364#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2365#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:04,366 INFO L290 TraceCheckUtils]: 46: Hoare triple {2365#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2365#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:04,366 INFO L290 TraceCheckUtils]: 47: Hoare triple {2365#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2366#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:04,367 INFO L290 TraceCheckUtils]: 48: Hoare triple {2366#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2366#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:04,367 INFO L290 TraceCheckUtils]: 49: Hoare triple {2366#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2367#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:04,367 INFO L290 TraceCheckUtils]: 50: Hoare triple {2367#(<= main_~i~0 22)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2367#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:04,368 INFO L290 TraceCheckUtils]: 51: Hoare triple {2367#(<= main_~i~0 22)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2368#(<= main_~i~0 23)} is VALID [2022-04-27 21:12:04,368 INFO L290 TraceCheckUtils]: 52: Hoare triple {2368#(<= main_~i~0 23)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2368#(<= main_~i~0 23)} is VALID [2022-04-27 21:12:04,368 INFO L290 TraceCheckUtils]: 53: Hoare triple {2368#(<= main_~i~0 23)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2369#(<= main_~i~0 24)} is VALID [2022-04-27 21:12:04,369 INFO L290 TraceCheckUtils]: 54: Hoare triple {2369#(<= main_~i~0 24)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2369#(<= main_~i~0 24)} is VALID [2022-04-27 21:12:04,369 INFO L290 TraceCheckUtils]: 55: Hoare triple {2369#(<= main_~i~0 24)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2370#(<= main_~i~0 25)} is VALID [2022-04-27 21:12:04,369 INFO L290 TraceCheckUtils]: 56: Hoare triple {2370#(<= main_~i~0 25)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2370#(<= main_~i~0 25)} is VALID [2022-04-27 21:12:04,370 INFO L290 TraceCheckUtils]: 57: Hoare triple {2370#(<= main_~i~0 25)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2371#(<= main_~i~0 26)} is VALID [2022-04-27 21:12:04,370 INFO L290 TraceCheckUtils]: 58: Hoare triple {2371#(<= main_~i~0 26)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2371#(<= main_~i~0 26)} is VALID [2022-04-27 21:12:04,370 INFO L290 TraceCheckUtils]: 59: Hoare triple {2371#(<= main_~i~0 26)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2372#(<= main_~i~0 27)} is VALID [2022-04-27 21:12:04,371 INFO L290 TraceCheckUtils]: 60: Hoare triple {2372#(<= main_~i~0 27)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2372#(<= main_~i~0 27)} is VALID [2022-04-27 21:12:04,371 INFO L290 TraceCheckUtils]: 61: Hoare triple {2372#(<= main_~i~0 27)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2373#(<= main_~i~0 28)} is VALID [2022-04-27 21:12:04,371 INFO L290 TraceCheckUtils]: 62: Hoare triple {2373#(<= main_~i~0 28)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2373#(<= main_~i~0 28)} is VALID [2022-04-27 21:12:04,372 INFO L290 TraceCheckUtils]: 63: Hoare triple {2373#(<= main_~i~0 28)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2374#(<= main_~i~0 29)} is VALID [2022-04-27 21:12:04,372 INFO L290 TraceCheckUtils]: 64: Hoare triple {2374#(<= main_~i~0 29)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2374#(<= main_~i~0 29)} is VALID [2022-04-27 21:12:04,373 INFO L290 TraceCheckUtils]: 65: Hoare triple {2374#(<= main_~i~0 29)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2375#(<= main_~i~0 30)} is VALID [2022-04-27 21:12:04,373 INFO L290 TraceCheckUtils]: 66: Hoare triple {2375#(<= main_~i~0 30)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2375#(<= main_~i~0 30)} is VALID [2022-04-27 21:12:04,373 INFO L290 TraceCheckUtils]: 67: Hoare triple {2375#(<= main_~i~0 30)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2376#(<= main_~i~0 31)} is VALID [2022-04-27 21:12:04,374 INFO L290 TraceCheckUtils]: 68: Hoare triple {2376#(<= main_~i~0 31)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2376#(<= main_~i~0 31)} is VALID [2022-04-27 21:12:04,374 INFO L290 TraceCheckUtils]: 69: Hoare triple {2376#(<= main_~i~0 31)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2377#(<= main_~i~0 32)} is VALID [2022-04-27 21:12:04,374 INFO L290 TraceCheckUtils]: 70: Hoare triple {2377#(<= main_~i~0 32)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2377#(<= main_~i~0 32)} is VALID [2022-04-27 21:12:04,375 INFO L290 TraceCheckUtils]: 71: Hoare triple {2377#(<= main_~i~0 32)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2378#(<= main_~i~0 33)} is VALID [2022-04-27 21:12:04,375 INFO L290 TraceCheckUtils]: 72: Hoare triple {2378#(<= main_~i~0 33)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2378#(<= main_~i~0 33)} is VALID [2022-04-27 21:12:04,375 INFO L290 TraceCheckUtils]: 73: Hoare triple {2378#(<= main_~i~0 33)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2379#(<= main_~i~0 34)} is VALID [2022-04-27 21:12:04,376 INFO L290 TraceCheckUtils]: 74: Hoare triple {2379#(<= main_~i~0 34)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2379#(<= main_~i~0 34)} is VALID [2022-04-27 21:12:04,376 INFO L290 TraceCheckUtils]: 75: Hoare triple {2379#(<= main_~i~0 34)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2380#(<= main_~i~0 35)} is VALID [2022-04-27 21:12:04,376 INFO L290 TraceCheckUtils]: 76: Hoare triple {2380#(<= main_~i~0 35)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2380#(<= main_~i~0 35)} is VALID [2022-04-27 21:12:04,377 INFO L290 TraceCheckUtils]: 77: Hoare triple {2380#(<= main_~i~0 35)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2381#(<= main_~i~0 36)} is VALID [2022-04-27 21:12:04,377 INFO L290 TraceCheckUtils]: 78: Hoare triple {2381#(<= main_~i~0 36)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2381#(<= main_~i~0 36)} is VALID [2022-04-27 21:12:04,377 INFO L290 TraceCheckUtils]: 79: Hoare triple {2381#(<= main_~i~0 36)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2382#(<= main_~i~0 37)} is VALID [2022-04-27 21:12:04,378 INFO L290 TraceCheckUtils]: 80: Hoare triple {2382#(<= main_~i~0 37)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2382#(<= main_~i~0 37)} is VALID [2022-04-27 21:12:04,378 INFO L290 TraceCheckUtils]: 81: Hoare triple {2382#(<= main_~i~0 37)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2383#(<= main_~i~0 38)} is VALID [2022-04-27 21:12:04,378 INFO L290 TraceCheckUtils]: 82: Hoare triple {2383#(<= main_~i~0 38)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2383#(<= main_~i~0 38)} is VALID [2022-04-27 21:12:04,379 INFO L290 TraceCheckUtils]: 83: Hoare triple {2383#(<= main_~i~0 38)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2384#(<= main_~i~0 39)} is VALID [2022-04-27 21:12:04,379 INFO L290 TraceCheckUtils]: 84: Hoare triple {2384#(<= main_~i~0 39)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2384#(<= main_~i~0 39)} is VALID [2022-04-27 21:12:04,383 INFO L290 TraceCheckUtils]: 85: Hoare triple {2384#(<= main_~i~0 39)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2385#(<= main_~i~0 40)} is VALID [2022-04-27 21:12:04,384 INFO L290 TraceCheckUtils]: 86: Hoare triple {2385#(<= main_~i~0 40)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2385#(<= main_~i~0 40)} is VALID [2022-04-27 21:12:04,384 INFO L290 TraceCheckUtils]: 87: Hoare triple {2385#(<= main_~i~0 40)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2386#(<= main_~i~0 41)} is VALID [2022-04-27 21:12:04,385 INFO L290 TraceCheckUtils]: 88: Hoare triple {2386#(<= main_~i~0 41)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2386#(<= main_~i~0 41)} is VALID [2022-04-27 21:12:04,385 INFO L290 TraceCheckUtils]: 89: Hoare triple {2386#(<= main_~i~0 41)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2387#(<= main_~i~0 42)} is VALID [2022-04-27 21:12:04,386 INFO L290 TraceCheckUtils]: 90: Hoare triple {2387#(<= main_~i~0 42)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2387#(<= main_~i~0 42)} is VALID [2022-04-27 21:12:04,386 INFO L290 TraceCheckUtils]: 91: Hoare triple {2387#(<= main_~i~0 42)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2388#(<= main_~i~0 43)} is VALID [2022-04-27 21:12:04,387 INFO L290 TraceCheckUtils]: 92: Hoare triple {2388#(<= main_~i~0 43)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2388#(<= main_~i~0 43)} is VALID [2022-04-27 21:12:04,387 INFO L290 TraceCheckUtils]: 93: Hoare triple {2388#(<= main_~i~0 43)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2389#(<= main_~i~0 44)} is VALID [2022-04-27 21:12:04,387 INFO L290 TraceCheckUtils]: 94: Hoare triple {2389#(<= main_~i~0 44)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2389#(<= main_~i~0 44)} is VALID [2022-04-27 21:12:04,388 INFO L290 TraceCheckUtils]: 95: Hoare triple {2389#(<= main_~i~0 44)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2390#(<= main_~i~0 45)} is VALID [2022-04-27 21:12:04,388 INFO L290 TraceCheckUtils]: 96: Hoare triple {2390#(<= main_~i~0 45)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2390#(<= main_~i~0 45)} is VALID [2022-04-27 21:12:04,389 INFO L290 TraceCheckUtils]: 97: Hoare triple {2390#(<= main_~i~0 45)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2391#(<= main_~i~0 46)} is VALID [2022-04-27 21:12:04,389 INFO L290 TraceCheckUtils]: 98: Hoare triple {2391#(<= main_~i~0 46)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:04,390 INFO L290 TraceCheckUtils]: 99: Hoare triple {2341#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {2341#false} is VALID [2022-04-27 21:12:04,390 INFO L272 TraceCheckUtils]: 100: Hoare triple {2341#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {2341#false} is VALID [2022-04-27 21:12:04,390 INFO L290 TraceCheckUtils]: 101: Hoare triple {2341#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2341#false} is VALID [2022-04-27 21:12:04,390 INFO L290 TraceCheckUtils]: 102: Hoare triple {2341#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:04,390 INFO L290 TraceCheckUtils]: 103: Hoare triple {2341#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:04,392 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:04,392 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:12:04,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1067125673] [2022-04-27 21:12:04,392 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1067125673] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:12:04,392 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2118344106] [2022-04-27 21:12:04,392 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-27 21:12:04,392 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:12:04,392 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:12:04,394 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:12:04,395 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 21:12:20,887 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 47 check-sat command(s) [2022-04-27 21:12:20,887 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:12:20,926 INFO L263 TraceCheckSpWp]: Trace formula consists of 391 conjuncts, 48 conjunts are in the unsatisfiable core [2022-04-27 21:12:20,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:20,987 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:12:21,761 INFO L272 TraceCheckUtils]: 0: Hoare triple {2340#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:21,762 INFO L290 TraceCheckUtils]: 1: Hoare triple {2340#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2340#true} is VALID [2022-04-27 21:12:21,762 INFO L290 TraceCheckUtils]: 2: Hoare triple {2340#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:21,762 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2340#true} {2340#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:21,762 INFO L272 TraceCheckUtils]: 4: Hoare triple {2340#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:21,762 INFO L290 TraceCheckUtils]: 5: Hoare triple {2340#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {2411#(<= main_~i~0 0)} is VALID [2022-04-27 21:12:21,763 INFO L290 TraceCheckUtils]: 6: Hoare triple {2411#(<= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2411#(<= main_~i~0 0)} is VALID [2022-04-27 21:12:21,763 INFO L290 TraceCheckUtils]: 7: Hoare triple {2411#(<= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2346#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:21,763 INFO L290 TraceCheckUtils]: 8: Hoare triple {2346#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2346#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:21,764 INFO L290 TraceCheckUtils]: 9: Hoare triple {2346#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2347#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:21,765 INFO L290 TraceCheckUtils]: 10: Hoare triple {2347#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2347#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:21,765 INFO L290 TraceCheckUtils]: 11: Hoare triple {2347#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2348#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:21,766 INFO L290 TraceCheckUtils]: 12: Hoare triple {2348#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2348#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:21,766 INFO L290 TraceCheckUtils]: 13: Hoare triple {2348#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2349#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:21,766 INFO L290 TraceCheckUtils]: 14: Hoare triple {2349#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2349#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:21,767 INFO L290 TraceCheckUtils]: 15: Hoare triple {2349#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2350#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:21,767 INFO L290 TraceCheckUtils]: 16: Hoare triple {2350#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2350#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:21,767 INFO L290 TraceCheckUtils]: 17: Hoare triple {2350#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2351#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:21,768 INFO L290 TraceCheckUtils]: 18: Hoare triple {2351#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2351#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:21,768 INFO L290 TraceCheckUtils]: 19: Hoare triple {2351#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2352#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:21,768 INFO L290 TraceCheckUtils]: 20: Hoare triple {2352#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2352#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:21,769 INFO L290 TraceCheckUtils]: 21: Hoare triple {2352#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2353#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:21,769 INFO L290 TraceCheckUtils]: 22: Hoare triple {2353#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2353#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:21,769 INFO L290 TraceCheckUtils]: 23: Hoare triple {2353#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2354#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:21,770 INFO L290 TraceCheckUtils]: 24: Hoare triple {2354#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2354#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:21,770 INFO L290 TraceCheckUtils]: 25: Hoare triple {2354#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2355#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:21,770 INFO L290 TraceCheckUtils]: 26: Hoare triple {2355#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2355#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:21,771 INFO L290 TraceCheckUtils]: 27: Hoare triple {2355#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2356#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:21,771 INFO L290 TraceCheckUtils]: 28: Hoare triple {2356#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2356#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:21,771 INFO L290 TraceCheckUtils]: 29: Hoare triple {2356#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2357#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:21,772 INFO L290 TraceCheckUtils]: 30: Hoare triple {2357#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2357#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:21,772 INFO L290 TraceCheckUtils]: 31: Hoare triple {2357#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2358#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:21,772 INFO L290 TraceCheckUtils]: 32: Hoare triple {2358#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2358#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:21,773 INFO L290 TraceCheckUtils]: 33: Hoare triple {2358#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2359#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:21,773 INFO L290 TraceCheckUtils]: 34: Hoare triple {2359#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2359#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:21,774 INFO L290 TraceCheckUtils]: 35: Hoare triple {2359#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2360#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:21,774 INFO L290 TraceCheckUtils]: 36: Hoare triple {2360#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2360#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:21,774 INFO L290 TraceCheckUtils]: 37: Hoare triple {2360#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2361#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:21,775 INFO L290 TraceCheckUtils]: 38: Hoare triple {2361#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2361#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:21,775 INFO L290 TraceCheckUtils]: 39: Hoare triple {2361#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2362#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:21,775 INFO L290 TraceCheckUtils]: 40: Hoare triple {2362#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2362#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:21,776 INFO L290 TraceCheckUtils]: 41: Hoare triple {2362#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2363#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:21,776 INFO L290 TraceCheckUtils]: 42: Hoare triple {2363#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2363#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:21,776 INFO L290 TraceCheckUtils]: 43: Hoare triple {2363#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2364#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:21,777 INFO L290 TraceCheckUtils]: 44: Hoare triple {2364#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2364#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:21,777 INFO L290 TraceCheckUtils]: 45: Hoare triple {2364#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2365#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:21,777 INFO L290 TraceCheckUtils]: 46: Hoare triple {2365#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2365#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:21,778 INFO L290 TraceCheckUtils]: 47: Hoare triple {2365#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2366#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:21,778 INFO L290 TraceCheckUtils]: 48: Hoare triple {2366#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2366#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:21,778 INFO L290 TraceCheckUtils]: 49: Hoare triple {2366#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2367#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:21,779 INFO L290 TraceCheckUtils]: 50: Hoare triple {2367#(<= main_~i~0 22)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2367#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:21,779 INFO L290 TraceCheckUtils]: 51: Hoare triple {2367#(<= main_~i~0 22)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2368#(<= main_~i~0 23)} is VALID [2022-04-27 21:12:21,779 INFO L290 TraceCheckUtils]: 52: Hoare triple {2368#(<= main_~i~0 23)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2368#(<= main_~i~0 23)} is VALID [2022-04-27 21:12:21,780 INFO L290 TraceCheckUtils]: 53: Hoare triple {2368#(<= main_~i~0 23)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2369#(<= main_~i~0 24)} is VALID [2022-04-27 21:12:21,780 INFO L290 TraceCheckUtils]: 54: Hoare triple {2369#(<= main_~i~0 24)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2369#(<= main_~i~0 24)} is VALID [2022-04-27 21:12:21,780 INFO L290 TraceCheckUtils]: 55: Hoare triple {2369#(<= main_~i~0 24)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2370#(<= main_~i~0 25)} is VALID [2022-04-27 21:12:21,781 INFO L290 TraceCheckUtils]: 56: Hoare triple {2370#(<= main_~i~0 25)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2370#(<= main_~i~0 25)} is VALID [2022-04-27 21:12:21,781 INFO L290 TraceCheckUtils]: 57: Hoare triple {2370#(<= main_~i~0 25)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2371#(<= main_~i~0 26)} is VALID [2022-04-27 21:12:21,781 INFO L290 TraceCheckUtils]: 58: Hoare triple {2371#(<= main_~i~0 26)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2371#(<= main_~i~0 26)} is VALID [2022-04-27 21:12:21,782 INFO L290 TraceCheckUtils]: 59: Hoare triple {2371#(<= main_~i~0 26)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2372#(<= main_~i~0 27)} is VALID [2022-04-27 21:12:21,782 INFO L290 TraceCheckUtils]: 60: Hoare triple {2372#(<= main_~i~0 27)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2372#(<= main_~i~0 27)} is VALID [2022-04-27 21:12:21,782 INFO L290 TraceCheckUtils]: 61: Hoare triple {2372#(<= main_~i~0 27)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2373#(<= main_~i~0 28)} is VALID [2022-04-27 21:12:21,783 INFO L290 TraceCheckUtils]: 62: Hoare triple {2373#(<= main_~i~0 28)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2373#(<= main_~i~0 28)} is VALID [2022-04-27 21:12:21,783 INFO L290 TraceCheckUtils]: 63: Hoare triple {2373#(<= main_~i~0 28)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2374#(<= main_~i~0 29)} is VALID [2022-04-27 21:12:21,783 INFO L290 TraceCheckUtils]: 64: Hoare triple {2374#(<= main_~i~0 29)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2374#(<= main_~i~0 29)} is VALID [2022-04-27 21:12:21,784 INFO L290 TraceCheckUtils]: 65: Hoare triple {2374#(<= main_~i~0 29)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2375#(<= main_~i~0 30)} is VALID [2022-04-27 21:12:21,784 INFO L290 TraceCheckUtils]: 66: Hoare triple {2375#(<= main_~i~0 30)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2375#(<= main_~i~0 30)} is VALID [2022-04-27 21:12:21,785 INFO L290 TraceCheckUtils]: 67: Hoare triple {2375#(<= main_~i~0 30)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2376#(<= main_~i~0 31)} is VALID [2022-04-27 21:12:21,785 INFO L290 TraceCheckUtils]: 68: Hoare triple {2376#(<= main_~i~0 31)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2376#(<= main_~i~0 31)} is VALID [2022-04-27 21:12:21,785 INFO L290 TraceCheckUtils]: 69: Hoare triple {2376#(<= main_~i~0 31)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2377#(<= main_~i~0 32)} is VALID [2022-04-27 21:12:21,786 INFO L290 TraceCheckUtils]: 70: Hoare triple {2377#(<= main_~i~0 32)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2377#(<= main_~i~0 32)} is VALID [2022-04-27 21:12:21,786 INFO L290 TraceCheckUtils]: 71: Hoare triple {2377#(<= main_~i~0 32)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2378#(<= main_~i~0 33)} is VALID [2022-04-27 21:12:21,786 INFO L290 TraceCheckUtils]: 72: Hoare triple {2378#(<= main_~i~0 33)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2378#(<= main_~i~0 33)} is VALID [2022-04-27 21:12:21,787 INFO L290 TraceCheckUtils]: 73: Hoare triple {2378#(<= main_~i~0 33)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2379#(<= main_~i~0 34)} is VALID [2022-04-27 21:12:21,787 INFO L290 TraceCheckUtils]: 74: Hoare triple {2379#(<= main_~i~0 34)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2379#(<= main_~i~0 34)} is VALID [2022-04-27 21:12:21,787 INFO L290 TraceCheckUtils]: 75: Hoare triple {2379#(<= main_~i~0 34)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2380#(<= main_~i~0 35)} is VALID [2022-04-27 21:12:21,788 INFO L290 TraceCheckUtils]: 76: Hoare triple {2380#(<= main_~i~0 35)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2380#(<= main_~i~0 35)} is VALID [2022-04-27 21:12:21,788 INFO L290 TraceCheckUtils]: 77: Hoare triple {2380#(<= main_~i~0 35)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2381#(<= main_~i~0 36)} is VALID [2022-04-27 21:12:21,788 INFO L290 TraceCheckUtils]: 78: Hoare triple {2381#(<= main_~i~0 36)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2381#(<= main_~i~0 36)} is VALID [2022-04-27 21:12:21,789 INFO L290 TraceCheckUtils]: 79: Hoare triple {2381#(<= main_~i~0 36)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2382#(<= main_~i~0 37)} is VALID [2022-04-27 21:12:21,789 INFO L290 TraceCheckUtils]: 80: Hoare triple {2382#(<= main_~i~0 37)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2382#(<= main_~i~0 37)} is VALID [2022-04-27 21:12:21,789 INFO L290 TraceCheckUtils]: 81: Hoare triple {2382#(<= main_~i~0 37)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2383#(<= main_~i~0 38)} is VALID [2022-04-27 21:12:21,790 INFO L290 TraceCheckUtils]: 82: Hoare triple {2383#(<= main_~i~0 38)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2383#(<= main_~i~0 38)} is VALID [2022-04-27 21:12:21,790 INFO L290 TraceCheckUtils]: 83: Hoare triple {2383#(<= main_~i~0 38)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2384#(<= main_~i~0 39)} is VALID [2022-04-27 21:12:21,790 INFO L290 TraceCheckUtils]: 84: Hoare triple {2384#(<= main_~i~0 39)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2384#(<= main_~i~0 39)} is VALID [2022-04-27 21:12:21,791 INFO L290 TraceCheckUtils]: 85: Hoare triple {2384#(<= main_~i~0 39)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2385#(<= main_~i~0 40)} is VALID [2022-04-27 21:12:21,791 INFO L290 TraceCheckUtils]: 86: Hoare triple {2385#(<= main_~i~0 40)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2385#(<= main_~i~0 40)} is VALID [2022-04-27 21:12:21,791 INFO L290 TraceCheckUtils]: 87: Hoare triple {2385#(<= main_~i~0 40)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2386#(<= main_~i~0 41)} is VALID [2022-04-27 21:12:21,792 INFO L290 TraceCheckUtils]: 88: Hoare triple {2386#(<= main_~i~0 41)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2386#(<= main_~i~0 41)} is VALID [2022-04-27 21:12:21,792 INFO L290 TraceCheckUtils]: 89: Hoare triple {2386#(<= main_~i~0 41)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2387#(<= main_~i~0 42)} is VALID [2022-04-27 21:12:21,792 INFO L290 TraceCheckUtils]: 90: Hoare triple {2387#(<= main_~i~0 42)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2387#(<= main_~i~0 42)} is VALID [2022-04-27 21:12:21,793 INFO L290 TraceCheckUtils]: 91: Hoare triple {2387#(<= main_~i~0 42)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2388#(<= main_~i~0 43)} is VALID [2022-04-27 21:12:21,793 INFO L290 TraceCheckUtils]: 92: Hoare triple {2388#(<= main_~i~0 43)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2388#(<= main_~i~0 43)} is VALID [2022-04-27 21:12:21,794 INFO L290 TraceCheckUtils]: 93: Hoare triple {2388#(<= main_~i~0 43)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2389#(<= main_~i~0 44)} is VALID [2022-04-27 21:12:21,794 INFO L290 TraceCheckUtils]: 94: Hoare triple {2389#(<= main_~i~0 44)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2389#(<= main_~i~0 44)} is VALID [2022-04-27 21:12:21,800 INFO L290 TraceCheckUtils]: 95: Hoare triple {2389#(<= main_~i~0 44)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2390#(<= main_~i~0 45)} is VALID [2022-04-27 21:12:21,801 INFO L290 TraceCheckUtils]: 96: Hoare triple {2390#(<= main_~i~0 45)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2390#(<= main_~i~0 45)} is VALID [2022-04-27 21:12:21,801 INFO L290 TraceCheckUtils]: 97: Hoare triple {2390#(<= main_~i~0 45)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2391#(<= main_~i~0 46)} is VALID [2022-04-27 21:12:21,802 INFO L290 TraceCheckUtils]: 98: Hoare triple {2391#(<= main_~i~0 46)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:21,802 INFO L290 TraceCheckUtils]: 99: Hoare triple {2341#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {2341#false} is VALID [2022-04-27 21:12:21,802 INFO L272 TraceCheckUtils]: 100: Hoare triple {2341#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {2341#false} is VALID [2022-04-27 21:12:21,802 INFO L290 TraceCheckUtils]: 101: Hoare triple {2341#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2341#false} is VALID [2022-04-27 21:12:21,802 INFO L290 TraceCheckUtils]: 102: Hoare triple {2341#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:21,802 INFO L290 TraceCheckUtils]: 103: Hoare triple {2341#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:21,803 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:21,803 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:12:24,660 INFO L290 TraceCheckUtils]: 103: Hoare triple {2341#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:24,660 INFO L290 TraceCheckUtils]: 102: Hoare triple {2341#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:24,660 INFO L290 TraceCheckUtils]: 101: Hoare triple {2341#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2341#false} is VALID [2022-04-27 21:12:24,660 INFO L272 TraceCheckUtils]: 100: Hoare triple {2341#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {2341#false} is VALID [2022-04-27 21:12:24,660 INFO L290 TraceCheckUtils]: 99: Hoare triple {2341#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {2341#false} is VALID [2022-04-27 21:12:24,661 INFO L290 TraceCheckUtils]: 98: Hoare triple {2721#(< main_~i~0 1024)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {2341#false} is VALID [2022-04-27 21:12:24,661 INFO L290 TraceCheckUtils]: 97: Hoare triple {2725#(< main_~i~0 1023)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2721#(< main_~i~0 1024)} is VALID [2022-04-27 21:12:24,662 INFO L290 TraceCheckUtils]: 96: Hoare triple {2725#(< main_~i~0 1023)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2725#(< main_~i~0 1023)} is VALID [2022-04-27 21:12:24,662 INFO L290 TraceCheckUtils]: 95: Hoare triple {2732#(< main_~i~0 1022)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2725#(< main_~i~0 1023)} is VALID [2022-04-27 21:12:24,662 INFO L290 TraceCheckUtils]: 94: Hoare triple {2732#(< main_~i~0 1022)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2732#(< main_~i~0 1022)} is VALID [2022-04-27 21:12:24,663 INFO L290 TraceCheckUtils]: 93: Hoare triple {2739#(< main_~i~0 1021)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2732#(< main_~i~0 1022)} is VALID [2022-04-27 21:12:24,663 INFO L290 TraceCheckUtils]: 92: Hoare triple {2739#(< main_~i~0 1021)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2739#(< main_~i~0 1021)} is VALID [2022-04-27 21:12:24,663 INFO L290 TraceCheckUtils]: 91: Hoare triple {2746#(< main_~i~0 1020)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2739#(< main_~i~0 1021)} is VALID [2022-04-27 21:12:24,664 INFO L290 TraceCheckUtils]: 90: Hoare triple {2746#(< main_~i~0 1020)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2746#(< main_~i~0 1020)} is VALID [2022-04-27 21:12:24,664 INFO L290 TraceCheckUtils]: 89: Hoare triple {2753#(< main_~i~0 1019)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2746#(< main_~i~0 1020)} is VALID [2022-04-27 21:12:24,664 INFO L290 TraceCheckUtils]: 88: Hoare triple {2753#(< main_~i~0 1019)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2753#(< main_~i~0 1019)} is VALID [2022-04-27 21:12:24,665 INFO L290 TraceCheckUtils]: 87: Hoare triple {2760#(< main_~i~0 1018)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2753#(< main_~i~0 1019)} is VALID [2022-04-27 21:12:24,665 INFO L290 TraceCheckUtils]: 86: Hoare triple {2760#(< main_~i~0 1018)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2760#(< main_~i~0 1018)} is VALID [2022-04-27 21:12:24,665 INFO L290 TraceCheckUtils]: 85: Hoare triple {2767#(< main_~i~0 1017)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2760#(< main_~i~0 1018)} is VALID [2022-04-27 21:12:24,666 INFO L290 TraceCheckUtils]: 84: Hoare triple {2767#(< main_~i~0 1017)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2767#(< main_~i~0 1017)} is VALID [2022-04-27 21:12:24,666 INFO L290 TraceCheckUtils]: 83: Hoare triple {2774#(< main_~i~0 1016)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2767#(< main_~i~0 1017)} is VALID [2022-04-27 21:12:24,666 INFO L290 TraceCheckUtils]: 82: Hoare triple {2774#(< main_~i~0 1016)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2774#(< main_~i~0 1016)} is VALID [2022-04-27 21:12:24,667 INFO L290 TraceCheckUtils]: 81: Hoare triple {2781#(< main_~i~0 1015)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2774#(< main_~i~0 1016)} is VALID [2022-04-27 21:12:24,667 INFO L290 TraceCheckUtils]: 80: Hoare triple {2781#(< main_~i~0 1015)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2781#(< main_~i~0 1015)} is VALID [2022-04-27 21:12:24,668 INFO L290 TraceCheckUtils]: 79: Hoare triple {2788#(< main_~i~0 1014)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2781#(< main_~i~0 1015)} is VALID [2022-04-27 21:12:24,668 INFO L290 TraceCheckUtils]: 78: Hoare triple {2788#(< main_~i~0 1014)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2788#(< main_~i~0 1014)} is VALID [2022-04-27 21:12:24,668 INFO L290 TraceCheckUtils]: 77: Hoare triple {2795#(< main_~i~0 1013)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2788#(< main_~i~0 1014)} is VALID [2022-04-27 21:12:24,669 INFO L290 TraceCheckUtils]: 76: Hoare triple {2795#(< main_~i~0 1013)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2795#(< main_~i~0 1013)} is VALID [2022-04-27 21:12:24,669 INFO L290 TraceCheckUtils]: 75: Hoare triple {2802#(< main_~i~0 1012)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2795#(< main_~i~0 1013)} is VALID [2022-04-27 21:12:24,669 INFO L290 TraceCheckUtils]: 74: Hoare triple {2802#(< main_~i~0 1012)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2802#(< main_~i~0 1012)} is VALID [2022-04-27 21:12:24,675 INFO L290 TraceCheckUtils]: 73: Hoare triple {2809#(< main_~i~0 1011)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2802#(< main_~i~0 1012)} is VALID [2022-04-27 21:12:24,676 INFO L290 TraceCheckUtils]: 72: Hoare triple {2809#(< main_~i~0 1011)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2809#(< main_~i~0 1011)} is VALID [2022-04-27 21:12:24,676 INFO L290 TraceCheckUtils]: 71: Hoare triple {2816#(< main_~i~0 1010)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2809#(< main_~i~0 1011)} is VALID [2022-04-27 21:12:24,676 INFO L290 TraceCheckUtils]: 70: Hoare triple {2816#(< main_~i~0 1010)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2816#(< main_~i~0 1010)} is VALID [2022-04-27 21:12:24,677 INFO L290 TraceCheckUtils]: 69: Hoare triple {2823#(< main_~i~0 1009)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2816#(< main_~i~0 1010)} is VALID [2022-04-27 21:12:24,679 INFO L290 TraceCheckUtils]: 68: Hoare triple {2823#(< main_~i~0 1009)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2823#(< main_~i~0 1009)} is VALID [2022-04-27 21:12:24,680 INFO L290 TraceCheckUtils]: 67: Hoare triple {2830#(< main_~i~0 1008)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2823#(< main_~i~0 1009)} is VALID [2022-04-27 21:12:24,680 INFO L290 TraceCheckUtils]: 66: Hoare triple {2830#(< main_~i~0 1008)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2830#(< main_~i~0 1008)} is VALID [2022-04-27 21:12:24,681 INFO L290 TraceCheckUtils]: 65: Hoare triple {2837#(< main_~i~0 1007)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2830#(< main_~i~0 1008)} is VALID [2022-04-27 21:12:24,681 INFO L290 TraceCheckUtils]: 64: Hoare triple {2837#(< main_~i~0 1007)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2837#(< main_~i~0 1007)} is VALID [2022-04-27 21:12:24,682 INFO L290 TraceCheckUtils]: 63: Hoare triple {2844#(< main_~i~0 1006)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2837#(< main_~i~0 1007)} is VALID [2022-04-27 21:12:24,682 INFO L290 TraceCheckUtils]: 62: Hoare triple {2844#(< main_~i~0 1006)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2844#(< main_~i~0 1006)} is VALID [2022-04-27 21:12:24,682 INFO L290 TraceCheckUtils]: 61: Hoare triple {2851#(< main_~i~0 1005)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2844#(< main_~i~0 1006)} is VALID [2022-04-27 21:12:24,683 INFO L290 TraceCheckUtils]: 60: Hoare triple {2851#(< main_~i~0 1005)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2851#(< main_~i~0 1005)} is VALID [2022-04-27 21:12:24,683 INFO L290 TraceCheckUtils]: 59: Hoare triple {2858#(< main_~i~0 1004)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2851#(< main_~i~0 1005)} is VALID [2022-04-27 21:12:24,684 INFO L290 TraceCheckUtils]: 58: Hoare triple {2858#(< main_~i~0 1004)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2858#(< main_~i~0 1004)} is VALID [2022-04-27 21:12:24,684 INFO L290 TraceCheckUtils]: 57: Hoare triple {2865#(< main_~i~0 1003)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2858#(< main_~i~0 1004)} is VALID [2022-04-27 21:12:24,685 INFO L290 TraceCheckUtils]: 56: Hoare triple {2865#(< main_~i~0 1003)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2865#(< main_~i~0 1003)} is VALID [2022-04-27 21:12:24,685 INFO L290 TraceCheckUtils]: 55: Hoare triple {2872#(< main_~i~0 1002)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2865#(< main_~i~0 1003)} is VALID [2022-04-27 21:12:24,686 INFO L290 TraceCheckUtils]: 54: Hoare triple {2872#(< main_~i~0 1002)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2872#(< main_~i~0 1002)} is VALID [2022-04-27 21:12:24,686 INFO L290 TraceCheckUtils]: 53: Hoare triple {2879#(< main_~i~0 1001)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2872#(< main_~i~0 1002)} is VALID [2022-04-27 21:12:24,687 INFO L290 TraceCheckUtils]: 52: Hoare triple {2879#(< main_~i~0 1001)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2879#(< main_~i~0 1001)} is VALID [2022-04-27 21:12:24,687 INFO L290 TraceCheckUtils]: 51: Hoare triple {2886#(< main_~i~0 1000)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2879#(< main_~i~0 1001)} is VALID [2022-04-27 21:12:24,687 INFO L290 TraceCheckUtils]: 50: Hoare triple {2886#(< main_~i~0 1000)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2886#(< main_~i~0 1000)} is VALID [2022-04-27 21:12:24,688 INFO L290 TraceCheckUtils]: 49: Hoare triple {2893#(< main_~i~0 999)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2886#(< main_~i~0 1000)} is VALID [2022-04-27 21:12:24,688 INFO L290 TraceCheckUtils]: 48: Hoare triple {2893#(< main_~i~0 999)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2893#(< main_~i~0 999)} is VALID [2022-04-27 21:12:24,689 INFO L290 TraceCheckUtils]: 47: Hoare triple {2900#(< main_~i~0 998)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2893#(< main_~i~0 999)} is VALID [2022-04-27 21:12:24,689 INFO L290 TraceCheckUtils]: 46: Hoare triple {2900#(< main_~i~0 998)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2900#(< main_~i~0 998)} is VALID [2022-04-27 21:12:24,690 INFO L290 TraceCheckUtils]: 45: Hoare triple {2907#(< main_~i~0 997)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2900#(< main_~i~0 998)} is VALID [2022-04-27 21:12:24,690 INFO L290 TraceCheckUtils]: 44: Hoare triple {2907#(< main_~i~0 997)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2907#(< main_~i~0 997)} is VALID [2022-04-27 21:12:24,691 INFO L290 TraceCheckUtils]: 43: Hoare triple {2914#(< main_~i~0 996)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2907#(< main_~i~0 997)} is VALID [2022-04-27 21:12:24,691 INFO L290 TraceCheckUtils]: 42: Hoare triple {2914#(< main_~i~0 996)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2914#(< main_~i~0 996)} is VALID [2022-04-27 21:12:24,692 INFO L290 TraceCheckUtils]: 41: Hoare triple {2921#(< main_~i~0 995)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2914#(< main_~i~0 996)} is VALID [2022-04-27 21:12:24,692 INFO L290 TraceCheckUtils]: 40: Hoare triple {2921#(< main_~i~0 995)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2921#(< main_~i~0 995)} is VALID [2022-04-27 21:12:24,692 INFO L290 TraceCheckUtils]: 39: Hoare triple {2928#(< main_~i~0 994)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2921#(< main_~i~0 995)} is VALID [2022-04-27 21:12:24,693 INFO L290 TraceCheckUtils]: 38: Hoare triple {2928#(< main_~i~0 994)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2928#(< main_~i~0 994)} is VALID [2022-04-27 21:12:24,693 INFO L290 TraceCheckUtils]: 37: Hoare triple {2935#(< main_~i~0 993)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2928#(< main_~i~0 994)} is VALID [2022-04-27 21:12:24,694 INFO L290 TraceCheckUtils]: 36: Hoare triple {2935#(< main_~i~0 993)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2935#(< main_~i~0 993)} is VALID [2022-04-27 21:12:24,694 INFO L290 TraceCheckUtils]: 35: Hoare triple {2942#(< main_~i~0 992)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2935#(< main_~i~0 993)} is VALID [2022-04-27 21:12:24,695 INFO L290 TraceCheckUtils]: 34: Hoare triple {2942#(< main_~i~0 992)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2942#(< main_~i~0 992)} is VALID [2022-04-27 21:12:24,695 INFO L290 TraceCheckUtils]: 33: Hoare triple {2949#(< main_~i~0 991)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2942#(< main_~i~0 992)} is VALID [2022-04-27 21:12:24,696 INFO L290 TraceCheckUtils]: 32: Hoare triple {2949#(< main_~i~0 991)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2949#(< main_~i~0 991)} is VALID [2022-04-27 21:12:24,696 INFO L290 TraceCheckUtils]: 31: Hoare triple {2956#(< main_~i~0 990)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2949#(< main_~i~0 991)} is VALID [2022-04-27 21:12:24,696 INFO L290 TraceCheckUtils]: 30: Hoare triple {2956#(< main_~i~0 990)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2956#(< main_~i~0 990)} is VALID [2022-04-27 21:12:24,697 INFO L290 TraceCheckUtils]: 29: Hoare triple {2963#(< main_~i~0 989)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2956#(< main_~i~0 990)} is VALID [2022-04-27 21:12:24,697 INFO L290 TraceCheckUtils]: 28: Hoare triple {2963#(< main_~i~0 989)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2963#(< main_~i~0 989)} is VALID [2022-04-27 21:12:24,698 INFO L290 TraceCheckUtils]: 27: Hoare triple {2970#(< main_~i~0 988)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2963#(< main_~i~0 989)} is VALID [2022-04-27 21:12:24,698 INFO L290 TraceCheckUtils]: 26: Hoare triple {2970#(< main_~i~0 988)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2970#(< main_~i~0 988)} is VALID [2022-04-27 21:12:24,699 INFO L290 TraceCheckUtils]: 25: Hoare triple {2977#(< main_~i~0 987)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2970#(< main_~i~0 988)} is VALID [2022-04-27 21:12:24,699 INFO L290 TraceCheckUtils]: 24: Hoare triple {2977#(< main_~i~0 987)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2977#(< main_~i~0 987)} is VALID [2022-04-27 21:12:24,699 INFO L290 TraceCheckUtils]: 23: Hoare triple {2984#(< main_~i~0 986)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2977#(< main_~i~0 987)} is VALID [2022-04-27 21:12:24,700 INFO L290 TraceCheckUtils]: 22: Hoare triple {2984#(< main_~i~0 986)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2984#(< main_~i~0 986)} is VALID [2022-04-27 21:12:24,700 INFO L290 TraceCheckUtils]: 21: Hoare triple {2991#(< main_~i~0 985)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2984#(< main_~i~0 986)} is VALID [2022-04-27 21:12:24,701 INFO L290 TraceCheckUtils]: 20: Hoare triple {2991#(< main_~i~0 985)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2991#(< main_~i~0 985)} is VALID [2022-04-27 21:12:24,701 INFO L290 TraceCheckUtils]: 19: Hoare triple {2998#(< main_~i~0 984)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2991#(< main_~i~0 985)} is VALID [2022-04-27 21:12:24,702 INFO L290 TraceCheckUtils]: 18: Hoare triple {2998#(< main_~i~0 984)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {2998#(< main_~i~0 984)} is VALID [2022-04-27 21:12:24,702 INFO L290 TraceCheckUtils]: 17: Hoare triple {3005#(< main_~i~0 983)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {2998#(< main_~i~0 984)} is VALID [2022-04-27 21:12:24,703 INFO L290 TraceCheckUtils]: 16: Hoare triple {3005#(< main_~i~0 983)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3005#(< main_~i~0 983)} is VALID [2022-04-27 21:12:24,703 INFO L290 TraceCheckUtils]: 15: Hoare triple {3012#(< main_~i~0 982)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3005#(< main_~i~0 983)} is VALID [2022-04-27 21:12:24,704 INFO L290 TraceCheckUtils]: 14: Hoare triple {3012#(< main_~i~0 982)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3012#(< main_~i~0 982)} is VALID [2022-04-27 21:12:24,704 INFO L290 TraceCheckUtils]: 13: Hoare triple {3019#(< main_~i~0 981)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3012#(< main_~i~0 982)} is VALID [2022-04-27 21:12:24,705 INFO L290 TraceCheckUtils]: 12: Hoare triple {3019#(< main_~i~0 981)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3019#(< main_~i~0 981)} is VALID [2022-04-27 21:12:24,705 INFO L290 TraceCheckUtils]: 11: Hoare triple {3026#(< main_~i~0 980)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3019#(< main_~i~0 981)} is VALID [2022-04-27 21:12:24,706 INFO L290 TraceCheckUtils]: 10: Hoare triple {3026#(< main_~i~0 980)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3026#(< main_~i~0 980)} is VALID [2022-04-27 21:12:24,706 INFO L290 TraceCheckUtils]: 9: Hoare triple {3033#(< main_~i~0 979)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3026#(< main_~i~0 980)} is VALID [2022-04-27 21:12:24,707 INFO L290 TraceCheckUtils]: 8: Hoare triple {3033#(< main_~i~0 979)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3033#(< main_~i~0 979)} is VALID [2022-04-27 21:12:24,707 INFO L290 TraceCheckUtils]: 7: Hoare triple {3040#(< main_~i~0 978)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {3033#(< main_~i~0 979)} is VALID [2022-04-27 21:12:24,708 INFO L290 TraceCheckUtils]: 6: Hoare triple {3040#(< main_~i~0 978)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {3040#(< main_~i~0 978)} is VALID [2022-04-27 21:12:24,708 INFO L290 TraceCheckUtils]: 5: Hoare triple {2340#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {3040#(< main_~i~0 978)} is VALID [2022-04-27 21:12:24,708 INFO L272 TraceCheckUtils]: 4: Hoare triple {2340#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:24,709 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2340#true} {2340#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:24,709 INFO L290 TraceCheckUtils]: 2: Hoare triple {2340#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:24,709 INFO L290 TraceCheckUtils]: 1: Hoare triple {2340#true} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2340#true} is VALID [2022-04-27 21:12:24,709 INFO L272 TraceCheckUtils]: 0: Hoare triple {2340#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2340#true} is VALID [2022-04-27 21:12:24,710 INFO L134 CoverageAnalysis]: Checked inductivity of 2116 backedges. 0 proven. 2116 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:24,710 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2118344106] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:12:24,711 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:12:24,711 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49, 49] total 98 [2022-04-27 21:12:24,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [560425409] [2022-04-27 21:12:24,711 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:12:24,712 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 104 [2022-04-27 21:12:24,713 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:12:24,713 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:24,865 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 203 edges. 203 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:12:24,866 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-04-27 21:12:24,866 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:12:24,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-04-27 21:12:24,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=4658, Invalid=4848, Unknown=0, NotChecked=0, Total=9506 [2022-04-27 21:12:24,870 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:28,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:28,699 INFO L93 Difference]: Finished difference Result 207 states and 254 transitions. [2022-04-27 21:12:28,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 97 states. [2022-04-27 21:12:28,700 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 104 [2022-04-27 21:12:28,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:12:28,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:28,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 254 transitions. [2022-04-27 21:12:28,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:28,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 254 transitions. [2022-04-27 21:12:28,718 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 97 states and 254 transitions. [2022-04-27 21:12:28,918 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 254 edges. 254 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:12:28,923 INFO L225 Difference]: With dead ends: 207 [2022-04-27 21:12:28,923 INFO L226 Difference]: Without dead ends: 201 [2022-04-27 21:12:28,931 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 352 GetRequests, 162 SyntacticMatches, 0 SemanticMatches, 190 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5728 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=13777, Invalid=22895, Unknown=0, NotChecked=0, Total=36672 [2022-04-27 21:12:28,932 INFO L413 NwaCegarLoop]: 12 mSDtfsCounter, 242 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 208 mSolverCounterSat, 151 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 242 SdHoareTripleChecker+Valid, 29 SdHoareTripleChecker+Invalid, 359 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 151 IncrementalHoareTripleChecker+Valid, 208 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 21:12:28,932 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [242 Valid, 29 Invalid, 359 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [151 Valid, 208 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 21:12:28,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2022-04-27 21:12:29,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2022-04-27 21:12:29,040 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:12:29,040 INFO L82 GeneralOperation]: Start isEquivalent. First operand 201 states. Second operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:29,041 INFO L74 IsIncluded]: Start isIncluded. First operand 201 states. Second operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:29,041 INFO L87 Difference]: Start difference. First operand 201 states. Second operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:29,047 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:29,047 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2022-04-27 21:12:29,047 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2022-04-27 21:12:29,047 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:12:29,047 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:12:29,048 INFO L74 IsIncluded]: Start isIncluded. First operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 201 states. [2022-04-27 21:12:29,048 INFO L87 Difference]: Start difference. First operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 201 states. [2022-04-27 21:12:29,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:29,054 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2022-04-27 21:12:29,054 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2022-04-27 21:12:29,054 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:12:29,054 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:12:29,054 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:12:29,054 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:12:29,055 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 201 states, 196 states have (on average 1.0051020408163265) internal successors, (197), 196 states have internal predecessors, (197), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:29,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2022-04-27 21:12:29,068 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 201 transitions. Word has length 104 [2022-04-27 21:12:29,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:12:29,068 INFO L495 AbstractCegarLoop]: Abstraction has 201 states and 201 transitions. [2022-04-27 21:12:29,069 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 98 states, 98 states have (on average 2.020408163265306) internal successors, (198), 97 states have internal predecessors, (198), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:29,069 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2022-04-27 21:12:29,075 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2022-04-27 21:12:29,075 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:12:29,075 INFO L195 NwaCegarLoop]: trace histogram [94, 94, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:12:29,104 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2022-04-27 21:12:29,291 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:12:29,291 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:12:29,292 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:12:29,292 INFO L85 PathProgramCache]: Analyzing trace with hash -560303625, now seen corresponding path program 6 times [2022-04-27 21:12:29,292 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:12:29,292 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [279809146] [2022-04-27 21:12:29,292 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:12:29,292 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:12:29,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:32,575 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:12:32,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:32,584 INFO L290 TraceCheckUtils]: 0: Hoare triple {4366#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4266#true} is VALID [2022-04-27 21:12:32,584 INFO L290 TraceCheckUtils]: 1: Hoare triple {4266#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4266#true} is VALID [2022-04-27 21:12:32,584 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4266#true} {4266#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4266#true} is VALID [2022-04-27 21:12:32,584 INFO L272 TraceCheckUtils]: 0: Hoare triple {4266#true} [42] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4366#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:12:32,585 INFO L290 TraceCheckUtils]: 1: Hoare triple {4366#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [44] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_4| 1))) (and (= (select |v_#valid_5| 1) 1) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= (select .cse0 1) 0) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 48 (select .cse0 0)) (= 1 (select |v_#valid_5| 3)) (= 12 (select |v_#length_3| 2)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_4|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_4|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4266#true} is VALID [2022-04-27 21:12:32,585 INFO L290 TraceCheckUtils]: 2: Hoare triple {4266#true} [47] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4266#true} is VALID [2022-04-27 21:12:32,585 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4266#true} {4266#true} [62] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4266#true} is VALID [2022-04-27 21:12:32,585 INFO L272 TraceCheckUtils]: 4: Hoare triple {4266#true} [43] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4266#true} is VALID [2022-04-27 21:12:32,585 INFO L290 TraceCheckUtils]: 5: Hoare triple {4266#true} [46] mainENTRY-->L16-3: Formula: (and (= v_main_~i~0_1 0) (= 0 |v_main_~#A~0.offset_2|) (< |v_#StackHeapBarrier_1| |v_main_~#A~0.base_2|) (= |v_#valid_1| (store |v_#valid_2| |v_main_~#A~0.base_2| 1)) (= 0 (select |v_#valid_2| |v_main_~#A~0.base_2|)) (= |v_#length_1| (store |v_#length_2| |v_main_~#A~0.base_2| 8192)) (not (= |v_main_~#A~0.base_2| 0))) InVars {#StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~#A~0.offset=|v_main_~#A~0.offset_2|, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, #length=|v_#length_1|, main_~#A~0.base=|v_main_~#A~0.base_2|} AuxVars[] AssignedVars[main_~#A~0.offset, #valid, main_~i~0, #length, main_~#A~0.base] {4271#(= main_~i~0 0)} is VALID [2022-04-27 21:12:32,585 INFO L290 TraceCheckUtils]: 6: Hoare triple {4271#(= main_~i~0 0)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4271#(= main_~i~0 0)} is VALID [2022-04-27 21:12:32,586 INFO L290 TraceCheckUtils]: 7: Hoare triple {4271#(= main_~i~0 0)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4272#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:32,586 INFO L290 TraceCheckUtils]: 8: Hoare triple {4272#(<= main_~i~0 1)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4272#(<= main_~i~0 1)} is VALID [2022-04-27 21:12:32,587 INFO L290 TraceCheckUtils]: 9: Hoare triple {4272#(<= main_~i~0 1)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4273#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:32,587 INFO L290 TraceCheckUtils]: 10: Hoare triple {4273#(<= main_~i~0 2)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4273#(<= main_~i~0 2)} is VALID [2022-04-27 21:12:32,587 INFO L290 TraceCheckUtils]: 11: Hoare triple {4273#(<= main_~i~0 2)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4274#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:32,587 INFO L290 TraceCheckUtils]: 12: Hoare triple {4274#(<= main_~i~0 3)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4274#(<= main_~i~0 3)} is VALID [2022-04-27 21:12:32,588 INFO L290 TraceCheckUtils]: 13: Hoare triple {4274#(<= main_~i~0 3)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4275#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:32,588 INFO L290 TraceCheckUtils]: 14: Hoare triple {4275#(<= main_~i~0 4)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4275#(<= main_~i~0 4)} is VALID [2022-04-27 21:12:32,589 INFO L290 TraceCheckUtils]: 15: Hoare triple {4275#(<= main_~i~0 4)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4276#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:32,589 INFO L290 TraceCheckUtils]: 16: Hoare triple {4276#(<= main_~i~0 5)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4276#(<= main_~i~0 5)} is VALID [2022-04-27 21:12:32,589 INFO L290 TraceCheckUtils]: 17: Hoare triple {4276#(<= main_~i~0 5)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4277#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:32,589 INFO L290 TraceCheckUtils]: 18: Hoare triple {4277#(<= main_~i~0 6)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4277#(<= main_~i~0 6)} is VALID [2022-04-27 21:12:32,590 INFO L290 TraceCheckUtils]: 19: Hoare triple {4277#(<= main_~i~0 6)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4278#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:32,590 INFO L290 TraceCheckUtils]: 20: Hoare triple {4278#(<= main_~i~0 7)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4278#(<= main_~i~0 7)} is VALID [2022-04-27 21:12:32,591 INFO L290 TraceCheckUtils]: 21: Hoare triple {4278#(<= main_~i~0 7)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4279#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:32,591 INFO L290 TraceCheckUtils]: 22: Hoare triple {4279#(<= main_~i~0 8)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4279#(<= main_~i~0 8)} is VALID [2022-04-27 21:12:32,591 INFO L290 TraceCheckUtils]: 23: Hoare triple {4279#(<= main_~i~0 8)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4280#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:32,592 INFO L290 TraceCheckUtils]: 24: Hoare triple {4280#(<= main_~i~0 9)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4280#(<= main_~i~0 9)} is VALID [2022-04-27 21:12:32,592 INFO L290 TraceCheckUtils]: 25: Hoare triple {4280#(<= main_~i~0 9)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4281#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:32,592 INFO L290 TraceCheckUtils]: 26: Hoare triple {4281#(<= main_~i~0 10)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4281#(<= main_~i~0 10)} is VALID [2022-04-27 21:12:32,593 INFO L290 TraceCheckUtils]: 27: Hoare triple {4281#(<= main_~i~0 10)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4282#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:32,593 INFO L290 TraceCheckUtils]: 28: Hoare triple {4282#(<= main_~i~0 11)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4282#(<= main_~i~0 11)} is VALID [2022-04-27 21:12:32,593 INFO L290 TraceCheckUtils]: 29: Hoare triple {4282#(<= main_~i~0 11)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4283#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:32,594 INFO L290 TraceCheckUtils]: 30: Hoare triple {4283#(<= main_~i~0 12)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4283#(<= main_~i~0 12)} is VALID [2022-04-27 21:12:32,594 INFO L290 TraceCheckUtils]: 31: Hoare triple {4283#(<= main_~i~0 12)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4284#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:32,594 INFO L290 TraceCheckUtils]: 32: Hoare triple {4284#(<= main_~i~0 13)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4284#(<= main_~i~0 13)} is VALID [2022-04-27 21:12:32,595 INFO L290 TraceCheckUtils]: 33: Hoare triple {4284#(<= main_~i~0 13)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4285#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:32,595 INFO L290 TraceCheckUtils]: 34: Hoare triple {4285#(<= main_~i~0 14)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4285#(<= main_~i~0 14)} is VALID [2022-04-27 21:12:32,595 INFO L290 TraceCheckUtils]: 35: Hoare triple {4285#(<= main_~i~0 14)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4286#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:32,596 INFO L290 TraceCheckUtils]: 36: Hoare triple {4286#(<= main_~i~0 15)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4286#(<= main_~i~0 15)} is VALID [2022-04-27 21:12:32,596 INFO L290 TraceCheckUtils]: 37: Hoare triple {4286#(<= main_~i~0 15)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4287#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:32,596 INFO L290 TraceCheckUtils]: 38: Hoare triple {4287#(<= main_~i~0 16)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4287#(<= main_~i~0 16)} is VALID [2022-04-27 21:12:32,597 INFO L290 TraceCheckUtils]: 39: Hoare triple {4287#(<= main_~i~0 16)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4288#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:32,597 INFO L290 TraceCheckUtils]: 40: Hoare triple {4288#(<= main_~i~0 17)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4288#(<= main_~i~0 17)} is VALID [2022-04-27 21:12:32,597 INFO L290 TraceCheckUtils]: 41: Hoare triple {4288#(<= main_~i~0 17)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4289#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:32,598 INFO L290 TraceCheckUtils]: 42: Hoare triple {4289#(<= main_~i~0 18)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4289#(<= main_~i~0 18)} is VALID [2022-04-27 21:12:32,598 INFO L290 TraceCheckUtils]: 43: Hoare triple {4289#(<= main_~i~0 18)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4290#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:32,598 INFO L290 TraceCheckUtils]: 44: Hoare triple {4290#(<= main_~i~0 19)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4290#(<= main_~i~0 19)} is VALID [2022-04-27 21:12:32,599 INFO L290 TraceCheckUtils]: 45: Hoare triple {4290#(<= main_~i~0 19)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4291#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:32,599 INFO L290 TraceCheckUtils]: 46: Hoare triple {4291#(<= main_~i~0 20)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4291#(<= main_~i~0 20)} is VALID [2022-04-27 21:12:32,599 INFO L290 TraceCheckUtils]: 47: Hoare triple {4291#(<= main_~i~0 20)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4292#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:32,600 INFO L290 TraceCheckUtils]: 48: Hoare triple {4292#(<= main_~i~0 21)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4292#(<= main_~i~0 21)} is VALID [2022-04-27 21:12:32,600 INFO L290 TraceCheckUtils]: 49: Hoare triple {4292#(<= main_~i~0 21)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4293#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:32,600 INFO L290 TraceCheckUtils]: 50: Hoare triple {4293#(<= main_~i~0 22)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4293#(<= main_~i~0 22)} is VALID [2022-04-27 21:12:32,601 INFO L290 TraceCheckUtils]: 51: Hoare triple {4293#(<= main_~i~0 22)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4294#(<= main_~i~0 23)} is VALID [2022-04-27 21:12:32,601 INFO L290 TraceCheckUtils]: 52: Hoare triple {4294#(<= main_~i~0 23)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4294#(<= main_~i~0 23)} is VALID [2022-04-27 21:12:32,601 INFO L290 TraceCheckUtils]: 53: Hoare triple {4294#(<= main_~i~0 23)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4295#(<= main_~i~0 24)} is VALID [2022-04-27 21:12:32,602 INFO L290 TraceCheckUtils]: 54: Hoare triple {4295#(<= main_~i~0 24)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4295#(<= main_~i~0 24)} is VALID [2022-04-27 21:12:32,602 INFO L290 TraceCheckUtils]: 55: Hoare triple {4295#(<= main_~i~0 24)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4296#(<= main_~i~0 25)} is VALID [2022-04-27 21:12:32,603 INFO L290 TraceCheckUtils]: 56: Hoare triple {4296#(<= main_~i~0 25)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4296#(<= main_~i~0 25)} is VALID [2022-04-27 21:12:32,604 INFO L290 TraceCheckUtils]: 57: Hoare triple {4296#(<= main_~i~0 25)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4297#(<= main_~i~0 26)} is VALID [2022-04-27 21:12:32,604 INFO L290 TraceCheckUtils]: 58: Hoare triple {4297#(<= main_~i~0 26)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4297#(<= main_~i~0 26)} is VALID [2022-04-27 21:12:32,605 INFO L290 TraceCheckUtils]: 59: Hoare triple {4297#(<= main_~i~0 26)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4298#(<= main_~i~0 27)} is VALID [2022-04-27 21:12:32,605 INFO L290 TraceCheckUtils]: 60: Hoare triple {4298#(<= main_~i~0 27)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4298#(<= main_~i~0 27)} is VALID [2022-04-27 21:12:32,606 INFO L290 TraceCheckUtils]: 61: Hoare triple {4298#(<= main_~i~0 27)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4299#(<= main_~i~0 28)} is VALID [2022-04-27 21:12:32,606 INFO L290 TraceCheckUtils]: 62: Hoare triple {4299#(<= main_~i~0 28)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4299#(<= main_~i~0 28)} is VALID [2022-04-27 21:12:32,607 INFO L290 TraceCheckUtils]: 63: Hoare triple {4299#(<= main_~i~0 28)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4300#(<= main_~i~0 29)} is VALID [2022-04-27 21:12:32,607 INFO L290 TraceCheckUtils]: 64: Hoare triple {4300#(<= main_~i~0 29)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4300#(<= main_~i~0 29)} is VALID [2022-04-27 21:12:32,607 INFO L290 TraceCheckUtils]: 65: Hoare triple {4300#(<= main_~i~0 29)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4301#(<= main_~i~0 30)} is VALID [2022-04-27 21:12:32,608 INFO L290 TraceCheckUtils]: 66: Hoare triple {4301#(<= main_~i~0 30)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4301#(<= main_~i~0 30)} is VALID [2022-04-27 21:12:32,608 INFO L290 TraceCheckUtils]: 67: Hoare triple {4301#(<= main_~i~0 30)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4302#(<= main_~i~0 31)} is VALID [2022-04-27 21:12:32,609 INFO L290 TraceCheckUtils]: 68: Hoare triple {4302#(<= main_~i~0 31)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4302#(<= main_~i~0 31)} is VALID [2022-04-27 21:12:32,609 INFO L290 TraceCheckUtils]: 69: Hoare triple {4302#(<= main_~i~0 31)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4303#(<= main_~i~0 32)} is VALID [2022-04-27 21:12:32,610 INFO L290 TraceCheckUtils]: 70: Hoare triple {4303#(<= main_~i~0 32)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4303#(<= main_~i~0 32)} is VALID [2022-04-27 21:12:32,610 INFO L290 TraceCheckUtils]: 71: Hoare triple {4303#(<= main_~i~0 32)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4304#(<= main_~i~0 33)} is VALID [2022-04-27 21:12:32,611 INFO L290 TraceCheckUtils]: 72: Hoare triple {4304#(<= main_~i~0 33)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4304#(<= main_~i~0 33)} is VALID [2022-04-27 21:12:32,611 INFO L290 TraceCheckUtils]: 73: Hoare triple {4304#(<= main_~i~0 33)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4305#(<= main_~i~0 34)} is VALID [2022-04-27 21:12:32,612 INFO L290 TraceCheckUtils]: 74: Hoare triple {4305#(<= main_~i~0 34)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4305#(<= main_~i~0 34)} is VALID [2022-04-27 21:12:32,612 INFO L290 TraceCheckUtils]: 75: Hoare triple {4305#(<= main_~i~0 34)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4306#(<= main_~i~0 35)} is VALID [2022-04-27 21:12:32,613 INFO L290 TraceCheckUtils]: 76: Hoare triple {4306#(<= main_~i~0 35)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4306#(<= main_~i~0 35)} is VALID [2022-04-27 21:12:32,613 INFO L290 TraceCheckUtils]: 77: Hoare triple {4306#(<= main_~i~0 35)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4307#(<= main_~i~0 36)} is VALID [2022-04-27 21:12:32,613 INFO L290 TraceCheckUtils]: 78: Hoare triple {4307#(<= main_~i~0 36)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4307#(<= main_~i~0 36)} is VALID [2022-04-27 21:12:32,614 INFO L290 TraceCheckUtils]: 79: Hoare triple {4307#(<= main_~i~0 36)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4308#(<= main_~i~0 37)} is VALID [2022-04-27 21:12:32,614 INFO L290 TraceCheckUtils]: 80: Hoare triple {4308#(<= main_~i~0 37)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4308#(<= main_~i~0 37)} is VALID [2022-04-27 21:12:32,615 INFO L290 TraceCheckUtils]: 81: Hoare triple {4308#(<= main_~i~0 37)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4309#(<= main_~i~0 38)} is VALID [2022-04-27 21:12:32,615 INFO L290 TraceCheckUtils]: 82: Hoare triple {4309#(<= main_~i~0 38)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4309#(<= main_~i~0 38)} is VALID [2022-04-27 21:12:32,616 INFO L290 TraceCheckUtils]: 83: Hoare triple {4309#(<= main_~i~0 38)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4310#(<= main_~i~0 39)} is VALID [2022-04-27 21:12:32,616 INFO L290 TraceCheckUtils]: 84: Hoare triple {4310#(<= main_~i~0 39)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4310#(<= main_~i~0 39)} is VALID [2022-04-27 21:12:32,617 INFO L290 TraceCheckUtils]: 85: Hoare triple {4310#(<= main_~i~0 39)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4311#(<= main_~i~0 40)} is VALID [2022-04-27 21:12:32,617 INFO L290 TraceCheckUtils]: 86: Hoare triple {4311#(<= main_~i~0 40)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4311#(<= main_~i~0 40)} is VALID [2022-04-27 21:12:32,618 INFO L290 TraceCheckUtils]: 87: Hoare triple {4311#(<= main_~i~0 40)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4312#(<= main_~i~0 41)} is VALID [2022-04-27 21:12:32,618 INFO L290 TraceCheckUtils]: 88: Hoare triple {4312#(<= main_~i~0 41)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4312#(<= main_~i~0 41)} is VALID [2022-04-27 21:12:32,619 INFO L290 TraceCheckUtils]: 89: Hoare triple {4312#(<= main_~i~0 41)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4313#(<= main_~i~0 42)} is VALID [2022-04-27 21:12:32,619 INFO L290 TraceCheckUtils]: 90: Hoare triple {4313#(<= main_~i~0 42)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4313#(<= main_~i~0 42)} is VALID [2022-04-27 21:12:32,620 INFO L290 TraceCheckUtils]: 91: Hoare triple {4313#(<= main_~i~0 42)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4314#(<= main_~i~0 43)} is VALID [2022-04-27 21:12:32,620 INFO L290 TraceCheckUtils]: 92: Hoare triple {4314#(<= main_~i~0 43)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4314#(<= main_~i~0 43)} is VALID [2022-04-27 21:12:32,621 INFO L290 TraceCheckUtils]: 93: Hoare triple {4314#(<= main_~i~0 43)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4315#(<= main_~i~0 44)} is VALID [2022-04-27 21:12:32,621 INFO L290 TraceCheckUtils]: 94: Hoare triple {4315#(<= main_~i~0 44)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4315#(<= main_~i~0 44)} is VALID [2022-04-27 21:12:32,622 INFO L290 TraceCheckUtils]: 95: Hoare triple {4315#(<= main_~i~0 44)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4316#(<= main_~i~0 45)} is VALID [2022-04-27 21:12:32,622 INFO L290 TraceCheckUtils]: 96: Hoare triple {4316#(<= main_~i~0 45)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4316#(<= main_~i~0 45)} is VALID [2022-04-27 21:12:32,623 INFO L290 TraceCheckUtils]: 97: Hoare triple {4316#(<= main_~i~0 45)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4317#(<= main_~i~0 46)} is VALID [2022-04-27 21:12:32,623 INFO L290 TraceCheckUtils]: 98: Hoare triple {4317#(<= main_~i~0 46)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4317#(<= main_~i~0 46)} is VALID [2022-04-27 21:12:32,624 INFO L290 TraceCheckUtils]: 99: Hoare triple {4317#(<= main_~i~0 46)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4318#(<= main_~i~0 47)} is VALID [2022-04-27 21:12:32,624 INFO L290 TraceCheckUtils]: 100: Hoare triple {4318#(<= main_~i~0 47)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4318#(<= main_~i~0 47)} is VALID [2022-04-27 21:12:32,624 INFO L290 TraceCheckUtils]: 101: Hoare triple {4318#(<= main_~i~0 47)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4319#(<= main_~i~0 48)} is VALID [2022-04-27 21:12:32,625 INFO L290 TraceCheckUtils]: 102: Hoare triple {4319#(<= main_~i~0 48)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4319#(<= main_~i~0 48)} is VALID [2022-04-27 21:12:32,625 INFO L290 TraceCheckUtils]: 103: Hoare triple {4319#(<= main_~i~0 48)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4320#(<= main_~i~0 49)} is VALID [2022-04-27 21:12:32,626 INFO L290 TraceCheckUtils]: 104: Hoare triple {4320#(<= main_~i~0 49)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4320#(<= main_~i~0 49)} is VALID [2022-04-27 21:12:32,626 INFO L290 TraceCheckUtils]: 105: Hoare triple {4320#(<= main_~i~0 49)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4321#(<= main_~i~0 50)} is VALID [2022-04-27 21:12:32,627 INFO L290 TraceCheckUtils]: 106: Hoare triple {4321#(<= main_~i~0 50)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4321#(<= main_~i~0 50)} is VALID [2022-04-27 21:12:32,627 INFO L290 TraceCheckUtils]: 107: Hoare triple {4321#(<= main_~i~0 50)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4322#(<= main_~i~0 51)} is VALID [2022-04-27 21:12:32,627 INFO L290 TraceCheckUtils]: 108: Hoare triple {4322#(<= main_~i~0 51)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4322#(<= main_~i~0 51)} is VALID [2022-04-27 21:12:32,628 INFO L290 TraceCheckUtils]: 109: Hoare triple {4322#(<= main_~i~0 51)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4323#(<= main_~i~0 52)} is VALID [2022-04-27 21:12:32,628 INFO L290 TraceCheckUtils]: 110: Hoare triple {4323#(<= main_~i~0 52)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4323#(<= main_~i~0 52)} is VALID [2022-04-27 21:12:32,629 INFO L290 TraceCheckUtils]: 111: Hoare triple {4323#(<= main_~i~0 52)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4324#(<= main_~i~0 53)} is VALID [2022-04-27 21:12:32,629 INFO L290 TraceCheckUtils]: 112: Hoare triple {4324#(<= main_~i~0 53)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4324#(<= main_~i~0 53)} is VALID [2022-04-27 21:12:32,630 INFO L290 TraceCheckUtils]: 113: Hoare triple {4324#(<= main_~i~0 53)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4325#(<= main_~i~0 54)} is VALID [2022-04-27 21:12:32,630 INFO L290 TraceCheckUtils]: 114: Hoare triple {4325#(<= main_~i~0 54)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4325#(<= main_~i~0 54)} is VALID [2022-04-27 21:12:32,630 INFO L290 TraceCheckUtils]: 115: Hoare triple {4325#(<= main_~i~0 54)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4326#(<= main_~i~0 55)} is VALID [2022-04-27 21:12:32,631 INFO L290 TraceCheckUtils]: 116: Hoare triple {4326#(<= main_~i~0 55)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4326#(<= main_~i~0 55)} is VALID [2022-04-27 21:12:32,631 INFO L290 TraceCheckUtils]: 117: Hoare triple {4326#(<= main_~i~0 55)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4327#(<= main_~i~0 56)} is VALID [2022-04-27 21:12:32,632 INFO L290 TraceCheckUtils]: 118: Hoare triple {4327#(<= main_~i~0 56)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4327#(<= main_~i~0 56)} is VALID [2022-04-27 21:12:32,633 INFO L290 TraceCheckUtils]: 119: Hoare triple {4327#(<= main_~i~0 56)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4328#(<= main_~i~0 57)} is VALID [2022-04-27 21:12:32,633 INFO L290 TraceCheckUtils]: 120: Hoare triple {4328#(<= main_~i~0 57)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4328#(<= main_~i~0 57)} is VALID [2022-04-27 21:12:32,634 INFO L290 TraceCheckUtils]: 121: Hoare triple {4328#(<= main_~i~0 57)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4329#(<= main_~i~0 58)} is VALID [2022-04-27 21:12:32,634 INFO L290 TraceCheckUtils]: 122: Hoare triple {4329#(<= main_~i~0 58)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4329#(<= main_~i~0 58)} is VALID [2022-04-27 21:12:32,635 INFO L290 TraceCheckUtils]: 123: Hoare triple {4329#(<= main_~i~0 58)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4330#(<= main_~i~0 59)} is VALID [2022-04-27 21:12:32,635 INFO L290 TraceCheckUtils]: 124: Hoare triple {4330#(<= main_~i~0 59)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4330#(<= main_~i~0 59)} is VALID [2022-04-27 21:12:32,636 INFO L290 TraceCheckUtils]: 125: Hoare triple {4330#(<= main_~i~0 59)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4331#(<= main_~i~0 60)} is VALID [2022-04-27 21:12:32,636 INFO L290 TraceCheckUtils]: 126: Hoare triple {4331#(<= main_~i~0 60)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4331#(<= main_~i~0 60)} is VALID [2022-04-27 21:12:32,636 INFO L290 TraceCheckUtils]: 127: Hoare triple {4331#(<= main_~i~0 60)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4332#(<= main_~i~0 61)} is VALID [2022-04-27 21:12:32,637 INFO L290 TraceCheckUtils]: 128: Hoare triple {4332#(<= main_~i~0 61)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4332#(<= main_~i~0 61)} is VALID [2022-04-27 21:12:32,637 INFO L290 TraceCheckUtils]: 129: Hoare triple {4332#(<= main_~i~0 61)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4333#(<= main_~i~0 62)} is VALID [2022-04-27 21:12:32,638 INFO L290 TraceCheckUtils]: 130: Hoare triple {4333#(<= main_~i~0 62)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4333#(<= main_~i~0 62)} is VALID [2022-04-27 21:12:32,638 INFO L290 TraceCheckUtils]: 131: Hoare triple {4333#(<= main_~i~0 62)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4334#(<= main_~i~0 63)} is VALID [2022-04-27 21:12:32,638 INFO L290 TraceCheckUtils]: 132: Hoare triple {4334#(<= main_~i~0 63)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4334#(<= main_~i~0 63)} is VALID [2022-04-27 21:12:32,639 INFO L290 TraceCheckUtils]: 133: Hoare triple {4334#(<= main_~i~0 63)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4335#(<= main_~i~0 64)} is VALID [2022-04-27 21:12:32,639 INFO L290 TraceCheckUtils]: 134: Hoare triple {4335#(<= main_~i~0 64)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4335#(<= main_~i~0 64)} is VALID [2022-04-27 21:12:32,640 INFO L290 TraceCheckUtils]: 135: Hoare triple {4335#(<= main_~i~0 64)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4336#(<= main_~i~0 65)} is VALID [2022-04-27 21:12:32,640 INFO L290 TraceCheckUtils]: 136: Hoare triple {4336#(<= main_~i~0 65)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4336#(<= main_~i~0 65)} is VALID [2022-04-27 21:12:32,641 INFO L290 TraceCheckUtils]: 137: Hoare triple {4336#(<= main_~i~0 65)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4337#(<= main_~i~0 66)} is VALID [2022-04-27 21:12:32,641 INFO L290 TraceCheckUtils]: 138: Hoare triple {4337#(<= main_~i~0 66)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4337#(<= main_~i~0 66)} is VALID [2022-04-27 21:12:32,642 INFO L290 TraceCheckUtils]: 139: Hoare triple {4337#(<= main_~i~0 66)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4338#(<= main_~i~0 67)} is VALID [2022-04-27 21:12:32,642 INFO L290 TraceCheckUtils]: 140: Hoare triple {4338#(<= main_~i~0 67)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4338#(<= main_~i~0 67)} is VALID [2022-04-27 21:12:32,643 INFO L290 TraceCheckUtils]: 141: Hoare triple {4338#(<= main_~i~0 67)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4339#(<= main_~i~0 68)} is VALID [2022-04-27 21:12:32,643 INFO L290 TraceCheckUtils]: 142: Hoare triple {4339#(<= main_~i~0 68)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4339#(<= main_~i~0 68)} is VALID [2022-04-27 21:12:32,643 INFO L290 TraceCheckUtils]: 143: Hoare triple {4339#(<= main_~i~0 68)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4340#(<= main_~i~0 69)} is VALID [2022-04-27 21:12:32,644 INFO L290 TraceCheckUtils]: 144: Hoare triple {4340#(<= main_~i~0 69)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4340#(<= main_~i~0 69)} is VALID [2022-04-27 21:12:32,644 INFO L290 TraceCheckUtils]: 145: Hoare triple {4340#(<= main_~i~0 69)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4341#(<= main_~i~0 70)} is VALID [2022-04-27 21:12:32,645 INFO L290 TraceCheckUtils]: 146: Hoare triple {4341#(<= main_~i~0 70)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4341#(<= main_~i~0 70)} is VALID [2022-04-27 21:12:32,645 INFO L290 TraceCheckUtils]: 147: Hoare triple {4341#(<= main_~i~0 70)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4342#(<= main_~i~0 71)} is VALID [2022-04-27 21:12:32,646 INFO L290 TraceCheckUtils]: 148: Hoare triple {4342#(<= main_~i~0 71)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4342#(<= main_~i~0 71)} is VALID [2022-04-27 21:12:32,646 INFO L290 TraceCheckUtils]: 149: Hoare triple {4342#(<= main_~i~0 71)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4343#(<= main_~i~0 72)} is VALID [2022-04-27 21:12:32,646 INFO L290 TraceCheckUtils]: 150: Hoare triple {4343#(<= main_~i~0 72)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4343#(<= main_~i~0 72)} is VALID [2022-04-27 21:12:32,647 INFO L290 TraceCheckUtils]: 151: Hoare triple {4343#(<= main_~i~0 72)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4344#(<= main_~i~0 73)} is VALID [2022-04-27 21:12:32,647 INFO L290 TraceCheckUtils]: 152: Hoare triple {4344#(<= main_~i~0 73)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4344#(<= main_~i~0 73)} is VALID [2022-04-27 21:12:32,648 INFO L290 TraceCheckUtils]: 153: Hoare triple {4344#(<= main_~i~0 73)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4345#(<= main_~i~0 74)} is VALID [2022-04-27 21:12:32,648 INFO L290 TraceCheckUtils]: 154: Hoare triple {4345#(<= main_~i~0 74)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4345#(<= main_~i~0 74)} is VALID [2022-04-27 21:12:32,649 INFO L290 TraceCheckUtils]: 155: Hoare triple {4345#(<= main_~i~0 74)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4346#(<= main_~i~0 75)} is VALID [2022-04-27 21:12:32,649 INFO L290 TraceCheckUtils]: 156: Hoare triple {4346#(<= main_~i~0 75)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4346#(<= main_~i~0 75)} is VALID [2022-04-27 21:12:32,650 INFO L290 TraceCheckUtils]: 157: Hoare triple {4346#(<= main_~i~0 75)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4347#(<= main_~i~0 76)} is VALID [2022-04-27 21:12:32,650 INFO L290 TraceCheckUtils]: 158: Hoare triple {4347#(<= main_~i~0 76)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4347#(<= main_~i~0 76)} is VALID [2022-04-27 21:12:32,650 INFO L290 TraceCheckUtils]: 159: Hoare triple {4347#(<= main_~i~0 76)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4348#(<= main_~i~0 77)} is VALID [2022-04-27 21:12:32,651 INFO L290 TraceCheckUtils]: 160: Hoare triple {4348#(<= main_~i~0 77)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4348#(<= main_~i~0 77)} is VALID [2022-04-27 21:12:32,651 INFO L290 TraceCheckUtils]: 161: Hoare triple {4348#(<= main_~i~0 77)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4349#(<= main_~i~0 78)} is VALID [2022-04-27 21:12:32,652 INFO L290 TraceCheckUtils]: 162: Hoare triple {4349#(<= main_~i~0 78)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4349#(<= main_~i~0 78)} is VALID [2022-04-27 21:12:32,652 INFO L290 TraceCheckUtils]: 163: Hoare triple {4349#(<= main_~i~0 78)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4350#(<= main_~i~0 79)} is VALID [2022-04-27 21:12:32,653 INFO L290 TraceCheckUtils]: 164: Hoare triple {4350#(<= main_~i~0 79)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4350#(<= main_~i~0 79)} is VALID [2022-04-27 21:12:32,653 INFO L290 TraceCheckUtils]: 165: Hoare triple {4350#(<= main_~i~0 79)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4351#(<= main_~i~0 80)} is VALID [2022-04-27 21:12:32,653 INFO L290 TraceCheckUtils]: 166: Hoare triple {4351#(<= main_~i~0 80)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4351#(<= main_~i~0 80)} is VALID [2022-04-27 21:12:32,654 INFO L290 TraceCheckUtils]: 167: Hoare triple {4351#(<= main_~i~0 80)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4352#(<= main_~i~0 81)} is VALID [2022-04-27 21:12:32,654 INFO L290 TraceCheckUtils]: 168: Hoare triple {4352#(<= main_~i~0 81)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4352#(<= main_~i~0 81)} is VALID [2022-04-27 21:12:32,655 INFO L290 TraceCheckUtils]: 169: Hoare triple {4352#(<= main_~i~0 81)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4353#(<= main_~i~0 82)} is VALID [2022-04-27 21:12:32,655 INFO L290 TraceCheckUtils]: 170: Hoare triple {4353#(<= main_~i~0 82)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4353#(<= main_~i~0 82)} is VALID [2022-04-27 21:12:32,656 INFO L290 TraceCheckUtils]: 171: Hoare triple {4353#(<= main_~i~0 82)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4354#(<= main_~i~0 83)} is VALID [2022-04-27 21:12:32,656 INFO L290 TraceCheckUtils]: 172: Hoare triple {4354#(<= main_~i~0 83)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4354#(<= main_~i~0 83)} is VALID [2022-04-27 21:12:32,656 INFO L290 TraceCheckUtils]: 173: Hoare triple {4354#(<= main_~i~0 83)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4355#(<= main_~i~0 84)} is VALID [2022-04-27 21:12:32,657 INFO L290 TraceCheckUtils]: 174: Hoare triple {4355#(<= main_~i~0 84)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4355#(<= main_~i~0 84)} is VALID [2022-04-27 21:12:32,657 INFO L290 TraceCheckUtils]: 175: Hoare triple {4355#(<= main_~i~0 84)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4356#(<= main_~i~0 85)} is VALID [2022-04-27 21:12:32,658 INFO L290 TraceCheckUtils]: 176: Hoare triple {4356#(<= main_~i~0 85)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4356#(<= main_~i~0 85)} is VALID [2022-04-27 21:12:32,658 INFO L290 TraceCheckUtils]: 177: Hoare triple {4356#(<= main_~i~0 85)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4357#(<= main_~i~0 86)} is VALID [2022-04-27 21:12:32,659 INFO L290 TraceCheckUtils]: 178: Hoare triple {4357#(<= main_~i~0 86)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4357#(<= main_~i~0 86)} is VALID [2022-04-27 21:12:32,659 INFO L290 TraceCheckUtils]: 179: Hoare triple {4357#(<= main_~i~0 86)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4358#(<= main_~i~0 87)} is VALID [2022-04-27 21:12:32,659 INFO L290 TraceCheckUtils]: 180: Hoare triple {4358#(<= main_~i~0 87)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4358#(<= main_~i~0 87)} is VALID [2022-04-27 21:12:32,660 INFO L290 TraceCheckUtils]: 181: Hoare triple {4358#(<= main_~i~0 87)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4359#(<= main_~i~0 88)} is VALID [2022-04-27 21:12:32,660 INFO L290 TraceCheckUtils]: 182: Hoare triple {4359#(<= main_~i~0 88)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4359#(<= main_~i~0 88)} is VALID [2022-04-27 21:12:32,661 INFO L290 TraceCheckUtils]: 183: Hoare triple {4359#(<= main_~i~0 88)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4360#(<= main_~i~0 89)} is VALID [2022-04-27 21:12:32,661 INFO L290 TraceCheckUtils]: 184: Hoare triple {4360#(<= main_~i~0 89)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4360#(<= main_~i~0 89)} is VALID [2022-04-27 21:12:32,662 INFO L290 TraceCheckUtils]: 185: Hoare triple {4360#(<= main_~i~0 89)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4361#(<= main_~i~0 90)} is VALID [2022-04-27 21:12:32,662 INFO L290 TraceCheckUtils]: 186: Hoare triple {4361#(<= main_~i~0 90)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4361#(<= main_~i~0 90)} is VALID [2022-04-27 21:12:32,662 INFO L290 TraceCheckUtils]: 187: Hoare triple {4361#(<= main_~i~0 90)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4362#(<= main_~i~0 91)} is VALID [2022-04-27 21:12:32,663 INFO L290 TraceCheckUtils]: 188: Hoare triple {4362#(<= main_~i~0 91)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4362#(<= main_~i~0 91)} is VALID [2022-04-27 21:12:32,663 INFO L290 TraceCheckUtils]: 189: Hoare triple {4362#(<= main_~i~0 91)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4363#(<= main_~i~0 92)} is VALID [2022-04-27 21:12:32,663 INFO L290 TraceCheckUtils]: 190: Hoare triple {4363#(<= main_~i~0 92)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4363#(<= main_~i~0 92)} is VALID [2022-04-27 21:12:32,664 INFO L290 TraceCheckUtils]: 191: Hoare triple {4363#(<= main_~i~0 92)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4364#(<= main_~i~0 93)} is VALID [2022-04-27 21:12:32,664 INFO L290 TraceCheckUtils]: 192: Hoare triple {4364#(<= main_~i~0 93)} [50] L16-3-->L16-2: Formula: (and (< v_main_~i~0_4 1024) (= (store |v_#memory_int_3| |v_main_~#A~0.base_5| (store (select |v_#memory_int_3| |v_main_~#A~0.base_5|) (+ (* v_main_~i~0_4 4) |v_main_~#A~0.offset_5|) v_main_~i~0_4)) |v_#memory_int_2|)) InVars {#memory_int=|v_#memory_int_3|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} OutVars{#memory_int=|v_#memory_int_2|, main_~i~0=v_main_~i~0_4, main_~#A~0.offset=|v_main_~#A~0.offset_5|, main_~#A~0.base=|v_main_~#A~0.base_5|} AuxVars[] AssignedVars[#memory_int] {4364#(<= main_~i~0 93)} is VALID [2022-04-27 21:12:32,665 INFO L290 TraceCheckUtils]: 193: Hoare triple {4364#(<= main_~i~0 93)} [52] L16-2-->L16-3: Formula: (= v_main_~i~0_5 (+ v_main_~i~0_6 1)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~i~0=v_main_~i~0_5} AuxVars[] AssignedVars[main_#t~post4, main_~i~0] {4365#(<= main_~i~0 94)} is VALID [2022-04-27 21:12:32,665 INFO L290 TraceCheckUtils]: 194: Hoare triple {4365#(<= main_~i~0 94)} [49] L16-3-->L16-4: Formula: (not (< v_main_~i~0_3 1024)) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3} AuxVars[] AssignedVars[] {4267#false} is VALID [2022-04-27 21:12:32,665 INFO L290 TraceCheckUtils]: 195: Hoare triple {4267#false} [51] L16-4-->L20: Formula: (= |v_main_#t~mem5_1| (select (select |v_#memory_int_1| |v_main_~#A~0.base_1|) (+ 4092 |v_main_~#A~0.offset_1|))) InVars {#memory_int=|v_#memory_int_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} OutVars{#memory_int=|v_#memory_int_1|, main_#t~mem5=|v_main_#t~mem5_1|, main_~#A~0.offset=|v_main_~#A~0.offset_1|, main_~#A~0.base=|v_main_~#A~0.base_1|} AuxVars[] AssignedVars[main_#t~mem5] {4267#false} is VALID [2022-04-27 21:12:32,665 INFO L272 TraceCheckUtils]: 196: Hoare triple {4267#false} [53] L20-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (not (= 1023 |v_main_#t~mem5_4|)) 1 0)) InVars {main_#t~mem5=|v_main_#t~mem5_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_#t~mem5] {4267#false} is VALID [2022-04-27 21:12:32,665 INFO L290 TraceCheckUtils]: 197: Hoare triple {4267#false} [55] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4267#false} is VALID [2022-04-27 21:12:32,665 INFO L290 TraceCheckUtils]: 198: Hoare triple {4267#false} [57] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4267#false} is VALID [2022-04-27 21:12:32,665 INFO L290 TraceCheckUtils]: 199: Hoare triple {4267#false} [59] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4267#false} is VALID [2022-04-27 21:12:32,669 INFO L134 CoverageAnalysis]: Checked inductivity of 8836 backedges. 0 proven. 8836 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:32,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:12:32,669 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [279809146] [2022-04-27 21:12:32,669 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [279809146] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:12:32,669 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [445497944] [2022-04-27 21:12:32,669 INFO L93 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2022-04-27 21:12:32,669 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:12:32,669 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:12:32,670 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:12:32,671 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process