/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loop-acceleration/const_1-2.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 21:20:15,060 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 21:20:15,061 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 21:20:15,096 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 21:20:15,096 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 21:20:15,097 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 21:20:15,098 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 21:20:15,099 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 21:20:15,100 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 21:20:15,101 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 21:20:15,102 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 21:20:15,102 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 21:20:15,103 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 21:20:15,106 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 21:20:15,107 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 21:20:15,110 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 21:20:15,110 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 21:20:15,114 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 21:20:15,119 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 21:20:15,124 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 21:20:15,126 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 21:20:15,127 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 21:20:15,128 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 21:20:15,130 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 21:20:15,131 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 21:20:15,135 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 21:20:15,141 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 21:20:15,142 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 21:20:15,145 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 21:20:15,145 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-27 21:20:15,165 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 21:20:15,166 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 21:20:15,166 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-27 21:20:15,166 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-27 21:20:15,167 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-27 21:20:15,167 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-27 21:20:15,167 INFO L138 SettingsManager]: * Use SBE=true [2022-04-27 21:20:15,168 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 21:20:15,168 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 21:20:15,168 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 21:20:15,168 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 21:20:15,169 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 21:20:15,169 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:20:15,170 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 21:20:15,170 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-27 21:20:15,170 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-27 21:20:15,170 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 21:20:15,170 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-27 21:20:15,170 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-27 21:20:15,170 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-27 21:20:15,171 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-27 21:20:15,171 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 21:20:15,171 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 21:20:15,383 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 21:20:15,404 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 21:20:15,406 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 21:20:15,407 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 21:20:15,408 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 21:20:15,408 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/const_1-2.c [2022-04-27 21:20:15,456 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fd2d33545/f52bf30cd08843e8996122fc4a065728/FLAG15dac052a [2022-04-27 21:20:15,742 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 21:20:15,743 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/const_1-2.c [2022-04-27 21:20:15,746 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fd2d33545/f52bf30cd08843e8996122fc4a065728/FLAG15dac052a [2022-04-27 21:20:16,190 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/fd2d33545/f52bf30cd08843e8996122fc4a065728 [2022-04-27 21:20:16,192 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 21:20:16,193 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 21:20:16,195 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 21:20:16,195 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 21:20:16,199 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 21:20:16,200 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,201 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6b7e5c52 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16, skipping insertion in model container [2022-04-27 21:20:16,201 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,206 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 21:20:16,215 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 21:20:16,359 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/const_1-2.c[321,334] [2022-04-27 21:20:16,373 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:20:16,390 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 21:20:16,399 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/const_1-2.c[321,334] [2022-04-27 21:20:16,402 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:20:16,416 INFO L208 MainTranslator]: Completed translation [2022-04-27 21:20:16,417 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16 WrapperNode [2022-04-27 21:20:16,418 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 21:20:16,419 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 21:20:16,420 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 21:20:16,420 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 21:20:16,427 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,428 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,433 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,433 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,439 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,443 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,446 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,448 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 21:20:16,448 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 21:20:16,449 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 21:20:16,449 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 21:20:16,450 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,455 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:20:16,462 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:16,484 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 21:20:16,501 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 21:20:16,523 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 21:20:16,523 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 21:20:16,524 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 21:20:16,524 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 21:20:16,524 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 21:20:16,524 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 21:20:16,524 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 21:20:16,525 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 21:20:16,525 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 21:20:16,526 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 21:20:16,574 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 21:20:16,575 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 21:20:16,664 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 21:20:16,669 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 21:20:16,669 INFO L299 CfgBuilder]: Removed 1 assume(true) statements. [2022-04-27 21:20:16,671 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:20:16 BoogieIcfgContainer [2022-04-27 21:20:16,671 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 21:20:16,672 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 21:20:16,672 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 21:20:16,673 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 21:20:16,675 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:20:16" (1/1) ... [2022-04-27 21:20:16,676 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-27 21:20:16,688 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:20:16 BasicIcfg [2022-04-27 21:20:16,688 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 21:20:16,689 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 21:20:16,690 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 21:20:16,692 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 21:20:16,692 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 09:20:16" (1/4) ... [2022-04-27 21:20:16,693 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@259d60a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:20:16, skipping insertion in model container [2022-04-27 21:20:16,693 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:16" (2/4) ... [2022-04-27 21:20:16,693 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@259d60a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:20:16, skipping insertion in model container [2022-04-27 21:20:16,693 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:20:16" (3/4) ... [2022-04-27 21:20:16,693 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@259d60a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 09:20:16, skipping insertion in model container [2022-04-27 21:20:16,693 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:20:16" (4/4) ... [2022-04-27 21:20:16,694 INFO L111 eAbstractionObserver]: Analyzing ICFG const_1-2.cqvasr [2022-04-27 21:20:16,704 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-27 21:20:16,704 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 21:20:16,733 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 21:20:16,738 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@1522013e, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@536d7526 [2022-04-27 21:20:16,738 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 21:20:16,744 INFO L276 IsEmpty]: Start isEmpty. Operand has 18 states, 10 states have (on average 1.4) internal successors, (14), 11 states have internal predecessors, (14), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:20:16,748 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-27 21:20:16,748 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:16,749 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:16,749 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:16,752 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:16,753 INFO L85 PathProgramCache]: Analyzing trace with hash -1690616289, now seen corresponding path program 1 times [2022-04-27 21:20:16,759 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:16,759 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135513320] [2022-04-27 21:20:16,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:16,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:16,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:16,856 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:16,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:16,874 INFO L290 TraceCheckUtils]: 0: Hoare triple {26#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {21#true} is VALID [2022-04-27 21:20:16,875 INFO L290 TraceCheckUtils]: 1: Hoare triple {21#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-27 21:20:16,880 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {21#true} {21#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-27 21:20:16,882 INFO L272 TraceCheckUtils]: 0: Hoare triple {21#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {26#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:16,882 INFO L290 TraceCheckUtils]: 1: Hoare triple {26#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {21#true} is VALID [2022-04-27 21:20:16,882 INFO L290 TraceCheckUtils]: 2: Hoare triple {21#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-27 21:20:16,883 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {21#true} {21#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-27 21:20:16,883 INFO L272 TraceCheckUtils]: 4: Hoare triple {21#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {21#true} is VALID [2022-04-27 21:20:16,883 INFO L290 TraceCheckUtils]: 5: Hoare triple {21#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {21#true} is VALID [2022-04-27 21:20:16,892 INFO L290 TraceCheckUtils]: 6: Hoare triple {21#true} [45] L16-2-->L16-3: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {22#false} is VALID [2022-04-27 21:20:16,892 INFO L272 TraceCheckUtils]: 7: Hoare triple {22#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {22#false} is VALID [2022-04-27 21:20:16,892 INFO L290 TraceCheckUtils]: 8: Hoare triple {22#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {22#false} is VALID [2022-04-27 21:20:16,892 INFO L290 TraceCheckUtils]: 9: Hoare triple {22#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {22#false} is VALID [2022-04-27 21:20:16,893 INFO L290 TraceCheckUtils]: 10: Hoare triple {22#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#false} is VALID [2022-04-27 21:20:16,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:16,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:16,894 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135513320] [2022-04-27 21:20:16,894 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135513320] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:20:16,894 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:20:16,894 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 21:20:16,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485874085] [2022-04-27 21:20:16,896 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:20:16,899 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:16,900 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:16,902 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:16,916 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 11 edges. 11 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:16,917 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 21:20:16,917 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:16,931 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 21:20:16,931 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:20:16,933 INFO L87 Difference]: Start difference. First operand has 18 states, 10 states have (on average 1.4) internal successors, (14), 11 states have internal predecessors, (14), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:16,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:16,985 INFO L93 Difference]: Finished difference Result 29 states and 32 transitions. [2022-04-27 21:20:16,985 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 21:20:16,985 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:16,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:16,986 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:16,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 32 transitions. [2022-04-27 21:20:16,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:16,994 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 32 transitions. [2022-04-27 21:20:16,994 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 32 transitions. [2022-04-27 21:20:17,062 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:17,067 INFO L225 Difference]: With dead ends: 29 [2022-04-27 21:20:17,067 INFO L226 Difference]: Without dead ends: 12 [2022-04-27 21:20:17,071 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:20:17,073 INFO L413 NwaCegarLoop]: 17 mSDtfsCounter, 9 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 20 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:17,074 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 20 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:17,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2022-04-27 21:20:17,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2022-04-27 21:20:17,093 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:17,093 INFO L82 GeneralOperation]: Start isEquivalent. First operand 12 states. Second operand has 12 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,094 INFO L74 IsIncluded]: Start isIncluded. First operand 12 states. Second operand has 12 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,094 INFO L87 Difference]: Start difference. First operand 12 states. Second operand has 12 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,096 INFO L93 Difference]: Finished difference Result 12 states and 12 transitions. [2022-04-27 21:20:17,096 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2022-04-27 21:20:17,096 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:17,096 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:17,096 INFO L74 IsIncluded]: Start isIncluded. First operand has 12 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 12 states. [2022-04-27 21:20:17,097 INFO L87 Difference]: Start difference. First operand has 12 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 12 states. [2022-04-27 21:20:17,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,098 INFO L93 Difference]: Finished difference Result 12 states and 12 transitions. [2022-04-27 21:20:17,098 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2022-04-27 21:20:17,099 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:17,099 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:17,099 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:17,099 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:17,099 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 7 states have (on average 1.1428571428571428) internal successors, (8), 7 states have internal predecessors, (8), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,100 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 12 transitions. [2022-04-27 21:20:17,101 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 12 transitions. Word has length 11 [2022-04-27 21:20:17,101 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:17,101 INFO L495 AbstractCegarLoop]: Abstraction has 12 states and 12 transitions. [2022-04-27 21:20:17,102 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,102 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2022-04-27 21:20:17,102 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-27 21:20:17,102 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:17,102 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:17,103 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 21:20:17,103 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:17,103 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:17,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1689692768, now seen corresponding path program 1 times [2022-04-27 21:20:17,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:17,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831897304] [2022-04-27 21:20:17,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:17,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:17,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:17,153 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:17,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:17,161 INFO L290 TraceCheckUtils]: 0: Hoare triple {116#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-27 21:20:17,161 INFO L290 TraceCheckUtils]: 1: Hoare triple {110#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 21:20:17,161 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {110#true} {110#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 21:20:17,162 INFO L272 TraceCheckUtils]: 0: Hoare triple {110#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {116#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:17,162 INFO L290 TraceCheckUtils]: 1: Hoare triple {116#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {110#true} is VALID [2022-04-27 21:20:17,162 INFO L290 TraceCheckUtils]: 2: Hoare triple {110#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 21:20:17,162 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {110#true} {110#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 21:20:17,162 INFO L272 TraceCheckUtils]: 4: Hoare triple {110#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {110#true} is VALID [2022-04-27 21:20:17,163 INFO L290 TraceCheckUtils]: 5: Hoare triple {110#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {115#(= main_~y~0 0)} is VALID [2022-04-27 21:20:17,163 INFO L290 TraceCheckUtils]: 6: Hoare triple {115#(= main_~y~0 0)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 21:20:17,164 INFO L272 TraceCheckUtils]: 7: Hoare triple {111#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {111#false} is VALID [2022-04-27 21:20:17,164 INFO L290 TraceCheckUtils]: 8: Hoare triple {111#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {111#false} is VALID [2022-04-27 21:20:17,164 INFO L290 TraceCheckUtils]: 9: Hoare triple {111#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 21:20:17,164 INFO L290 TraceCheckUtils]: 10: Hoare triple {111#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {111#false} is VALID [2022-04-27 21:20:17,164 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:17,164 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:17,165 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831897304] [2022-04-27 21:20:17,165 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831897304] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:20:17,165 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:20:17,165 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 21:20:17,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [191084630] [2022-04-27 21:20:17,165 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:20:17,166 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:17,166 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:17,166 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,175 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 11 edges. 11 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:17,175 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 21:20:17,175 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:17,176 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 21:20:17,176 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 21:20:17,176 INFO L87 Difference]: Start difference. First operand 12 states and 12 transitions. Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,221 INFO L93 Difference]: Finished difference Result 18 states and 18 transitions. [2022-04-27 21:20:17,221 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 21:20:17,222 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:17,222 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:17,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 18 transitions. [2022-04-27 21:20:17,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 18 transitions. [2022-04-27 21:20:17,232 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 18 transitions. [2022-04-27 21:20:17,250 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:17,252 INFO L225 Difference]: With dead ends: 18 [2022-04-27 21:20:17,253 INFO L226 Difference]: Without dead ends: 13 [2022-04-27 21:20:17,254 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 21:20:17,256 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 6 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 8 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 11 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 8 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:17,257 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 18 Invalid, 11 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 8 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:17,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2022-04-27 21:20:17,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2022-04-27 21:20:17,265 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:17,265 INFO L82 GeneralOperation]: Start isEquivalent. First operand 13 states. Second operand has 13 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,266 INFO L74 IsIncluded]: Start isIncluded. First operand 13 states. Second operand has 13 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,266 INFO L87 Difference]: Start difference. First operand 13 states. Second operand has 13 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,267 INFO L93 Difference]: Finished difference Result 13 states and 13 transitions. [2022-04-27 21:20:17,267 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2022-04-27 21:20:17,267 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:17,267 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:17,267 INFO L74 IsIncluded]: Start isIncluded. First operand has 13 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 13 states. [2022-04-27 21:20:17,267 INFO L87 Difference]: Start difference. First operand has 13 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 13 states. [2022-04-27 21:20:17,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,268 INFO L93 Difference]: Finished difference Result 13 states and 13 transitions. [2022-04-27 21:20:17,268 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2022-04-27 21:20:17,268 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:17,269 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:17,269 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:17,269 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:17,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 8 states have (on average 1.125) internal successors, (9), 8 states have internal predecessors, (9), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2022-04-27 21:20:17,270 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 11 [2022-04-27 21:20:17,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:17,270 INFO L495 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2022-04-27 21:20:17,270 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,270 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2022-04-27 21:20:17,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2022-04-27 21:20:17,270 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:17,271 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:17,271 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 21:20:17,271 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:17,271 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:17,271 INFO L85 PathProgramCache]: Analyzing trace with hash -814146699, now seen corresponding path program 1 times [2022-04-27 21:20:17,272 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:17,272 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280261401] [2022-04-27 21:20:17,272 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:17,272 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:17,295 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:17,355 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:17,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:17,370 INFO L290 TraceCheckUtils]: 0: Hoare triple {203#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {196#true} is VALID [2022-04-27 21:20:17,370 INFO L290 TraceCheckUtils]: 1: Hoare triple {196#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,370 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {196#true} {196#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,371 INFO L272 TraceCheckUtils]: 0: Hoare triple {196#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {203#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:17,371 INFO L290 TraceCheckUtils]: 1: Hoare triple {203#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {196#true} is VALID [2022-04-27 21:20:17,371 INFO L290 TraceCheckUtils]: 2: Hoare triple {196#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,372 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {196#true} {196#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,372 INFO L272 TraceCheckUtils]: 4: Hoare triple {196#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,372 INFO L290 TraceCheckUtils]: 5: Hoare triple {196#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {201#(= main_~y~0 0)} is VALID [2022-04-27 21:20:17,373 INFO L290 TraceCheckUtils]: 6: Hoare triple {201#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {202#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:17,373 INFO L290 TraceCheckUtils]: 7: Hoare triple {202#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 1))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,373 INFO L272 TraceCheckUtils]: 8: Hoare triple {197#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {197#false} is VALID [2022-04-27 21:20:17,374 INFO L290 TraceCheckUtils]: 9: Hoare triple {197#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {197#false} is VALID [2022-04-27 21:20:17,374 INFO L290 TraceCheckUtils]: 10: Hoare triple {197#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,374 INFO L290 TraceCheckUtils]: 11: Hoare triple {197#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,374 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:17,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:17,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280261401] [2022-04-27 21:20:17,375 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280261401] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:17,375 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1753949785] [2022-04-27 21:20:17,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:17,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:17,375 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:17,376 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:17,389 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 21:20:17,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:17,423 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 21:20:17,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:17,430 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:17,482 INFO L272 TraceCheckUtils]: 0: Hoare triple {196#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,484 INFO L290 TraceCheckUtils]: 1: Hoare triple {196#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {196#true} is VALID [2022-04-27 21:20:17,484 INFO L290 TraceCheckUtils]: 2: Hoare triple {196#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,484 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {196#true} {196#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,484 INFO L272 TraceCheckUtils]: 4: Hoare triple {196#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,485 INFO L290 TraceCheckUtils]: 5: Hoare triple {196#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {201#(= main_~y~0 0)} is VALID [2022-04-27 21:20:17,488 INFO L290 TraceCheckUtils]: 6: Hoare triple {201#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {225#(= main_~y~0 1)} is VALID [2022-04-27 21:20:17,489 INFO L290 TraceCheckUtils]: 7: Hoare triple {225#(= main_~y~0 1)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,489 INFO L272 TraceCheckUtils]: 8: Hoare triple {197#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {197#false} is VALID [2022-04-27 21:20:17,490 INFO L290 TraceCheckUtils]: 9: Hoare triple {197#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {197#false} is VALID [2022-04-27 21:20:17,490 INFO L290 TraceCheckUtils]: 10: Hoare triple {197#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,490 INFO L290 TraceCheckUtils]: 11: Hoare triple {197#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,490 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:17,490 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:17,570 INFO L290 TraceCheckUtils]: 11: Hoare triple {197#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,571 INFO L290 TraceCheckUtils]: 10: Hoare triple {197#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,571 INFO L290 TraceCheckUtils]: 9: Hoare triple {197#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {197#false} is VALID [2022-04-27 21:20:17,573 INFO L272 TraceCheckUtils]: 8: Hoare triple {197#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {197#false} is VALID [2022-04-27 21:20:17,574 INFO L290 TraceCheckUtils]: 7: Hoare triple {253#(< (mod main_~y~0 4294967296) 1024)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {197#false} is VALID [2022-04-27 21:20:17,575 INFO L290 TraceCheckUtils]: 6: Hoare triple {257#(< (mod (+ main_~y~0 1) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {253#(< (mod main_~y~0 4294967296) 1024)} is VALID [2022-04-27 21:20:17,576 INFO L290 TraceCheckUtils]: 5: Hoare triple {196#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {257#(< (mod (+ main_~y~0 1) 4294967296) 1024)} is VALID [2022-04-27 21:20:17,576 INFO L272 TraceCheckUtils]: 4: Hoare triple {196#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,576 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {196#true} {196#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,576 INFO L290 TraceCheckUtils]: 2: Hoare triple {196#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,576 INFO L290 TraceCheckUtils]: 1: Hoare triple {196#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {196#true} is VALID [2022-04-27 21:20:17,576 INFO L272 TraceCheckUtils]: 0: Hoare triple {196#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {196#true} is VALID [2022-04-27 21:20:17,577 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:17,580 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1753949785] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:17,580 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:17,580 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-27 21:20:17,581 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007921962] [2022-04-27 21:20:17,581 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:17,582 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 21:20:17,583 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:17,583 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,598 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 19 edges. 19 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:17,598 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 21:20:17,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:17,599 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 21:20:17,600 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2022-04-27 21:20:17,601 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,700 INFO L93 Difference]: Finished difference Result 21 states and 23 transitions. [2022-04-27 21:20:17,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:20:17,701 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 12 [2022-04-27 21:20:17,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:17,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 23 transitions. [2022-04-27 21:20:17,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 23 transitions. [2022-04-27 21:20:17,712 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 23 transitions. [2022-04-27 21:20:17,730 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:17,731 INFO L225 Difference]: With dead ends: 21 [2022-04-27 21:20:17,731 INFO L226 Difference]: Without dead ends: 16 [2022-04-27 21:20:17,731 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-04-27 21:20:17,734 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 6 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 20 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 23 SdHoareTripleChecker+Invalid, 30 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 20 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:17,735 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 23 Invalid, 30 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 20 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:17,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2022-04-27 21:20:17,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2022-04-27 21:20:17,743 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:17,744 INFO L82 GeneralOperation]: Start isEquivalent. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,744 INFO L74 IsIncluded]: Start isIncluded. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,745 INFO L87 Difference]: Start difference. First operand 16 states. Second operand has 16 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,746 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 21:20:17,746 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 21:20:17,746 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:17,746 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:17,747 INFO L74 IsIncluded]: Start isIncluded. First operand has 16 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 21:20:17,748 INFO L87 Difference]: Start difference. First operand has 16 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 16 states. [2022-04-27 21:20:17,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:17,750 INFO L93 Difference]: Finished difference Result 16 states and 16 transitions. [2022-04-27 21:20:17,750 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 21:20:17,750 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:17,750 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:17,750 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:17,750 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:17,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 11 states have (on average 1.0909090909090908) internal successors, (12), 11 states have internal predecessors, (12), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2022-04-27 21:20:17,752 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 12 [2022-04-27 21:20:17,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:17,753 INFO L495 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2022-04-27 21:20:17,754 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 1.75) internal successors, (14), 7 states have internal predecessors, (14), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:17,754 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2022-04-27 21:20:17,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 21:20:17,755 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:17,755 INFO L195 NwaCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:17,775 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:17,966 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:17,966 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:17,967 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:17,967 INFO L85 PathProgramCache]: Analyzing trace with hash 200712928, now seen corresponding path program 2 times [2022-04-27 21:20:17,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:17,967 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [504049162] [2022-04-27 21:20:17,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:17,968 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:18,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:18,120 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:18,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:18,135 INFO L290 TraceCheckUtils]: 0: Hoare triple {389#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:20:18,136 INFO L290 TraceCheckUtils]: 1: Hoare triple {379#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,136 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {379#true} {379#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,137 INFO L272 TraceCheckUtils]: 0: Hoare triple {379#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {389#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:18,137 INFO L290 TraceCheckUtils]: 1: Hoare triple {389#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:20:18,137 INFO L290 TraceCheckUtils]: 2: Hoare triple {379#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,137 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {379#true} {379#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,137 INFO L272 TraceCheckUtils]: 4: Hoare triple {379#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,138 INFO L290 TraceCheckUtils]: 5: Hoare triple {379#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {384#(= main_~y~0 0)} is VALID [2022-04-27 21:20:18,138 INFO L290 TraceCheckUtils]: 6: Hoare triple {384#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {385#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:18,139 INFO L290 TraceCheckUtils]: 7: Hoare triple {385#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {386#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:20:18,139 INFO L290 TraceCheckUtils]: 8: Hoare triple {386#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {387#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:20:18,140 INFO L290 TraceCheckUtils]: 9: Hoare triple {387#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {388#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 4))} is VALID [2022-04-27 21:20:18,141 INFO L290 TraceCheckUtils]: 10: Hoare triple {388#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 4))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,141 INFO L272 TraceCheckUtils]: 11: Hoare triple {380#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {380#false} is VALID [2022-04-27 21:20:18,141 INFO L290 TraceCheckUtils]: 12: Hoare triple {380#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#false} is VALID [2022-04-27 21:20:18,141 INFO L290 TraceCheckUtils]: 13: Hoare triple {380#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,142 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,142 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:18,142 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:18,142 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [504049162] [2022-04-27 21:20:18,142 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [504049162] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:18,142 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1294809976] [2022-04-27 21:20:18,142 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:20:18,142 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:18,143 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:18,143 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:18,161 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 21:20:18,196 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:20:18,197 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:18,199 INFO L263 TraceCheckSpWp]: Trace formula consists of 73 conjuncts, 11 conjunts are in the unsatisfiable core [2022-04-27 21:20:18,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:18,205 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:18,442 INFO L272 TraceCheckUtils]: 0: Hoare triple {379#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,443 INFO L290 TraceCheckUtils]: 1: Hoare triple {379#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:20:18,444 INFO L290 TraceCheckUtils]: 2: Hoare triple {379#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,444 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {379#true} {379#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,444 INFO L272 TraceCheckUtils]: 4: Hoare triple {379#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,445 INFO L290 TraceCheckUtils]: 5: Hoare triple {379#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {384#(= main_~y~0 0)} is VALID [2022-04-27 21:20:18,445 INFO L290 TraceCheckUtils]: 6: Hoare triple {384#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {385#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:18,446 INFO L290 TraceCheckUtils]: 7: Hoare triple {385#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {386#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:20:18,446 INFO L290 TraceCheckUtils]: 8: Hoare triple {386#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {387#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:20:18,448 INFO L290 TraceCheckUtils]: 9: Hoare triple {387#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {420#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:20:18,448 INFO L290 TraceCheckUtils]: 10: Hoare triple {420#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,449 INFO L272 TraceCheckUtils]: 11: Hoare triple {380#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {380#false} is VALID [2022-04-27 21:20:18,449 INFO L290 TraceCheckUtils]: 12: Hoare triple {380#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#false} is VALID [2022-04-27 21:20:18,449 INFO L290 TraceCheckUtils]: 13: Hoare triple {380#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,449 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,449 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:18,449 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:18,582 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,583 INFO L290 TraceCheckUtils]: 13: Hoare triple {380#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,583 INFO L290 TraceCheckUtils]: 12: Hoare triple {380#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#false} is VALID [2022-04-27 21:20:18,585 INFO L272 TraceCheckUtils]: 11: Hoare triple {380#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {380#false} is VALID [2022-04-27 21:20:18,586 INFO L290 TraceCheckUtils]: 10: Hoare triple {448#(< (mod main_~y~0 4294967296) 1024)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:20:18,587 INFO L290 TraceCheckUtils]: 9: Hoare triple {452#(< (mod (+ main_~y~0 1) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {448#(< (mod main_~y~0 4294967296) 1024)} is VALID [2022-04-27 21:20:18,589 INFO L290 TraceCheckUtils]: 8: Hoare triple {456#(< (mod (+ main_~y~0 2) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {452#(< (mod (+ main_~y~0 1) 4294967296) 1024)} is VALID [2022-04-27 21:20:18,589 INFO L290 TraceCheckUtils]: 7: Hoare triple {460#(< (mod (+ main_~y~0 3) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {456#(< (mod (+ main_~y~0 2) 4294967296) 1024)} is VALID [2022-04-27 21:20:18,590 INFO L290 TraceCheckUtils]: 6: Hoare triple {464#(< (mod (+ main_~y~0 4) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {460#(< (mod (+ main_~y~0 3) 4294967296) 1024)} is VALID [2022-04-27 21:20:18,590 INFO L290 TraceCheckUtils]: 5: Hoare triple {379#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {464#(< (mod (+ main_~y~0 4) 4294967296) 1024)} is VALID [2022-04-27 21:20:18,592 INFO L272 TraceCheckUtils]: 4: Hoare triple {379#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,592 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {379#true} {379#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,592 INFO L290 TraceCheckUtils]: 2: Hoare triple {379#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,592 INFO L290 TraceCheckUtils]: 1: Hoare triple {379#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:20:18,593 INFO L272 TraceCheckUtils]: 0: Hoare triple {379#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:20:18,593 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:18,593 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1294809976] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:18,595 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:18,595 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7] total 14 [2022-04-27 21:20:18,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1799241849] [2022-04-27 21:20:18,597 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:18,598 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:20:18,599 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:18,599 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:18,614 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:18,615 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 21:20:18,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:18,616 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 21:20:18,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2022-04-27 21:20:18,616 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:19,022 INFO L93 Difference]: Finished difference Result 27 states and 32 transitions. [2022-04-27 21:20:19,022 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 21:20:19,023 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:20:19,023 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:19,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 32 transitions. [2022-04-27 21:20:19,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 32 transitions. [2022-04-27 21:20:19,025 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 32 transitions. [2022-04-27 21:20:19,070 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 32 edges. 32 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:19,071 INFO L225 Difference]: With dead ends: 27 [2022-04-27 21:20:19,071 INFO L226 Difference]: Without dead ends: 22 [2022-04-27 21:20:19,071 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 25 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=175, Invalid=377, Unknown=0, NotChecked=0, Total=552 [2022-04-27 21:20:19,072 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 6 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 62 mSolverCounterSat, 25 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 38 SdHoareTripleChecker+Invalid, 87 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 25 IncrementalHoareTripleChecker+Valid, 62 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:19,072 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 38 Invalid, 87 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [25 Valid, 62 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:20:19,072 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2022-04-27 21:20:19,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2022-04-27 21:20:19,085 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:19,085 INFO L82 GeneralOperation]: Start isEquivalent. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,085 INFO L74 IsIncluded]: Start isIncluded. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,085 INFO L87 Difference]: Start difference. First operand 22 states. Second operand has 22 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:19,087 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2022-04-27 21:20:19,087 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2022-04-27 21:20:19,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:19,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:19,087 INFO L74 IsIncluded]: Start isIncluded. First operand has 22 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-27 21:20:19,087 INFO L87 Difference]: Start difference. First operand has 22 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 22 states. [2022-04-27 21:20:19,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:19,088 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2022-04-27 21:20:19,088 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2022-04-27 21:20:19,088 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:19,088 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:19,088 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:19,088 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:19,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 17 states have (on average 1.0588235294117647) internal successors, (18), 17 states have internal predecessors, (18), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2022-04-27 21:20:19,089 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 15 [2022-04-27 21:20:19,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:19,089 INFO L495 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2022-04-27 21:20:19,090 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 1.4285714285714286) internal successors, (20), 13 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:19,090 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2022-04-27 21:20:19,090 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-04-27 21:20:19,090 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:19,090 INFO L195 NwaCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:19,109 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:19,303 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 21:20:19,304 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:19,304 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:19,304 INFO L85 PathProgramCache]: Analyzing trace with hash 270494400, now seen corresponding path program 3 times [2022-04-27 21:20:19,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:19,304 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1795777887] [2022-04-27 21:20:19,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:19,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:19,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:19,484 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:19,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:19,501 INFO L290 TraceCheckUtils]: 0: Hoare triple {650#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {634#true} is VALID [2022-04-27 21:20:19,501 INFO L290 TraceCheckUtils]: 1: Hoare triple {634#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,502 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {634#true} {634#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,502 INFO L272 TraceCheckUtils]: 0: Hoare triple {634#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {650#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:19,503 INFO L290 TraceCheckUtils]: 1: Hoare triple {650#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {634#true} is VALID [2022-04-27 21:20:19,503 INFO L290 TraceCheckUtils]: 2: Hoare triple {634#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,503 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {634#true} {634#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,503 INFO L272 TraceCheckUtils]: 4: Hoare triple {634#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,503 INFO L290 TraceCheckUtils]: 5: Hoare triple {634#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {639#(= main_~y~0 0)} is VALID [2022-04-27 21:20:19,504 INFO L290 TraceCheckUtils]: 6: Hoare triple {639#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {640#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:19,505 INFO L290 TraceCheckUtils]: 7: Hoare triple {640#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {641#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:20:19,505 INFO L290 TraceCheckUtils]: 8: Hoare triple {641#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {642#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:20:19,506 INFO L290 TraceCheckUtils]: 9: Hoare triple {642#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {643#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:20:19,516 INFO L290 TraceCheckUtils]: 10: Hoare triple {643#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {644#(and (<= 5 main_~y~0) (<= main_~y~0 5))} is VALID [2022-04-27 21:20:19,517 INFO L290 TraceCheckUtils]: 11: Hoare triple {644#(and (<= 5 main_~y~0) (<= main_~y~0 5))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {645#(and (<= main_~y~0 6) (<= 6 main_~y~0))} is VALID [2022-04-27 21:20:19,519 INFO L290 TraceCheckUtils]: 12: Hoare triple {645#(and (<= main_~y~0 6) (<= 6 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {646#(and (<= 7 main_~y~0) (<= main_~y~0 7))} is VALID [2022-04-27 21:20:19,520 INFO L290 TraceCheckUtils]: 13: Hoare triple {646#(and (<= 7 main_~y~0) (<= main_~y~0 7))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {647#(and (<= main_~y~0 8) (<= 8 main_~y~0))} is VALID [2022-04-27 21:20:19,520 INFO L290 TraceCheckUtils]: 14: Hoare triple {647#(and (<= main_~y~0 8) (<= 8 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {648#(and (<= 9 main_~y~0) (<= main_~y~0 9))} is VALID [2022-04-27 21:20:19,521 INFO L290 TraceCheckUtils]: 15: Hoare triple {648#(and (<= 9 main_~y~0) (<= main_~y~0 9))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {649#(and (<= main_~y~0 10) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:20:19,521 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#(and (<= main_~y~0 10) (not (<= (+ (div main_~y~0 4294967296) 1) 0)))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:19,522 INFO L272 TraceCheckUtils]: 17: Hoare triple {635#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {635#false} is VALID [2022-04-27 21:20:19,522 INFO L290 TraceCheckUtils]: 18: Hoare triple {635#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {635#false} is VALID [2022-04-27 21:20:19,522 INFO L290 TraceCheckUtils]: 19: Hoare triple {635#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:19,522 INFO L290 TraceCheckUtils]: 20: Hoare triple {635#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:19,525 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:19,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:19,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1795777887] [2022-04-27 21:20:19,526 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1795777887] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:19,526 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [562735923] [2022-04-27 21:20:19,526 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 21:20:19,526 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:19,526 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:19,540 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:19,541 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 21:20:19,583 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2022-04-27 21:20:19,584 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:19,585 INFO L263 TraceCheckSpWp]: Trace formula consists of 103 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-27 21:20:19,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:19,594 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:19,848 INFO L272 TraceCheckUtils]: 0: Hoare triple {634#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,849 INFO L290 TraceCheckUtils]: 1: Hoare triple {634#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {634#true} is VALID [2022-04-27 21:20:19,849 INFO L290 TraceCheckUtils]: 2: Hoare triple {634#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,849 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {634#true} {634#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,849 INFO L272 TraceCheckUtils]: 4: Hoare triple {634#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:19,849 INFO L290 TraceCheckUtils]: 5: Hoare triple {634#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {639#(= main_~y~0 0)} is VALID [2022-04-27 21:20:19,850 INFO L290 TraceCheckUtils]: 6: Hoare triple {639#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {640#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:19,850 INFO L290 TraceCheckUtils]: 7: Hoare triple {640#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {641#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:20:19,851 INFO L290 TraceCheckUtils]: 8: Hoare triple {641#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {642#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:20:19,851 INFO L290 TraceCheckUtils]: 9: Hoare triple {642#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {643#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:20:19,852 INFO L290 TraceCheckUtils]: 10: Hoare triple {643#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {644#(and (<= 5 main_~y~0) (<= main_~y~0 5))} is VALID [2022-04-27 21:20:19,852 INFO L290 TraceCheckUtils]: 11: Hoare triple {644#(and (<= 5 main_~y~0) (<= main_~y~0 5))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {645#(and (<= main_~y~0 6) (<= 6 main_~y~0))} is VALID [2022-04-27 21:20:19,853 INFO L290 TraceCheckUtils]: 12: Hoare triple {645#(and (<= main_~y~0 6) (<= 6 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {646#(and (<= 7 main_~y~0) (<= main_~y~0 7))} is VALID [2022-04-27 21:20:19,853 INFO L290 TraceCheckUtils]: 13: Hoare triple {646#(and (<= 7 main_~y~0) (<= main_~y~0 7))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {647#(and (<= main_~y~0 8) (<= 8 main_~y~0))} is VALID [2022-04-27 21:20:19,854 INFO L290 TraceCheckUtils]: 14: Hoare triple {647#(and (<= main_~y~0 8) (<= 8 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {648#(and (<= 9 main_~y~0) (<= main_~y~0 9))} is VALID [2022-04-27 21:20:19,854 INFO L290 TraceCheckUtils]: 15: Hoare triple {648#(and (<= 9 main_~y~0) (<= main_~y~0 9))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {699#(and (<= main_~y~0 10) (<= 10 main_~y~0))} is VALID [2022-04-27 21:20:19,855 INFO L290 TraceCheckUtils]: 16: Hoare triple {699#(and (<= main_~y~0 10) (<= 10 main_~y~0))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:19,855 INFO L272 TraceCheckUtils]: 17: Hoare triple {635#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {635#false} is VALID [2022-04-27 21:20:19,855 INFO L290 TraceCheckUtils]: 18: Hoare triple {635#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {635#false} is VALID [2022-04-27 21:20:19,855 INFO L290 TraceCheckUtils]: 19: Hoare triple {635#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:19,855 INFO L290 TraceCheckUtils]: 20: Hoare triple {635#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:19,855 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:19,856 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:20,137 INFO L290 TraceCheckUtils]: 20: Hoare triple {635#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:20,137 INFO L290 TraceCheckUtils]: 19: Hoare triple {635#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:20,137 INFO L290 TraceCheckUtils]: 18: Hoare triple {635#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {635#false} is VALID [2022-04-27 21:20:20,137 INFO L272 TraceCheckUtils]: 17: Hoare triple {635#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {635#false} is VALID [2022-04-27 21:20:20,138 INFO L290 TraceCheckUtils]: 16: Hoare triple {727#(< (mod main_~y~0 4294967296) 1024)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {635#false} is VALID [2022-04-27 21:20:20,138 INFO L290 TraceCheckUtils]: 15: Hoare triple {731#(< (mod (+ main_~y~0 1) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {727#(< (mod main_~y~0 4294967296) 1024)} is VALID [2022-04-27 21:20:20,139 INFO L290 TraceCheckUtils]: 14: Hoare triple {735#(< (mod (+ main_~y~0 2) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {731#(< (mod (+ main_~y~0 1) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,140 INFO L290 TraceCheckUtils]: 13: Hoare triple {739#(< (mod (+ main_~y~0 3) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {735#(< (mod (+ main_~y~0 2) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,140 INFO L290 TraceCheckUtils]: 12: Hoare triple {743#(< (mod (+ main_~y~0 4) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {739#(< (mod (+ main_~y~0 3) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,146 INFO L290 TraceCheckUtils]: 11: Hoare triple {747#(< (mod (+ 5 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {743#(< (mod (+ main_~y~0 4) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,147 INFO L290 TraceCheckUtils]: 10: Hoare triple {751#(< (mod (+ main_~y~0 6) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {747#(< (mod (+ 5 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,148 INFO L290 TraceCheckUtils]: 9: Hoare triple {755#(< (mod (+ 7 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {751#(< (mod (+ main_~y~0 6) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,151 INFO L290 TraceCheckUtils]: 8: Hoare triple {759#(< (mod (+ main_~y~0 8) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {755#(< (mod (+ 7 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,163 INFO L290 TraceCheckUtils]: 7: Hoare triple {763#(< (mod (+ main_~y~0 9) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {759#(< (mod (+ main_~y~0 8) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,164 INFO L290 TraceCheckUtils]: 6: Hoare triple {767#(< (mod (+ main_~y~0 10) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {763#(< (mod (+ main_~y~0 9) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,164 INFO L290 TraceCheckUtils]: 5: Hoare triple {634#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {767#(< (mod (+ main_~y~0 10) 4294967296) 1024)} is VALID [2022-04-27 21:20:20,164 INFO L272 TraceCheckUtils]: 4: Hoare triple {634#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:20,164 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {634#true} {634#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:20,164 INFO L290 TraceCheckUtils]: 2: Hoare triple {634#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:20,165 INFO L290 TraceCheckUtils]: 1: Hoare triple {634#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {634#true} is VALID [2022-04-27 21:20:20,165 INFO L272 TraceCheckUtils]: 0: Hoare triple {634#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {634#true} is VALID [2022-04-27 21:20:20,165 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:20,165 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [562735923] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:20,165 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:20,165 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13] total 26 [2022-04-27 21:20:20,165 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1498119893] [2022-04-27 21:20:20,165 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:20,166 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 21 [2022-04-27 21:20:20,166 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:20,166 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:20,189 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:20,190 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 26 states [2022-04-27 21:20:20,190 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:20,190 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2022-04-27 21:20:20,190 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=458, Unknown=0, NotChecked=0, Total=650 [2022-04-27 21:20:20,191 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:23,986 INFO L93 Difference]: Finished difference Result 39 states and 50 transitions. [2022-04-27 21:20:23,986 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2022-04-27 21:20:23,987 INFO L78 Accepts]: Start accepts. Automaton has has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 21 [2022-04-27 21:20:23,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:23,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 50 transitions. [2022-04-27 21:20:23,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,989 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 50 transitions. [2022-04-27 21:20:23,989 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 25 states and 50 transitions. [2022-04-27 21:20:24,052 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:24,053 INFO L225 Difference]: With dead ends: 39 [2022-04-27 21:20:24,053 INFO L226 Difference]: Without dead ends: 34 [2022-04-27 21:20:24,054 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 31 SyntacticMatches, 1 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=643, Invalid=1613, Unknown=0, NotChecked=0, Total=2256 [2022-04-27 21:20:24,055 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 6 mSDsluCounter, 62 mSDsCounter, 0 mSdLazyCounter, 194 mSolverCounterSat, 36 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 73 SdHoareTripleChecker+Invalid, 230 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 36 IncrementalHoareTripleChecker+Valid, 194 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:24,055 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 73 Invalid, 230 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [36 Valid, 194 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 21:20:24,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2022-04-27 21:20:24,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2022-04-27 21:20:24,083 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:24,083 INFO L82 GeneralOperation]: Start isEquivalent. First operand 34 states. Second operand has 34 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,084 INFO L74 IsIncluded]: Start isIncluded. First operand 34 states. Second operand has 34 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,084 INFO L87 Difference]: Start difference. First operand 34 states. Second operand has 34 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:24,085 INFO L93 Difference]: Finished difference Result 34 states and 34 transitions. [2022-04-27 21:20:24,085 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 34 transitions. [2022-04-27 21:20:24,085 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:24,085 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:24,085 INFO L74 IsIncluded]: Start isIncluded. First operand has 34 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 34 states. [2022-04-27 21:20:24,085 INFO L87 Difference]: Start difference. First operand has 34 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 34 states. [2022-04-27 21:20:24,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:24,086 INFO L93 Difference]: Finished difference Result 34 states and 34 transitions. [2022-04-27 21:20:24,086 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 34 transitions. [2022-04-27 21:20:24,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:24,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:24,087 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:24,087 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:24,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34 states, 29 states have (on average 1.0344827586206897) internal successors, (30), 29 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 34 transitions. [2022-04-27 21:20:24,093 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 34 transitions. Word has length 21 [2022-04-27 21:20:24,093 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:24,093 INFO L495 AbstractCegarLoop]: Abstraction has 34 states and 34 transitions. [2022-04-27 21:20:24,093 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,093 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 34 transitions. [2022-04-27 21:20:24,095 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-27 21:20:24,096 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:24,096 INFO L195 NwaCegarLoop]: trace histogram [22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:24,127 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:24,310 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:24,310 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:24,311 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:24,311 INFO L85 PathProgramCache]: Analyzing trace with hash 749126272, now seen corresponding path program 4 times [2022-04-27 21:20:24,311 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:24,311 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63580762] [2022-04-27 21:20:24,311 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:24,311 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:24,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:24,756 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:24,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:24,773 INFO L290 TraceCheckUtils]: 0: Hoare triple {1061#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 21:20:24,773 INFO L290 TraceCheckUtils]: 1: Hoare triple {1033#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:24,774 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1033#true} {1033#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:24,774 INFO L272 TraceCheckUtils]: 0: Hoare triple {1033#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1061#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:24,774 INFO L290 TraceCheckUtils]: 1: Hoare triple {1061#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 21:20:24,774 INFO L290 TraceCheckUtils]: 2: Hoare triple {1033#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:24,774 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1033#true} {1033#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:24,774 INFO L272 TraceCheckUtils]: 4: Hoare triple {1033#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:24,775 INFO L290 TraceCheckUtils]: 5: Hoare triple {1033#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {1038#(= main_~y~0 0)} is VALID [2022-04-27 21:20:24,775 INFO L290 TraceCheckUtils]: 6: Hoare triple {1038#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1039#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:24,776 INFO L290 TraceCheckUtils]: 7: Hoare triple {1039#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1040#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:20:24,776 INFO L290 TraceCheckUtils]: 8: Hoare triple {1040#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1041#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:20:24,777 INFO L290 TraceCheckUtils]: 9: Hoare triple {1041#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1042#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:20:24,778 INFO L290 TraceCheckUtils]: 10: Hoare triple {1042#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1043#(and (<= 5 main_~y~0) (<= main_~y~0 5))} is VALID [2022-04-27 21:20:24,778 INFO L290 TraceCheckUtils]: 11: Hoare triple {1043#(and (<= 5 main_~y~0) (<= main_~y~0 5))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1044#(and (<= main_~y~0 6) (<= 6 main_~y~0))} is VALID [2022-04-27 21:20:24,779 INFO L290 TraceCheckUtils]: 12: Hoare triple {1044#(and (<= main_~y~0 6) (<= 6 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1045#(and (<= 7 main_~y~0) (<= main_~y~0 7))} is VALID [2022-04-27 21:20:24,779 INFO L290 TraceCheckUtils]: 13: Hoare triple {1045#(and (<= 7 main_~y~0) (<= main_~y~0 7))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1046#(and (<= main_~y~0 8) (<= 8 main_~y~0))} is VALID [2022-04-27 21:20:24,780 INFO L290 TraceCheckUtils]: 14: Hoare triple {1046#(and (<= main_~y~0 8) (<= 8 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1047#(and (<= 9 main_~y~0) (<= main_~y~0 9))} is VALID [2022-04-27 21:20:24,780 INFO L290 TraceCheckUtils]: 15: Hoare triple {1047#(and (<= 9 main_~y~0) (<= main_~y~0 9))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1048#(and (<= main_~y~0 10) (<= 10 main_~y~0))} is VALID [2022-04-27 21:20:24,781 INFO L290 TraceCheckUtils]: 16: Hoare triple {1048#(and (<= main_~y~0 10) (<= 10 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1049#(and (<= main_~y~0 11) (<= 11 main_~y~0))} is VALID [2022-04-27 21:20:24,781 INFO L290 TraceCheckUtils]: 17: Hoare triple {1049#(and (<= main_~y~0 11) (<= 11 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1050#(and (<= 12 main_~y~0) (<= main_~y~0 12))} is VALID [2022-04-27 21:20:24,782 INFO L290 TraceCheckUtils]: 18: Hoare triple {1050#(and (<= 12 main_~y~0) (<= main_~y~0 12))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1051#(and (<= main_~y~0 13) (<= 13 main_~y~0))} is VALID [2022-04-27 21:20:24,782 INFO L290 TraceCheckUtils]: 19: Hoare triple {1051#(and (<= main_~y~0 13) (<= 13 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1052#(and (<= 14 main_~y~0) (<= main_~y~0 14))} is VALID [2022-04-27 21:20:24,783 INFO L290 TraceCheckUtils]: 20: Hoare triple {1052#(and (<= 14 main_~y~0) (<= main_~y~0 14))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1053#(and (<= main_~y~0 15) (<= 15 main_~y~0))} is VALID [2022-04-27 21:20:24,784 INFO L290 TraceCheckUtils]: 21: Hoare triple {1053#(and (<= main_~y~0 15) (<= 15 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1054#(and (<= 16 main_~y~0) (<= main_~y~0 16))} is VALID [2022-04-27 21:20:24,784 INFO L290 TraceCheckUtils]: 22: Hoare triple {1054#(and (<= 16 main_~y~0) (<= main_~y~0 16))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1055#(and (<= main_~y~0 17) (<= 17 main_~y~0))} is VALID [2022-04-27 21:20:24,785 INFO L290 TraceCheckUtils]: 23: Hoare triple {1055#(and (<= main_~y~0 17) (<= 17 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1056#(and (<= 18 main_~y~0) (<= main_~y~0 18))} is VALID [2022-04-27 21:20:24,785 INFO L290 TraceCheckUtils]: 24: Hoare triple {1056#(and (<= 18 main_~y~0) (<= main_~y~0 18))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1057#(and (<= 19 main_~y~0) (<= main_~y~0 19))} is VALID [2022-04-27 21:20:24,786 INFO L290 TraceCheckUtils]: 25: Hoare triple {1057#(and (<= 19 main_~y~0) (<= main_~y~0 19))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1058#(and (<= 20 main_~y~0) (<= main_~y~0 20))} is VALID [2022-04-27 21:20:24,786 INFO L290 TraceCheckUtils]: 26: Hoare triple {1058#(and (<= 20 main_~y~0) (<= main_~y~0 20))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1059#(and (<= main_~y~0 21) (<= 21 main_~y~0))} is VALID [2022-04-27 21:20:24,787 INFO L290 TraceCheckUtils]: 27: Hoare triple {1059#(and (<= main_~y~0 21) (<= 21 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1060#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 22))} is VALID [2022-04-27 21:20:24,787 INFO L290 TraceCheckUtils]: 28: Hoare triple {1060#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 22))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:24,788 INFO L272 TraceCheckUtils]: 29: Hoare triple {1034#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1034#false} is VALID [2022-04-27 21:20:24,788 INFO L290 TraceCheckUtils]: 30: Hoare triple {1034#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1034#false} is VALID [2022-04-27 21:20:24,788 INFO L290 TraceCheckUtils]: 31: Hoare triple {1034#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:24,788 INFO L290 TraceCheckUtils]: 32: Hoare triple {1034#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:24,788 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:24,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:24,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63580762] [2022-04-27 21:20:24,789 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63580762] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:24,789 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1631355195] [2022-04-27 21:20:24,789 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 21:20:24,789 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:24,789 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:24,790 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:24,791 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 21:20:24,846 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 21:20:24,847 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:24,848 INFO L263 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 47 conjunts are in the unsatisfiable core [2022-04-27 21:20:24,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:24,858 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:25,244 INFO L272 TraceCheckUtils]: 0: Hoare triple {1033#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:25,245 INFO L290 TraceCheckUtils]: 1: Hoare triple {1033#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 21:20:25,245 INFO L290 TraceCheckUtils]: 2: Hoare triple {1033#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:25,245 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1033#true} {1033#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:25,245 INFO L272 TraceCheckUtils]: 4: Hoare triple {1033#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:25,245 INFO L290 TraceCheckUtils]: 5: Hoare triple {1033#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {1038#(= main_~y~0 0)} is VALID [2022-04-27 21:20:25,246 INFO L290 TraceCheckUtils]: 6: Hoare triple {1038#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1039#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:20:25,246 INFO L290 TraceCheckUtils]: 7: Hoare triple {1039#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1040#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:20:25,247 INFO L290 TraceCheckUtils]: 8: Hoare triple {1040#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1041#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:20:25,247 INFO L290 TraceCheckUtils]: 9: Hoare triple {1041#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1042#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:20:25,248 INFO L290 TraceCheckUtils]: 10: Hoare triple {1042#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1043#(and (<= 5 main_~y~0) (<= main_~y~0 5))} is VALID [2022-04-27 21:20:25,248 INFO L290 TraceCheckUtils]: 11: Hoare triple {1043#(and (<= 5 main_~y~0) (<= main_~y~0 5))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1044#(and (<= main_~y~0 6) (<= 6 main_~y~0))} is VALID [2022-04-27 21:20:25,249 INFO L290 TraceCheckUtils]: 12: Hoare triple {1044#(and (<= main_~y~0 6) (<= 6 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1045#(and (<= 7 main_~y~0) (<= main_~y~0 7))} is VALID [2022-04-27 21:20:25,249 INFO L290 TraceCheckUtils]: 13: Hoare triple {1045#(and (<= 7 main_~y~0) (<= main_~y~0 7))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1046#(and (<= main_~y~0 8) (<= 8 main_~y~0))} is VALID [2022-04-27 21:20:25,250 INFO L290 TraceCheckUtils]: 14: Hoare triple {1046#(and (<= main_~y~0 8) (<= 8 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1047#(and (<= 9 main_~y~0) (<= main_~y~0 9))} is VALID [2022-04-27 21:20:25,250 INFO L290 TraceCheckUtils]: 15: Hoare triple {1047#(and (<= 9 main_~y~0) (<= main_~y~0 9))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1048#(and (<= main_~y~0 10) (<= 10 main_~y~0))} is VALID [2022-04-27 21:20:25,251 INFO L290 TraceCheckUtils]: 16: Hoare triple {1048#(and (<= main_~y~0 10) (<= 10 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1049#(and (<= main_~y~0 11) (<= 11 main_~y~0))} is VALID [2022-04-27 21:20:25,251 INFO L290 TraceCheckUtils]: 17: Hoare triple {1049#(and (<= main_~y~0 11) (<= 11 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1050#(and (<= 12 main_~y~0) (<= main_~y~0 12))} is VALID [2022-04-27 21:20:25,252 INFO L290 TraceCheckUtils]: 18: Hoare triple {1050#(and (<= 12 main_~y~0) (<= main_~y~0 12))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1051#(and (<= main_~y~0 13) (<= 13 main_~y~0))} is VALID [2022-04-27 21:20:25,252 INFO L290 TraceCheckUtils]: 19: Hoare triple {1051#(and (<= main_~y~0 13) (<= 13 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1052#(and (<= 14 main_~y~0) (<= main_~y~0 14))} is VALID [2022-04-27 21:20:25,254 INFO L290 TraceCheckUtils]: 20: Hoare triple {1052#(and (<= 14 main_~y~0) (<= main_~y~0 14))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1053#(and (<= main_~y~0 15) (<= 15 main_~y~0))} is VALID [2022-04-27 21:20:25,254 INFO L290 TraceCheckUtils]: 21: Hoare triple {1053#(and (<= main_~y~0 15) (<= 15 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1054#(and (<= 16 main_~y~0) (<= main_~y~0 16))} is VALID [2022-04-27 21:20:25,255 INFO L290 TraceCheckUtils]: 22: Hoare triple {1054#(and (<= 16 main_~y~0) (<= main_~y~0 16))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1055#(and (<= main_~y~0 17) (<= 17 main_~y~0))} is VALID [2022-04-27 21:20:25,255 INFO L290 TraceCheckUtils]: 23: Hoare triple {1055#(and (<= main_~y~0 17) (<= 17 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1056#(and (<= 18 main_~y~0) (<= main_~y~0 18))} is VALID [2022-04-27 21:20:25,256 INFO L290 TraceCheckUtils]: 24: Hoare triple {1056#(and (<= 18 main_~y~0) (<= main_~y~0 18))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1057#(and (<= 19 main_~y~0) (<= main_~y~0 19))} is VALID [2022-04-27 21:20:25,256 INFO L290 TraceCheckUtils]: 25: Hoare triple {1057#(and (<= 19 main_~y~0) (<= main_~y~0 19))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1058#(and (<= 20 main_~y~0) (<= main_~y~0 20))} is VALID [2022-04-27 21:20:25,257 INFO L290 TraceCheckUtils]: 26: Hoare triple {1058#(and (<= 20 main_~y~0) (<= main_~y~0 20))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1059#(and (<= main_~y~0 21) (<= 21 main_~y~0))} is VALID [2022-04-27 21:20:25,257 INFO L290 TraceCheckUtils]: 27: Hoare triple {1059#(and (<= main_~y~0 21) (<= 21 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1146#(and (<= main_~y~0 22) (<= 22 main_~y~0))} is VALID [2022-04-27 21:20:25,258 INFO L290 TraceCheckUtils]: 28: Hoare triple {1146#(and (<= main_~y~0 22) (<= 22 main_~y~0))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:25,258 INFO L272 TraceCheckUtils]: 29: Hoare triple {1034#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1034#false} is VALID [2022-04-27 21:20:25,258 INFO L290 TraceCheckUtils]: 30: Hoare triple {1034#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1034#false} is VALID [2022-04-27 21:20:25,258 INFO L290 TraceCheckUtils]: 31: Hoare triple {1034#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:25,258 INFO L290 TraceCheckUtils]: 32: Hoare triple {1034#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:25,258 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:25,258 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:26,182 INFO L290 TraceCheckUtils]: 32: Hoare triple {1034#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:26,183 INFO L290 TraceCheckUtils]: 31: Hoare triple {1034#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:26,183 INFO L290 TraceCheckUtils]: 30: Hoare triple {1034#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1034#false} is VALID [2022-04-27 21:20:26,183 INFO L272 TraceCheckUtils]: 29: Hoare triple {1034#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1034#false} is VALID [2022-04-27 21:20:26,187 INFO L290 TraceCheckUtils]: 28: Hoare triple {1174#(< (mod main_~y~0 4294967296) 1024)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {1034#false} is VALID [2022-04-27 21:20:26,190 INFO L290 TraceCheckUtils]: 27: Hoare triple {1178#(< (mod (+ main_~y~0 1) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1174#(< (mod main_~y~0 4294967296) 1024)} is VALID [2022-04-27 21:20:26,192 INFO L290 TraceCheckUtils]: 26: Hoare triple {1182#(< (mod (+ main_~y~0 2) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1178#(< (mod (+ main_~y~0 1) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,193 INFO L290 TraceCheckUtils]: 25: Hoare triple {1186#(< (mod (+ main_~y~0 3) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1182#(< (mod (+ main_~y~0 2) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,193 INFO L290 TraceCheckUtils]: 24: Hoare triple {1190#(< (mod (+ main_~y~0 4) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1186#(< (mod (+ main_~y~0 3) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,194 INFO L290 TraceCheckUtils]: 23: Hoare triple {1194#(< (mod (+ 5 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1190#(< (mod (+ main_~y~0 4) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,195 INFO L290 TraceCheckUtils]: 22: Hoare triple {1198#(< (mod (+ main_~y~0 6) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1194#(< (mod (+ 5 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,195 INFO L290 TraceCheckUtils]: 21: Hoare triple {1202#(< (mod (+ 7 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1198#(< (mod (+ main_~y~0 6) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,196 INFO L290 TraceCheckUtils]: 20: Hoare triple {1206#(< (mod (+ main_~y~0 8) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1202#(< (mod (+ 7 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,196 INFO L290 TraceCheckUtils]: 19: Hoare triple {1210#(< (mod (+ main_~y~0 9) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1206#(< (mod (+ main_~y~0 8) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,197 INFO L290 TraceCheckUtils]: 18: Hoare triple {1214#(< (mod (+ main_~y~0 10) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1210#(< (mod (+ main_~y~0 9) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,198 INFO L290 TraceCheckUtils]: 17: Hoare triple {1218#(< (mod (+ main_~y~0 11) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1214#(< (mod (+ main_~y~0 10) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,198 INFO L290 TraceCheckUtils]: 16: Hoare triple {1222#(< (mod (+ main_~y~0 12) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1218#(< (mod (+ main_~y~0 11) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,199 INFO L290 TraceCheckUtils]: 15: Hoare triple {1226#(< (mod (+ main_~y~0 13) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1222#(< (mod (+ main_~y~0 12) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,199 INFO L290 TraceCheckUtils]: 14: Hoare triple {1230#(< (mod (+ main_~y~0 14) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1226#(< (mod (+ main_~y~0 13) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,200 INFO L290 TraceCheckUtils]: 13: Hoare triple {1234#(< (mod (+ main_~y~0 15) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1230#(< (mod (+ main_~y~0 14) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,201 INFO L290 TraceCheckUtils]: 12: Hoare triple {1238#(< (mod (+ main_~y~0 16) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1234#(< (mod (+ main_~y~0 15) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,201 INFO L290 TraceCheckUtils]: 11: Hoare triple {1242#(< (mod (+ main_~y~0 17) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1238#(< (mod (+ main_~y~0 16) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,202 INFO L290 TraceCheckUtils]: 10: Hoare triple {1246#(< (mod (+ main_~y~0 18) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1242#(< (mod (+ main_~y~0 17) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,204 INFO L290 TraceCheckUtils]: 9: Hoare triple {1250#(< (mod (+ 19 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1246#(< (mod (+ main_~y~0 18) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,204 INFO L290 TraceCheckUtils]: 8: Hoare triple {1254#(< (mod (+ main_~y~0 20) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1250#(< (mod (+ 19 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,205 INFO L290 TraceCheckUtils]: 7: Hoare triple {1258#(< (mod (+ main_~y~0 21) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1254#(< (mod (+ main_~y~0 20) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,205 INFO L290 TraceCheckUtils]: 6: Hoare triple {1262#(< (mod (+ main_~y~0 22) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1258#(< (mod (+ main_~y~0 21) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,206 INFO L290 TraceCheckUtils]: 5: Hoare triple {1033#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {1262#(< (mod (+ main_~y~0 22) 4294967296) 1024)} is VALID [2022-04-27 21:20:26,206 INFO L272 TraceCheckUtils]: 4: Hoare triple {1033#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:26,206 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1033#true} {1033#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:26,207 INFO L290 TraceCheckUtils]: 2: Hoare triple {1033#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:26,207 INFO L290 TraceCheckUtils]: 1: Hoare triple {1033#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1033#true} is VALID [2022-04-27 21:20:26,207 INFO L272 TraceCheckUtils]: 0: Hoare triple {1033#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1033#true} is VALID [2022-04-27 21:20:26,208 INFO L134 CoverageAnalysis]: Checked inductivity of 253 backedges. 0 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:26,209 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1631355195] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:26,209 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:26,209 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25] total 50 [2022-04-27 21:20:26,209 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [144533398] [2022-04-27 21:20:26,209 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:26,210 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-27 21:20:26,210 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:26,210 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:26,260 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 61 edges. 61 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:26,261 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 50 states [2022-04-27 21:20:26,261 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:26,261 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2022-04-27 21:20:26,262 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=672, Invalid=1778, Unknown=0, NotChecked=0, Total=2450 [2022-04-27 21:20:26,262 INFO L87 Difference]: Start difference. First operand 34 states and 34 transitions. Second operand has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:21:42,374 INFO L93 Difference]: Finished difference Result 63 states and 86 transitions. [2022-04-27 21:21:42,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-27 21:21:42,374 INFO L78 Accepts]: Start accepts. Automaton has has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-27 21:21:42,374 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:21:42,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 86 transitions. [2022-04-27 21:21:42,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 86 transitions. [2022-04-27 21:21:42,378 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 86 transitions. [2022-04-27 21:21:42,529 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 86 edges. 86 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:21:42,530 INFO L225 Difference]: With dead ends: 63 [2022-04-27 21:21:42,530 INFO L226 Difference]: Without dead ends: 58 [2022-04-27 21:21:42,532 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 138 GetRequests, 43 SyntacticMatches, 1 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1111 ImplicationChecksByTransitivity, 75.8s TimeCoverageRelationStatistics Valid=2443, Invalid=6677, Unknown=0, NotChecked=0, Total=9120 [2022-04-27 21:21:42,532 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 6 mSDsluCounter, 122 mSDsCounter, 0 mSdLazyCounter, 684 mSolverCounterSat, 105 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 6 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 789 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 105 IncrementalHoareTripleChecker+Valid, 684 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-04-27 21:21:42,532 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [6 Valid, 133 Invalid, 789 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [105 Valid, 684 Invalid, 0 Unknown, 0 Unchecked, 0.6s Time] [2022-04-27 21:21:42,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2022-04-27 21:21:42,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2022-04-27 21:21:42,586 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:21:42,587 INFO L82 GeneralOperation]: Start isEquivalent. First operand 58 states. Second operand has 58 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 53 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,588 INFO L74 IsIncluded]: Start isIncluded. First operand 58 states. Second operand has 58 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 53 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,588 INFO L87 Difference]: Start difference. First operand 58 states. Second operand has 58 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 53 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:21:42,591 INFO L93 Difference]: Finished difference Result 58 states and 58 transitions. [2022-04-27 21:21:42,591 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 58 transitions. [2022-04-27 21:21:42,591 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:21:42,591 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:21:42,592 INFO L74 IsIncluded]: Start isIncluded. First operand has 58 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 53 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 58 states. [2022-04-27 21:21:42,593 INFO L87 Difference]: Start difference. First operand has 58 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 53 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 58 states. [2022-04-27 21:21:42,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:21:42,595 INFO L93 Difference]: Finished difference Result 58 states and 58 transitions. [2022-04-27 21:21:42,595 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 58 transitions. [2022-04-27 21:21:42,598 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:21:42,598 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:21:42,598 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:21:42,598 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:21:42,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 53 states have (on average 1.0188679245283019) internal successors, (54), 53 states have internal predecessors, (54), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 58 transitions. [2022-04-27 21:21:42,600 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 58 transitions. Word has length 33 [2022-04-27 21:21:42,601 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:21:42,601 INFO L495 AbstractCegarLoop]: Abstraction has 58 states and 58 transitions. [2022-04-27 21:21:42,601 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 50 states, 50 states have (on average 1.12) internal successors, (56), 49 states have internal predecessors, (56), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:42,602 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 58 transitions. [2022-04-27 21:21:42,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2022-04-27 21:21:42,605 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:21:42,605 INFO L195 NwaCegarLoop]: trace histogram [46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:21:42,629 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 21:21:42,827 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:21:42,827 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:21:42,828 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:21:42,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1712624128, now seen corresponding path program 5 times [2022-04-27 21:21:42,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:21:42,828 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1453981618] [2022-04-27 21:21:42,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:21:42,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:21:42,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:21:44,008 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:21:44,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:21:44,015 INFO L290 TraceCheckUtils]: 0: Hoare triple {1772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1720#true} is VALID [2022-04-27 21:21:44,015 INFO L290 TraceCheckUtils]: 1: Hoare triple {1720#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:21:44,015 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1720#true} {1720#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:21:44,022 INFO L272 TraceCheckUtils]: 0: Hoare triple {1720#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:21:44,022 INFO L290 TraceCheckUtils]: 1: Hoare triple {1772#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1720#true} is VALID [2022-04-27 21:21:44,022 INFO L290 TraceCheckUtils]: 2: Hoare triple {1720#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:21:44,022 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1720#true} {1720#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:21:44,022 INFO L272 TraceCheckUtils]: 4: Hoare triple {1720#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:21:44,023 INFO L290 TraceCheckUtils]: 5: Hoare triple {1720#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {1725#(= main_~y~0 0)} is VALID [2022-04-27 21:21:44,023 INFO L290 TraceCheckUtils]: 6: Hoare triple {1725#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1726#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:21:44,024 INFO L290 TraceCheckUtils]: 7: Hoare triple {1726#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1727#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:21:44,024 INFO L290 TraceCheckUtils]: 8: Hoare triple {1727#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1728#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:21:44,025 INFO L290 TraceCheckUtils]: 9: Hoare triple {1728#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1729#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:21:44,025 INFO L290 TraceCheckUtils]: 10: Hoare triple {1729#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1730#(and (<= 5 main_~y~0) (<= main_~y~0 5))} is VALID [2022-04-27 21:21:44,026 INFO L290 TraceCheckUtils]: 11: Hoare triple {1730#(and (<= 5 main_~y~0) (<= main_~y~0 5))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1731#(and (<= main_~y~0 6) (<= 6 main_~y~0))} is VALID [2022-04-27 21:21:44,026 INFO L290 TraceCheckUtils]: 12: Hoare triple {1731#(and (<= main_~y~0 6) (<= 6 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1732#(and (<= 7 main_~y~0) (<= main_~y~0 7))} is VALID [2022-04-27 21:21:44,027 INFO L290 TraceCheckUtils]: 13: Hoare triple {1732#(and (<= 7 main_~y~0) (<= main_~y~0 7))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1733#(and (<= main_~y~0 8) (<= 8 main_~y~0))} is VALID [2022-04-27 21:21:44,027 INFO L290 TraceCheckUtils]: 14: Hoare triple {1733#(and (<= main_~y~0 8) (<= 8 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1734#(and (<= 9 main_~y~0) (<= main_~y~0 9))} is VALID [2022-04-27 21:21:44,028 INFO L290 TraceCheckUtils]: 15: Hoare triple {1734#(and (<= 9 main_~y~0) (<= main_~y~0 9))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1735#(and (<= main_~y~0 10) (<= 10 main_~y~0))} is VALID [2022-04-27 21:21:44,028 INFO L290 TraceCheckUtils]: 16: Hoare triple {1735#(and (<= main_~y~0 10) (<= 10 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1736#(and (<= main_~y~0 11) (<= 11 main_~y~0))} is VALID [2022-04-27 21:21:44,029 INFO L290 TraceCheckUtils]: 17: Hoare triple {1736#(and (<= main_~y~0 11) (<= 11 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1737#(and (<= 12 main_~y~0) (<= main_~y~0 12))} is VALID [2022-04-27 21:21:44,029 INFO L290 TraceCheckUtils]: 18: Hoare triple {1737#(and (<= 12 main_~y~0) (<= main_~y~0 12))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1738#(and (<= main_~y~0 13) (<= 13 main_~y~0))} is VALID [2022-04-27 21:21:44,030 INFO L290 TraceCheckUtils]: 19: Hoare triple {1738#(and (<= main_~y~0 13) (<= 13 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1739#(and (<= 14 main_~y~0) (<= main_~y~0 14))} is VALID [2022-04-27 21:21:44,030 INFO L290 TraceCheckUtils]: 20: Hoare triple {1739#(and (<= 14 main_~y~0) (<= main_~y~0 14))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1740#(and (<= main_~y~0 15) (<= 15 main_~y~0))} is VALID [2022-04-27 21:21:44,031 INFO L290 TraceCheckUtils]: 21: Hoare triple {1740#(and (<= main_~y~0 15) (<= 15 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1741#(and (<= 16 main_~y~0) (<= main_~y~0 16))} is VALID [2022-04-27 21:21:44,031 INFO L290 TraceCheckUtils]: 22: Hoare triple {1741#(and (<= 16 main_~y~0) (<= main_~y~0 16))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1742#(and (<= main_~y~0 17) (<= 17 main_~y~0))} is VALID [2022-04-27 21:21:44,032 INFO L290 TraceCheckUtils]: 23: Hoare triple {1742#(and (<= main_~y~0 17) (<= 17 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1743#(and (<= 18 main_~y~0) (<= main_~y~0 18))} is VALID [2022-04-27 21:21:44,032 INFO L290 TraceCheckUtils]: 24: Hoare triple {1743#(and (<= 18 main_~y~0) (<= main_~y~0 18))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1744#(and (<= 19 main_~y~0) (<= main_~y~0 19))} is VALID [2022-04-27 21:21:44,033 INFO L290 TraceCheckUtils]: 25: Hoare triple {1744#(and (<= 19 main_~y~0) (<= main_~y~0 19))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1745#(and (<= 20 main_~y~0) (<= main_~y~0 20))} is VALID [2022-04-27 21:21:44,033 INFO L290 TraceCheckUtils]: 26: Hoare triple {1745#(and (<= 20 main_~y~0) (<= main_~y~0 20))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1746#(and (<= main_~y~0 21) (<= 21 main_~y~0))} is VALID [2022-04-27 21:21:44,034 INFO L290 TraceCheckUtils]: 27: Hoare triple {1746#(and (<= main_~y~0 21) (<= 21 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1747#(and (<= main_~y~0 22) (<= 22 main_~y~0))} is VALID [2022-04-27 21:21:44,034 INFO L290 TraceCheckUtils]: 28: Hoare triple {1747#(and (<= main_~y~0 22) (<= 22 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1748#(and (<= main_~y~0 23) (<= 23 main_~y~0))} is VALID [2022-04-27 21:21:44,035 INFO L290 TraceCheckUtils]: 29: Hoare triple {1748#(and (<= main_~y~0 23) (<= 23 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1749#(and (<= 24 main_~y~0) (<= main_~y~0 24))} is VALID [2022-04-27 21:21:44,035 INFO L290 TraceCheckUtils]: 30: Hoare triple {1749#(and (<= 24 main_~y~0) (<= main_~y~0 24))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1750#(and (<= 25 main_~y~0) (<= main_~y~0 25))} is VALID [2022-04-27 21:21:44,036 INFO L290 TraceCheckUtils]: 31: Hoare triple {1750#(and (<= 25 main_~y~0) (<= main_~y~0 25))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1751#(and (<= main_~y~0 26) (<= 26 main_~y~0))} is VALID [2022-04-27 21:21:44,036 INFO L290 TraceCheckUtils]: 32: Hoare triple {1751#(and (<= main_~y~0 26) (<= 26 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1752#(and (<= main_~y~0 27) (<= 27 main_~y~0))} is VALID [2022-04-27 21:21:44,037 INFO L290 TraceCheckUtils]: 33: Hoare triple {1752#(and (<= main_~y~0 27) (<= 27 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1753#(and (<= main_~y~0 28) (<= 28 main_~y~0))} is VALID [2022-04-27 21:21:44,037 INFO L290 TraceCheckUtils]: 34: Hoare triple {1753#(and (<= main_~y~0 28) (<= 28 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1754#(and (<= 29 main_~y~0) (<= main_~y~0 29))} is VALID [2022-04-27 21:21:44,038 INFO L290 TraceCheckUtils]: 35: Hoare triple {1754#(and (<= 29 main_~y~0) (<= main_~y~0 29))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1755#(and (<= main_~y~0 30) (<= 30 main_~y~0))} is VALID [2022-04-27 21:21:44,038 INFO L290 TraceCheckUtils]: 36: Hoare triple {1755#(and (<= main_~y~0 30) (<= 30 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1756#(and (<= main_~y~0 31) (<= 31 main_~y~0))} is VALID [2022-04-27 21:21:44,039 INFO L290 TraceCheckUtils]: 37: Hoare triple {1756#(and (<= main_~y~0 31) (<= 31 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1757#(and (<= main_~y~0 32) (<= 32 main_~y~0))} is VALID [2022-04-27 21:21:44,039 INFO L290 TraceCheckUtils]: 38: Hoare triple {1757#(and (<= main_~y~0 32) (<= 32 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1758#(and (<= 33 main_~y~0) (<= main_~y~0 33))} is VALID [2022-04-27 21:21:44,040 INFO L290 TraceCheckUtils]: 39: Hoare triple {1758#(and (<= 33 main_~y~0) (<= main_~y~0 33))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1759#(and (<= main_~y~0 34) (<= 34 main_~y~0))} is VALID [2022-04-27 21:21:44,040 INFO L290 TraceCheckUtils]: 40: Hoare triple {1759#(and (<= main_~y~0 34) (<= 34 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1760#(and (<= 35 main_~y~0) (<= main_~y~0 35))} is VALID [2022-04-27 21:21:44,041 INFO L290 TraceCheckUtils]: 41: Hoare triple {1760#(and (<= 35 main_~y~0) (<= main_~y~0 35))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1761#(and (<= 36 main_~y~0) (<= main_~y~0 36))} is VALID [2022-04-27 21:21:44,041 INFO L290 TraceCheckUtils]: 42: Hoare triple {1761#(and (<= 36 main_~y~0) (<= main_~y~0 36))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1762#(and (<= main_~y~0 37) (<= 37 main_~y~0))} is VALID [2022-04-27 21:21:44,042 INFO L290 TraceCheckUtils]: 43: Hoare triple {1762#(and (<= main_~y~0 37) (<= 37 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1763#(and (<= 38 main_~y~0) (<= main_~y~0 38))} is VALID [2022-04-27 21:21:44,042 INFO L290 TraceCheckUtils]: 44: Hoare triple {1763#(and (<= 38 main_~y~0) (<= main_~y~0 38))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1764#(and (<= 39 main_~y~0) (<= main_~y~0 39))} is VALID [2022-04-27 21:21:44,043 INFO L290 TraceCheckUtils]: 45: Hoare triple {1764#(and (<= 39 main_~y~0) (<= main_~y~0 39))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1765#(and (<= 40 main_~y~0) (<= main_~y~0 40))} is VALID [2022-04-27 21:21:44,043 INFO L290 TraceCheckUtils]: 46: Hoare triple {1765#(and (<= 40 main_~y~0) (<= main_~y~0 40))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1766#(and (<= 41 main_~y~0) (<= main_~y~0 41))} is VALID [2022-04-27 21:21:44,044 INFO L290 TraceCheckUtils]: 47: Hoare triple {1766#(and (<= 41 main_~y~0) (<= main_~y~0 41))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1767#(and (<= main_~y~0 42) (<= 42 main_~y~0))} is VALID [2022-04-27 21:21:44,044 INFO L290 TraceCheckUtils]: 48: Hoare triple {1767#(and (<= main_~y~0 42) (<= 42 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1768#(and (<= 43 main_~y~0) (<= main_~y~0 43))} is VALID [2022-04-27 21:21:44,045 INFO L290 TraceCheckUtils]: 49: Hoare triple {1768#(and (<= 43 main_~y~0) (<= main_~y~0 43))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1769#(and (<= main_~y~0 44) (<= 44 main_~y~0))} is VALID [2022-04-27 21:21:44,045 INFO L290 TraceCheckUtils]: 50: Hoare triple {1769#(and (<= main_~y~0 44) (<= 44 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1770#(and (<= main_~y~0 45) (<= 45 main_~y~0))} is VALID [2022-04-27 21:21:44,046 INFO L290 TraceCheckUtils]: 51: Hoare triple {1770#(and (<= main_~y~0 45) (<= 45 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1771#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 46))} is VALID [2022-04-27 21:21:44,046 INFO L290 TraceCheckUtils]: 52: Hoare triple {1771#(and (not (<= (+ (div main_~y~0 4294967296) 1) 0)) (<= main_~y~0 46))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:21:44,046 INFO L272 TraceCheckUtils]: 53: Hoare triple {1721#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1721#false} is VALID [2022-04-27 21:21:44,046 INFO L290 TraceCheckUtils]: 54: Hoare triple {1721#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1721#false} is VALID [2022-04-27 21:21:44,046 INFO L290 TraceCheckUtils]: 55: Hoare triple {1721#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:21:44,046 INFO L290 TraceCheckUtils]: 56: Hoare triple {1721#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:21:44,047 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:21:44,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:21:44,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1453981618] [2022-04-27 21:21:44,047 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1453981618] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:21:44,047 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2082617450] [2022-04-27 21:21:44,048 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-27 21:21:44,048 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:21:44,048 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:21:44,048 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:21:44,049 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 21:22:16,788 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2022-04-27 21:22:16,789 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:22:16,809 INFO L263 TraceCheckSpWp]: Trace formula consists of 283 conjuncts, 95 conjunts are in the unsatisfiable core [2022-04-27 21:22:16,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:22:16,835 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:22:17,404 INFO L272 TraceCheckUtils]: 0: Hoare triple {1720#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:17,404 INFO L290 TraceCheckUtils]: 1: Hoare triple {1720#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1720#true} is VALID [2022-04-27 21:22:17,405 INFO L290 TraceCheckUtils]: 2: Hoare triple {1720#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:17,405 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1720#true} {1720#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:17,405 INFO L272 TraceCheckUtils]: 4: Hoare triple {1720#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:17,405 INFO L290 TraceCheckUtils]: 5: Hoare triple {1720#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {1725#(= main_~y~0 0)} is VALID [2022-04-27 21:22:17,405 INFO L290 TraceCheckUtils]: 6: Hoare triple {1725#(= main_~y~0 0)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1726#(and (<= 1 main_~y~0) (<= main_~y~0 1))} is VALID [2022-04-27 21:22:17,406 INFO L290 TraceCheckUtils]: 7: Hoare triple {1726#(and (<= 1 main_~y~0) (<= main_~y~0 1))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1727#(and (<= 2 main_~y~0) (<= main_~y~0 2))} is VALID [2022-04-27 21:22:17,406 INFO L290 TraceCheckUtils]: 8: Hoare triple {1727#(and (<= 2 main_~y~0) (<= main_~y~0 2))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1728#(and (<= main_~y~0 3) (<= 3 main_~y~0))} is VALID [2022-04-27 21:22:17,407 INFO L290 TraceCheckUtils]: 9: Hoare triple {1728#(and (<= main_~y~0 3) (<= 3 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1729#(and (<= main_~y~0 4) (<= 4 main_~y~0))} is VALID [2022-04-27 21:22:17,407 INFO L290 TraceCheckUtils]: 10: Hoare triple {1729#(and (<= main_~y~0 4) (<= 4 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1730#(and (<= 5 main_~y~0) (<= main_~y~0 5))} is VALID [2022-04-27 21:22:17,408 INFO L290 TraceCheckUtils]: 11: Hoare triple {1730#(and (<= 5 main_~y~0) (<= main_~y~0 5))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1731#(and (<= main_~y~0 6) (<= 6 main_~y~0))} is VALID [2022-04-27 21:22:17,408 INFO L290 TraceCheckUtils]: 12: Hoare triple {1731#(and (<= main_~y~0 6) (<= 6 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1732#(and (<= 7 main_~y~0) (<= main_~y~0 7))} is VALID [2022-04-27 21:22:17,409 INFO L290 TraceCheckUtils]: 13: Hoare triple {1732#(and (<= 7 main_~y~0) (<= main_~y~0 7))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1733#(and (<= main_~y~0 8) (<= 8 main_~y~0))} is VALID [2022-04-27 21:22:17,409 INFO L290 TraceCheckUtils]: 14: Hoare triple {1733#(and (<= main_~y~0 8) (<= 8 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1734#(and (<= 9 main_~y~0) (<= main_~y~0 9))} is VALID [2022-04-27 21:22:17,410 INFO L290 TraceCheckUtils]: 15: Hoare triple {1734#(and (<= 9 main_~y~0) (<= main_~y~0 9))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1735#(and (<= main_~y~0 10) (<= 10 main_~y~0))} is VALID [2022-04-27 21:22:17,410 INFO L290 TraceCheckUtils]: 16: Hoare triple {1735#(and (<= main_~y~0 10) (<= 10 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1736#(and (<= main_~y~0 11) (<= 11 main_~y~0))} is VALID [2022-04-27 21:22:17,411 INFO L290 TraceCheckUtils]: 17: Hoare triple {1736#(and (<= main_~y~0 11) (<= 11 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1737#(and (<= 12 main_~y~0) (<= main_~y~0 12))} is VALID [2022-04-27 21:22:17,411 INFO L290 TraceCheckUtils]: 18: Hoare triple {1737#(and (<= 12 main_~y~0) (<= main_~y~0 12))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1738#(and (<= main_~y~0 13) (<= 13 main_~y~0))} is VALID [2022-04-27 21:22:17,412 INFO L290 TraceCheckUtils]: 19: Hoare triple {1738#(and (<= main_~y~0 13) (<= 13 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1739#(and (<= 14 main_~y~0) (<= main_~y~0 14))} is VALID [2022-04-27 21:22:17,412 INFO L290 TraceCheckUtils]: 20: Hoare triple {1739#(and (<= 14 main_~y~0) (<= main_~y~0 14))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1740#(and (<= main_~y~0 15) (<= 15 main_~y~0))} is VALID [2022-04-27 21:22:17,413 INFO L290 TraceCheckUtils]: 21: Hoare triple {1740#(and (<= main_~y~0 15) (<= 15 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1741#(and (<= 16 main_~y~0) (<= main_~y~0 16))} is VALID [2022-04-27 21:22:17,413 INFO L290 TraceCheckUtils]: 22: Hoare triple {1741#(and (<= 16 main_~y~0) (<= main_~y~0 16))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1742#(and (<= main_~y~0 17) (<= 17 main_~y~0))} is VALID [2022-04-27 21:22:17,414 INFO L290 TraceCheckUtils]: 23: Hoare triple {1742#(and (<= main_~y~0 17) (<= 17 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1743#(and (<= 18 main_~y~0) (<= main_~y~0 18))} is VALID [2022-04-27 21:22:17,414 INFO L290 TraceCheckUtils]: 24: Hoare triple {1743#(and (<= 18 main_~y~0) (<= main_~y~0 18))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1744#(and (<= 19 main_~y~0) (<= main_~y~0 19))} is VALID [2022-04-27 21:22:17,415 INFO L290 TraceCheckUtils]: 25: Hoare triple {1744#(and (<= 19 main_~y~0) (<= main_~y~0 19))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1745#(and (<= 20 main_~y~0) (<= main_~y~0 20))} is VALID [2022-04-27 21:22:17,415 INFO L290 TraceCheckUtils]: 26: Hoare triple {1745#(and (<= 20 main_~y~0) (<= main_~y~0 20))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1746#(and (<= main_~y~0 21) (<= 21 main_~y~0))} is VALID [2022-04-27 21:22:17,416 INFO L290 TraceCheckUtils]: 27: Hoare triple {1746#(and (<= main_~y~0 21) (<= 21 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1747#(and (<= main_~y~0 22) (<= 22 main_~y~0))} is VALID [2022-04-27 21:22:17,416 INFO L290 TraceCheckUtils]: 28: Hoare triple {1747#(and (<= main_~y~0 22) (<= 22 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1748#(and (<= main_~y~0 23) (<= 23 main_~y~0))} is VALID [2022-04-27 21:22:17,417 INFO L290 TraceCheckUtils]: 29: Hoare triple {1748#(and (<= main_~y~0 23) (<= 23 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1749#(and (<= 24 main_~y~0) (<= main_~y~0 24))} is VALID [2022-04-27 21:22:17,417 INFO L290 TraceCheckUtils]: 30: Hoare triple {1749#(and (<= 24 main_~y~0) (<= main_~y~0 24))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1750#(and (<= 25 main_~y~0) (<= main_~y~0 25))} is VALID [2022-04-27 21:22:17,417 INFO L290 TraceCheckUtils]: 31: Hoare triple {1750#(and (<= 25 main_~y~0) (<= main_~y~0 25))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1751#(and (<= main_~y~0 26) (<= 26 main_~y~0))} is VALID [2022-04-27 21:22:17,418 INFO L290 TraceCheckUtils]: 32: Hoare triple {1751#(and (<= main_~y~0 26) (<= 26 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1752#(and (<= main_~y~0 27) (<= 27 main_~y~0))} is VALID [2022-04-27 21:22:17,418 INFO L290 TraceCheckUtils]: 33: Hoare triple {1752#(and (<= main_~y~0 27) (<= 27 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1753#(and (<= main_~y~0 28) (<= 28 main_~y~0))} is VALID [2022-04-27 21:22:17,419 INFO L290 TraceCheckUtils]: 34: Hoare triple {1753#(and (<= main_~y~0 28) (<= 28 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1754#(and (<= 29 main_~y~0) (<= main_~y~0 29))} is VALID [2022-04-27 21:22:17,419 INFO L290 TraceCheckUtils]: 35: Hoare triple {1754#(and (<= 29 main_~y~0) (<= main_~y~0 29))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1755#(and (<= main_~y~0 30) (<= 30 main_~y~0))} is VALID [2022-04-27 21:22:17,420 INFO L290 TraceCheckUtils]: 36: Hoare triple {1755#(and (<= main_~y~0 30) (<= 30 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1756#(and (<= main_~y~0 31) (<= 31 main_~y~0))} is VALID [2022-04-27 21:22:17,421 INFO L290 TraceCheckUtils]: 37: Hoare triple {1756#(and (<= main_~y~0 31) (<= 31 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1757#(and (<= main_~y~0 32) (<= 32 main_~y~0))} is VALID [2022-04-27 21:22:17,421 INFO L290 TraceCheckUtils]: 38: Hoare triple {1757#(and (<= main_~y~0 32) (<= 32 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1758#(and (<= 33 main_~y~0) (<= main_~y~0 33))} is VALID [2022-04-27 21:22:17,422 INFO L290 TraceCheckUtils]: 39: Hoare triple {1758#(and (<= 33 main_~y~0) (<= main_~y~0 33))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1759#(and (<= main_~y~0 34) (<= 34 main_~y~0))} is VALID [2022-04-27 21:22:17,422 INFO L290 TraceCheckUtils]: 40: Hoare triple {1759#(and (<= main_~y~0 34) (<= 34 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1760#(and (<= 35 main_~y~0) (<= main_~y~0 35))} is VALID [2022-04-27 21:22:17,423 INFO L290 TraceCheckUtils]: 41: Hoare triple {1760#(and (<= 35 main_~y~0) (<= main_~y~0 35))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1761#(and (<= 36 main_~y~0) (<= main_~y~0 36))} is VALID [2022-04-27 21:22:17,423 INFO L290 TraceCheckUtils]: 42: Hoare triple {1761#(and (<= 36 main_~y~0) (<= main_~y~0 36))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1762#(and (<= main_~y~0 37) (<= 37 main_~y~0))} is VALID [2022-04-27 21:22:17,424 INFO L290 TraceCheckUtils]: 43: Hoare triple {1762#(and (<= main_~y~0 37) (<= 37 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1763#(and (<= 38 main_~y~0) (<= main_~y~0 38))} is VALID [2022-04-27 21:22:17,424 INFO L290 TraceCheckUtils]: 44: Hoare triple {1763#(and (<= 38 main_~y~0) (<= main_~y~0 38))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1764#(and (<= 39 main_~y~0) (<= main_~y~0 39))} is VALID [2022-04-27 21:22:17,425 INFO L290 TraceCheckUtils]: 45: Hoare triple {1764#(and (<= 39 main_~y~0) (<= main_~y~0 39))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1765#(and (<= 40 main_~y~0) (<= main_~y~0 40))} is VALID [2022-04-27 21:22:17,425 INFO L290 TraceCheckUtils]: 46: Hoare triple {1765#(and (<= 40 main_~y~0) (<= main_~y~0 40))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1766#(and (<= 41 main_~y~0) (<= main_~y~0 41))} is VALID [2022-04-27 21:22:17,426 INFO L290 TraceCheckUtils]: 47: Hoare triple {1766#(and (<= 41 main_~y~0) (<= main_~y~0 41))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1767#(and (<= main_~y~0 42) (<= 42 main_~y~0))} is VALID [2022-04-27 21:22:17,426 INFO L290 TraceCheckUtils]: 48: Hoare triple {1767#(and (<= main_~y~0 42) (<= 42 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1768#(and (<= 43 main_~y~0) (<= main_~y~0 43))} is VALID [2022-04-27 21:22:17,427 INFO L290 TraceCheckUtils]: 49: Hoare triple {1768#(and (<= 43 main_~y~0) (<= main_~y~0 43))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1769#(and (<= main_~y~0 44) (<= 44 main_~y~0))} is VALID [2022-04-27 21:22:17,427 INFO L290 TraceCheckUtils]: 50: Hoare triple {1769#(and (<= main_~y~0 44) (<= 44 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1770#(and (<= main_~y~0 45) (<= 45 main_~y~0))} is VALID [2022-04-27 21:22:17,428 INFO L290 TraceCheckUtils]: 51: Hoare triple {1770#(and (<= main_~y~0 45) (<= 45 main_~y~0))} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1929#(and (<= main_~y~0 46) (<= 46 main_~y~0))} is VALID [2022-04-27 21:22:17,428 INFO L290 TraceCheckUtils]: 52: Hoare triple {1929#(and (<= main_~y~0 46) (<= 46 main_~y~0))} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:22:17,428 INFO L272 TraceCheckUtils]: 53: Hoare triple {1721#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1721#false} is VALID [2022-04-27 21:22:17,428 INFO L290 TraceCheckUtils]: 54: Hoare triple {1721#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1721#false} is VALID [2022-04-27 21:22:17,428 INFO L290 TraceCheckUtils]: 55: Hoare triple {1721#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:22:17,429 INFO L290 TraceCheckUtils]: 56: Hoare triple {1721#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:22:17,429 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:22:17,429 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:22:20,543 INFO L290 TraceCheckUtils]: 56: Hoare triple {1721#false} [53] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:22:20,543 INFO L290 TraceCheckUtils]: 55: Hoare triple {1721#false} [51] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:22:20,543 INFO L290 TraceCheckUtils]: 54: Hoare triple {1721#false} [50] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1721#false} is VALID [2022-04-27 21:22:20,543 INFO L272 TraceCheckUtils]: 53: Hoare triple {1721#false} [48] L16-3-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_4 4294967296) 1) 1 0)) InVars {main_~x~0=v_main_~x~0_4} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0] {1721#false} is VALID [2022-04-27 21:22:20,544 INFO L290 TraceCheckUtils]: 52: Hoare triple {1957#(< (mod main_~y~0 4294967296) 1024)} [46] L16-2-->L16-3: Formula: (not (< (mod v_main_~y~0_4 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_4} OutVars{main_~y~0=v_main_~y~0_4} AuxVars[] AssignedVars[] {1721#false} is VALID [2022-04-27 21:22:20,544 INFO L290 TraceCheckUtils]: 51: Hoare triple {1961#(< (mod (+ main_~y~0 1) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1957#(< (mod main_~y~0 4294967296) 1024)} is VALID [2022-04-27 21:22:20,545 INFO L290 TraceCheckUtils]: 50: Hoare triple {1965#(< (mod (+ main_~y~0 2) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1961#(< (mod (+ main_~y~0 1) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,546 INFO L290 TraceCheckUtils]: 49: Hoare triple {1969#(< (mod (+ main_~y~0 3) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1965#(< (mod (+ main_~y~0 2) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,546 INFO L290 TraceCheckUtils]: 48: Hoare triple {1973#(< (mod (+ main_~y~0 4) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1969#(< (mod (+ main_~y~0 3) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,547 INFO L290 TraceCheckUtils]: 47: Hoare triple {1977#(< (mod (+ 5 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1973#(< (mod (+ main_~y~0 4) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,547 INFO L290 TraceCheckUtils]: 46: Hoare triple {1981#(< (mod (+ main_~y~0 6) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1977#(< (mod (+ 5 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,548 INFO L290 TraceCheckUtils]: 45: Hoare triple {1985#(< (mod (+ 7 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1981#(< (mod (+ main_~y~0 6) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,549 INFO L290 TraceCheckUtils]: 44: Hoare triple {1989#(< (mod (+ main_~y~0 8) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1985#(< (mod (+ 7 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,549 INFO L290 TraceCheckUtils]: 43: Hoare triple {1993#(< (mod (+ main_~y~0 9) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1989#(< (mod (+ main_~y~0 8) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,558 INFO L290 TraceCheckUtils]: 42: Hoare triple {1997#(< (mod (+ main_~y~0 10) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1993#(< (mod (+ main_~y~0 9) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,558 INFO L290 TraceCheckUtils]: 41: Hoare triple {2001#(< (mod (+ main_~y~0 11) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {1997#(< (mod (+ main_~y~0 10) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,559 INFO L290 TraceCheckUtils]: 40: Hoare triple {2005#(< (mod (+ main_~y~0 12) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2001#(< (mod (+ main_~y~0 11) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,560 INFO L290 TraceCheckUtils]: 39: Hoare triple {2009#(< (mod (+ main_~y~0 13) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2005#(< (mod (+ main_~y~0 12) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,560 INFO L290 TraceCheckUtils]: 38: Hoare triple {2013#(< (mod (+ main_~y~0 14) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2009#(< (mod (+ main_~y~0 13) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,561 INFO L290 TraceCheckUtils]: 37: Hoare triple {2017#(< (mod (+ main_~y~0 15) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2013#(< (mod (+ main_~y~0 14) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,561 INFO L290 TraceCheckUtils]: 36: Hoare triple {2021#(< (mod (+ main_~y~0 16) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2017#(< (mod (+ main_~y~0 15) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,562 INFO L290 TraceCheckUtils]: 35: Hoare triple {2025#(< (mod (+ main_~y~0 17) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2021#(< (mod (+ main_~y~0 16) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,563 INFO L290 TraceCheckUtils]: 34: Hoare triple {2029#(< (mod (+ main_~y~0 18) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2025#(< (mod (+ main_~y~0 17) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,563 INFO L290 TraceCheckUtils]: 33: Hoare triple {2033#(< (mod (+ 19 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2029#(< (mod (+ main_~y~0 18) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,564 INFO L290 TraceCheckUtils]: 32: Hoare triple {2037#(< (mod (+ main_~y~0 20) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2033#(< (mod (+ 19 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,564 INFO L290 TraceCheckUtils]: 31: Hoare triple {2041#(< (mod (+ main_~y~0 21) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2037#(< (mod (+ main_~y~0 20) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,565 INFO L290 TraceCheckUtils]: 30: Hoare triple {2045#(< (mod (+ main_~y~0 22) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2041#(< (mod (+ main_~y~0 21) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,566 INFO L290 TraceCheckUtils]: 29: Hoare triple {2049#(< (mod (+ 23 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2045#(< (mod (+ main_~y~0 22) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,566 INFO L290 TraceCheckUtils]: 28: Hoare triple {2053#(< (mod (+ main_~y~0 24) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2049#(< (mod (+ 23 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,567 INFO L290 TraceCheckUtils]: 27: Hoare triple {2057#(< (mod (+ main_~y~0 25) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2053#(< (mod (+ main_~y~0 24) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,567 INFO L290 TraceCheckUtils]: 26: Hoare triple {2061#(< (mod (+ main_~y~0 26) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2057#(< (mod (+ main_~y~0 25) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,568 INFO L290 TraceCheckUtils]: 25: Hoare triple {2065#(< (mod (+ main_~y~0 27) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2061#(< (mod (+ main_~y~0 26) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,569 INFO L290 TraceCheckUtils]: 24: Hoare triple {2069#(< (mod (+ main_~y~0 28) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2065#(< (mod (+ main_~y~0 27) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,569 INFO L290 TraceCheckUtils]: 23: Hoare triple {2073#(< (mod (+ 29 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2069#(< (mod (+ main_~y~0 28) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,570 INFO L290 TraceCheckUtils]: 22: Hoare triple {2077#(< (mod (+ 30 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2073#(< (mod (+ 29 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,571 INFO L290 TraceCheckUtils]: 21: Hoare triple {2081#(< (mod (+ main_~y~0 31) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2077#(< (mod (+ 30 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,571 INFO L290 TraceCheckUtils]: 20: Hoare triple {2085#(< (mod (+ 32 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2081#(< (mod (+ main_~y~0 31) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,572 INFO L290 TraceCheckUtils]: 19: Hoare triple {2089#(< (mod (+ main_~y~0 33) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2085#(< (mod (+ 32 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,573 INFO L290 TraceCheckUtils]: 18: Hoare triple {2093#(< (mod (+ main_~y~0 34) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2089#(< (mod (+ main_~y~0 33) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,573 INFO L290 TraceCheckUtils]: 17: Hoare triple {2097#(< (mod (+ 35 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2093#(< (mod (+ main_~y~0 34) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,574 INFO L290 TraceCheckUtils]: 16: Hoare triple {2101#(< (mod (+ main_~y~0 36) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2097#(< (mod (+ 35 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,575 INFO L290 TraceCheckUtils]: 15: Hoare triple {2105#(< (mod (+ main_~y~0 37) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2101#(< (mod (+ main_~y~0 36) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,575 INFO L290 TraceCheckUtils]: 14: Hoare triple {2109#(< (mod (+ main_~y~0 38) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2105#(< (mod (+ main_~y~0 37) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,576 INFO L290 TraceCheckUtils]: 13: Hoare triple {2113#(< (mod (+ main_~y~0 39) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2109#(< (mod (+ main_~y~0 38) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,577 INFO L290 TraceCheckUtils]: 12: Hoare triple {2117#(< (mod (+ 40 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2113#(< (mod (+ main_~y~0 39) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,577 INFO L290 TraceCheckUtils]: 11: Hoare triple {2121#(< (mod (+ 41 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2117#(< (mod (+ 40 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,578 INFO L290 TraceCheckUtils]: 10: Hoare triple {2125#(< (mod (+ 42 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2121#(< (mod (+ 41 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,578 INFO L290 TraceCheckUtils]: 9: Hoare triple {2129#(< (mod (+ main_~y~0 43) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2125#(< (mod (+ 42 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,579 INFO L290 TraceCheckUtils]: 8: Hoare triple {2133#(< (mod (+ 44 main_~y~0) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2129#(< (mod (+ main_~y~0 43) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,580 INFO L290 TraceCheckUtils]: 7: Hoare triple {2137#(< (mod (+ main_~y~0 45) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2133#(< (mod (+ 44 main_~y~0) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,581 INFO L290 TraceCheckUtils]: 6: Hoare triple {2141#(< (mod (+ main_~y~0 46) 4294967296) 1024)} [47] L16-2-->L16-2: Formula: (and (= v_main_~x~0_1 0) (= v_main_~y~0_1 (+ v_main_~y~0_2 1)) (< (mod v_main_~y~0_2 4294967296) 1024)) InVars {main_~y~0=v_main_~y~0_2} OutVars{main_#t~post4=|v_main_#t~post4_1|, main_~y~0=v_main_~y~0_1, main_~x~0=v_main_~x~0_1} AuxVars[] AssignedVars[main_~x~0, main_#t~post4, main_~y~0] {2137#(< (mod (+ main_~y~0 45) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,581 INFO L290 TraceCheckUtils]: 5: Hoare triple {1720#true} [43] mainENTRY-->L16-2: Formula: (and (= v_main_~x~0_3 1) (= v_main_~y~0_3 0)) InVars {} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_3} AuxVars[] AssignedVars[main_~x~0, main_~y~0] {2141#(< (mod (+ main_~y~0 46) 4294967296) 1024)} is VALID [2022-04-27 21:22:20,581 INFO L272 TraceCheckUtils]: 4: Hoare triple {1720#true} [40] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:20,581 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1720#true} {1720#true} [56] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:20,582 INFO L290 TraceCheckUtils]: 2: Hoare triple {1720#true} [44] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:20,582 INFO L290 TraceCheckUtils]: 1: Hoare triple {1720#true} [41] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#length_1| 2) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1720#true} is VALID [2022-04-27 21:22:20,582 INFO L272 TraceCheckUtils]: 0: Hoare triple {1720#true} [39] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1720#true} is VALID [2022-04-27 21:22:20,582 INFO L134 CoverageAnalysis]: Checked inductivity of 1081 backedges. 0 proven. 1081 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:22:20,583 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2082617450] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:22:20,583 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:22:20,583 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49, 49] total 98 [2022-04-27 21:22:20,583 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1391316875] [2022-04-27 21:22:20,583 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:22:20,584 INFO L78 Accepts]: Start accepts. Automaton has has 98 states, 98 states have (on average 1.0612244897959184) internal successors, (104), 97 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 57 [2022-04-27 21:22:20,584 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:22:20,584 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 98 states, 98 states have (on average 1.0612244897959184) internal successors, (104), 97 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:22:20,653 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 109 edges. 109 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:22:20,653 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 98 states [2022-04-27 21:22:20,653 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:22:20,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2022-04-27 21:22:20,656 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=2496, Invalid=7010, Unknown=0, NotChecked=0, Total=9506 [2022-04-27 21:22:20,656 INFO L87 Difference]: Start difference. First operand 58 states and 58 transitions. Second operand has 98 states, 98 states have (on average 1.0612244897959184) internal successors, (104), 97 states have internal predecessors, (104), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:23:02,349 WARN L232 SmtUtils]: Spent 5.99s on a formula simplification. DAG size of input: 196 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 21:23:36,570 WARN L232 SmtUtils]: Spent 7.21s on a formula simplification. DAG size of input: 192 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 21:24:16,062 WARN L232 SmtUtils]: Spent 6.31s on a formula simplification. DAG size of input: 188 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 21:24:18,107 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (< (mod (+ c_main_~y~0 24) 4294967296) 1024) (< (mod (+ 23 c_main_~y~0) 4294967296) 1024) (< (mod (+ 22 c_main_~y~0) 4294967296) 1024) (< (mod (+ 17 c_main_~y~0) 4294967296) 1024) (< (mod (+ 32 c_main_~y~0) 4294967296) 1024) (< (mod (+ 34 c_main_~y~0) 4294967296) 1024) (< (mod (+ 5 c_main_~y~0) 4294967296) 1024) (< (mod c_main_~y~0 4294967296) 1024) (< (mod (+ 21 c_main_~y~0) 4294967296) 1024) (< (mod (+ 16 c_main_~y~0) 4294967296) 1024) (< (mod (+ 7 c_main_~y~0) 4294967296) 1024) (< (mod (+ 4 c_main_~y~0) 4294967296) 1024) (< (mod (+ 9 c_main_~y~0) 4294967296) 1024) (< (mod (+ 42 c_main_~y~0) 4294967296) 1024) (< (mod (+ 3 c_main_~y~0) 4294967296) 1024) (< (mod (+ 20 c_main_~y~0) 4294967296) 1024) (< (mod (+ c_main_~y~0 1) 4294967296) 1024) (< (mod (+ 31 c_main_~y~0) 4294967296) 1024) (< (mod (+ 15 c_main_~y~0) 4294967296) 1024) (< (mod (+ 30 c_main_~y~0) 4294967296) 1024) (< (mod (+ 37 c_main_~y~0) 4294967296) 1024) (< (mod (+ 12 c_main_~y~0) 4294967296) 1024) (< (mod (+ c_main_~y~0 27) 4294967296) 1024) (< (mod (+ 6 c_main_~y~0) 4294967296) 1024) (< (mod (+ 14 c_main_~y~0) 4294967296) 1024) (< (mod (+ 40 c_main_~y~0) 4294967296) 1024) (< (mod (+ 10 c_main_~y~0) 4294967296) 1024) (< (mod (+ 38 c_main_~y~0) 4294967296) 1024) (< (mod (+ 13 c_main_~y~0) 4294967296) 1024) (< (mod (+ 11 c_main_~y~0) 4294967296) 1024) (< (mod (+ 41 c_main_~y~0) 4294967296) 1024) (< (mod (+ 36 c_main_~y~0) 4294967296) 1024) (< (mod (+ 18 c_main_~y~0) 4294967296) 1024) (< (mod (+ 25 c_main_~y~0) 4294967296) 1024) (< (mod (+ 28 c_main_~y~0) 4294967296) 1024) (< (mod (+ 33 c_main_~y~0) 4294967296) 1024) (< (mod (+ 29 c_main_~y~0) 4294967296) 1024) (< (mod (+ 35 c_main_~y~0) 4294967296) 1024) (< (mod (+ 8 c_main_~y~0) 4294967296) 1024) (< (mod (+ 19 c_main_~y~0) 4294967296) 1024) (< (mod (+ 39 c_main_~y~0) 4294967296) 1024) (< (mod (+ 43 c_main_~y~0) 4294967296) 1024) (= |c_#NULL.offset| |c_old(#NULL.offset)|) (< (mod (+ 26 c_main_~y~0) 4294967296) 1024) (< (mod (+ 2 c_main_~y~0) 4294967296) 1024)) is different from false [2022-04-27 21:25:57,835 WARN L232 SmtUtils]: Spent 5.11s on a formula simplification. DAG size of input: 176 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 21:26:48,408 WARN L232 SmtUtils]: Spent 6.17s on a formula simplification. DAG size of input: 172 DAG size of output: 16 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate)