/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loop-acceleration/diamond_1-2.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 21:20:20,638 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 21:20:20,640 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 21:20:20,661 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 21:20:20,661 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 21:20:20,662 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 21:20:20,666 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 21:20:20,670 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 21:20:20,672 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 21:20:20,679 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 21:20:20,680 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 21:20:20,680 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 21:20:20,681 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 21:20:20,681 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 21:20:20,682 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 21:20:20,682 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 21:20:20,683 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 21:20:20,683 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 21:20:20,687 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 21:20:20,690 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 21:20:20,691 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 21:20:20,692 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 21:20:20,692 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 21:20:20,693 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 21:20:20,694 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 21:20:20,697 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 21:20:20,702 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 21:20:20,703 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 21:20:20,704 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 21:20:20,704 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-27 21:20:20,725 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 21:20:20,725 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 21:20:20,726 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-27 21:20:20,726 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-27 21:20:20,727 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-27 21:20:20,727 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-27 21:20:20,727 INFO L138 SettingsManager]: * Use SBE=true [2022-04-27 21:20:20,727 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 21:20:20,727 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 21:20:20,728 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 21:20:20,729 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 21:20:20,729 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 21:20:20,729 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 21:20:20,729 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:20:20,729 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 21:20:20,729 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-27 21:20:20,729 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-27 21:20:20,730 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 21:20:20,730 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-27 21:20:20,730 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-27 21:20:20,730 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-27 21:20:20,730 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-27 21:20:20,731 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 21:20:20,731 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 21:20:20,903 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 21:20:20,920 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 21:20:20,922 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 21:20:20,923 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 21:20:20,923 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 21:20:20,924 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/diamond_1-2.c [2022-04-27 21:20:20,966 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/99cea50d2/23fe3354ee8943c3b24214a57d5a5ef0/FLAG426ddf175 [2022-04-27 21:20:21,324 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 21:20:21,324 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/diamond_1-2.c [2022-04-27 21:20:21,329 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/99cea50d2/23fe3354ee8943c3b24214a57d5a5ef0/FLAG426ddf175 [2022-04-27 21:20:21,336 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/99cea50d2/23fe3354ee8943c3b24214a57d5a5ef0 [2022-04-27 21:20:21,338 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 21:20:21,339 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 21:20:21,340 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 21:20:21,340 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 21:20:21,343 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 21:20:21,346 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,347 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@779b8d9b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21, skipping insertion in model container [2022-04-27 21:20:21,347 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,352 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 21:20:21,360 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 21:20:21,498 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/diamond_1-2.c[373,386] [2022-04-27 21:20:21,510 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:20:21,515 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 21:20:21,523 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/diamond_1-2.c[373,386] [2022-04-27 21:20:21,525 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:20:21,533 INFO L208 MainTranslator]: Completed translation [2022-04-27 21:20:21,534 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21 WrapperNode [2022-04-27 21:20:21,534 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 21:20:21,535 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 21:20:21,536 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 21:20:21,536 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 21:20:21,542 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,543 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,547 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,547 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,557 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,560 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,561 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,563 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 21:20:21,564 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 21:20:21,564 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 21:20:21,564 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 21:20:21,565 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,570 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:20:21,576 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:21,585 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 21:20:21,600 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 21:20:21,619 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 21:20:21,620 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 21:20:21,620 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 21:20:21,620 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 21:20:21,620 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 21:20:21,621 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 21:20:21,621 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 21:20:21,621 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 21:20:21,622 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 21:20:21,662 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 21:20:21,665 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 21:20:21,790 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 21:20:21,794 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 21:20:21,794 INFO L299 CfgBuilder]: Removed 1 assume(true) statements. [2022-04-27 21:20:21,795 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:20:21 BoogieIcfgContainer [2022-04-27 21:20:21,795 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 21:20:21,796 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 21:20:21,796 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 21:20:21,797 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 21:20:21,802 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:20:21" (1/1) ... [2022-04-27 21:20:21,804 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-27 21:20:21,832 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:20:21 BasicIcfg [2022-04-27 21:20:21,832 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 21:20:21,833 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 21:20:21,833 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 21:20:21,835 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 21:20:21,835 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 09:20:21" (1/4) ... [2022-04-27 21:20:21,836 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ee17edc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:20:21, skipping insertion in model container [2022-04-27 21:20:21,836 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:20:21" (2/4) ... [2022-04-27 21:20:21,836 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ee17edc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:20:21, skipping insertion in model container [2022-04-27 21:20:21,836 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:20:21" (3/4) ... [2022-04-27 21:20:21,836 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5ee17edc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 09:20:21, skipping insertion in model container [2022-04-27 21:20:21,837 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:20:21" (4/4) ... [2022-04-27 21:20:21,837 INFO L111 eAbstractionObserver]: Analyzing ICFG diamond_1-2.cqvasr [2022-04-27 21:20:21,846 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-27 21:20:21,846 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 21:20:21,898 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 21:20:21,902 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@37e8cfcd, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@ffde458 [2022-04-27 21:20:21,903 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 21:20:21,908 INFO L276 IsEmpty]: Start isEmpty. Operand has 19 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 12 states have internal predecessors, (16), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:20:21,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-27 21:20:21,912 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:21,913 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:21,913 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:21,917 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:21,917 INFO L85 PathProgramCache]: Analyzing trace with hash -756157467, now seen corresponding path program 1 times [2022-04-27 21:20:21,923 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:21,924 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802343421] [2022-04-27 21:20:21,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:21,924 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:21,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,057 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:22,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,081 INFO L290 TraceCheckUtils]: 0: Hoare triple {27#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {22#true} is VALID [2022-04-27 21:20:22,081 INFO L290 TraceCheckUtils]: 1: Hoare triple {22#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#true} is VALID [2022-04-27 21:20:22,081 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {22#true} {22#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#true} is VALID [2022-04-27 21:20:22,084 INFO L272 TraceCheckUtils]: 0: Hoare triple {22#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {27#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:22,085 INFO L290 TraceCheckUtils]: 1: Hoare triple {27#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {22#true} is VALID [2022-04-27 21:20:22,085 INFO L290 TraceCheckUtils]: 2: Hoare triple {22#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#true} is VALID [2022-04-27 21:20:22,085 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {22#true} {22#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#true} is VALID [2022-04-27 21:20:22,086 INFO L272 TraceCheckUtils]: 4: Hoare triple {22#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {22#true} is VALID [2022-04-27 21:20:22,086 INFO L290 TraceCheckUtils]: 5: Hoare triple {22#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {22#true} is VALID [2022-04-27 21:20:22,087 INFO L290 TraceCheckUtils]: 6: Hoare triple {22#true} [51] L18-2-->L17-2: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {23#false} is VALID [2022-04-27 21:20:22,087 INFO L272 TraceCheckUtils]: 7: Hoare triple {23#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {23#false} is VALID [2022-04-27 21:20:22,087 INFO L290 TraceCheckUtils]: 8: Hoare triple {23#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {23#false} is VALID [2022-04-27 21:20:22,087 INFO L290 TraceCheckUtils]: 9: Hoare triple {23#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {23#false} is VALID [2022-04-27 21:20:22,088 INFO L290 TraceCheckUtils]: 10: Hoare triple {23#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {23#false} is VALID [2022-04-27 21:20:22,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:22,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:22,089 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802343421] [2022-04-27 21:20:22,090 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802343421] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:20:22,090 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:20:22,090 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 21:20:22,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1165572257] [2022-04-27 21:20:22,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:20:22,095 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:22,096 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:22,098 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,114 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 11 edges. 11 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:22,114 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 21:20:22,115 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:22,131 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 21:20:22,132 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:20:22,134 INFO L87 Difference]: Start difference. First operand has 19 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 12 states have internal predecessors, (16), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:22,203 INFO L93 Difference]: Finished difference Result 30 states and 34 transitions. [2022-04-27 21:20:22,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 21:20:22,203 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:22,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:22,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-27 21:20:22,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 34 transitions. [2022-04-27 21:20:22,216 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 34 transitions. [2022-04-27 21:20:22,279 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 34 edges. 34 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:22,284 INFO L225 Difference]: With dead ends: 30 [2022-04-27 21:20:22,284 INFO L226 Difference]: Without dead ends: 13 [2022-04-27 21:20:22,286 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:20:22,288 INFO L413 NwaCegarLoop]: 19 mSDtfsCounter, 11 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 12 SdHoareTripleChecker+Valid, 22 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:22,289 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [12 Valid, 22 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:22,307 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2022-04-27 21:20:22,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2022-04-27 21:20:22,315 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:22,315 INFO L82 GeneralOperation]: Start isEquivalent. First operand 13 states. Second operand has 13 states, 8 states have (on average 1.25) internal successors, (10), 8 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,316 INFO L74 IsIncluded]: Start isIncluded. First operand 13 states. Second operand has 13 states, 8 states have (on average 1.25) internal successors, (10), 8 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,316 INFO L87 Difference]: Start difference. First operand 13 states. Second operand has 13 states, 8 states have (on average 1.25) internal successors, (10), 8 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:22,317 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2022-04-27 21:20:22,318 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 14 transitions. [2022-04-27 21:20:22,318 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:22,318 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:22,318 INFO L74 IsIncluded]: Start isIncluded. First operand has 13 states, 8 states have (on average 1.25) internal successors, (10), 8 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 13 states. [2022-04-27 21:20:22,319 INFO L87 Difference]: Start difference. First operand has 13 states, 8 states have (on average 1.25) internal successors, (10), 8 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 13 states. [2022-04-27 21:20:22,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:22,321 INFO L93 Difference]: Finished difference Result 13 states and 14 transitions. [2022-04-27 21:20:22,321 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 14 transitions. [2022-04-27 21:20:22,321 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:22,321 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:22,321 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:22,321 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:22,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13 states, 8 states have (on average 1.25) internal successors, (10), 8 states have internal predecessors, (10), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2022-04-27 21:20:22,340 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 14 transitions. Word has length 11 [2022-04-27 21:20:22,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:22,340 INFO L495 AbstractCegarLoop]: Abstraction has 13 states and 14 transitions. [2022-04-27 21:20:22,341 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 2.3333333333333335) internal successors, (7), 2 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,341 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 14 transitions. [2022-04-27 21:20:22,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2022-04-27 21:20:22,341 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:22,342 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:22,342 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 21:20:22,342 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:22,343 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:22,343 INFO L85 PathProgramCache]: Analyzing trace with hash -755233946, now seen corresponding path program 1 times [2022-04-27 21:20:22,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:22,343 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090368100] [2022-04-27 21:20:22,343 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:22,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:22,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,415 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:22,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,423 INFO L290 TraceCheckUtils]: 0: Hoare triple {121#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {115#true} is VALID [2022-04-27 21:20:22,424 INFO L290 TraceCheckUtils]: 1: Hoare triple {115#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 21:20:22,424 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {115#true} {115#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 21:20:22,425 INFO L272 TraceCheckUtils]: 0: Hoare triple {115#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {121#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:22,425 INFO L290 TraceCheckUtils]: 1: Hoare triple {121#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {115#true} is VALID [2022-04-27 21:20:22,425 INFO L290 TraceCheckUtils]: 2: Hoare triple {115#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 21:20:22,427 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {115#true} {115#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 21:20:22,427 INFO L272 TraceCheckUtils]: 4: Hoare triple {115#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {115#true} is VALID [2022-04-27 21:20:22,428 INFO L290 TraceCheckUtils]: 5: Hoare triple {115#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {120#(= main_~x~0 0)} is VALID [2022-04-27 21:20:22,428 INFO L290 TraceCheckUtils]: 6: Hoare triple {120#(= main_~x~0 0)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-27 21:20:22,428 INFO L272 TraceCheckUtils]: 7: Hoare triple {116#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {116#false} is VALID [2022-04-27 21:20:22,429 INFO L290 TraceCheckUtils]: 8: Hoare triple {116#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {116#false} is VALID [2022-04-27 21:20:22,429 INFO L290 TraceCheckUtils]: 9: Hoare triple {116#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-27 21:20:22,429 INFO L290 TraceCheckUtils]: 10: Hoare triple {116#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {116#false} is VALID [2022-04-27 21:20:22,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:22,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:22,429 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090368100] [2022-04-27 21:20:22,430 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090368100] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:20:22,430 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:20:22,430 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 21:20:22,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1071966906] [2022-04-27 21:20:22,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:20:22,431 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:22,431 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:22,431 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,452 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 11 edges. 11 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:22,452 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 21:20:22,452 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:22,453 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 21:20:22,453 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 21:20:22,453 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. Second operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:22,501 INFO L93 Difference]: Finished difference Result 20 states and 22 transitions. [2022-04-27 21:20:22,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 21:20:22,502 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 11 [2022-04-27 21:20:22,502 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:22,502 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 22 transitions. [2022-04-27 21:20:22,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,510 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 22 transitions. [2022-04-27 21:20:22,510 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 22 transitions. [2022-04-27 21:20:22,543 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 22 edges. 22 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:22,544 INFO L225 Difference]: With dead ends: 20 [2022-04-27 21:20:22,544 INFO L226 Difference]: Without dead ends: 15 [2022-04-27 21:20:22,544 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 21:20:22,545 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 10 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 12 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 18 SdHoareTripleChecker+Invalid, 16 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 12 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:22,546 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 18 Invalid, 16 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 12 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:22,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2022-04-27 21:20:22,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 14. [2022-04-27 21:20:22,549 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:22,549 INFO L82 GeneralOperation]: Start isEquivalent. First operand 15 states. Second operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 9 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,550 INFO L74 IsIncluded]: Start isIncluded. First operand 15 states. Second operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 9 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,550 INFO L87 Difference]: Start difference. First operand 15 states. Second operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 9 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:22,552 INFO L93 Difference]: Finished difference Result 15 states and 17 transitions. [2022-04-27 21:20:22,552 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 17 transitions. [2022-04-27 21:20:22,552 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:22,552 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:22,553 INFO L74 IsIncluded]: Start isIncluded. First operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 9 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 15 states. [2022-04-27 21:20:22,553 INFO L87 Difference]: Start difference. First operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 9 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 15 states. [2022-04-27 21:20:22,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:22,555 INFO L93 Difference]: Finished difference Result 15 states and 17 transitions. [2022-04-27 21:20:22,555 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 17 transitions. [2022-04-27 21:20:22,555 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:22,555 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:22,555 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:22,555 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:22,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 9 states have (on average 1.2222222222222223) internal successors, (11), 9 states have internal predecessors, (11), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 15 transitions. [2022-04-27 21:20:22,557 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 15 transitions. Word has length 11 [2022-04-27 21:20:22,558 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:22,558 INFO L495 AbstractCegarLoop]: Abstraction has 14 states and 15 transitions. [2022-04-27 21:20:22,558 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 1.75) internal successors, (7), 3 states have internal predecessors, (7), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,558 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 15 transitions. [2022-04-27 21:20:22,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2022-04-27 21:20:22,559 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:22,559 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:22,559 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 21:20:22,559 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:22,560 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:22,560 INFO L85 PathProgramCache]: Analyzing trace with hash 980092676, now seen corresponding path program 1 times [2022-04-27 21:20:22,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:22,560 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1448225957] [2022-04-27 21:20:22,560 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:22,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:22,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,686 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:22,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,693 INFO L290 TraceCheckUtils]: 0: Hoare triple {215#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {208#true} is VALID [2022-04-27 21:20:22,693 INFO L290 TraceCheckUtils]: 1: Hoare triple {208#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,694 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {208#true} {208#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,694 INFO L272 TraceCheckUtils]: 0: Hoare triple {208#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {215#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:22,694 INFO L290 TraceCheckUtils]: 1: Hoare triple {215#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {208#true} is VALID [2022-04-27 21:20:22,694 INFO L290 TraceCheckUtils]: 2: Hoare triple {208#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,695 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {208#true} {208#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,695 INFO L272 TraceCheckUtils]: 4: Hoare triple {208#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,697 INFO L290 TraceCheckUtils]: 5: Hoare triple {208#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {213#(= main_~x~0 0)} is VALID [2022-04-27 21:20:22,697 INFO L290 TraceCheckUtils]: 6: Hoare triple {213#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {213#(= main_~x~0 0)} is VALID [2022-04-27 21:20:22,698 INFO L290 TraceCheckUtils]: 7: Hoare triple {213#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {214#(and (<= main_~x~0 1) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:20:22,699 INFO L290 TraceCheckUtils]: 8: Hoare triple {214#(and (<= main_~x~0 1) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,699 INFO L272 TraceCheckUtils]: 9: Hoare triple {209#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {209#false} is VALID [2022-04-27 21:20:22,699 INFO L290 TraceCheckUtils]: 10: Hoare triple {209#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {209#false} is VALID [2022-04-27 21:20:22,699 INFO L290 TraceCheckUtils]: 11: Hoare triple {209#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,699 INFO L290 TraceCheckUtils]: 12: Hoare triple {209#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,700 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:22,700 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:22,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1448225957] [2022-04-27 21:20:22,700 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1448225957] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:22,700 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1749500505] [2022-04-27 21:20:22,701 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:22,701 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:22,701 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:22,708 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:22,715 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 21:20:22,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,741 INFO L263 TraceCheckSpWp]: Trace formula consists of 58 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 21:20:22,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:22,755 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:22,808 INFO L272 TraceCheckUtils]: 0: Hoare triple {208#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,809 INFO L290 TraceCheckUtils]: 1: Hoare triple {208#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {208#true} is VALID [2022-04-27 21:20:22,809 INFO L290 TraceCheckUtils]: 2: Hoare triple {208#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,809 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {208#true} {208#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,809 INFO L272 TraceCheckUtils]: 4: Hoare triple {208#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,809 INFO L290 TraceCheckUtils]: 5: Hoare triple {208#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {213#(= main_~x~0 0)} is VALID [2022-04-27 21:20:22,810 INFO L290 TraceCheckUtils]: 6: Hoare triple {213#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {213#(= main_~x~0 0)} is VALID [2022-04-27 21:20:22,810 INFO L290 TraceCheckUtils]: 7: Hoare triple {213#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {240#(= main_~x~0 1)} is VALID [2022-04-27 21:20:22,811 INFO L290 TraceCheckUtils]: 8: Hoare triple {240#(= main_~x~0 1)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,811 INFO L272 TraceCheckUtils]: 9: Hoare triple {209#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {209#false} is VALID [2022-04-27 21:20:22,811 INFO L290 TraceCheckUtils]: 10: Hoare triple {209#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {209#false} is VALID [2022-04-27 21:20:22,811 INFO L290 TraceCheckUtils]: 11: Hoare triple {209#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,812 INFO L290 TraceCheckUtils]: 12: Hoare triple {209#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,812 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:22,812 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:22,872 INFO L290 TraceCheckUtils]: 12: Hoare triple {209#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,872 INFO L290 TraceCheckUtils]: 11: Hoare triple {209#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,872 INFO L290 TraceCheckUtils]: 10: Hoare triple {209#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {209#false} is VALID [2022-04-27 21:20:22,872 INFO L272 TraceCheckUtils]: 9: Hoare triple {209#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {209#false} is VALID [2022-04-27 21:20:22,873 INFO L290 TraceCheckUtils]: 8: Hoare triple {268#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {209#false} is VALID [2022-04-27 21:20:22,874 INFO L290 TraceCheckUtils]: 7: Hoare triple {272#(< (mod (+ main_~x~0 1) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {268#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:20:22,874 INFO L290 TraceCheckUtils]: 6: Hoare triple {272#(< (mod (+ main_~x~0 1) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {272#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:20:22,875 INFO L290 TraceCheckUtils]: 5: Hoare triple {208#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {272#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:20:22,875 INFO L272 TraceCheckUtils]: 4: Hoare triple {208#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,875 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {208#true} {208#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,875 INFO L290 TraceCheckUtils]: 2: Hoare triple {208#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,875 INFO L290 TraceCheckUtils]: 1: Hoare triple {208#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {208#true} is VALID [2022-04-27 21:20:22,876 INFO L272 TraceCheckUtils]: 0: Hoare triple {208#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {208#true} is VALID [2022-04-27 21:20:22,876 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:22,879 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1749500505] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:22,879 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:22,879 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4, 4] total 8 [2022-04-27 21:20:22,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747482305] [2022-04-27 21:20:22,879 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:22,880 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 13 [2022-04-27 21:20:22,880 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:22,881 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:22,897 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 21 edges. 21 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:22,898 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 8 states [2022-04-27 21:20:22,898 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:22,898 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2022-04-27 21:20:22,898 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2022-04-27 21:20:22,899 INFO L87 Difference]: Start difference. First operand 14 states and 15 transitions. Second operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:23,058 INFO L93 Difference]: Finished difference Result 25 states and 31 transitions. [2022-04-27 21:20:23,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:20:23,058 INFO L78 Accepts]: Start accepts. Automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 13 [2022-04-27 21:20:23,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:23,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 31 transitions. [2022-04-27 21:20:23,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 31 transitions. [2022-04-27 21:20:23,066 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 31 transitions. [2022-04-27 21:20:23,091 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:23,093 INFO L225 Difference]: With dead ends: 25 [2022-04-27 21:20:23,093 INFO L226 Difference]: Without dead ends: 20 [2022-04-27 21:20:23,094 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 26 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=83, Unknown=0, NotChecked=0, Total=132 [2022-04-27 21:20:23,097 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 15 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 35 mSolverCounterSat, 18 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 28 SdHoareTripleChecker+Invalid, 53 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 18 IncrementalHoareTripleChecker+Valid, 35 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:23,098 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 28 Invalid, 53 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [18 Valid, 35 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:20:23,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2022-04-27 21:20:23,107 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2022-04-27 21:20:23,107 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:23,108 INFO L82 GeneralOperation]: Start isEquivalent. First operand 20 states. Second operand has 20 states, 15 states have (on average 1.3333333333333333) internal successors, (20), 15 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,108 INFO L74 IsIncluded]: Start isIncluded. First operand 20 states. Second operand has 20 states, 15 states have (on average 1.3333333333333333) internal successors, (20), 15 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,109 INFO L87 Difference]: Start difference. First operand 20 states. Second operand has 20 states, 15 states have (on average 1.3333333333333333) internal successors, (20), 15 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:23,110 INFO L93 Difference]: Finished difference Result 20 states and 24 transitions. [2022-04-27 21:20:23,111 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2022-04-27 21:20:23,111 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:23,111 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:23,112 INFO L74 IsIncluded]: Start isIncluded. First operand has 20 states, 15 states have (on average 1.3333333333333333) internal successors, (20), 15 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 20 states. [2022-04-27 21:20:23,113 INFO L87 Difference]: Start difference. First operand has 20 states, 15 states have (on average 1.3333333333333333) internal successors, (20), 15 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 20 states. [2022-04-27 21:20:23,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:23,114 INFO L93 Difference]: Finished difference Result 20 states and 24 transitions. [2022-04-27 21:20:23,115 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2022-04-27 21:20:23,115 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:23,115 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:23,115 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:23,115 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:23,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 15 states have (on average 1.3333333333333333) internal successors, (20), 15 states have internal predecessors, (20), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 24 transitions. [2022-04-27 21:20:23,116 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 24 transitions. Word has length 13 [2022-04-27 21:20:23,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:23,117 INFO L495 AbstractCegarLoop]: Abstraction has 20 states and 24 transitions. [2022-04-27 21:20:23,117 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 8 states, 8 states have (on average 2.0) internal successors, (16), 7 states have internal predecessors, (16), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,117 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 24 transitions. [2022-04-27 21:20:23,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 21:20:23,118 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:23,118 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:23,134 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 21:20:23,318 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:23,319 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:23,319 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:23,319 INFO L85 PathProgramCache]: Analyzing trace with hash -341862240, now seen corresponding path program 1 times [2022-04-27 21:20:23,319 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:23,320 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839682914] [2022-04-27 21:20:23,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:23,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:23,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:23,400 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:23,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:23,421 INFO L290 TraceCheckUtils]: 0: Hoare triple {421#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {413#true} is VALID [2022-04-27 21:20:23,422 INFO L290 TraceCheckUtils]: 1: Hoare triple {413#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,422 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {413#true} {413#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,423 INFO L272 TraceCheckUtils]: 0: Hoare triple {413#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {421#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:23,423 INFO L290 TraceCheckUtils]: 1: Hoare triple {421#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {413#true} is VALID [2022-04-27 21:20:23,423 INFO L290 TraceCheckUtils]: 2: Hoare triple {413#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,423 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {413#true} {413#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,423 INFO L272 TraceCheckUtils]: 4: Hoare triple {413#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,424 INFO L290 TraceCheckUtils]: 5: Hoare triple {413#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {418#(= main_~x~0 0)} is VALID [2022-04-27 21:20:23,424 INFO L290 TraceCheckUtils]: 6: Hoare triple {418#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {418#(= main_~x~0 0)} is VALID [2022-04-27 21:20:23,425 INFO L290 TraceCheckUtils]: 7: Hoare triple {418#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:23,425 INFO L290 TraceCheckUtils]: 8: Hoare triple {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:23,426 INFO L290 TraceCheckUtils]: 9: Hoare triple {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {420#(and (<= main_~x~0 4) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:20:23,426 INFO L290 TraceCheckUtils]: 10: Hoare triple {420#(and (<= main_~x~0 4) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,427 INFO L272 TraceCheckUtils]: 11: Hoare triple {414#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {414#false} is VALID [2022-04-27 21:20:23,427 INFO L290 TraceCheckUtils]: 12: Hoare triple {414#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {414#false} is VALID [2022-04-27 21:20:23,427 INFO L290 TraceCheckUtils]: 13: Hoare triple {414#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,427 INFO L290 TraceCheckUtils]: 14: Hoare triple {414#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,427 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:23,427 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:23,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839682914] [2022-04-27 21:20:23,428 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839682914] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:23,428 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2070234924] [2022-04-27 21:20:23,428 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:23,428 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:23,428 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:23,429 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:23,432 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 21:20:23,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:23,459 INFO L263 TraceCheckSpWp]: Trace formula consists of 61 conjuncts, 7 conjunts are in the unsatisfiable core [2022-04-27 21:20:23,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:23,463 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:23,683 INFO L272 TraceCheckUtils]: 0: Hoare triple {413#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,683 INFO L290 TraceCheckUtils]: 1: Hoare triple {413#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {413#true} is VALID [2022-04-27 21:20:23,684 INFO L290 TraceCheckUtils]: 2: Hoare triple {413#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,684 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {413#true} {413#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,684 INFO L272 TraceCheckUtils]: 4: Hoare triple {413#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,684 INFO L290 TraceCheckUtils]: 5: Hoare triple {413#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {418#(= main_~x~0 0)} is VALID [2022-04-27 21:20:23,685 INFO L290 TraceCheckUtils]: 6: Hoare triple {418#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {418#(= main_~x~0 0)} is VALID [2022-04-27 21:20:23,686 INFO L290 TraceCheckUtils]: 7: Hoare triple {418#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:23,686 INFO L290 TraceCheckUtils]: 8: Hoare triple {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:23,687 INFO L290 TraceCheckUtils]: 9: Hoare triple {419#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {452#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:23,687 INFO L290 TraceCheckUtils]: 10: Hoare triple {452#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,688 INFO L272 TraceCheckUtils]: 11: Hoare triple {414#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {414#false} is VALID [2022-04-27 21:20:23,688 INFO L290 TraceCheckUtils]: 12: Hoare triple {414#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {414#false} is VALID [2022-04-27 21:20:23,688 INFO L290 TraceCheckUtils]: 13: Hoare triple {414#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,688 INFO L290 TraceCheckUtils]: 14: Hoare triple {414#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,688 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:23,688 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:23,762 INFO L290 TraceCheckUtils]: 14: Hoare triple {414#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,763 INFO L290 TraceCheckUtils]: 13: Hoare triple {414#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,763 INFO L290 TraceCheckUtils]: 12: Hoare triple {414#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {414#false} is VALID [2022-04-27 21:20:23,763 INFO L272 TraceCheckUtils]: 11: Hoare triple {414#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {414#false} is VALID [2022-04-27 21:20:23,764 INFO L290 TraceCheckUtils]: 10: Hoare triple {480#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {414#false} is VALID [2022-04-27 21:20:23,765 INFO L290 TraceCheckUtils]: 9: Hoare triple {484#(< (mod (+ main_~x~0 2) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {480#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:20:23,766 INFO L290 TraceCheckUtils]: 8: Hoare triple {484#(< (mod (+ main_~x~0 2) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {484#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:23,767 INFO L290 TraceCheckUtils]: 7: Hoare triple {491#(< (mod (+ main_~x~0 4) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {484#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:23,768 INFO L290 TraceCheckUtils]: 6: Hoare triple {491#(< (mod (+ main_~x~0 4) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {491#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:23,768 INFO L290 TraceCheckUtils]: 5: Hoare triple {413#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {491#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:23,769 INFO L272 TraceCheckUtils]: 4: Hoare triple {413#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,769 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {413#true} {413#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,769 INFO L290 TraceCheckUtils]: 2: Hoare triple {413#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,769 INFO L290 TraceCheckUtils]: 1: Hoare triple {413#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {413#true} is VALID [2022-04-27 21:20:23,769 INFO L272 TraceCheckUtils]: 0: Hoare triple {413#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {413#true} is VALID [2022-04-27 21:20:23,769 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:23,770 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2070234924] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:23,770 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:23,770 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5] total 10 [2022-04-27 21:20:23,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236216508] [2022-04-27 21:20:23,770 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:23,771 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:20:23,771 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:23,771 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:23,792 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 25 edges. 25 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:23,792 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 21:20:23,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:23,792 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 21:20:23,793 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=58, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:20:23,793 INFO L87 Difference]: Start difference. First operand 20 states and 24 transitions. Second operand has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:24,176 INFO L93 Difference]: Finished difference Result 36 states and 48 transitions. [2022-04-27 21:20:24,176 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 21:20:24,177 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:20:24,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:24,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 41 transitions. [2022-04-27 21:20:24,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 41 transitions. [2022-04-27 21:20:24,179 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 41 transitions. [2022-04-27 21:20:24,215 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:24,216 INFO L225 Difference]: With dead ends: 36 [2022-04-27 21:20:24,216 INFO L226 Difference]: Without dead ends: 31 [2022-04-27 21:20:24,217 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 28 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=96, Invalid=176, Unknown=0, NotChecked=0, Total=272 [2022-04-27 21:20:24,217 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 17 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 76 mSolverCounterSat, 24 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 17 SdHoareTripleChecker+Valid, 43 SdHoareTripleChecker+Invalid, 100 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 24 IncrementalHoareTripleChecker+Valid, 76 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:24,218 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [17 Valid, 43 Invalid, 100 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [24 Valid, 76 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:20:24,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2022-04-27 21:20:24,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 24. [2022-04-27 21:20:24,236 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:24,236 INFO L82 GeneralOperation]: Start isEquivalent. First operand 31 states. Second operand has 24 states, 19 states have (on average 1.368421052631579) internal successors, (26), 19 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,236 INFO L74 IsIncluded]: Start isIncluded. First operand 31 states. Second operand has 24 states, 19 states have (on average 1.368421052631579) internal successors, (26), 19 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,236 INFO L87 Difference]: Start difference. First operand 31 states. Second operand has 24 states, 19 states have (on average 1.368421052631579) internal successors, (26), 19 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,238 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:24,238 INFO L93 Difference]: Finished difference Result 31 states and 40 transitions. [2022-04-27 21:20:24,238 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 40 transitions. [2022-04-27 21:20:24,238 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:24,238 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:24,239 INFO L74 IsIncluded]: Start isIncluded. First operand has 24 states, 19 states have (on average 1.368421052631579) internal successors, (26), 19 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 31 states. [2022-04-27 21:20:24,239 INFO L87 Difference]: Start difference. First operand has 24 states, 19 states have (on average 1.368421052631579) internal successors, (26), 19 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 31 states. [2022-04-27 21:20:24,240 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:24,240 INFO L93 Difference]: Finished difference Result 31 states and 40 transitions. [2022-04-27 21:20:24,240 INFO L276 IsEmpty]: Start isEmpty. Operand 31 states and 40 transitions. [2022-04-27 21:20:24,240 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:24,240 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:24,241 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:24,241 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:24,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 19 states have (on average 1.368421052631579) internal successors, (26), 19 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,242 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 30 transitions. [2022-04-27 21:20:24,242 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 30 transitions. Word has length 15 [2022-04-27 21:20:24,242 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:24,242 INFO L495 AbstractCegarLoop]: Abstraction has 24 states and 30 transitions. [2022-04-27 21:20:24,242 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.0) internal successors, (20), 9 states have internal predecessors, (20), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:24,242 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 30 transitions. [2022-04-27 21:20:24,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2022-04-27 21:20:24,243 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:24,243 INFO L195 NwaCegarLoop]: trace histogram [5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:24,261 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:24,459 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 21:20:24,459 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:24,460 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:24,460 INFO L85 PathProgramCache]: Analyzing trace with hash 265640572, now seen corresponding path program 2 times [2022-04-27 21:20:24,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:24,460 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678366771] [2022-04-27 21:20:24,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:24,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:24,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:24,561 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:24,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:24,565 INFO L290 TraceCheckUtils]: 0: Hoare triple {694#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {683#true} is VALID [2022-04-27 21:20:24,566 INFO L290 TraceCheckUtils]: 1: Hoare triple {683#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,566 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {683#true} {683#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,566 INFO L272 TraceCheckUtils]: 0: Hoare triple {683#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {694#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:24,566 INFO L290 TraceCheckUtils]: 1: Hoare triple {694#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {683#true} is VALID [2022-04-27 21:20:24,567 INFO L290 TraceCheckUtils]: 2: Hoare triple {683#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,567 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {683#true} {683#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,567 INFO L272 TraceCheckUtils]: 4: Hoare triple {683#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,567 INFO L290 TraceCheckUtils]: 5: Hoare triple {683#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {688#(= main_~x~0 0)} is VALID [2022-04-27 21:20:24,567 INFO L290 TraceCheckUtils]: 6: Hoare triple {688#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {688#(= main_~x~0 0)} is VALID [2022-04-27 21:20:24,568 INFO L290 TraceCheckUtils]: 7: Hoare triple {688#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:24,568 INFO L290 TraceCheckUtils]: 8: Hoare triple {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:24,569 INFO L290 TraceCheckUtils]: 9: Hoare triple {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:24,569 INFO L290 TraceCheckUtils]: 10: Hoare triple {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:24,570 INFO L290 TraceCheckUtils]: 11: Hoare triple {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:24,570 INFO L290 TraceCheckUtils]: 12: Hoare triple {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:24,570 INFO L290 TraceCheckUtils]: 13: Hoare triple {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:24,571 INFO L290 TraceCheckUtils]: 14: Hoare triple {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:24,571 INFO L290 TraceCheckUtils]: 15: Hoare triple {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {693#(and (not (<= (+ (div main_~x~0 4294967296) 1) 0)) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:24,572 INFO L290 TraceCheckUtils]: 16: Hoare triple {693#(and (not (<= (+ (div main_~x~0 4294967296) 1) 0)) (<= main_~x~0 5))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:24,572 INFO L272 TraceCheckUtils]: 17: Hoare triple {684#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {684#false} is VALID [2022-04-27 21:20:24,572 INFO L290 TraceCheckUtils]: 18: Hoare triple {684#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {684#false} is VALID [2022-04-27 21:20:24,572 INFO L290 TraceCheckUtils]: 19: Hoare triple {684#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:24,572 INFO L290 TraceCheckUtils]: 20: Hoare triple {684#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:24,573 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:24,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:24,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678366771] [2022-04-27 21:20:24,573 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678366771] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:24,573 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1936284120] [2022-04-27 21:20:24,573 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:20:24,573 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:24,573 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:24,574 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:24,609 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 21:20:24,627 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:20:24,631 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:24,631 INFO L263 TraceCheckSpWp]: Trace formula consists of 78 conjuncts, 13 conjunts are in the unsatisfiable core [2022-04-27 21:20:24,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:24,636 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:24,838 INFO L272 TraceCheckUtils]: 0: Hoare triple {683#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,839 INFO L290 TraceCheckUtils]: 1: Hoare triple {683#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {683#true} is VALID [2022-04-27 21:20:24,839 INFO L290 TraceCheckUtils]: 2: Hoare triple {683#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,839 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {683#true} {683#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,839 INFO L272 TraceCheckUtils]: 4: Hoare triple {683#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:24,839 INFO L290 TraceCheckUtils]: 5: Hoare triple {683#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {688#(= main_~x~0 0)} is VALID [2022-04-27 21:20:24,840 INFO L290 TraceCheckUtils]: 6: Hoare triple {688#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {688#(= main_~x~0 0)} is VALID [2022-04-27 21:20:24,840 INFO L290 TraceCheckUtils]: 7: Hoare triple {688#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:24,840 INFO L290 TraceCheckUtils]: 8: Hoare triple {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:24,841 INFO L290 TraceCheckUtils]: 9: Hoare triple {689#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:24,841 INFO L290 TraceCheckUtils]: 10: Hoare triple {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:24,842 INFO L290 TraceCheckUtils]: 11: Hoare triple {690#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:24,842 INFO L290 TraceCheckUtils]: 12: Hoare triple {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:24,843 INFO L290 TraceCheckUtils]: 13: Hoare triple {691#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:24,843 INFO L290 TraceCheckUtils]: 14: Hoare triple {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:24,844 INFO L290 TraceCheckUtils]: 15: Hoare triple {692#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {743#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:24,844 INFO L290 TraceCheckUtils]: 16: Hoare triple {743#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:24,844 INFO L272 TraceCheckUtils]: 17: Hoare triple {684#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {684#false} is VALID [2022-04-27 21:20:24,845 INFO L290 TraceCheckUtils]: 18: Hoare triple {684#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {684#false} is VALID [2022-04-27 21:20:24,845 INFO L290 TraceCheckUtils]: 19: Hoare triple {684#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:24,845 INFO L290 TraceCheckUtils]: 20: Hoare triple {684#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:24,845 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:24,845 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:25,009 INFO L290 TraceCheckUtils]: 20: Hoare triple {684#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:25,010 INFO L290 TraceCheckUtils]: 19: Hoare triple {684#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:25,010 INFO L290 TraceCheckUtils]: 18: Hoare triple {684#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {684#false} is VALID [2022-04-27 21:20:25,010 INFO L272 TraceCheckUtils]: 17: Hoare triple {684#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {684#false} is VALID [2022-04-27 21:20:25,011 INFO L290 TraceCheckUtils]: 16: Hoare triple {771#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {684#false} is VALID [2022-04-27 21:20:25,013 INFO L290 TraceCheckUtils]: 15: Hoare triple {775#(< (mod (+ main_~x~0 1) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {771#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:20:25,013 INFO L290 TraceCheckUtils]: 14: Hoare triple {775#(< (mod (+ main_~x~0 1) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {775#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:20:25,014 INFO L290 TraceCheckUtils]: 13: Hoare triple {782#(< (mod (+ main_~x~0 2) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {775#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:20:25,014 INFO L290 TraceCheckUtils]: 12: Hoare triple {782#(< (mod (+ main_~x~0 2) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {782#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:25,015 INFO L290 TraceCheckUtils]: 11: Hoare triple {789#(< (mod (+ main_~x~0 3) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {782#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:25,016 INFO L290 TraceCheckUtils]: 10: Hoare triple {789#(< (mod (+ main_~x~0 3) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {789#(< (mod (+ main_~x~0 3) 4294967296) 99)} is VALID [2022-04-27 21:20:25,017 INFO L290 TraceCheckUtils]: 9: Hoare triple {796#(< (mod (+ main_~x~0 4) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {789#(< (mod (+ main_~x~0 3) 4294967296) 99)} is VALID [2022-04-27 21:20:25,017 INFO L290 TraceCheckUtils]: 8: Hoare triple {796#(< (mod (+ main_~x~0 4) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {796#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:25,018 INFO L290 TraceCheckUtils]: 7: Hoare triple {803#(< (mod (+ 5 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {796#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:25,018 INFO L290 TraceCheckUtils]: 6: Hoare triple {803#(< (mod (+ 5 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {803#(< (mod (+ 5 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:20:25,020 INFO L290 TraceCheckUtils]: 5: Hoare triple {683#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {803#(< (mod (+ 5 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:20:25,020 INFO L272 TraceCheckUtils]: 4: Hoare triple {683#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:25,020 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {683#true} {683#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:25,020 INFO L290 TraceCheckUtils]: 2: Hoare triple {683#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:25,020 INFO L290 TraceCheckUtils]: 1: Hoare triple {683#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {683#true} is VALID [2022-04-27 21:20:25,020 INFO L272 TraceCheckUtils]: 0: Hoare triple {683#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {683#true} is VALID [2022-04-27 21:20:25,021 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:25,021 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1936284120] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:25,021 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:25,021 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 16 [2022-04-27 21:20:25,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [404051704] [2022-04-27 21:20:25,021 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:25,022 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 21 [2022-04-27 21:20:25,022 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:25,022 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,077 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 37 edges. 37 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:25,077 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 16 states [2022-04-27 21:20:25,077 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:25,078 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2022-04-27 21:20:25,078 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=163, Unknown=0, NotChecked=0, Total=240 [2022-04-27 21:20:25,078 INFO L87 Difference]: Start difference. First operand 24 states and 30 transitions. Second operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:25,870 INFO L93 Difference]: Finished difference Result 71 states and 101 transitions. [2022-04-27 21:20:25,870 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2022-04-27 21:20:25,870 INFO L78 Accepts]: Start accepts. Automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 21 [2022-04-27 21:20:25,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:25,870 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 59 transitions. [2022-04-27 21:20:25,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 59 transitions. [2022-04-27 21:20:25,873 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 15 states and 59 transitions. [2022-04-27 21:20:25,962 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 59 edges. 59 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:25,964 INFO L225 Difference]: With dead ends: 71 [2022-04-27 21:20:25,964 INFO L226 Difference]: Without dead ends: 66 [2022-04-27 21:20:25,965 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 37 SyntacticMatches, 1 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=233, Invalid=523, Unknown=0, NotChecked=0, Total=756 [2022-04-27 21:20:25,965 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 31 mSDsluCounter, 37 mSDsCounter, 0 mSdLazyCounter, 170 mSolverCounterSat, 72 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 31 SdHoareTripleChecker+Valid, 48 SdHoareTripleChecker+Invalid, 242 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 72 IncrementalHoareTripleChecker+Valid, 170 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:25,966 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [31 Valid, 48 Invalid, 242 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [72 Valid, 170 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 21:20:25,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2022-04-27 21:20:25,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 36. [2022-04-27 21:20:25,992 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:25,992 INFO L82 GeneralOperation]: Start isEquivalent. First operand 66 states. Second operand has 36 states, 31 states have (on average 1.4193548387096775) internal successors, (44), 31 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,993 INFO L74 IsIncluded]: Start isIncluded. First operand 66 states. Second operand has 36 states, 31 states have (on average 1.4193548387096775) internal successors, (44), 31 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,993 INFO L87 Difference]: Start difference. First operand 66 states. Second operand has 36 states, 31 states have (on average 1.4193548387096775) internal successors, (44), 31 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:25,995 INFO L93 Difference]: Finished difference Result 66 states and 90 transitions. [2022-04-27 21:20:25,995 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 90 transitions. [2022-04-27 21:20:25,995 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:25,995 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:25,995 INFO L74 IsIncluded]: Start isIncluded. First operand has 36 states, 31 states have (on average 1.4193548387096775) internal successors, (44), 31 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 66 states. [2022-04-27 21:20:25,996 INFO L87 Difference]: Start difference. First operand has 36 states, 31 states have (on average 1.4193548387096775) internal successors, (44), 31 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 66 states. [2022-04-27 21:20:25,997 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:25,997 INFO L93 Difference]: Finished difference Result 66 states and 90 transitions. [2022-04-27 21:20:25,997 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 90 transitions. [2022-04-27 21:20:25,998 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:25,998 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:25,998 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:25,998 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:25,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 31 states have (on average 1.4193548387096775) internal successors, (44), 31 states have internal predecessors, (44), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:25,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 48 transitions. [2022-04-27 21:20:25,999 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 48 transitions. Word has length 21 [2022-04-27 21:20:25,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:25,999 INFO L495 AbstractCegarLoop]: Abstraction has 36 states and 48 transitions. [2022-04-27 21:20:25,999 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 16 states, 16 states have (on average 2.0) internal successors, (32), 15 states have internal predecessors, (32), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:26,000 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 48 transitions. [2022-04-27 21:20:26,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 21:20:26,013 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:26,013 INFO L195 NwaCegarLoop]: trace histogram [6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:26,031 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:26,226 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:26,226 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:26,226 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:26,226 INFO L85 PathProgramCache]: Analyzing trace with hash -819090412, now seen corresponding path program 2 times [2022-04-27 21:20:26,226 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:26,227 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [645088018] [2022-04-27 21:20:26,227 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:26,227 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:26,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:26,335 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:26,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:26,342 INFO L290 TraceCheckUtils]: 0: Hoare triple {1160#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1148#true} is VALID [2022-04-27 21:20:26,342 INFO L290 TraceCheckUtils]: 1: Hoare triple {1148#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,342 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1148#true} {1148#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,343 INFO L272 TraceCheckUtils]: 0: Hoare triple {1148#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1160#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:26,343 INFO L290 TraceCheckUtils]: 1: Hoare triple {1160#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1148#true} is VALID [2022-04-27 21:20:26,343 INFO L290 TraceCheckUtils]: 2: Hoare triple {1148#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,343 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1148#true} {1148#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,343 INFO L272 TraceCheckUtils]: 4: Hoare triple {1148#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,343 INFO L290 TraceCheckUtils]: 5: Hoare triple {1148#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {1153#(= main_~x~0 0)} is VALID [2022-04-27 21:20:26,344 INFO L290 TraceCheckUtils]: 6: Hoare triple {1153#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1153#(= main_~x~0 0)} is VALID [2022-04-27 21:20:26,344 INFO L290 TraceCheckUtils]: 7: Hoare triple {1153#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:26,345 INFO L290 TraceCheckUtils]: 8: Hoare triple {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:26,345 INFO L290 TraceCheckUtils]: 9: Hoare triple {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:26,346 INFO L290 TraceCheckUtils]: 10: Hoare triple {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:26,346 INFO L290 TraceCheckUtils]: 11: Hoare triple {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:26,346 INFO L290 TraceCheckUtils]: 12: Hoare triple {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:26,347 INFO L290 TraceCheckUtils]: 13: Hoare triple {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:26,347 INFO L290 TraceCheckUtils]: 14: Hoare triple {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:26,348 INFO L290 TraceCheckUtils]: 15: Hoare triple {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:26,348 INFO L290 TraceCheckUtils]: 16: Hoare triple {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:26,349 INFO L290 TraceCheckUtils]: 17: Hoare triple {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1159#(and (<= main_~x~0 12) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:20:26,349 INFO L290 TraceCheckUtils]: 18: Hoare triple {1159#(and (<= main_~x~0 12) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,349 INFO L272 TraceCheckUtils]: 19: Hoare triple {1149#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {1149#false} is VALID [2022-04-27 21:20:26,349 INFO L290 TraceCheckUtils]: 20: Hoare triple {1149#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1149#false} is VALID [2022-04-27 21:20:26,349 INFO L290 TraceCheckUtils]: 21: Hoare triple {1149#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,350 INFO L290 TraceCheckUtils]: 22: Hoare triple {1149#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,350 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:26,350 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:26,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [645088018] [2022-04-27 21:20:26,350 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [645088018] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:26,350 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [903701906] [2022-04-27 21:20:26,350 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:20:26,350 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:26,350 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:26,351 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:26,359 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 21:20:26,390 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:20:26,390 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:26,390 INFO L263 TraceCheckSpWp]: Trace formula consists of 77 conjuncts, 15 conjunts are in the unsatisfiable core [2022-04-27 21:20:26,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:26,399 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:26,613 INFO L272 TraceCheckUtils]: 0: Hoare triple {1148#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,613 INFO L290 TraceCheckUtils]: 1: Hoare triple {1148#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1148#true} is VALID [2022-04-27 21:20:26,613 INFO L290 TraceCheckUtils]: 2: Hoare triple {1148#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,613 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1148#true} {1148#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,613 INFO L272 TraceCheckUtils]: 4: Hoare triple {1148#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,614 INFO L290 TraceCheckUtils]: 5: Hoare triple {1148#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {1153#(= main_~x~0 0)} is VALID [2022-04-27 21:20:26,614 INFO L290 TraceCheckUtils]: 6: Hoare triple {1153#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1153#(= main_~x~0 0)} is VALID [2022-04-27 21:20:26,614 INFO L290 TraceCheckUtils]: 7: Hoare triple {1153#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:26,615 INFO L290 TraceCheckUtils]: 8: Hoare triple {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:26,615 INFO L290 TraceCheckUtils]: 9: Hoare triple {1154#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:26,615 INFO L290 TraceCheckUtils]: 10: Hoare triple {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:26,616 INFO L290 TraceCheckUtils]: 11: Hoare triple {1155#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:26,616 INFO L290 TraceCheckUtils]: 12: Hoare triple {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:26,617 INFO L290 TraceCheckUtils]: 13: Hoare triple {1156#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:26,617 INFO L290 TraceCheckUtils]: 14: Hoare triple {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:26,618 INFO L290 TraceCheckUtils]: 15: Hoare triple {1157#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:26,618 INFO L290 TraceCheckUtils]: 16: Hoare triple {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:26,618 INFO L290 TraceCheckUtils]: 17: Hoare triple {1158#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1215#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:26,619 INFO L290 TraceCheckUtils]: 18: Hoare triple {1215#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,619 INFO L272 TraceCheckUtils]: 19: Hoare triple {1149#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {1149#false} is VALID [2022-04-27 21:20:26,619 INFO L290 TraceCheckUtils]: 20: Hoare triple {1149#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1149#false} is VALID [2022-04-27 21:20:26,619 INFO L290 TraceCheckUtils]: 21: Hoare triple {1149#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,620 INFO L290 TraceCheckUtils]: 22: Hoare triple {1149#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,620 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:26,620 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:26,779 INFO L290 TraceCheckUtils]: 22: Hoare triple {1149#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,780 INFO L290 TraceCheckUtils]: 21: Hoare triple {1149#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,780 INFO L290 TraceCheckUtils]: 20: Hoare triple {1149#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1149#false} is VALID [2022-04-27 21:20:26,780 INFO L272 TraceCheckUtils]: 19: Hoare triple {1149#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {1149#false} is VALID [2022-04-27 21:20:26,781 INFO L290 TraceCheckUtils]: 18: Hoare triple {1243#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1149#false} is VALID [2022-04-27 21:20:26,782 INFO L290 TraceCheckUtils]: 17: Hoare triple {1247#(< (mod (+ main_~x~0 2) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1243#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:20:26,782 INFO L290 TraceCheckUtils]: 16: Hoare triple {1247#(< (mod (+ main_~x~0 2) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1247#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:26,783 INFO L290 TraceCheckUtils]: 15: Hoare triple {1254#(< (mod (+ main_~x~0 4) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1247#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:26,784 INFO L290 TraceCheckUtils]: 14: Hoare triple {1254#(< (mod (+ main_~x~0 4) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1254#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:26,785 INFO L290 TraceCheckUtils]: 13: Hoare triple {1261#(< (mod (+ main_~x~0 6) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1254#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:26,789 INFO L290 TraceCheckUtils]: 12: Hoare triple {1261#(< (mod (+ main_~x~0 6) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1261#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:20:26,790 INFO L290 TraceCheckUtils]: 11: Hoare triple {1268#(< (mod (+ main_~x~0 8) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1261#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:20:26,791 INFO L290 TraceCheckUtils]: 10: Hoare triple {1268#(< (mod (+ main_~x~0 8) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1268#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:20:26,792 INFO L290 TraceCheckUtils]: 9: Hoare triple {1275#(< (mod (+ main_~x~0 10) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1268#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:20:26,792 INFO L290 TraceCheckUtils]: 8: Hoare triple {1275#(< (mod (+ main_~x~0 10) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1275#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:20:26,793 INFO L290 TraceCheckUtils]: 7: Hoare triple {1282#(< (mod (+ main_~x~0 12) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1275#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:20:26,793 INFO L290 TraceCheckUtils]: 6: Hoare triple {1282#(< (mod (+ main_~x~0 12) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1282#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:20:26,793 INFO L290 TraceCheckUtils]: 5: Hoare triple {1148#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {1282#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:20:26,793 INFO L272 TraceCheckUtils]: 4: Hoare triple {1148#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,794 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1148#true} {1148#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,794 INFO L290 TraceCheckUtils]: 2: Hoare triple {1148#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,794 INFO L290 TraceCheckUtils]: 1: Hoare triple {1148#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1148#true} is VALID [2022-04-27 21:20:26,794 INFO L272 TraceCheckUtils]: 0: Hoare triple {1148#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1148#true} is VALID [2022-04-27 21:20:26,794 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:26,794 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [903701906] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:26,794 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:26,794 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9] total 18 [2022-04-27 21:20:26,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266857085] [2022-04-27 21:20:26,795 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:26,795 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:20:26,795 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:26,795 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:26,822 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 41 edges. 41 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:26,822 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-04-27 21:20:26,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:26,822 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-04-27 21:20:26,823 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=96, Invalid=210, Unknown=0, NotChecked=0, Total=306 [2022-04-27 21:20:26,823 INFO L87 Difference]: Start difference. First operand 36 states and 48 transitions. Second operand has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,040 INFO L93 Difference]: Finished difference Result 149 states and 217 transitions. [2022-04-27 21:20:28,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2022-04-27 21:20:28,040 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:20:28,040 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:28,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,042 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 69 transitions. [2022-04-27 21:20:28,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,044 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 69 transitions. [2022-04-27 21:20:28,044 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 18 states and 69 transitions. [2022-04-27 21:20:28,132 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 69 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:28,134 INFO L225 Difference]: With dead ends: 149 [2022-04-27 21:20:28,135 INFO L226 Difference]: Without dead ends: 144 [2022-04-27 21:20:28,135 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 151 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=324, Invalid=732, Unknown=0, NotChecked=0, Total=1056 [2022-04-27 21:20:28,136 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 27 mSDsluCounter, 37 mSDsCounter, 0 mSdLazyCounter, 218 mSolverCounterSat, 72 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 48 SdHoareTripleChecker+Invalid, 290 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 72 IncrementalHoareTripleChecker+Valid, 218 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:28,136 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 48 Invalid, 290 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [72 Valid, 218 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 21:20:28,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2022-04-27 21:20:28,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 80. [2022-04-27 21:20:28,247 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:28,248 INFO L82 GeneralOperation]: Start isEquivalent. First operand 144 states. Second operand has 80 states, 75 states have (on average 1.4666666666666666) internal successors, (110), 75 states have internal predecessors, (110), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,248 INFO L74 IsIncluded]: Start isIncluded. First operand 144 states. Second operand has 80 states, 75 states have (on average 1.4666666666666666) internal successors, (110), 75 states have internal predecessors, (110), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,248 INFO L87 Difference]: Start difference. First operand 144 states. Second operand has 80 states, 75 states have (on average 1.4666666666666666) internal successors, (110), 75 states have internal predecessors, (110), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,254 INFO L93 Difference]: Finished difference Result 144 states and 205 transitions. [2022-04-27 21:20:28,254 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 205 transitions. [2022-04-27 21:20:28,258 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:28,259 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:28,260 INFO L74 IsIncluded]: Start isIncluded. First operand has 80 states, 75 states have (on average 1.4666666666666666) internal successors, (110), 75 states have internal predecessors, (110), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 144 states. [2022-04-27 21:20:28,260 INFO L87 Difference]: Start difference. First operand has 80 states, 75 states have (on average 1.4666666666666666) internal successors, (110), 75 states have internal predecessors, (110), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 144 states. [2022-04-27 21:20:28,267 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,267 INFO L93 Difference]: Finished difference Result 144 states and 205 transitions. [2022-04-27 21:20:28,267 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 205 transitions. [2022-04-27 21:20:28,268 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:28,268 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:28,268 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:28,268 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:28,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 75 states have (on average 1.4666666666666666) internal successors, (110), 75 states have internal predecessors, (110), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 114 transitions. [2022-04-27 21:20:28,271 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 114 transitions. Word has length 23 [2022-04-27 21:20:28,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:28,272 INFO L495 AbstractCegarLoop]: Abstraction has 80 states and 114 transitions. [2022-04-27 21:20:28,273 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 2.0) internal successors, (36), 17 states have internal predecessors, (36), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,273 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 114 transitions. [2022-04-27 21:20:28,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2022-04-27 21:20:28,273 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:28,273 INFO L195 NwaCegarLoop]: trace histogram [9, 6, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:28,293 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:28,493 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:28,494 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:28,494 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:28,494 INFO L85 PathProgramCache]: Analyzing trace with hash -382718831, now seen corresponding path program 1 times [2022-04-27 21:20:28,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:28,494 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1320433867] [2022-04-27 21:20:28,494 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:28,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:28,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:28,530 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:28,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:28,537 INFO L290 TraceCheckUtils]: 0: Hoare triple {1980#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1974#true} is VALID [2022-04-27 21:20:28,537 INFO L290 TraceCheckUtils]: 1: Hoare triple {1974#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1974#true} is VALID [2022-04-27 21:20:28,538 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1974#true} {1974#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1974#true} is VALID [2022-04-27 21:20:28,538 INFO L272 TraceCheckUtils]: 0: Hoare triple {1974#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1980#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:28,538 INFO L290 TraceCheckUtils]: 1: Hoare triple {1980#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1974#true} is VALID [2022-04-27 21:20:28,538 INFO L290 TraceCheckUtils]: 2: Hoare triple {1974#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1974#true} is VALID [2022-04-27 21:20:28,538 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1974#true} {1974#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1974#true} is VALID [2022-04-27 21:20:28,538 INFO L272 TraceCheckUtils]: 4: Hoare triple {1974#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1974#true} is VALID [2022-04-27 21:20:28,539 INFO L290 TraceCheckUtils]: 5: Hoare triple {1974#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {1974#true} is VALID [2022-04-27 21:20:28,539 INFO L290 TraceCheckUtils]: 6: Hoare triple {1974#true} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1974#true} is VALID [2022-04-27 21:20:28,539 INFO L290 TraceCheckUtils]: 7: Hoare triple {1974#true} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,539 INFO L290 TraceCheckUtils]: 8: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,540 INFO L290 TraceCheckUtils]: 9: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,540 INFO L290 TraceCheckUtils]: 10: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,540 INFO L290 TraceCheckUtils]: 11: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,541 INFO L290 TraceCheckUtils]: 12: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,541 INFO L290 TraceCheckUtils]: 13: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,542 INFO L290 TraceCheckUtils]: 14: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,542 INFO L290 TraceCheckUtils]: 15: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,542 INFO L290 TraceCheckUtils]: 16: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,543 INFO L290 TraceCheckUtils]: 17: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,543 INFO L290 TraceCheckUtils]: 18: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} is VALID [2022-04-27 21:20:28,543 INFO L290 TraceCheckUtils]: 19: Hoare triple {1979#(= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1975#false} is VALID [2022-04-27 21:20:28,543 INFO L290 TraceCheckUtils]: 20: Hoare triple {1975#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1975#false} is VALID [2022-04-27 21:20:28,543 INFO L290 TraceCheckUtils]: 21: Hoare triple {1975#false} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L290 TraceCheckUtils]: 22: Hoare triple {1975#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L290 TraceCheckUtils]: 23: Hoare triple {1975#false} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L290 TraceCheckUtils]: 24: Hoare triple {1975#false} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L272 TraceCheckUtils]: 25: Hoare triple {1975#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L290 TraceCheckUtils]: 26: Hoare triple {1975#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L290 TraceCheckUtils]: 27: Hoare triple {1975#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L290 TraceCheckUtils]: 28: Hoare triple {1975#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1975#false} is VALID [2022-04-27 21:20:28,544 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 47 proven. 0 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2022-04-27 21:20:28,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:28,545 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1320433867] [2022-04-27 21:20:28,545 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1320433867] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:20:28,545 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:20:28,545 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 21:20:28,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547762530] [2022-04-27 21:20:28,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:20:28,545 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 29 [2022-04-27 21:20:28,545 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:28,546 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,557 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 18 edges. 18 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:28,557 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 21:20:28,557 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:28,558 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 21:20:28,558 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 21:20:28,558 INFO L87 Difference]: Start difference. First operand 80 states and 114 transitions. Second operand has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,694 INFO L93 Difference]: Finished difference Result 136 states and 195 transitions. [2022-04-27 21:20:28,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 21:20:28,695 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 29 [2022-04-27 21:20:28,695 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:28,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 27 transitions. [2022-04-27 21:20:28,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 27 transitions. [2022-04-27 21:20:28,697 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 27 transitions. [2022-04-27 21:20:28,715 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 27 edges. 27 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:28,717 INFO L225 Difference]: With dead ends: 136 [2022-04-27 21:20:28,717 INFO L226 Difference]: Without dead ends: 90 [2022-04-27 21:20:28,718 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 21:20:28,719 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 10 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 10 mSolverCounterSat, 3 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 22 SdHoareTripleChecker+Invalid, 13 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 3 IncrementalHoareTripleChecker+Valid, 10 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:28,719 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 22 Invalid, 13 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [3 Valid, 10 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:28,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2022-04-27 21:20:28,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 63. [2022-04-27 21:20:28,792 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:28,792 INFO L82 GeneralOperation]: Start isEquivalent. First operand 90 states. Second operand has 63 states, 58 states have (on average 1.2758620689655173) internal successors, (74), 58 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,792 INFO L74 IsIncluded]: Start isIncluded. First operand 90 states. Second operand has 63 states, 58 states have (on average 1.2758620689655173) internal successors, (74), 58 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,792 INFO L87 Difference]: Start difference. First operand 90 states. Second operand has 63 states, 58 states have (on average 1.2758620689655173) internal successors, (74), 58 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,794 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,795 INFO L93 Difference]: Finished difference Result 90 states and 105 transitions. [2022-04-27 21:20:28,795 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 105 transitions. [2022-04-27 21:20:28,795 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:28,795 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:28,795 INFO L74 IsIncluded]: Start isIncluded. First operand has 63 states, 58 states have (on average 1.2758620689655173) internal successors, (74), 58 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 90 states. [2022-04-27 21:20:28,795 INFO L87 Difference]: Start difference. First operand has 63 states, 58 states have (on average 1.2758620689655173) internal successors, (74), 58 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 90 states. [2022-04-27 21:20:28,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,797 INFO L93 Difference]: Finished difference Result 90 states and 105 transitions. [2022-04-27 21:20:28,797 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 105 transitions. [2022-04-27 21:20:28,797 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:28,797 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:28,797 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:28,797 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:28,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 58 states have (on average 1.2758620689655173) internal successors, (74), 58 states have internal predecessors, (74), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 78 transitions. [2022-04-27 21:20:28,799 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 78 transitions. Word has length 29 [2022-04-27 21:20:28,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:28,799 INFO L495 AbstractCegarLoop]: Abstraction has 63 states and 78 transitions. [2022-04-27 21:20:28,799 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 3.5) internal successors, (14), 3 states have internal predecessors, (14), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,799 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 78 transitions. [2022-04-27 21:20:28,800 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-27 21:20:28,800 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:28,800 INFO L195 NwaCegarLoop]: trace histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:28,800 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6 [2022-04-27 21:20:28,800 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:28,801 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:28,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1436785103, now seen corresponding path program 2 times [2022-04-27 21:20:28,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:28,801 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [394604640] [2022-04-27 21:20:28,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:28,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:28,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:28,851 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:28,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:28,860 INFO L290 TraceCheckUtils]: 0: Hoare triple {2474#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2468#true} is VALID [2022-04-27 21:20:28,860 INFO L290 TraceCheckUtils]: 1: Hoare triple {2468#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2468#true} is VALID [2022-04-27 21:20:28,860 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2468#true} {2468#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2468#true} is VALID [2022-04-27 21:20:28,861 INFO L272 TraceCheckUtils]: 0: Hoare triple {2468#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2474#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:28,861 INFO L290 TraceCheckUtils]: 1: Hoare triple {2474#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2468#true} is VALID [2022-04-27 21:20:28,861 INFO L290 TraceCheckUtils]: 2: Hoare triple {2468#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2468#true} is VALID [2022-04-27 21:20:28,861 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2468#true} {2468#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2468#true} is VALID [2022-04-27 21:20:28,861 INFO L272 TraceCheckUtils]: 4: Hoare triple {2468#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2468#true} is VALID [2022-04-27 21:20:28,861 INFO L290 TraceCheckUtils]: 5: Hoare triple {2468#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {2468#true} is VALID [2022-04-27 21:20:28,861 INFO L290 TraceCheckUtils]: 6: Hoare triple {2468#true} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2468#true} is VALID [2022-04-27 21:20:28,862 INFO L290 TraceCheckUtils]: 7: Hoare triple {2468#true} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {2473#(not (= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0))} is VALID [2022-04-27 21:20:28,862 INFO L290 TraceCheckUtils]: 8: Hoare triple {2473#(not (= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2473#(not (= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0))} is VALID [2022-04-27 21:20:28,863 INFO L290 TraceCheckUtils]: 9: Hoare triple {2473#(not (= (+ (* (- 2) (div main_~y~0 2)) main_~y~0) 0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,863 INFO L290 TraceCheckUtils]: 10: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,863 INFO L290 TraceCheckUtils]: 11: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,863 INFO L290 TraceCheckUtils]: 12: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,863 INFO L290 TraceCheckUtils]: 13: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,863 INFO L290 TraceCheckUtils]: 14: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,864 INFO L290 TraceCheckUtils]: 15: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,864 INFO L290 TraceCheckUtils]: 16: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,864 INFO L290 TraceCheckUtils]: 17: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,864 INFO L290 TraceCheckUtils]: 18: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 19: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 20: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 21: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 22: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 23: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 24: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,865 INFO L290 TraceCheckUtils]: 25: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L290 TraceCheckUtils]: 26: Hoare triple {2469#false} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L290 TraceCheckUtils]: 27: Hoare triple {2469#false} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L290 TraceCheckUtils]: 28: Hoare triple {2469#false} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L272 TraceCheckUtils]: 29: Hoare triple {2469#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L290 TraceCheckUtils]: 30: Hoare triple {2469#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L290 TraceCheckUtils]: 31: Hoare triple {2469#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,866 INFO L290 TraceCheckUtils]: 32: Hoare triple {2469#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2469#false} is VALID [2022-04-27 21:20:28,867 INFO L134 CoverageAnalysis]: Checked inductivity of 121 backedges. 40 proven. 0 refuted. 0 times theorem prover too weak. 81 trivial. 0 not checked. [2022-04-27 21:20:28,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:28,867 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [394604640] [2022-04-27 21:20:28,867 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [394604640] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:20:28,867 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:20:28,867 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2022-04-27 21:20:28,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823227985] [2022-04-27 21:20:28,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:20:28,869 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-27 21:20:28,869 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:28,869 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,878 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:28,878 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 4 states [2022-04-27 21:20:28,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:28,879 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2022-04-27 21:20:28,879 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2022-04-27 21:20:28,879 INFO L87 Difference]: Start difference. First operand 63 states and 78 transitions. Second operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:28,977 INFO L93 Difference]: Finished difference Result 88 states and 103 transitions. [2022-04-27 21:20:28,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2022-04-27 21:20:28,977 INFO L78 Accepts]: Start accepts. Automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 33 [2022-04-27 21:20:28,978 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:28,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 26 transitions. [2022-04-27 21:20:28,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:28,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4 states to 4 states and 26 transitions. [2022-04-27 21:20:28,979 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 4 states and 26 transitions. [2022-04-27 21:20:28,994 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 26 edges. 26 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:28,996 INFO L225 Difference]: With dead ends: 88 [2022-04-27 21:20:28,996 INFO L226 Difference]: Without dead ends: 64 [2022-04-27 21:20:28,996 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2022-04-27 21:20:28,996 INFO L413 NwaCegarLoop]: 17 mSDtfsCounter, 9 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 11 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 9 SdHoareTripleChecker+Valid, 24 SdHoareTripleChecker+Invalid, 13 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 11 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:28,997 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [9 Valid, 24 Invalid, 13 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 11 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:20:28,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2022-04-27 21:20:29,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2022-04-27 21:20:29,083 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:29,083 INFO L82 GeneralOperation]: Start isEquivalent. First operand 64 states. Second operand has 63 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 58 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:29,083 INFO L74 IsIncluded]: Start isIncluded. First operand 64 states. Second operand has 63 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 58 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:29,084 INFO L87 Difference]: Start difference. First operand 64 states. Second operand has 63 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 58 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:29,085 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:29,085 INFO L93 Difference]: Finished difference Result 64 states and 66 transitions. [2022-04-27 21:20:29,085 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 66 transitions. [2022-04-27 21:20:29,085 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:29,085 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:29,086 INFO L74 IsIncluded]: Start isIncluded. First operand has 63 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 58 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 64 states. [2022-04-27 21:20:29,086 INFO L87 Difference]: Start difference. First operand has 63 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 58 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 64 states. [2022-04-27 21:20:29,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:29,087 INFO L93 Difference]: Finished difference Result 64 states and 66 transitions. [2022-04-27 21:20:29,087 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 66 transitions. [2022-04-27 21:20:29,087 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:29,087 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:29,087 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:29,087 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:29,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 58 states have (on average 1.0517241379310345) internal successors, (61), 58 states have internal predecessors, (61), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:29,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 65 transitions. [2022-04-27 21:20:29,089 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 65 transitions. Word has length 33 [2022-04-27 21:20:29,089 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:29,089 INFO L495 AbstractCegarLoop]: Abstraction has 63 states and 65 transitions. [2022-04-27 21:20:29,089 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 4 states, 4 states have (on average 3.25) internal successors, (13), 3 states have internal predecessors, (13), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:29,089 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 65 transitions. [2022-04-27 21:20:29,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2022-04-27 21:20:29,089 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:29,089 INFO L195 NwaCegarLoop]: trace histogram [12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:29,090 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7 [2022-04-27 21:20:29,090 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:29,090 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:29,090 INFO L85 PathProgramCache]: Analyzing trace with hash -1063807026, now seen corresponding path program 3 times [2022-04-27 21:20:29,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:29,090 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1469443998] [2022-04-27 21:20:29,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:29,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:29,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:29,295 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:29,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:29,300 INFO L290 TraceCheckUtils]: 0: Hoare triple {2856#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2838#true} is VALID [2022-04-27 21:20:29,300 INFO L290 TraceCheckUtils]: 1: Hoare triple {2838#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:29,300 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2838#true} {2838#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:29,301 INFO L272 TraceCheckUtils]: 0: Hoare triple {2838#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2856#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:29,301 INFO L290 TraceCheckUtils]: 1: Hoare triple {2856#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2838#true} is VALID [2022-04-27 21:20:29,301 INFO L290 TraceCheckUtils]: 2: Hoare triple {2838#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:29,301 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2838#true} {2838#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:29,301 INFO L272 TraceCheckUtils]: 4: Hoare triple {2838#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:29,302 INFO L290 TraceCheckUtils]: 5: Hoare triple {2838#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {2843#(= main_~x~0 0)} is VALID [2022-04-27 21:20:29,302 INFO L290 TraceCheckUtils]: 6: Hoare triple {2843#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2843#(= main_~x~0 0)} is VALID [2022-04-27 21:20:29,302 INFO L290 TraceCheckUtils]: 7: Hoare triple {2843#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:29,303 INFO L290 TraceCheckUtils]: 8: Hoare triple {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:29,303 INFO L290 TraceCheckUtils]: 9: Hoare triple {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:29,304 INFO L290 TraceCheckUtils]: 10: Hoare triple {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:29,304 INFO L290 TraceCheckUtils]: 11: Hoare triple {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:29,304 INFO L290 TraceCheckUtils]: 12: Hoare triple {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:29,305 INFO L290 TraceCheckUtils]: 13: Hoare triple {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:29,305 INFO L290 TraceCheckUtils]: 14: Hoare triple {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:29,306 INFO L290 TraceCheckUtils]: 15: Hoare triple {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:29,306 INFO L290 TraceCheckUtils]: 16: Hoare triple {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:29,307 INFO L290 TraceCheckUtils]: 17: Hoare triple {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:29,307 INFO L290 TraceCheckUtils]: 18: Hoare triple {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:29,307 INFO L290 TraceCheckUtils]: 19: Hoare triple {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:29,308 INFO L290 TraceCheckUtils]: 20: Hoare triple {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:29,308 INFO L290 TraceCheckUtils]: 21: Hoare triple {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:29,309 INFO L290 TraceCheckUtils]: 22: Hoare triple {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:29,309 INFO L290 TraceCheckUtils]: 23: Hoare triple {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:29,310 INFO L290 TraceCheckUtils]: 24: Hoare triple {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:29,310 INFO L290 TraceCheckUtils]: 25: Hoare triple {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:29,310 INFO L290 TraceCheckUtils]: 26: Hoare triple {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:29,311 INFO L290 TraceCheckUtils]: 27: Hoare triple {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:29,311 INFO L290 TraceCheckUtils]: 28: Hoare triple {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:29,312 INFO L290 TraceCheckUtils]: 29: Hoare triple {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2855#(and (<= main_~x~0 12) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:20:29,312 INFO L290 TraceCheckUtils]: 30: Hoare triple {2855#(and (<= main_~x~0 12) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:29,312 INFO L272 TraceCheckUtils]: 31: Hoare triple {2839#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {2839#false} is VALID [2022-04-27 21:20:29,312 INFO L290 TraceCheckUtils]: 32: Hoare triple {2839#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2839#false} is VALID [2022-04-27 21:20:29,312 INFO L290 TraceCheckUtils]: 33: Hoare triple {2839#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:29,313 INFO L290 TraceCheckUtils]: 34: Hoare triple {2839#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:29,313 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:29,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:29,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1469443998] [2022-04-27 21:20:29,313 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1469443998] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:29,313 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [270180533] [2022-04-27 21:20:29,313 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 21:20:29,313 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:29,313 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:29,322 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:29,322 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 21:20:29,387 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2022-04-27 21:20:29,387 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:29,388 INFO L263 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 30 conjunts are in the unsatisfiable core [2022-04-27 21:20:29,400 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:29,401 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:30,004 INFO L272 TraceCheckUtils]: 0: Hoare triple {2838#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,005 INFO L290 TraceCheckUtils]: 1: Hoare triple {2838#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2838#true} is VALID [2022-04-27 21:20:30,005 INFO L290 TraceCheckUtils]: 2: Hoare triple {2838#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,005 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2838#true} {2838#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,005 INFO L272 TraceCheckUtils]: 4: Hoare triple {2838#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,005 INFO L290 TraceCheckUtils]: 5: Hoare triple {2838#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {2843#(= main_~x~0 0)} is VALID [2022-04-27 21:20:30,006 INFO L290 TraceCheckUtils]: 6: Hoare triple {2843#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2843#(= main_~x~0 0)} is VALID [2022-04-27 21:20:30,006 INFO L290 TraceCheckUtils]: 7: Hoare triple {2843#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:30,006 INFO L290 TraceCheckUtils]: 8: Hoare triple {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:30,007 INFO L290 TraceCheckUtils]: 9: Hoare triple {2844#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:30,008 INFO L290 TraceCheckUtils]: 10: Hoare triple {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:30,008 INFO L290 TraceCheckUtils]: 11: Hoare triple {2845#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:30,009 INFO L290 TraceCheckUtils]: 12: Hoare triple {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:30,010 INFO L290 TraceCheckUtils]: 13: Hoare triple {2846#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:30,015 INFO L290 TraceCheckUtils]: 14: Hoare triple {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:30,016 INFO L290 TraceCheckUtils]: 15: Hoare triple {2847#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:30,017 INFO L290 TraceCheckUtils]: 16: Hoare triple {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:30,017 INFO L290 TraceCheckUtils]: 17: Hoare triple {2848#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:30,018 INFO L290 TraceCheckUtils]: 18: Hoare triple {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:30,018 INFO L290 TraceCheckUtils]: 19: Hoare triple {2849#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:30,019 INFO L290 TraceCheckUtils]: 20: Hoare triple {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:30,021 INFO L290 TraceCheckUtils]: 21: Hoare triple {2850#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:30,021 INFO L290 TraceCheckUtils]: 22: Hoare triple {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:30,022 INFO L290 TraceCheckUtils]: 23: Hoare triple {2851#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:30,023 INFO L290 TraceCheckUtils]: 24: Hoare triple {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:30,023 INFO L290 TraceCheckUtils]: 25: Hoare triple {2852#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:30,024 INFO L290 TraceCheckUtils]: 26: Hoare triple {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:30,024 INFO L290 TraceCheckUtils]: 27: Hoare triple {2853#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:30,025 INFO L290 TraceCheckUtils]: 28: Hoare triple {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:30,025 INFO L290 TraceCheckUtils]: 29: Hoare triple {2854#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2947#(and (<= main_~x~0 12) (<= 12 main_~x~0) (<= (mod main_~y~0 2) 0))} is VALID [2022-04-27 21:20:30,026 INFO L290 TraceCheckUtils]: 30: Hoare triple {2947#(and (<= main_~x~0 12) (<= 12 main_~x~0) (<= (mod main_~y~0 2) 0))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2947#(and (<= main_~x~0 12) (<= 12 main_~x~0) (<= (mod main_~y~0 2) 0))} is VALID [2022-04-27 21:20:30,026 INFO L272 TraceCheckUtils]: 31: Hoare triple {2947#(and (<= main_~x~0 12) (<= 12 main_~x~0) (<= (mod main_~y~0 2) 0))} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {2954#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:20:30,027 INFO L290 TraceCheckUtils]: 32: Hoare triple {2954#(<= 1 |__VERIFIER_assert_#in~cond|)} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2958#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:20:30,027 INFO L290 TraceCheckUtils]: 33: Hoare triple {2958#(<= 1 __VERIFIER_assert_~cond)} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:30,027 INFO L290 TraceCheckUtils]: 34: Hoare triple {2839#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:30,028 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 144 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:30,028 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:30,445 INFO L290 TraceCheckUtils]: 34: Hoare triple {2839#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:30,445 INFO L290 TraceCheckUtils]: 33: Hoare triple {2958#(<= 1 __VERIFIER_assert_~cond)} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2839#false} is VALID [2022-04-27 21:20:30,446 INFO L290 TraceCheckUtils]: 32: Hoare triple {2954#(<= 1 |__VERIFIER_assert_#in~cond|)} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2958#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:20:30,446 INFO L272 TraceCheckUtils]: 31: Hoare triple {2974#(= (mod main_~x~0 2) (mod main_~y~0 2))} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {2954#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:20:30,447 INFO L290 TraceCheckUtils]: 30: Hoare triple {2974#(= (mod main_~x~0 2) (mod main_~y~0 2))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {2974#(= (mod main_~x~0 2) (mod main_~y~0 2))} is VALID [2022-04-27 21:20:30,447 INFO L290 TraceCheckUtils]: 29: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2974#(= (mod main_~x~0 2) (mod main_~y~0 2))} is VALID [2022-04-27 21:20:30,447 INFO L290 TraceCheckUtils]: 28: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,448 INFO L290 TraceCheckUtils]: 27: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,448 INFO L290 TraceCheckUtils]: 26: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,449 INFO L290 TraceCheckUtils]: 25: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,449 INFO L290 TraceCheckUtils]: 24: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,450 INFO L290 TraceCheckUtils]: 23: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,450 INFO L290 TraceCheckUtils]: 22: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,450 INFO L290 TraceCheckUtils]: 21: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,451 INFO L290 TraceCheckUtils]: 20: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,451 INFO L290 TraceCheckUtils]: 19: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,452 INFO L290 TraceCheckUtils]: 18: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,452 INFO L290 TraceCheckUtils]: 17: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,452 INFO L290 TraceCheckUtils]: 16: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,453 INFO L290 TraceCheckUtils]: 15: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,453 INFO L290 TraceCheckUtils]: 14: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,454 INFO L290 TraceCheckUtils]: 13: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,454 INFO L290 TraceCheckUtils]: 12: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,455 INFO L290 TraceCheckUtils]: 11: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,455 INFO L290 TraceCheckUtils]: 10: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,455 INFO L290 TraceCheckUtils]: 9: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,456 INFO L290 TraceCheckUtils]: 8: Hoare triple {2981#(<= (mod (+ main_~x~0 1) 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,456 INFO L290 TraceCheckUtils]: 7: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {2981#(<= (mod (+ main_~x~0 1) 2) 0)} is VALID [2022-04-27 21:20:30,456 INFO L290 TraceCheckUtils]: 6: Hoare triple {2988#(<= (mod main_~x~0 2) 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,457 INFO L290 TraceCheckUtils]: 5: Hoare triple {2838#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {2988#(<= (mod main_~x~0 2) 0)} is VALID [2022-04-27 21:20:30,457 INFO L272 TraceCheckUtils]: 4: Hoare triple {2838#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,457 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2838#true} {2838#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,457 INFO L290 TraceCheckUtils]: 2: Hoare triple {2838#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,457 INFO L290 TraceCheckUtils]: 1: Hoare triple {2838#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2838#true} is VALID [2022-04-27 21:20:30,457 INFO L272 TraceCheckUtils]: 0: Hoare triple {2838#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2838#true} is VALID [2022-04-27 21:20:30,458 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 0 proven. 84 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2022-04-27 21:20:30,458 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [270180533] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:30,458 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:30,458 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 17, 7] total 22 [2022-04-27 21:20:30,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021747296] [2022-04-27 21:20:30,458 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:30,459 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-27 21:20:30,459 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:30,459 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:30,492 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 50 edges. 50 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:30,492 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 22 states [2022-04-27 21:20:30,492 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:30,493 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2022-04-27 21:20:30,493 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=394, Unknown=0, NotChecked=0, Total=462 [2022-04-27 21:20:30,493 INFO L87 Difference]: Start difference. First operand 63 states and 65 transitions. Second operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:31,945 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:31,945 INFO L93 Difference]: Finished difference Result 77 states and 80 transitions. [2022-04-27 21:20:31,945 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2022-04-27 21:20:31,945 INFO L78 Accepts]: Start accepts. Automaton has has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 35 [2022-04-27 21:20:31,946 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:31,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:31,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 67 transitions. [2022-04-27 21:20:31,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:31,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 67 transitions. [2022-04-27 21:20:31,948 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 27 states and 67 transitions. [2022-04-27 21:20:32,006 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:32,007 INFO L225 Difference]: With dead ends: 77 [2022-04-27 21:20:32,007 INFO L226 Difference]: Without dead ends: 69 [2022-04-27 21:20:32,008 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 65 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 297 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=253, Invalid=1817, Unknown=0, NotChecked=0, Total=2070 [2022-04-27 21:20:32,010 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 46 mSDsluCounter, 67 mSDsCounter, 0 mSdLazyCounter, 615 mSolverCounterSat, 52 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 46 SdHoareTripleChecker+Valid, 78 SdHoareTripleChecker+Invalid, 667 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 52 IncrementalHoareTripleChecker+Valid, 615 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:32,010 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [46 Valid, 78 Invalid, 667 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [52 Valid, 615 Invalid, 0 Unknown, 0 Unchecked, 0.5s Time] [2022-04-27 21:20:32,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2022-04-27 21:20:32,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 65. [2022-04-27 21:20:32,094 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:32,095 INFO L82 GeneralOperation]: Start isEquivalent. First operand 69 states. Second operand has 65 states, 60 states have (on average 1.05) internal successors, (63), 60 states have internal predecessors, (63), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:32,095 INFO L74 IsIncluded]: Start isIncluded. First operand 69 states. Second operand has 65 states, 60 states have (on average 1.05) internal successors, (63), 60 states have internal predecessors, (63), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:32,096 INFO L87 Difference]: Start difference. First operand 69 states. Second operand has 65 states, 60 states have (on average 1.05) internal successors, (63), 60 states have internal predecessors, (63), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:32,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:32,097 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2022-04-27 21:20:32,097 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 71 transitions. [2022-04-27 21:20:32,098 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:32,098 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:32,098 INFO L74 IsIncluded]: Start isIncluded. First operand has 65 states, 60 states have (on average 1.05) internal successors, (63), 60 states have internal predecessors, (63), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 69 states. [2022-04-27 21:20:32,098 INFO L87 Difference]: Start difference. First operand has 65 states, 60 states have (on average 1.05) internal successors, (63), 60 states have internal predecessors, (63), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 69 states. [2022-04-27 21:20:32,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:32,108 INFO L93 Difference]: Finished difference Result 69 states and 71 transitions. [2022-04-27 21:20:32,108 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 71 transitions. [2022-04-27 21:20:32,109 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:32,109 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:32,109 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:32,109 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:32,109 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 65 states, 60 states have (on average 1.05) internal successors, (63), 60 states have internal predecessors, (63), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:32,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 67 transitions. [2022-04-27 21:20:32,115 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 67 transitions. Word has length 35 [2022-04-27 21:20:32,116 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:32,116 INFO L495 AbstractCegarLoop]: Abstraction has 65 states and 67 transitions. [2022-04-27 21:20:32,116 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 22 states, 22 states have (on average 1.9545454545454546) internal successors, (43), 20 states have internal predecessors, (43), 4 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:32,116 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 67 transitions. [2022-04-27 21:20:32,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2022-04-27 21:20:32,116 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:32,116 INFO L195 NwaCegarLoop]: trace histogram [13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:32,124 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Ended with exit code 0 [2022-04-27 21:20:32,322 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:32,323 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:32,323 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:32,323 INFO L85 PathProgramCache]: Analyzing trace with hash 794106220, now seen corresponding path program 4 times [2022-04-27 21:20:32,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:32,323 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [683803223] [2022-04-27 21:20:32,323 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:32,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:32,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:32,526 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:32,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:32,530 INFO L290 TraceCheckUtils]: 0: Hoare triple {3493#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3474#true} is VALID [2022-04-27 21:20:32,530 INFO L290 TraceCheckUtils]: 1: Hoare triple {3474#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,531 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3474#true} {3474#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,531 INFO L272 TraceCheckUtils]: 0: Hoare triple {3474#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3493#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:32,531 INFO L290 TraceCheckUtils]: 1: Hoare triple {3493#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3474#true} is VALID [2022-04-27 21:20:32,531 INFO L290 TraceCheckUtils]: 2: Hoare triple {3474#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,531 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3474#true} {3474#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,531 INFO L272 TraceCheckUtils]: 4: Hoare triple {3474#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,532 INFO L290 TraceCheckUtils]: 5: Hoare triple {3474#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {3479#(= main_~x~0 0)} is VALID [2022-04-27 21:20:32,532 INFO L290 TraceCheckUtils]: 6: Hoare triple {3479#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3479#(= main_~x~0 0)} is VALID [2022-04-27 21:20:32,532 INFO L290 TraceCheckUtils]: 7: Hoare triple {3479#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:32,533 INFO L290 TraceCheckUtils]: 8: Hoare triple {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:32,533 INFO L290 TraceCheckUtils]: 9: Hoare triple {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:32,534 INFO L290 TraceCheckUtils]: 10: Hoare triple {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:32,534 INFO L290 TraceCheckUtils]: 11: Hoare triple {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:32,534 INFO L290 TraceCheckUtils]: 12: Hoare triple {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:32,535 INFO L290 TraceCheckUtils]: 13: Hoare triple {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:32,535 INFO L290 TraceCheckUtils]: 14: Hoare triple {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:32,536 INFO L290 TraceCheckUtils]: 15: Hoare triple {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:32,536 INFO L290 TraceCheckUtils]: 16: Hoare triple {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:32,537 INFO L290 TraceCheckUtils]: 17: Hoare triple {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:32,537 INFO L290 TraceCheckUtils]: 18: Hoare triple {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:32,538 INFO L290 TraceCheckUtils]: 19: Hoare triple {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:32,538 INFO L290 TraceCheckUtils]: 20: Hoare triple {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:32,538 INFO L290 TraceCheckUtils]: 21: Hoare triple {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:32,539 INFO L290 TraceCheckUtils]: 22: Hoare triple {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:32,540 INFO L290 TraceCheckUtils]: 23: Hoare triple {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:32,540 INFO L290 TraceCheckUtils]: 24: Hoare triple {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:32,541 INFO L290 TraceCheckUtils]: 25: Hoare triple {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:32,541 INFO L290 TraceCheckUtils]: 26: Hoare triple {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:32,541 INFO L290 TraceCheckUtils]: 27: Hoare triple {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:32,542 INFO L290 TraceCheckUtils]: 28: Hoare triple {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:32,542 INFO L290 TraceCheckUtils]: 29: Hoare triple {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:32,543 INFO L290 TraceCheckUtils]: 30: Hoare triple {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:32,543 INFO L290 TraceCheckUtils]: 31: Hoare triple {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3492#(and (<= main_~x~0 13) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:20:32,554 INFO L290 TraceCheckUtils]: 32: Hoare triple {3492#(and (<= main_~x~0 13) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:32,554 INFO L272 TraceCheckUtils]: 33: Hoare triple {3475#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {3475#false} is VALID [2022-04-27 21:20:32,554 INFO L290 TraceCheckUtils]: 34: Hoare triple {3475#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3475#false} is VALID [2022-04-27 21:20:32,555 INFO L290 TraceCheckUtils]: 35: Hoare triple {3475#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:32,555 INFO L290 TraceCheckUtils]: 36: Hoare triple {3475#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:32,555 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:32,555 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:32,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [683803223] [2022-04-27 21:20:32,555 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [683803223] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:32,555 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [177821974] [2022-04-27 21:20:32,555 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 21:20:32,556 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:32,556 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:32,557 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:32,574 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 21:20:32,603 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 21:20:32,604 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:32,605 INFO L263 TraceCheckSpWp]: Trace formula consists of 118 conjuncts, 29 conjunts are in the unsatisfiable core [2022-04-27 21:20:32,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:32,611 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:32,902 INFO L272 TraceCheckUtils]: 0: Hoare triple {3474#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,902 INFO L290 TraceCheckUtils]: 1: Hoare triple {3474#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3474#true} is VALID [2022-04-27 21:20:32,902 INFO L290 TraceCheckUtils]: 2: Hoare triple {3474#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,903 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3474#true} {3474#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,903 INFO L272 TraceCheckUtils]: 4: Hoare triple {3474#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:32,903 INFO L290 TraceCheckUtils]: 5: Hoare triple {3474#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {3479#(= main_~x~0 0)} is VALID [2022-04-27 21:20:32,904 INFO L290 TraceCheckUtils]: 6: Hoare triple {3479#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3479#(= main_~x~0 0)} is VALID [2022-04-27 21:20:32,904 INFO L290 TraceCheckUtils]: 7: Hoare triple {3479#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:32,904 INFO L290 TraceCheckUtils]: 8: Hoare triple {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:20:32,905 INFO L290 TraceCheckUtils]: 9: Hoare triple {3480#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:32,905 INFO L290 TraceCheckUtils]: 10: Hoare triple {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:32,906 INFO L290 TraceCheckUtils]: 11: Hoare triple {3481#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:32,906 INFO L290 TraceCheckUtils]: 12: Hoare triple {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:20:32,906 INFO L290 TraceCheckUtils]: 13: Hoare triple {3482#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:32,907 INFO L290 TraceCheckUtils]: 14: Hoare triple {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:32,907 INFO L290 TraceCheckUtils]: 15: Hoare triple {3483#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:32,908 INFO L290 TraceCheckUtils]: 16: Hoare triple {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:20:32,908 INFO L290 TraceCheckUtils]: 17: Hoare triple {3484#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:32,908 INFO L290 TraceCheckUtils]: 18: Hoare triple {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:32,909 INFO L290 TraceCheckUtils]: 19: Hoare triple {3485#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:32,909 INFO L290 TraceCheckUtils]: 20: Hoare triple {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:20:32,910 INFO L290 TraceCheckUtils]: 21: Hoare triple {3486#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:32,910 INFO L290 TraceCheckUtils]: 22: Hoare triple {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:32,910 INFO L290 TraceCheckUtils]: 23: Hoare triple {3487#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:32,911 INFO L290 TraceCheckUtils]: 24: Hoare triple {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:20:32,911 INFO L290 TraceCheckUtils]: 25: Hoare triple {3488#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:32,912 INFO L290 TraceCheckUtils]: 26: Hoare triple {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:32,912 INFO L290 TraceCheckUtils]: 27: Hoare triple {3489#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:32,913 INFO L290 TraceCheckUtils]: 28: Hoare triple {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:20:32,913 INFO L290 TraceCheckUtils]: 29: Hoare triple {3490#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:32,913 INFO L290 TraceCheckUtils]: 30: Hoare triple {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:32,914 INFO L290 TraceCheckUtils]: 31: Hoare triple {3491#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3590#(and (<= main_~x~0 13) (<= 13 main_~x~0))} is VALID [2022-04-27 21:20:32,914 INFO L290 TraceCheckUtils]: 32: Hoare triple {3590#(and (<= main_~x~0 13) (<= 13 main_~x~0))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:32,914 INFO L272 TraceCheckUtils]: 33: Hoare triple {3475#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {3475#false} is VALID [2022-04-27 21:20:32,915 INFO L290 TraceCheckUtils]: 34: Hoare triple {3475#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3475#false} is VALID [2022-04-27 21:20:32,915 INFO L290 TraceCheckUtils]: 35: Hoare triple {3475#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:32,915 INFO L290 TraceCheckUtils]: 36: Hoare triple {3475#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:32,915 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:32,915 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:33,379 INFO L290 TraceCheckUtils]: 36: Hoare triple {3475#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:33,379 INFO L290 TraceCheckUtils]: 35: Hoare triple {3475#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:33,379 INFO L290 TraceCheckUtils]: 34: Hoare triple {3475#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3475#false} is VALID [2022-04-27 21:20:33,380 INFO L272 TraceCheckUtils]: 33: Hoare triple {3475#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {3475#false} is VALID [2022-04-27 21:20:33,380 INFO L290 TraceCheckUtils]: 32: Hoare triple {3618#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {3475#false} is VALID [2022-04-27 21:20:33,381 INFO L290 TraceCheckUtils]: 31: Hoare triple {3622#(< (mod (+ main_~x~0 1) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3618#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:20:33,381 INFO L290 TraceCheckUtils]: 30: Hoare triple {3622#(< (mod (+ main_~x~0 1) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3622#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:20:33,381 INFO L290 TraceCheckUtils]: 29: Hoare triple {3629#(< (mod (+ main_~x~0 2) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3622#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:20:33,382 INFO L290 TraceCheckUtils]: 28: Hoare triple {3629#(< (mod (+ main_~x~0 2) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3629#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:33,382 INFO L290 TraceCheckUtils]: 27: Hoare triple {3636#(< (mod (+ main_~x~0 3) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3629#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:20:33,383 INFO L290 TraceCheckUtils]: 26: Hoare triple {3636#(< (mod (+ main_~x~0 3) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3636#(< (mod (+ main_~x~0 3) 4294967296) 99)} is VALID [2022-04-27 21:20:33,383 INFO L290 TraceCheckUtils]: 25: Hoare triple {3643#(< (mod (+ main_~x~0 4) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3636#(< (mod (+ main_~x~0 3) 4294967296) 99)} is VALID [2022-04-27 21:20:33,384 INFO L290 TraceCheckUtils]: 24: Hoare triple {3643#(< (mod (+ main_~x~0 4) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3643#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:33,384 INFO L290 TraceCheckUtils]: 23: Hoare triple {3650#(< (mod (+ 5 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3643#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:20:33,385 INFO L290 TraceCheckUtils]: 22: Hoare triple {3650#(< (mod (+ 5 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3650#(< (mod (+ 5 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:20:33,385 INFO L290 TraceCheckUtils]: 21: Hoare triple {3657#(< (mod (+ main_~x~0 6) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3650#(< (mod (+ 5 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:20:33,385 INFO L290 TraceCheckUtils]: 20: Hoare triple {3657#(< (mod (+ main_~x~0 6) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3657#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:20:33,386 INFO L290 TraceCheckUtils]: 19: Hoare triple {3664#(< (mod (+ 7 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3657#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:20:33,386 INFO L290 TraceCheckUtils]: 18: Hoare triple {3664#(< (mod (+ 7 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3664#(< (mod (+ 7 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:20:33,387 INFO L290 TraceCheckUtils]: 17: Hoare triple {3671#(< (mod (+ main_~x~0 8) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3664#(< (mod (+ 7 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:20:33,387 INFO L290 TraceCheckUtils]: 16: Hoare triple {3671#(< (mod (+ main_~x~0 8) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3671#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:20:33,388 INFO L290 TraceCheckUtils]: 15: Hoare triple {3678#(< (mod (+ main_~x~0 9) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3671#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:20:33,388 INFO L290 TraceCheckUtils]: 14: Hoare triple {3678#(< (mod (+ main_~x~0 9) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3678#(< (mod (+ main_~x~0 9) 4294967296) 99)} is VALID [2022-04-27 21:20:33,389 INFO L290 TraceCheckUtils]: 13: Hoare triple {3685#(< (mod (+ main_~x~0 10) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3678#(< (mod (+ main_~x~0 9) 4294967296) 99)} is VALID [2022-04-27 21:20:33,389 INFO L290 TraceCheckUtils]: 12: Hoare triple {3685#(< (mod (+ main_~x~0 10) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3685#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:20:33,390 INFO L290 TraceCheckUtils]: 11: Hoare triple {3692#(< (mod (+ main_~x~0 11) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3685#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:20:33,390 INFO L290 TraceCheckUtils]: 10: Hoare triple {3692#(< (mod (+ main_~x~0 11) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3692#(< (mod (+ main_~x~0 11) 4294967296) 99)} is VALID [2022-04-27 21:20:33,391 INFO L290 TraceCheckUtils]: 9: Hoare triple {3699#(< (mod (+ main_~x~0 12) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3692#(< (mod (+ main_~x~0 11) 4294967296) 99)} is VALID [2022-04-27 21:20:33,391 INFO L290 TraceCheckUtils]: 8: Hoare triple {3699#(< (mod (+ main_~x~0 12) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3699#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:20:33,392 INFO L290 TraceCheckUtils]: 7: Hoare triple {3706#(< (mod (+ main_~x~0 13) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {3699#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:20:33,392 INFO L290 TraceCheckUtils]: 6: Hoare triple {3706#(< (mod (+ main_~x~0 13) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {3706#(< (mod (+ main_~x~0 13) 4294967296) 99)} is VALID [2022-04-27 21:20:33,392 INFO L290 TraceCheckUtils]: 5: Hoare triple {3474#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {3706#(< (mod (+ main_~x~0 13) 4294967296) 99)} is VALID [2022-04-27 21:20:33,392 INFO L272 TraceCheckUtils]: 4: Hoare triple {3474#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:33,392 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3474#true} {3474#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:33,392 INFO L290 TraceCheckUtils]: 2: Hoare triple {3474#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:33,393 INFO L290 TraceCheckUtils]: 1: Hoare triple {3474#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3474#true} is VALID [2022-04-27 21:20:33,393 INFO L272 TraceCheckUtils]: 0: Hoare triple {3474#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3474#true} is VALID [2022-04-27 21:20:33,393 INFO L134 CoverageAnalysis]: Checked inductivity of 169 backedges. 0 proven. 169 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:33,393 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [177821974] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:33,393 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:33,393 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16] total 32 [2022-04-27 21:20:33,393 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1321927733] [2022-04-27 21:20:33,393 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:33,394 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 37 [2022-04-27 21:20:33,394 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:33,394 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:33,446 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 69 edges. 69 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:33,446 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-04-27 21:20:33,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:33,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-04-27 21:20:33,447 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=285, Invalid=707, Unknown=0, NotChecked=0, Total=992 [2022-04-27 21:20:33,447 INFO L87 Difference]: Start difference. First operand 65 states and 67 transitions. Second operand has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:41,024 INFO L93 Difference]: Finished difference Result 103 states and 112 transitions. [2022-04-27 21:20:41,024 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2022-04-27 21:20:41,024 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 37 [2022-04-27 21:20:41,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:20:41,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 95 transitions. [2022-04-27 21:20:41,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,026 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 95 transitions. [2022-04-27 21:20:41,026 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 31 states and 95 transitions. [2022-04-27 21:20:41,204 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 95 edges. 95 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:41,205 INFO L225 Difference]: With dead ends: 103 [2022-04-27 21:20:41,205 INFO L226 Difference]: Without dead ends: 98 [2022-04-27 21:20:41,206 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 61 SyntacticMatches, 1 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 460 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=985, Invalid=2555, Unknown=0, NotChecked=0, Total=3540 [2022-04-27 21:20:41,207 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 45 mSDsluCounter, 82 mSDsCounter, 0 mSdLazyCounter, 625 mSolverCounterSat, 176 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 45 SdHoareTripleChecker+Valid, 93 SdHoareTripleChecker+Invalid, 801 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 176 IncrementalHoareTripleChecker+Valid, 625 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-04-27 21:20:41,207 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [45 Valid, 93 Invalid, 801 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [176 Valid, 625 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-04-27 21:20:41,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2022-04-27 21:20:41,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 97. [2022-04-27 21:20:41,326 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:20:41,327 INFO L82 GeneralOperation]: Start isEquivalent. First operand 98 states. Second operand has 97 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 92 states have internal predecessors, (95), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,327 INFO L74 IsIncluded]: Start isIncluded. First operand 98 states. Second operand has 97 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 92 states have internal predecessors, (95), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,327 INFO L87 Difference]: Start difference. First operand 98 states. Second operand has 97 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 92 states have internal predecessors, (95), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:41,328 INFO L93 Difference]: Finished difference Result 98 states and 100 transitions. [2022-04-27 21:20:41,328 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 100 transitions. [2022-04-27 21:20:41,328 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:41,329 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:41,329 INFO L74 IsIncluded]: Start isIncluded. First operand has 97 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 92 states have internal predecessors, (95), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 98 states. [2022-04-27 21:20:41,329 INFO L87 Difference]: Start difference. First operand has 97 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 92 states have internal predecessors, (95), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 98 states. [2022-04-27 21:20:41,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:20:41,330 INFO L93 Difference]: Finished difference Result 98 states and 100 transitions. [2022-04-27 21:20:41,330 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 100 transitions. [2022-04-27 21:20:41,330 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:20:41,330 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:20:41,330 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:20:41,330 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:20:41,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 92 states have (on average 1.0326086956521738) internal successors, (95), 92 states have internal predecessors, (95), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 99 transitions. [2022-04-27 21:20:41,332 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 99 transitions. Word has length 37 [2022-04-27 21:20:41,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:20:41,332 INFO L495 AbstractCegarLoop]: Abstraction has 97 states and 99 transitions. [2022-04-27 21:20:41,332 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 32 states have (on average 2.0) internal successors, (64), 31 states have internal predecessors, (64), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:41,332 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 99 transitions. [2022-04-27 21:20:41,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2022-04-27 21:20:41,333 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:20:41,333 INFO L195 NwaCegarLoop]: trace histogram [14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:20:41,350 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-27 21:20:41,539 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:41,540 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:20:41,540 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:20:41,540 INFO L85 PathProgramCache]: Analyzing trace with hash -1208240388, now seen corresponding path program 3 times [2022-04-27 21:20:41,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:20:41,540 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800231087] [2022-04-27 21:20:41,540 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:20:41,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:20:41,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:41,772 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:20:41,774 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:41,782 INFO L290 TraceCheckUtils]: 0: Hoare triple {4304#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4284#true} is VALID [2022-04-27 21:20:41,782 INFO L290 TraceCheckUtils]: 1: Hoare triple {4284#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:41,783 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4284#true} {4284#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:41,783 INFO L272 TraceCheckUtils]: 0: Hoare triple {4284#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4304#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:20:41,783 INFO L290 TraceCheckUtils]: 1: Hoare triple {4304#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4284#true} is VALID [2022-04-27 21:20:41,783 INFO L290 TraceCheckUtils]: 2: Hoare triple {4284#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:41,783 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4284#true} {4284#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:41,783 INFO L272 TraceCheckUtils]: 4: Hoare triple {4284#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:41,784 INFO L290 TraceCheckUtils]: 5: Hoare triple {4284#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {4289#(= main_~x~0 0)} is VALID [2022-04-27 21:20:41,784 INFO L290 TraceCheckUtils]: 6: Hoare triple {4289#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4289#(= main_~x~0 0)} is VALID [2022-04-27 21:20:41,784 INFO L290 TraceCheckUtils]: 7: Hoare triple {4289#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:41,785 INFO L290 TraceCheckUtils]: 8: Hoare triple {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:41,785 INFO L290 TraceCheckUtils]: 9: Hoare triple {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:41,786 INFO L290 TraceCheckUtils]: 10: Hoare triple {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:41,786 INFO L290 TraceCheckUtils]: 11: Hoare triple {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:41,786 INFO L290 TraceCheckUtils]: 12: Hoare triple {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:41,787 INFO L290 TraceCheckUtils]: 13: Hoare triple {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:41,787 INFO L290 TraceCheckUtils]: 14: Hoare triple {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:41,788 INFO L290 TraceCheckUtils]: 15: Hoare triple {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:41,788 INFO L290 TraceCheckUtils]: 16: Hoare triple {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:41,788 INFO L290 TraceCheckUtils]: 17: Hoare triple {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:41,789 INFO L290 TraceCheckUtils]: 18: Hoare triple {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:41,789 INFO L290 TraceCheckUtils]: 19: Hoare triple {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:20:41,790 INFO L290 TraceCheckUtils]: 20: Hoare triple {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:20:41,790 INFO L290 TraceCheckUtils]: 21: Hoare triple {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:20:41,790 INFO L290 TraceCheckUtils]: 22: Hoare triple {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:20:41,791 INFO L290 TraceCheckUtils]: 23: Hoare triple {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:20:41,791 INFO L290 TraceCheckUtils]: 24: Hoare triple {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:20:41,792 INFO L290 TraceCheckUtils]: 25: Hoare triple {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:20:41,792 INFO L290 TraceCheckUtils]: 26: Hoare triple {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:20:41,792 INFO L290 TraceCheckUtils]: 27: Hoare triple {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:20:41,793 INFO L290 TraceCheckUtils]: 28: Hoare triple {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:20:41,793 INFO L290 TraceCheckUtils]: 29: Hoare triple {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:20:41,794 INFO L290 TraceCheckUtils]: 30: Hoare triple {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:20:41,794 INFO L290 TraceCheckUtils]: 31: Hoare triple {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:20:41,794 INFO L290 TraceCheckUtils]: 32: Hoare triple {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:20:41,795 INFO L290 TraceCheckUtils]: 33: Hoare triple {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4303#(and (not (<= (+ (div main_~x~0 4294967296) 1) 0)) (<= main_~x~0 28))} is VALID [2022-04-27 21:20:41,795 INFO L290 TraceCheckUtils]: 34: Hoare triple {4303#(and (not (<= (+ (div main_~x~0 4294967296) 1) 0)) (<= main_~x~0 28))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:41,795 INFO L272 TraceCheckUtils]: 35: Hoare triple {4285#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {4285#false} is VALID [2022-04-27 21:20:41,796 INFO L290 TraceCheckUtils]: 36: Hoare triple {4285#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4285#false} is VALID [2022-04-27 21:20:41,796 INFO L290 TraceCheckUtils]: 37: Hoare triple {4285#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:41,796 INFO L290 TraceCheckUtils]: 38: Hoare triple {4285#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:41,796 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:41,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:20:41,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800231087] [2022-04-27 21:20:41,796 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800231087] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:20:41,796 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [710781791] [2022-04-27 21:20:41,797 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 21:20:41,797 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:20:41,797 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:20:41,798 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:20:41,798 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 21:20:41,891 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2022-04-27 21:20:41,891 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:20:41,892 INFO L263 TraceCheckSpWp]: Trace formula consists of 109 conjuncts, 35 conjunts are in the unsatisfiable core [2022-04-27 21:20:41,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:20:41,900 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:20:42,217 INFO L272 TraceCheckUtils]: 0: Hoare triple {4284#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:42,218 INFO L290 TraceCheckUtils]: 1: Hoare triple {4284#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4284#true} is VALID [2022-04-27 21:20:42,218 INFO L290 TraceCheckUtils]: 2: Hoare triple {4284#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:42,218 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4284#true} {4284#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:42,218 INFO L272 TraceCheckUtils]: 4: Hoare triple {4284#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:42,218 INFO L290 TraceCheckUtils]: 5: Hoare triple {4284#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {4289#(= main_~x~0 0)} is VALID [2022-04-27 21:20:42,219 INFO L290 TraceCheckUtils]: 6: Hoare triple {4289#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4289#(= main_~x~0 0)} is VALID [2022-04-27 21:20:42,219 INFO L290 TraceCheckUtils]: 7: Hoare triple {4289#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:42,219 INFO L290 TraceCheckUtils]: 8: Hoare triple {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:20:42,220 INFO L290 TraceCheckUtils]: 9: Hoare triple {4290#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:42,220 INFO L290 TraceCheckUtils]: 10: Hoare triple {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:20:42,220 INFO L290 TraceCheckUtils]: 11: Hoare triple {4291#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:42,221 INFO L290 TraceCheckUtils]: 12: Hoare triple {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:20:42,221 INFO L290 TraceCheckUtils]: 13: Hoare triple {4292#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:42,222 INFO L290 TraceCheckUtils]: 14: Hoare triple {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:20:42,222 INFO L290 TraceCheckUtils]: 15: Hoare triple {4293#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:42,222 INFO L290 TraceCheckUtils]: 16: Hoare triple {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:20:42,223 INFO L290 TraceCheckUtils]: 17: Hoare triple {4294#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:42,223 INFO L290 TraceCheckUtils]: 18: Hoare triple {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:20:42,224 INFO L290 TraceCheckUtils]: 19: Hoare triple {4295#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:20:42,224 INFO L290 TraceCheckUtils]: 20: Hoare triple {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:20:42,225 INFO L290 TraceCheckUtils]: 21: Hoare triple {4296#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:20:42,225 INFO L290 TraceCheckUtils]: 22: Hoare triple {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:20:42,226 INFO L290 TraceCheckUtils]: 23: Hoare triple {4297#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:20:42,226 INFO L290 TraceCheckUtils]: 24: Hoare triple {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:20:42,226 INFO L290 TraceCheckUtils]: 25: Hoare triple {4298#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:20:42,227 INFO L290 TraceCheckUtils]: 26: Hoare triple {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:20:42,227 INFO L290 TraceCheckUtils]: 27: Hoare triple {4299#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:20:42,228 INFO L290 TraceCheckUtils]: 28: Hoare triple {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:20:42,228 INFO L290 TraceCheckUtils]: 29: Hoare triple {4300#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:20:42,229 INFO L290 TraceCheckUtils]: 30: Hoare triple {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:20:42,229 INFO L290 TraceCheckUtils]: 31: Hoare triple {4301#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:20:42,229 INFO L290 TraceCheckUtils]: 32: Hoare triple {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:20:42,230 INFO L290 TraceCheckUtils]: 33: Hoare triple {4302#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4407#(and (<= 28 main_~x~0) (not (= (mod main_~y~0 2) 0)) (<= main_~x~0 28))} is VALID [2022-04-27 21:20:42,231 INFO L290 TraceCheckUtils]: 34: Hoare triple {4407#(and (<= 28 main_~x~0) (not (= (mod main_~y~0 2) 0)) (<= main_~x~0 28))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:42,231 INFO L272 TraceCheckUtils]: 35: Hoare triple {4285#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {4285#false} is VALID [2022-04-27 21:20:42,231 INFO L290 TraceCheckUtils]: 36: Hoare triple {4285#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4285#false} is VALID [2022-04-27 21:20:42,231 INFO L290 TraceCheckUtils]: 37: Hoare triple {4285#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:42,231 INFO L290 TraceCheckUtils]: 38: Hoare triple {4285#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:42,231 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:42,232 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:20:43,256 INFO L290 TraceCheckUtils]: 38: Hoare triple {4285#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:43,256 INFO L290 TraceCheckUtils]: 37: Hoare triple {4426#(not (<= __VERIFIER_assert_~cond 0))} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4285#false} is VALID [2022-04-27 21:20:43,257 INFO L290 TraceCheckUtils]: 36: Hoare triple {4430#(< 0 |__VERIFIER_assert_#in~cond|)} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4426#(not (<= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:20:43,257 INFO L272 TraceCheckUtils]: 35: Hoare triple {4434#(= (mod main_~x~0 2) (mod main_~y~0 2))} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {4430#(< 0 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:20:43,258 INFO L290 TraceCheckUtils]: 34: Hoare triple {4438#(or (< (mod main_~x~0 4294967296) 99) (= (mod main_~x~0 2) (mod main_~y~0 2)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {4434#(= (mod main_~x~0 2) (mod main_~y~0 2))} is VALID [2022-04-27 21:20:43,259 INFO L290 TraceCheckUtils]: 33: Hoare triple {4442#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 2) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4438#(or (< (mod main_~x~0 4294967296) 99) (= (mod main_~x~0 2) (mod main_~y~0 2)))} is VALID [2022-04-27 21:20:43,260 INFO L290 TraceCheckUtils]: 32: Hoare triple {4442#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 2) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4442#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 2) 4294967296) 99))} is VALID [2022-04-27 21:20:43,261 INFO L290 TraceCheckUtils]: 31: Hoare triple {4449#(or (< (mod (+ main_~x~0 4) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4442#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 2) 4294967296) 99))} is VALID [2022-04-27 21:20:43,261 INFO L290 TraceCheckUtils]: 30: Hoare triple {4449#(or (< (mod (+ main_~x~0 4) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4449#(or (< (mod (+ main_~x~0 4) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,262 INFO L290 TraceCheckUtils]: 29: Hoare triple {4456#(or (< (mod (+ main_~x~0 6) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4449#(or (< (mod (+ main_~x~0 4) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,262 INFO L290 TraceCheckUtils]: 28: Hoare triple {4456#(or (< (mod (+ main_~x~0 6) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4456#(or (< (mod (+ main_~x~0 6) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,263 INFO L290 TraceCheckUtils]: 27: Hoare triple {4463#(or (< (mod (+ main_~x~0 8) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4456#(or (< (mod (+ main_~x~0 6) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,264 INFO L290 TraceCheckUtils]: 26: Hoare triple {4463#(or (< (mod (+ main_~x~0 8) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4463#(or (< (mod (+ main_~x~0 8) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,264 INFO L290 TraceCheckUtils]: 25: Hoare triple {4470#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 10) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4463#(or (< (mod (+ main_~x~0 8) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,265 INFO L290 TraceCheckUtils]: 24: Hoare triple {4470#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 10) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4470#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 10) 4294967296) 99))} is VALID [2022-04-27 21:20:43,265 INFO L290 TraceCheckUtils]: 23: Hoare triple {4477#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 12) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4470#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 10) 4294967296) 99))} is VALID [2022-04-27 21:20:43,266 INFO L290 TraceCheckUtils]: 22: Hoare triple {4477#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 12) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4477#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 12) 4294967296) 99))} is VALID [2022-04-27 21:20:43,267 INFO L290 TraceCheckUtils]: 21: Hoare triple {4484#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 14) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4477#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 12) 4294967296) 99))} is VALID [2022-04-27 21:20:43,267 INFO L290 TraceCheckUtils]: 20: Hoare triple {4484#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 14) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4484#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 14) 4294967296) 99))} is VALID [2022-04-27 21:20:43,269 INFO L290 TraceCheckUtils]: 19: Hoare triple {4491#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 16) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4484#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 14) 4294967296) 99))} is VALID [2022-04-27 21:20:43,269 INFO L290 TraceCheckUtils]: 18: Hoare triple {4491#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 16) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4491#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 16) 4294967296) 99))} is VALID [2022-04-27 21:20:43,271 INFO L290 TraceCheckUtils]: 17: Hoare triple {4498#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 18) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4491#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 16) 4294967296) 99))} is VALID [2022-04-27 21:20:43,271 INFO L290 TraceCheckUtils]: 16: Hoare triple {4498#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 18) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4498#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 18) 4294967296) 99))} is VALID [2022-04-27 21:20:43,272 INFO L290 TraceCheckUtils]: 15: Hoare triple {4505#(or (< (mod (+ main_~x~0 20) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4498#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 18) 4294967296) 99))} is VALID [2022-04-27 21:20:43,273 INFO L290 TraceCheckUtils]: 14: Hoare triple {4505#(or (< (mod (+ main_~x~0 20) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4505#(or (< (mod (+ main_~x~0 20) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,274 INFO L290 TraceCheckUtils]: 13: Hoare triple {4512#(or (< (mod (+ main_~x~0 22) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4505#(or (< (mod (+ main_~x~0 20) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,274 INFO L290 TraceCheckUtils]: 12: Hoare triple {4512#(or (< (mod (+ main_~x~0 22) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4512#(or (< (mod (+ main_~x~0 22) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,275 INFO L290 TraceCheckUtils]: 11: Hoare triple {4519#(or (< (mod (+ main_~x~0 24) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4512#(or (< (mod (+ main_~x~0 22) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,275 INFO L290 TraceCheckUtils]: 10: Hoare triple {4519#(or (< (mod (+ main_~x~0 24) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4519#(or (< (mod (+ main_~x~0 24) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,276 INFO L290 TraceCheckUtils]: 9: Hoare triple {4526#(or (< (mod (+ main_~x~0 26) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4519#(or (< (mod (+ main_~x~0 24) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,283 INFO L290 TraceCheckUtils]: 8: Hoare triple {4526#(or (< (mod (+ main_~x~0 26) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4526#(or (< (mod (+ main_~x~0 26) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,284 INFO L290 TraceCheckUtils]: 7: Hoare triple {4533#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 28) 4294967296) 99))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {4526#(or (< (mod (+ main_~x~0 26) 4294967296) 99) (<= 1 (mod main_~x~0 2)))} is VALID [2022-04-27 21:20:43,285 INFO L290 TraceCheckUtils]: 6: Hoare triple {4533#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 28) 4294967296) 99))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {4533#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 28) 4294967296) 99))} is VALID [2022-04-27 21:20:43,285 INFO L290 TraceCheckUtils]: 5: Hoare triple {4284#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {4533#(or (<= 1 (mod main_~x~0 2)) (< (mod (+ main_~x~0 28) 4294967296) 99))} is VALID [2022-04-27 21:20:43,285 INFO L272 TraceCheckUtils]: 4: Hoare triple {4284#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:43,285 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4284#true} {4284#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:43,286 INFO L290 TraceCheckUtils]: 2: Hoare triple {4284#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:43,286 INFO L290 TraceCheckUtils]: 1: Hoare triple {4284#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4284#true} is VALID [2022-04-27 21:20:43,286 INFO L272 TraceCheckUtils]: 0: Hoare triple {4284#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4284#true} is VALID [2022-04-27 21:20:43,286 INFO L134 CoverageAnalysis]: Checked inductivity of 196 backedges. 0 proven. 196 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:20:43,286 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [710781791] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:20:43,287 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:20:43,287 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 20] total 37 [2022-04-27 21:20:43,287 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840231821] [2022-04-27 21:20:43,287 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:20:43,288 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 39 [2022-04-27 21:20:43,288 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:20:43,288 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:20:43,345 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 76 edges. 76 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:20:43,346 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-04-27 21:20:43,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:20:43,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-04-27 21:20:43,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1005, Unknown=0, NotChecked=0, Total=1332 [2022-04-27 21:20:43,347 INFO L87 Difference]: Start difference. First operand 97 states and 99 transitions. Second operand has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:21:12,190 INFO L93 Difference]: Finished difference Result 138 states and 155 transitions. [2022-04-27 21:21:12,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2022-04-27 21:21:12,190 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 39 [2022-04-27 21:21:12,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:21:12,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 101 transitions. [2022-04-27 21:21:12,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,192 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 101 transitions. [2022-04-27 21:21:12,192 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 38 states and 101 transitions. [2022-04-27 21:21:12,526 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 101 edges. 101 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:21:12,527 INFO L225 Difference]: With dead ends: 138 [2022-04-27 21:21:12,527 INFO L226 Difference]: Without dead ends: 129 [2022-04-27 21:21:12,529 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 132 GetRequests, 61 SyntacticMatches, 1 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 837 ImplicationChecksByTransitivity, 24.9s TimeCoverageRelationStatistics Valid=1222, Invalid=3890, Unknown=0, NotChecked=0, Total=5112 [2022-04-27 21:21:12,529 INFO L413 NwaCegarLoop]: 9 mSDtfsCounter, 149 mSDsluCounter, 97 mSDsCounter, 0 mSdLazyCounter, 752 mSolverCounterSat, 179 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 149 SdHoareTripleChecker+Valid, 106 SdHoareTripleChecker+Invalid, 931 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 179 IncrementalHoareTripleChecker+Valid, 752 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:21:12,529 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [149 Valid, 106 Invalid, 931 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [179 Valid, 752 Invalid, 0 Unknown, 0 Unchecked, 2.0s Time] [2022-04-27 21:21:12,530 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2022-04-27 21:21:12,683 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 129. [2022-04-27 21:21:12,683 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:21:12,684 INFO L82 GeneralOperation]: Start isEquivalent. First operand 129 states. Second operand has 129 states, 124 states have (on average 1.0241935483870968) internal successors, (127), 124 states have internal predecessors, (127), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,684 INFO L74 IsIncluded]: Start isIncluded. First operand 129 states. Second operand has 129 states, 124 states have (on average 1.0241935483870968) internal successors, (127), 124 states have internal predecessors, (127), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,684 INFO L87 Difference]: Start difference. First operand 129 states. Second operand has 129 states, 124 states have (on average 1.0241935483870968) internal successors, (127), 124 states have internal predecessors, (127), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:21:12,692 INFO L93 Difference]: Finished difference Result 129 states and 131 transitions. [2022-04-27 21:21:12,692 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 131 transitions. [2022-04-27 21:21:12,693 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:21:12,693 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:21:12,693 INFO L74 IsIncluded]: Start isIncluded. First operand has 129 states, 124 states have (on average 1.0241935483870968) internal successors, (127), 124 states have internal predecessors, (127), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 129 states. [2022-04-27 21:21:12,693 INFO L87 Difference]: Start difference. First operand has 129 states, 124 states have (on average 1.0241935483870968) internal successors, (127), 124 states have internal predecessors, (127), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 129 states. [2022-04-27 21:21:12,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:21:12,695 INFO L93 Difference]: Finished difference Result 129 states and 131 transitions. [2022-04-27 21:21:12,695 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 131 transitions. [2022-04-27 21:21:12,695 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:21:12,695 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:21:12,696 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:21:12,696 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:21:12,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 124 states have (on average 1.0241935483870968) internal successors, (127), 124 states have internal predecessors, (127), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 131 transitions. [2022-04-27 21:21:12,698 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 131 transitions. Word has length 39 [2022-04-27 21:21:12,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:21:12,698 INFO L495 AbstractCegarLoop]: Abstraction has 129 states and 131 transitions. [2022-04-27 21:21:12,700 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 36 states have (on average 1.9444444444444444) internal successors, (70), 35 states have internal predecessors, (70), 3 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:12,700 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 131 transitions. [2022-04-27 21:21:12,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 70 [2022-04-27 21:21:12,701 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:21:12,702 INFO L195 NwaCegarLoop]: trace histogram [29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:21:12,713 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-27 21:21:12,908 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable10,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:21:12,908 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:21:12,909 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:21:12,909 INFO L85 PathProgramCache]: Analyzing trace with hash -1642006708, now seen corresponding path program 5 times [2022-04-27 21:21:12,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:21:12,909 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1635021088] [2022-04-27 21:21:12,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:21:12,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:21:12,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:21:13,522 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:21:13,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:21:13,532 INFO L290 TraceCheckUtils]: 0: Hoare triple {5324#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5289#true} is VALID [2022-04-27 21:21:13,532 INFO L290 TraceCheckUtils]: 1: Hoare triple {5289#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:13,532 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {5289#true} {5289#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:13,533 INFO L272 TraceCheckUtils]: 0: Hoare triple {5289#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5324#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:21:13,533 INFO L290 TraceCheckUtils]: 1: Hoare triple {5324#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5289#true} is VALID [2022-04-27 21:21:13,533 INFO L290 TraceCheckUtils]: 2: Hoare triple {5289#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:13,533 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5289#true} {5289#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:13,533 INFO L272 TraceCheckUtils]: 4: Hoare triple {5289#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:13,533 INFO L290 TraceCheckUtils]: 5: Hoare triple {5289#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {5294#(= main_~x~0 0)} is VALID [2022-04-27 21:21:13,533 INFO L290 TraceCheckUtils]: 6: Hoare triple {5294#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5294#(= main_~x~0 0)} is VALID [2022-04-27 21:21:13,534 INFO L290 TraceCheckUtils]: 7: Hoare triple {5294#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:21:13,534 INFO L290 TraceCheckUtils]: 8: Hoare triple {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:21:13,535 INFO L290 TraceCheckUtils]: 9: Hoare triple {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:21:13,535 INFO L290 TraceCheckUtils]: 10: Hoare triple {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:21:13,536 INFO L290 TraceCheckUtils]: 11: Hoare triple {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:21:13,536 INFO L290 TraceCheckUtils]: 12: Hoare triple {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:21:13,536 INFO L290 TraceCheckUtils]: 13: Hoare triple {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:21:13,537 INFO L290 TraceCheckUtils]: 14: Hoare triple {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:21:13,537 INFO L290 TraceCheckUtils]: 15: Hoare triple {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:21:13,537 INFO L290 TraceCheckUtils]: 16: Hoare triple {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:21:13,538 INFO L290 TraceCheckUtils]: 17: Hoare triple {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:21:13,538 INFO L290 TraceCheckUtils]: 18: Hoare triple {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:21:13,539 INFO L290 TraceCheckUtils]: 19: Hoare triple {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:21:13,539 INFO L290 TraceCheckUtils]: 20: Hoare triple {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:21:13,540 INFO L290 TraceCheckUtils]: 21: Hoare triple {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:21:13,540 INFO L290 TraceCheckUtils]: 22: Hoare triple {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:21:13,540 INFO L290 TraceCheckUtils]: 23: Hoare triple {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:21:13,541 INFO L290 TraceCheckUtils]: 24: Hoare triple {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:21:13,541 INFO L290 TraceCheckUtils]: 25: Hoare triple {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:21:13,541 INFO L290 TraceCheckUtils]: 26: Hoare triple {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:21:13,542 INFO L290 TraceCheckUtils]: 27: Hoare triple {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:21:13,542 INFO L290 TraceCheckUtils]: 28: Hoare triple {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:21:13,543 INFO L290 TraceCheckUtils]: 29: Hoare triple {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:21:13,543 INFO L290 TraceCheckUtils]: 30: Hoare triple {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:21:13,543 INFO L290 TraceCheckUtils]: 31: Hoare triple {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} is VALID [2022-04-27 21:21:13,544 INFO L290 TraceCheckUtils]: 32: Hoare triple {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} is VALID [2022-04-27 21:21:13,544 INFO L290 TraceCheckUtils]: 33: Hoare triple {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:21:13,545 INFO L290 TraceCheckUtils]: 34: Hoare triple {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:21:13,545 INFO L290 TraceCheckUtils]: 35: Hoare triple {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} is VALID [2022-04-27 21:21:13,545 INFO L290 TraceCheckUtils]: 36: Hoare triple {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} is VALID [2022-04-27 21:21:13,546 INFO L290 TraceCheckUtils]: 37: Hoare triple {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:21:13,546 INFO L290 TraceCheckUtils]: 38: Hoare triple {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:21:13,547 INFO L290 TraceCheckUtils]: 39: Hoare triple {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} is VALID [2022-04-27 21:21:13,547 INFO L290 TraceCheckUtils]: 40: Hoare triple {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} is VALID [2022-04-27 21:21:13,548 INFO L290 TraceCheckUtils]: 41: Hoare triple {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:21:13,548 INFO L290 TraceCheckUtils]: 42: Hoare triple {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:21:13,548 INFO L290 TraceCheckUtils]: 43: Hoare triple {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} is VALID [2022-04-27 21:21:13,549 INFO L290 TraceCheckUtils]: 44: Hoare triple {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} is VALID [2022-04-27 21:21:13,549 INFO L290 TraceCheckUtils]: 45: Hoare triple {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:21:13,550 INFO L290 TraceCheckUtils]: 46: Hoare triple {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:21:13,550 INFO L290 TraceCheckUtils]: 47: Hoare triple {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} is VALID [2022-04-27 21:21:13,551 INFO L290 TraceCheckUtils]: 48: Hoare triple {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} is VALID [2022-04-27 21:21:13,552 INFO L290 TraceCheckUtils]: 49: Hoare triple {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:21:13,552 INFO L290 TraceCheckUtils]: 50: Hoare triple {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:21:13,553 INFO L290 TraceCheckUtils]: 51: Hoare triple {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} is VALID [2022-04-27 21:21:13,553 INFO L290 TraceCheckUtils]: 52: Hoare triple {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} is VALID [2022-04-27 21:21:13,554 INFO L290 TraceCheckUtils]: 53: Hoare triple {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:21:13,554 INFO L290 TraceCheckUtils]: 54: Hoare triple {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:21:13,555 INFO L290 TraceCheckUtils]: 55: Hoare triple {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} is VALID [2022-04-27 21:21:13,556 INFO L290 TraceCheckUtils]: 56: Hoare triple {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} is VALID [2022-04-27 21:21:13,556 INFO L290 TraceCheckUtils]: 57: Hoare triple {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:21:13,557 INFO L290 TraceCheckUtils]: 58: Hoare triple {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:21:13,557 INFO L290 TraceCheckUtils]: 59: Hoare triple {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} is VALID [2022-04-27 21:21:13,558 INFO L290 TraceCheckUtils]: 60: Hoare triple {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} is VALID [2022-04-27 21:21:13,559 INFO L290 TraceCheckUtils]: 61: Hoare triple {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:21:13,559 INFO L290 TraceCheckUtils]: 62: Hoare triple {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:21:13,560 INFO L290 TraceCheckUtils]: 63: Hoare triple {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5323#(and (<= main_~x~0 29) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:21:13,560 INFO L290 TraceCheckUtils]: 64: Hoare triple {5323#(and (<= main_~x~0 29) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:13,561 INFO L272 TraceCheckUtils]: 65: Hoare triple {5290#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {5290#false} is VALID [2022-04-27 21:21:13,561 INFO L290 TraceCheckUtils]: 66: Hoare triple {5290#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5290#false} is VALID [2022-04-27 21:21:13,561 INFO L290 TraceCheckUtils]: 67: Hoare triple {5290#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:13,561 INFO L290 TraceCheckUtils]: 68: Hoare triple {5290#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:13,562 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:21:13,562 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:21:13,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1635021088] [2022-04-27 21:21:13,562 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1635021088] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:21:13,562 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2101456552] [2022-04-27 21:21:13,562 INFO L93 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2022-04-27 21:21:13,562 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:21:13,562 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:21:13,576 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:21:13,577 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 21:21:24,448 INFO L228 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2022-04-27 21:21:24,448 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:21:24,460 INFO L263 TraceCheckSpWp]: Trace formula consists of 198 conjuncts, 61 conjunts are in the unsatisfiable core [2022-04-27 21:21:24,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:21:24,480 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:21:25,112 INFO L272 TraceCheckUtils]: 0: Hoare triple {5289#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:25,113 INFO L290 TraceCheckUtils]: 1: Hoare triple {5289#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5289#true} is VALID [2022-04-27 21:21:25,113 INFO L290 TraceCheckUtils]: 2: Hoare triple {5289#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:25,113 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5289#true} {5289#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:25,113 INFO L272 TraceCheckUtils]: 4: Hoare triple {5289#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:25,113 INFO L290 TraceCheckUtils]: 5: Hoare triple {5289#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {5294#(= main_~x~0 0)} is VALID [2022-04-27 21:21:25,113 INFO L290 TraceCheckUtils]: 6: Hoare triple {5294#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5294#(= main_~x~0 0)} is VALID [2022-04-27 21:21:25,114 INFO L290 TraceCheckUtils]: 7: Hoare triple {5294#(= main_~x~0 0)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:21:25,114 INFO L290 TraceCheckUtils]: 8: Hoare triple {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} is VALID [2022-04-27 21:21:25,115 INFO L290 TraceCheckUtils]: 9: Hoare triple {5295#(and (<= 1 main_~x~0) (<= main_~x~0 1))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:21:25,115 INFO L290 TraceCheckUtils]: 10: Hoare triple {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:21:25,116 INFO L290 TraceCheckUtils]: 11: Hoare triple {5296#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:21:25,116 INFO L290 TraceCheckUtils]: 12: Hoare triple {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} is VALID [2022-04-27 21:21:25,116 INFO L290 TraceCheckUtils]: 13: Hoare triple {5297#(and (<= main_~x~0 3) (<= 3 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:21:25,117 INFO L290 TraceCheckUtils]: 14: Hoare triple {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:21:25,117 INFO L290 TraceCheckUtils]: 15: Hoare triple {5298#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:21:25,118 INFO L290 TraceCheckUtils]: 16: Hoare triple {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} is VALID [2022-04-27 21:21:25,118 INFO L290 TraceCheckUtils]: 17: Hoare triple {5299#(and (<= 5 main_~x~0) (<= main_~x~0 5))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:21:25,118 INFO L290 TraceCheckUtils]: 18: Hoare triple {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:21:25,119 INFO L290 TraceCheckUtils]: 19: Hoare triple {5300#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:21:25,119 INFO L290 TraceCheckUtils]: 20: Hoare triple {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} is VALID [2022-04-27 21:21:25,120 INFO L290 TraceCheckUtils]: 21: Hoare triple {5301#(and (<= main_~x~0 7) (<= 7 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:21:25,120 INFO L290 TraceCheckUtils]: 22: Hoare triple {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:21:25,120 INFO L290 TraceCheckUtils]: 23: Hoare triple {5302#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:21:25,121 INFO L290 TraceCheckUtils]: 24: Hoare triple {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} is VALID [2022-04-27 21:21:25,121 INFO L290 TraceCheckUtils]: 25: Hoare triple {5303#(and (<= main_~x~0 9) (<= 9 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:21:25,122 INFO L290 TraceCheckUtils]: 26: Hoare triple {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:21:25,122 INFO L290 TraceCheckUtils]: 27: Hoare triple {5304#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:21:25,122 INFO L290 TraceCheckUtils]: 28: Hoare triple {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} is VALID [2022-04-27 21:21:25,123 INFO L290 TraceCheckUtils]: 29: Hoare triple {5305#(and (<= main_~x~0 11) (<= 11 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:21:25,123 INFO L290 TraceCheckUtils]: 30: Hoare triple {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:21:25,124 INFO L290 TraceCheckUtils]: 31: Hoare triple {5306#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} is VALID [2022-04-27 21:21:25,124 INFO L290 TraceCheckUtils]: 32: Hoare triple {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} is VALID [2022-04-27 21:21:25,124 INFO L290 TraceCheckUtils]: 33: Hoare triple {5307#(and (<= main_~x~0 13) (<= 13 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:21:25,125 INFO L290 TraceCheckUtils]: 34: Hoare triple {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:21:25,125 INFO L290 TraceCheckUtils]: 35: Hoare triple {5308#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} is VALID [2022-04-27 21:21:25,126 INFO L290 TraceCheckUtils]: 36: Hoare triple {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} is VALID [2022-04-27 21:21:25,126 INFO L290 TraceCheckUtils]: 37: Hoare triple {5309#(and (<= 15 main_~x~0) (<= main_~x~0 15))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:21:25,126 INFO L290 TraceCheckUtils]: 38: Hoare triple {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:21:25,127 INFO L290 TraceCheckUtils]: 39: Hoare triple {5310#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} is VALID [2022-04-27 21:21:25,127 INFO L290 TraceCheckUtils]: 40: Hoare triple {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} is VALID [2022-04-27 21:21:25,128 INFO L290 TraceCheckUtils]: 41: Hoare triple {5311#(and (<= 17 main_~x~0) (<= main_~x~0 17))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:21:25,128 INFO L290 TraceCheckUtils]: 42: Hoare triple {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:21:25,128 INFO L290 TraceCheckUtils]: 43: Hoare triple {5312#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} is VALID [2022-04-27 21:21:25,129 INFO L290 TraceCheckUtils]: 44: Hoare triple {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} is VALID [2022-04-27 21:21:25,129 INFO L290 TraceCheckUtils]: 45: Hoare triple {5313#(and (<= 19 main_~x~0) (<= main_~x~0 19))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:21:25,130 INFO L290 TraceCheckUtils]: 46: Hoare triple {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:21:25,130 INFO L290 TraceCheckUtils]: 47: Hoare triple {5314#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} is VALID [2022-04-27 21:21:25,130 INFO L290 TraceCheckUtils]: 48: Hoare triple {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} is VALID [2022-04-27 21:21:25,131 INFO L290 TraceCheckUtils]: 49: Hoare triple {5315#(and (<= 21 main_~x~0) (<= main_~x~0 21))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:21:25,131 INFO L290 TraceCheckUtils]: 50: Hoare triple {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:21:25,132 INFO L290 TraceCheckUtils]: 51: Hoare triple {5316#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} is VALID [2022-04-27 21:21:25,132 INFO L290 TraceCheckUtils]: 52: Hoare triple {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} is VALID [2022-04-27 21:21:25,132 INFO L290 TraceCheckUtils]: 53: Hoare triple {5317#(and (<= 23 main_~x~0) (<= main_~x~0 23))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:21:25,133 INFO L290 TraceCheckUtils]: 54: Hoare triple {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:21:25,133 INFO L290 TraceCheckUtils]: 55: Hoare triple {5318#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} is VALID [2022-04-27 21:21:25,134 INFO L290 TraceCheckUtils]: 56: Hoare triple {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} is VALID [2022-04-27 21:21:25,134 INFO L290 TraceCheckUtils]: 57: Hoare triple {5319#(and (<= main_~x~0 25) (<= 25 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:21:25,134 INFO L290 TraceCheckUtils]: 58: Hoare triple {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:21:25,135 INFO L290 TraceCheckUtils]: 59: Hoare triple {5320#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} is VALID [2022-04-27 21:21:25,135 INFO L290 TraceCheckUtils]: 60: Hoare triple {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} is VALID [2022-04-27 21:21:25,136 INFO L290 TraceCheckUtils]: 61: Hoare triple {5321#(and (<= 27 main_~x~0) (<= main_~x~0 27))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:21:25,136 INFO L290 TraceCheckUtils]: 62: Hoare triple {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:21:25,137 INFO L290 TraceCheckUtils]: 63: Hoare triple {5322#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5517#(and (<= main_~x~0 29) (<= 29 main_~x~0))} is VALID [2022-04-27 21:21:25,137 INFO L290 TraceCheckUtils]: 64: Hoare triple {5517#(and (<= main_~x~0 29) (<= 29 main_~x~0))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:25,137 INFO L272 TraceCheckUtils]: 65: Hoare triple {5290#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {5290#false} is VALID [2022-04-27 21:21:25,137 INFO L290 TraceCheckUtils]: 66: Hoare triple {5290#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5290#false} is VALID [2022-04-27 21:21:25,137 INFO L290 TraceCheckUtils]: 67: Hoare triple {5290#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:25,137 INFO L290 TraceCheckUtils]: 68: Hoare triple {5290#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:25,138 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:21:25,138 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:21:26,591 INFO L290 TraceCheckUtils]: 68: Hoare triple {5290#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:26,591 INFO L290 TraceCheckUtils]: 67: Hoare triple {5290#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:26,591 INFO L290 TraceCheckUtils]: 66: Hoare triple {5290#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5290#false} is VALID [2022-04-27 21:21:26,591 INFO L272 TraceCheckUtils]: 65: Hoare triple {5290#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {5290#false} is VALID [2022-04-27 21:21:26,592 INFO L290 TraceCheckUtils]: 64: Hoare triple {5545#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {5290#false} is VALID [2022-04-27 21:21:26,592 INFO L290 TraceCheckUtils]: 63: Hoare triple {5549#(< (mod (+ main_~x~0 1) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5545#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:21:26,593 INFO L290 TraceCheckUtils]: 62: Hoare triple {5549#(< (mod (+ main_~x~0 1) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5549#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:21:26,593 INFO L290 TraceCheckUtils]: 61: Hoare triple {5556#(< (mod (+ main_~x~0 2) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5549#(< (mod (+ main_~x~0 1) 4294967296) 99)} is VALID [2022-04-27 21:21:26,593 INFO L290 TraceCheckUtils]: 60: Hoare triple {5556#(< (mod (+ main_~x~0 2) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5556#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:21:26,594 INFO L290 TraceCheckUtils]: 59: Hoare triple {5563#(< (mod (+ main_~x~0 3) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5556#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:21:26,594 INFO L290 TraceCheckUtils]: 58: Hoare triple {5563#(< (mod (+ main_~x~0 3) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5563#(< (mod (+ main_~x~0 3) 4294967296) 99)} is VALID [2022-04-27 21:21:26,595 INFO L290 TraceCheckUtils]: 57: Hoare triple {5570#(< (mod (+ main_~x~0 4) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5563#(< (mod (+ main_~x~0 3) 4294967296) 99)} is VALID [2022-04-27 21:21:26,595 INFO L290 TraceCheckUtils]: 56: Hoare triple {5570#(< (mod (+ main_~x~0 4) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5570#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:21:26,596 INFO L290 TraceCheckUtils]: 55: Hoare triple {5577#(< (mod (+ 5 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5570#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:21:26,596 INFO L290 TraceCheckUtils]: 54: Hoare triple {5577#(< (mod (+ 5 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5577#(< (mod (+ 5 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,597 INFO L290 TraceCheckUtils]: 53: Hoare triple {5584#(< (mod (+ main_~x~0 6) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5577#(< (mod (+ 5 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,597 INFO L290 TraceCheckUtils]: 52: Hoare triple {5584#(< (mod (+ main_~x~0 6) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5584#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:21:26,598 INFO L290 TraceCheckUtils]: 51: Hoare triple {5591#(< (mod (+ 7 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5584#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:21:26,598 INFO L290 TraceCheckUtils]: 50: Hoare triple {5591#(< (mod (+ 7 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5591#(< (mod (+ 7 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,599 INFO L290 TraceCheckUtils]: 49: Hoare triple {5598#(< (mod (+ main_~x~0 8) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5591#(< (mod (+ 7 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,607 INFO L290 TraceCheckUtils]: 48: Hoare triple {5598#(< (mod (+ main_~x~0 8) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5598#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:21:26,607 INFO L290 TraceCheckUtils]: 47: Hoare triple {5605#(< (mod (+ main_~x~0 9) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5598#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:21:26,608 INFO L290 TraceCheckUtils]: 46: Hoare triple {5605#(< (mod (+ main_~x~0 9) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5605#(< (mod (+ main_~x~0 9) 4294967296) 99)} is VALID [2022-04-27 21:21:26,608 INFO L290 TraceCheckUtils]: 45: Hoare triple {5612#(< (mod (+ main_~x~0 10) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5605#(< (mod (+ main_~x~0 9) 4294967296) 99)} is VALID [2022-04-27 21:21:26,608 INFO L290 TraceCheckUtils]: 44: Hoare triple {5612#(< (mod (+ main_~x~0 10) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5612#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:21:26,609 INFO L290 TraceCheckUtils]: 43: Hoare triple {5619#(< (mod (+ main_~x~0 11) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5612#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:21:26,609 INFO L290 TraceCheckUtils]: 42: Hoare triple {5619#(< (mod (+ main_~x~0 11) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5619#(< (mod (+ main_~x~0 11) 4294967296) 99)} is VALID [2022-04-27 21:21:26,610 INFO L290 TraceCheckUtils]: 41: Hoare triple {5626#(< (mod (+ main_~x~0 12) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5619#(< (mod (+ main_~x~0 11) 4294967296) 99)} is VALID [2022-04-27 21:21:26,610 INFO L290 TraceCheckUtils]: 40: Hoare triple {5626#(< (mod (+ main_~x~0 12) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5626#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:21:26,611 INFO L290 TraceCheckUtils]: 39: Hoare triple {5633#(< (mod (+ main_~x~0 13) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5626#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:21:26,611 INFO L290 TraceCheckUtils]: 38: Hoare triple {5633#(< (mod (+ main_~x~0 13) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5633#(< (mod (+ main_~x~0 13) 4294967296) 99)} is VALID [2022-04-27 21:21:26,612 INFO L290 TraceCheckUtils]: 37: Hoare triple {5640#(< (mod (+ main_~x~0 14) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5633#(< (mod (+ main_~x~0 13) 4294967296) 99)} is VALID [2022-04-27 21:21:26,612 INFO L290 TraceCheckUtils]: 36: Hoare triple {5640#(< (mod (+ main_~x~0 14) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5640#(< (mod (+ main_~x~0 14) 4294967296) 99)} is VALID [2022-04-27 21:21:26,612 INFO L290 TraceCheckUtils]: 35: Hoare triple {5647#(< (mod (+ main_~x~0 15) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5640#(< (mod (+ main_~x~0 14) 4294967296) 99)} is VALID [2022-04-27 21:21:26,613 INFO L290 TraceCheckUtils]: 34: Hoare triple {5647#(< (mod (+ main_~x~0 15) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5647#(< (mod (+ main_~x~0 15) 4294967296) 99)} is VALID [2022-04-27 21:21:26,613 INFO L290 TraceCheckUtils]: 33: Hoare triple {5654#(< (mod (+ main_~x~0 16) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5647#(< (mod (+ main_~x~0 15) 4294967296) 99)} is VALID [2022-04-27 21:21:26,614 INFO L290 TraceCheckUtils]: 32: Hoare triple {5654#(< (mod (+ main_~x~0 16) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5654#(< (mod (+ main_~x~0 16) 4294967296) 99)} is VALID [2022-04-27 21:21:26,614 INFO L290 TraceCheckUtils]: 31: Hoare triple {5661#(< (mod (+ main_~x~0 17) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5654#(< (mod (+ main_~x~0 16) 4294967296) 99)} is VALID [2022-04-27 21:21:26,615 INFO L290 TraceCheckUtils]: 30: Hoare triple {5661#(< (mod (+ main_~x~0 17) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5661#(< (mod (+ main_~x~0 17) 4294967296) 99)} is VALID [2022-04-27 21:21:26,615 INFO L290 TraceCheckUtils]: 29: Hoare triple {5668#(< (mod (+ main_~x~0 18) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5661#(< (mod (+ main_~x~0 17) 4294967296) 99)} is VALID [2022-04-27 21:21:26,616 INFO L290 TraceCheckUtils]: 28: Hoare triple {5668#(< (mod (+ main_~x~0 18) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5668#(< (mod (+ main_~x~0 18) 4294967296) 99)} is VALID [2022-04-27 21:21:26,616 INFO L290 TraceCheckUtils]: 27: Hoare triple {5675#(< (mod (+ 19 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5668#(< (mod (+ main_~x~0 18) 4294967296) 99)} is VALID [2022-04-27 21:21:26,616 INFO L290 TraceCheckUtils]: 26: Hoare triple {5675#(< (mod (+ 19 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5675#(< (mod (+ 19 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,617 INFO L290 TraceCheckUtils]: 25: Hoare triple {5682#(< (mod (+ main_~x~0 20) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5675#(< (mod (+ 19 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,617 INFO L290 TraceCheckUtils]: 24: Hoare triple {5682#(< (mod (+ main_~x~0 20) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5682#(< (mod (+ main_~x~0 20) 4294967296) 99)} is VALID [2022-04-27 21:21:26,618 INFO L290 TraceCheckUtils]: 23: Hoare triple {5689#(< (mod (+ main_~x~0 21) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5682#(< (mod (+ main_~x~0 20) 4294967296) 99)} is VALID [2022-04-27 21:21:26,618 INFO L290 TraceCheckUtils]: 22: Hoare triple {5689#(< (mod (+ main_~x~0 21) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5689#(< (mod (+ main_~x~0 21) 4294967296) 99)} is VALID [2022-04-27 21:21:26,619 INFO L290 TraceCheckUtils]: 21: Hoare triple {5696#(< (mod (+ main_~x~0 22) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5689#(< (mod (+ main_~x~0 21) 4294967296) 99)} is VALID [2022-04-27 21:21:26,619 INFO L290 TraceCheckUtils]: 20: Hoare triple {5696#(< (mod (+ main_~x~0 22) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5696#(< (mod (+ main_~x~0 22) 4294967296) 99)} is VALID [2022-04-27 21:21:26,620 INFO L290 TraceCheckUtils]: 19: Hoare triple {5703#(< (mod (+ 23 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5696#(< (mod (+ main_~x~0 22) 4294967296) 99)} is VALID [2022-04-27 21:21:26,623 INFO L290 TraceCheckUtils]: 18: Hoare triple {5703#(< (mod (+ 23 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5703#(< (mod (+ 23 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,624 INFO L290 TraceCheckUtils]: 17: Hoare triple {5710#(< (mod (+ main_~x~0 24) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5703#(< (mod (+ 23 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,624 INFO L290 TraceCheckUtils]: 16: Hoare triple {5710#(< (mod (+ main_~x~0 24) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5710#(< (mod (+ main_~x~0 24) 4294967296) 99)} is VALID [2022-04-27 21:21:26,624 INFO L290 TraceCheckUtils]: 15: Hoare triple {5717#(< (mod (+ main_~x~0 25) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5710#(< (mod (+ main_~x~0 24) 4294967296) 99)} is VALID [2022-04-27 21:21:26,625 INFO L290 TraceCheckUtils]: 14: Hoare triple {5717#(< (mod (+ main_~x~0 25) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5717#(< (mod (+ main_~x~0 25) 4294967296) 99)} is VALID [2022-04-27 21:21:26,625 INFO L290 TraceCheckUtils]: 13: Hoare triple {5724#(< (mod (+ main_~x~0 26) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5717#(< (mod (+ main_~x~0 25) 4294967296) 99)} is VALID [2022-04-27 21:21:26,626 INFO L290 TraceCheckUtils]: 12: Hoare triple {5724#(< (mod (+ main_~x~0 26) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5724#(< (mod (+ main_~x~0 26) 4294967296) 99)} is VALID [2022-04-27 21:21:26,626 INFO L290 TraceCheckUtils]: 11: Hoare triple {5731#(< (mod (+ main_~x~0 27) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5724#(< (mod (+ main_~x~0 26) 4294967296) 99)} is VALID [2022-04-27 21:21:26,626 INFO L290 TraceCheckUtils]: 10: Hoare triple {5731#(< (mod (+ main_~x~0 27) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5731#(< (mod (+ main_~x~0 27) 4294967296) 99)} is VALID [2022-04-27 21:21:26,627 INFO L290 TraceCheckUtils]: 9: Hoare triple {5738#(< (mod (+ main_~x~0 28) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5731#(< (mod (+ main_~x~0 27) 4294967296) 99)} is VALID [2022-04-27 21:21:26,627 INFO L290 TraceCheckUtils]: 8: Hoare triple {5738#(< (mod (+ main_~x~0 28) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5738#(< (mod (+ main_~x~0 28) 4294967296) 99)} is VALID [2022-04-27 21:21:26,628 INFO L290 TraceCheckUtils]: 7: Hoare triple {5745#(< (mod (+ 29 main_~x~0) 4294967296) 99)} [55] L18-->L18-2: Formula: (and (= (mod v_main_~y~0_4 2) 0) (= v_main_~x~0_7 (+ v_main_~x~0_8 1))) InVars {main_~x~0=v_main_~x~0_8, main_~y~0=v_main_~y~0_4} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~y~0=v_main_~y~0_4, main_~x~0=v_main_~x~0_7} AuxVars[] AssignedVars[main_~x~0, main_#t~post5] {5738#(< (mod (+ main_~x~0 28) 4294967296) 99)} is VALID [2022-04-27 21:21:26,628 INFO L290 TraceCheckUtils]: 6: Hoare triple {5745#(< (mod (+ 29 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {5745#(< (mod (+ 29 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,629 INFO L290 TraceCheckUtils]: 5: Hoare triple {5289#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {5745#(< (mod (+ 29 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:21:26,629 INFO L272 TraceCheckUtils]: 4: Hoare triple {5289#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:26,629 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5289#true} {5289#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:26,629 INFO L290 TraceCheckUtils]: 2: Hoare triple {5289#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:26,629 INFO L290 TraceCheckUtils]: 1: Hoare triple {5289#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5289#true} is VALID [2022-04-27 21:21:26,629 INFO L272 TraceCheckUtils]: 0: Hoare triple {5289#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5289#true} is VALID [2022-04-27 21:21:26,630 INFO L134 CoverageAnalysis]: Checked inductivity of 841 backedges. 0 proven. 841 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:21:26,630 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2101456552] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:21:26,630 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:21:26,630 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 32, 32] total 64 [2022-04-27 21:21:26,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686306870] [2022-04-27 21:21:26,630 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:21:26,631 INFO L78 Accepts]: Start accepts. Automaton has has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 69 [2022-04-27 21:21:26,631 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:21:26,631 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:21:26,741 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 133 edges. 133 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:21:26,742 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 64 states [2022-04-27 21:21:26,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:21:26,743 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2022-04-27 21:21:26,744 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1085, Invalid=2947, Unknown=0, NotChecked=0, Total=4032 [2022-04-27 21:21:26,744 INFO L87 Difference]: Start difference. First operand 129 states and 131 transitions. Second operand has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:24:55,038 INFO L93 Difference]: Finished difference Result 199 states and 216 transitions. [2022-04-27 21:24:55,038 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2022-04-27 21:24:55,038 INFO L78 Accepts]: Start accepts. Automaton has has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 69 [2022-04-27 21:24:55,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:24:55,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 183 transitions. [2022-04-27 21:24:55,040 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 183 transitions. [2022-04-27 21:24:55,041 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 63 states and 183 transitions. [2022-04-27 21:24:55,339 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 183 edges. 183 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:24:55,342 INFO L225 Difference]: With dead ends: 199 [2022-04-27 21:24:55,342 INFO L226 Difference]: Without dead ends: 194 [2022-04-27 21:24:55,345 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 109 SyntacticMatches, 1 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2075 ImplicationChecksByTransitivity, 204.2s TimeCoverageRelationStatistics Valid=4018, Invalid=11227, Unknown=7, NotChecked=0, Total=15252 [2022-04-27 21:24:55,345 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 112 mSDsluCounter, 152 mSDsCounter, 0 mSdLazyCounter, 2527 mSolverCounterSat, 596 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.7s Time, 0 mProtectedPredicate, 0 mProtectedAction, 112 SdHoareTripleChecker+Valid, 163 SdHoareTripleChecker+Invalid, 3123 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 596 IncrementalHoareTripleChecker+Valid, 2527 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.7s IncrementalHoareTripleChecker+Time [2022-04-27 21:24:55,345 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [112 Valid, 163 Invalid, 3123 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [596 Valid, 2527 Invalid, 0 Unknown, 0 Unchecked, 2.7s Time] [2022-04-27 21:24:55,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2022-04-27 21:24:55,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 193. [2022-04-27 21:24:55,564 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:24:55,564 INFO L82 GeneralOperation]: Start isEquivalent. First operand 194 states. Second operand has 193 states, 188 states have (on average 1.0159574468085106) internal successors, (191), 188 states have internal predecessors, (191), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,564 INFO L74 IsIncluded]: Start isIncluded. First operand 194 states. Second operand has 193 states, 188 states have (on average 1.0159574468085106) internal successors, (191), 188 states have internal predecessors, (191), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,565 INFO L87 Difference]: Start difference. First operand 194 states. Second operand has 193 states, 188 states have (on average 1.0159574468085106) internal successors, (191), 188 states have internal predecessors, (191), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:24:55,567 INFO L93 Difference]: Finished difference Result 194 states and 196 transitions. [2022-04-27 21:24:55,567 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 196 transitions. [2022-04-27 21:24:55,567 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:24:55,567 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:24:55,568 INFO L74 IsIncluded]: Start isIncluded. First operand has 193 states, 188 states have (on average 1.0159574468085106) internal successors, (191), 188 states have internal predecessors, (191), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 194 states. [2022-04-27 21:24:55,568 INFO L87 Difference]: Start difference. First operand has 193 states, 188 states have (on average 1.0159574468085106) internal successors, (191), 188 states have internal predecessors, (191), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 194 states. [2022-04-27 21:24:55,570 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:24:55,570 INFO L93 Difference]: Finished difference Result 194 states and 196 transitions. [2022-04-27 21:24:55,570 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 196 transitions. [2022-04-27 21:24:55,570 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:24:55,571 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:24:55,571 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:24:55,571 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:24:55,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 193 states, 188 states have (on average 1.0159574468085106) internal successors, (191), 188 states have internal predecessors, (191), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,573 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 193 states to 193 states and 195 transitions. [2022-04-27 21:24:55,573 INFO L78 Accepts]: Start accepts. Automaton has 193 states and 195 transitions. Word has length 69 [2022-04-27 21:24:55,573 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:24:55,574 INFO L495 AbstractCegarLoop]: Abstraction has 193 states and 195 transitions. [2022-04-27 21:24:55,574 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 64 states, 64 states have (on average 2.0) internal successors, (128), 63 states have internal predecessors, (128), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:55,574 INFO L276 IsEmpty]: Start isEmpty. Operand 193 states and 195 transitions. [2022-04-27 21:24:55,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2022-04-27 21:24:55,574 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:24:55,574 INFO L195 NwaCegarLoop]: trace histogram [30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:24:55,581 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2022-04-27 21:24:55,780 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable11 [2022-04-27 21:24:55,780 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:24:55,781 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:24:55,781 INFO L85 PathProgramCache]: Analyzing trace with hash -1425056564, now seen corresponding path program 4 times [2022-04-27 21:24:55,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:24:55,781 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658919422] [2022-04-27 21:24:55,781 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:24:55,781 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:24:55,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:24:56,344 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:24:56,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:24:56,348 INFO L290 TraceCheckUtils]: 0: Hoare triple {6903#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6867#true} is VALID [2022-04-27 21:24:56,348 INFO L290 TraceCheckUtils]: 1: Hoare triple {6867#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:56,348 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {6867#true} {6867#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:56,349 INFO L272 TraceCheckUtils]: 0: Hoare triple {6867#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6903#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:24:56,349 INFO L290 TraceCheckUtils]: 1: Hoare triple {6903#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6867#true} is VALID [2022-04-27 21:24:56,349 INFO L290 TraceCheckUtils]: 2: Hoare triple {6867#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:56,349 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6867#true} {6867#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:56,349 INFO L272 TraceCheckUtils]: 4: Hoare triple {6867#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:56,349 INFO L290 TraceCheckUtils]: 5: Hoare triple {6867#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {6872#(= main_~x~0 0)} is VALID [2022-04-27 21:24:56,350 INFO L290 TraceCheckUtils]: 6: Hoare triple {6872#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6872#(= main_~x~0 0)} is VALID [2022-04-27 21:24:56,350 INFO L290 TraceCheckUtils]: 7: Hoare triple {6872#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:24:56,351 INFO L290 TraceCheckUtils]: 8: Hoare triple {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:24:56,351 INFO L290 TraceCheckUtils]: 9: Hoare triple {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:24:56,351 INFO L290 TraceCheckUtils]: 10: Hoare triple {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:24:56,352 INFO L290 TraceCheckUtils]: 11: Hoare triple {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:24:56,352 INFO L290 TraceCheckUtils]: 12: Hoare triple {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:24:56,353 INFO L290 TraceCheckUtils]: 13: Hoare triple {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:24:56,353 INFO L290 TraceCheckUtils]: 14: Hoare triple {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:24:56,354 INFO L290 TraceCheckUtils]: 15: Hoare triple {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:24:56,354 INFO L290 TraceCheckUtils]: 16: Hoare triple {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:24:56,355 INFO L290 TraceCheckUtils]: 17: Hoare triple {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:24:56,355 INFO L290 TraceCheckUtils]: 18: Hoare triple {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:24:56,355 INFO L290 TraceCheckUtils]: 19: Hoare triple {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:24:56,356 INFO L290 TraceCheckUtils]: 20: Hoare triple {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:24:56,356 INFO L290 TraceCheckUtils]: 21: Hoare triple {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:24:56,356 INFO L290 TraceCheckUtils]: 22: Hoare triple {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:24:56,357 INFO L290 TraceCheckUtils]: 23: Hoare triple {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:24:56,357 INFO L290 TraceCheckUtils]: 24: Hoare triple {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:24:56,358 INFO L290 TraceCheckUtils]: 25: Hoare triple {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:24:56,358 INFO L290 TraceCheckUtils]: 26: Hoare triple {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:24:56,358 INFO L290 TraceCheckUtils]: 27: Hoare triple {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:24:56,359 INFO L290 TraceCheckUtils]: 28: Hoare triple {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:24:56,359 INFO L290 TraceCheckUtils]: 29: Hoare triple {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:24:56,359 INFO L290 TraceCheckUtils]: 30: Hoare triple {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:24:56,360 INFO L290 TraceCheckUtils]: 31: Hoare triple {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:24:56,360 INFO L290 TraceCheckUtils]: 32: Hoare triple {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:24:56,361 INFO L290 TraceCheckUtils]: 33: Hoare triple {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:24:56,361 INFO L290 TraceCheckUtils]: 34: Hoare triple {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:24:56,361 INFO L290 TraceCheckUtils]: 35: Hoare triple {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} is VALID [2022-04-27 21:24:56,362 INFO L290 TraceCheckUtils]: 36: Hoare triple {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} is VALID [2022-04-27 21:24:56,362 INFO L290 TraceCheckUtils]: 37: Hoare triple {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} is VALID [2022-04-27 21:24:56,362 INFO L290 TraceCheckUtils]: 38: Hoare triple {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} is VALID [2022-04-27 21:24:56,363 INFO L290 TraceCheckUtils]: 39: Hoare triple {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} is VALID [2022-04-27 21:24:56,363 INFO L290 TraceCheckUtils]: 40: Hoare triple {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} is VALID [2022-04-27 21:24:56,364 INFO L290 TraceCheckUtils]: 41: Hoare triple {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} is VALID [2022-04-27 21:24:56,364 INFO L290 TraceCheckUtils]: 42: Hoare triple {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} is VALID [2022-04-27 21:24:56,364 INFO L290 TraceCheckUtils]: 43: Hoare triple {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} is VALID [2022-04-27 21:24:56,365 INFO L290 TraceCheckUtils]: 44: Hoare triple {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} is VALID [2022-04-27 21:24:56,365 INFO L290 TraceCheckUtils]: 45: Hoare triple {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} is VALID [2022-04-27 21:24:56,365 INFO L290 TraceCheckUtils]: 46: Hoare triple {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} is VALID [2022-04-27 21:24:56,366 INFO L290 TraceCheckUtils]: 47: Hoare triple {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} is VALID [2022-04-27 21:24:56,366 INFO L290 TraceCheckUtils]: 48: Hoare triple {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} is VALID [2022-04-27 21:24:56,367 INFO L290 TraceCheckUtils]: 49: Hoare triple {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} is VALID [2022-04-27 21:24:56,367 INFO L290 TraceCheckUtils]: 50: Hoare triple {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} is VALID [2022-04-27 21:24:56,367 INFO L290 TraceCheckUtils]: 51: Hoare triple {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} is VALID [2022-04-27 21:24:56,368 INFO L290 TraceCheckUtils]: 52: Hoare triple {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} is VALID [2022-04-27 21:24:56,368 INFO L290 TraceCheckUtils]: 53: Hoare triple {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} is VALID [2022-04-27 21:24:56,369 INFO L290 TraceCheckUtils]: 54: Hoare triple {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} is VALID [2022-04-27 21:24:56,369 INFO L290 TraceCheckUtils]: 55: Hoare triple {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} is VALID [2022-04-27 21:24:56,369 INFO L290 TraceCheckUtils]: 56: Hoare triple {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} is VALID [2022-04-27 21:24:56,370 INFO L290 TraceCheckUtils]: 57: Hoare triple {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} is VALID [2022-04-27 21:24:56,370 INFO L290 TraceCheckUtils]: 58: Hoare triple {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} is VALID [2022-04-27 21:24:56,370 INFO L290 TraceCheckUtils]: 59: Hoare triple {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} is VALID [2022-04-27 21:24:56,371 INFO L290 TraceCheckUtils]: 60: Hoare triple {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} is VALID [2022-04-27 21:24:56,371 INFO L290 TraceCheckUtils]: 61: Hoare triple {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} is VALID [2022-04-27 21:24:56,372 INFO L290 TraceCheckUtils]: 62: Hoare triple {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} is VALID [2022-04-27 21:24:56,372 INFO L290 TraceCheckUtils]: 63: Hoare triple {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} is VALID [2022-04-27 21:24:56,372 INFO L290 TraceCheckUtils]: 64: Hoare triple {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} is VALID [2022-04-27 21:24:56,373 INFO L290 TraceCheckUtils]: 65: Hoare triple {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6902#(and (<= main_~x~0 60) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} is VALID [2022-04-27 21:24:56,373 INFO L290 TraceCheckUtils]: 66: Hoare triple {6902#(and (<= main_~x~0 60) (not (<= (+ (div main_~x~0 4294967296) 1) 0)))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:56,373 INFO L272 TraceCheckUtils]: 67: Hoare triple {6868#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {6868#false} is VALID [2022-04-27 21:24:56,373 INFO L290 TraceCheckUtils]: 68: Hoare triple {6868#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6868#false} is VALID [2022-04-27 21:24:56,373 INFO L290 TraceCheckUtils]: 69: Hoare triple {6868#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:56,374 INFO L290 TraceCheckUtils]: 70: Hoare triple {6868#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:56,374 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:24:56,374 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:24:56,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658919422] [2022-04-27 21:24:56,374 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658919422] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:24:56,374 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [259882986] [2022-04-27 21:24:56,375 INFO L93 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2022-04-27 21:24:56,375 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:24:56,375 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:24:56,375 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:24:56,401 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 21:24:56,473 INFO L228 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2022-04-27 21:24:56,473 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:24:56,474 INFO L263 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 63 conjunts are in the unsatisfiable core [2022-04-27 21:24:56,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:24:56,483 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:24:57,018 INFO L272 TraceCheckUtils]: 0: Hoare triple {6867#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:57,018 INFO L290 TraceCheckUtils]: 1: Hoare triple {6867#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6867#true} is VALID [2022-04-27 21:24:57,019 INFO L290 TraceCheckUtils]: 2: Hoare triple {6867#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:57,019 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6867#true} {6867#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:57,019 INFO L272 TraceCheckUtils]: 4: Hoare triple {6867#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:57,019 INFO L290 TraceCheckUtils]: 5: Hoare triple {6867#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {6872#(= main_~x~0 0)} is VALID [2022-04-27 21:24:57,019 INFO L290 TraceCheckUtils]: 6: Hoare triple {6872#(= main_~x~0 0)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6872#(= main_~x~0 0)} is VALID [2022-04-27 21:24:57,020 INFO L290 TraceCheckUtils]: 7: Hoare triple {6872#(= main_~x~0 0)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:24:57,020 INFO L290 TraceCheckUtils]: 8: Hoare triple {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} is VALID [2022-04-27 21:24:57,020 INFO L290 TraceCheckUtils]: 9: Hoare triple {6873#(and (<= 2 main_~x~0) (<= main_~x~0 2))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:24:57,021 INFO L290 TraceCheckUtils]: 10: Hoare triple {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} is VALID [2022-04-27 21:24:57,021 INFO L290 TraceCheckUtils]: 11: Hoare triple {6874#(and (<= main_~x~0 4) (<= 4 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:24:57,021 INFO L290 TraceCheckUtils]: 12: Hoare triple {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} is VALID [2022-04-27 21:24:57,022 INFO L290 TraceCheckUtils]: 13: Hoare triple {6875#(and (<= 6 main_~x~0) (<= main_~x~0 6))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:24:57,022 INFO L290 TraceCheckUtils]: 14: Hoare triple {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} is VALID [2022-04-27 21:24:57,023 INFO L290 TraceCheckUtils]: 15: Hoare triple {6876#(and (<= main_~x~0 8) (<= 8 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:24:57,023 INFO L290 TraceCheckUtils]: 16: Hoare triple {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} is VALID [2022-04-27 21:24:57,023 INFO L290 TraceCheckUtils]: 17: Hoare triple {6877#(and (<= main_~x~0 10) (<= 10 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:24:57,024 INFO L290 TraceCheckUtils]: 18: Hoare triple {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} is VALID [2022-04-27 21:24:57,024 INFO L290 TraceCheckUtils]: 19: Hoare triple {6878#(and (<= main_~x~0 12) (<= 12 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:24:57,024 INFO L290 TraceCheckUtils]: 20: Hoare triple {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} is VALID [2022-04-27 21:24:57,025 INFO L290 TraceCheckUtils]: 21: Hoare triple {6879#(and (<= 14 main_~x~0) (<= main_~x~0 14))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:24:57,025 INFO L290 TraceCheckUtils]: 22: Hoare triple {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} is VALID [2022-04-27 21:24:57,026 INFO L290 TraceCheckUtils]: 23: Hoare triple {6880#(and (<= main_~x~0 16) (<= 16 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:24:57,026 INFO L290 TraceCheckUtils]: 24: Hoare triple {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} is VALID [2022-04-27 21:24:57,026 INFO L290 TraceCheckUtils]: 25: Hoare triple {6881#(and (<= main_~x~0 18) (<= 18 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:24:57,027 INFO L290 TraceCheckUtils]: 26: Hoare triple {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} is VALID [2022-04-27 21:24:57,027 INFO L290 TraceCheckUtils]: 27: Hoare triple {6882#(and (<= main_~x~0 20) (<= 20 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:24:57,028 INFO L290 TraceCheckUtils]: 28: Hoare triple {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} is VALID [2022-04-27 21:24:57,028 INFO L290 TraceCheckUtils]: 29: Hoare triple {6883#(and (<= 22 main_~x~0) (<= main_~x~0 22))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:24:57,028 INFO L290 TraceCheckUtils]: 30: Hoare triple {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} is VALID [2022-04-27 21:24:57,029 INFO L290 TraceCheckUtils]: 31: Hoare triple {6884#(and (<= main_~x~0 24) (<= 24 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:24:57,029 INFO L290 TraceCheckUtils]: 32: Hoare triple {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} is VALID [2022-04-27 21:24:57,032 INFO L290 TraceCheckUtils]: 33: Hoare triple {6885#(and (<= main_~x~0 26) (<= 26 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:24:57,032 INFO L290 TraceCheckUtils]: 34: Hoare triple {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} is VALID [2022-04-27 21:24:57,032 INFO L290 TraceCheckUtils]: 35: Hoare triple {6886#(and (<= 28 main_~x~0) (<= main_~x~0 28))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} is VALID [2022-04-27 21:24:57,033 INFO L290 TraceCheckUtils]: 36: Hoare triple {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} is VALID [2022-04-27 21:24:57,033 INFO L290 TraceCheckUtils]: 37: Hoare triple {6887#(and (<= 30 main_~x~0) (<= main_~x~0 30))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} is VALID [2022-04-27 21:24:57,033 INFO L290 TraceCheckUtils]: 38: Hoare triple {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} is VALID [2022-04-27 21:24:57,034 INFO L290 TraceCheckUtils]: 39: Hoare triple {6888#(and (<= main_~x~0 32) (<= 32 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} is VALID [2022-04-27 21:24:57,034 INFO L290 TraceCheckUtils]: 40: Hoare triple {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} is VALID [2022-04-27 21:24:57,035 INFO L290 TraceCheckUtils]: 41: Hoare triple {6889#(and (<= main_~x~0 34) (<= 34 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} is VALID [2022-04-27 21:24:57,035 INFO L290 TraceCheckUtils]: 42: Hoare triple {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} is VALID [2022-04-27 21:24:57,036 INFO L290 TraceCheckUtils]: 43: Hoare triple {6890#(and (<= main_~x~0 36) (<= 36 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} is VALID [2022-04-27 21:24:57,036 INFO L290 TraceCheckUtils]: 44: Hoare triple {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} is VALID [2022-04-27 21:24:57,036 INFO L290 TraceCheckUtils]: 45: Hoare triple {6891#(and (<= main_~x~0 38) (<= 38 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} is VALID [2022-04-27 21:24:57,037 INFO L290 TraceCheckUtils]: 46: Hoare triple {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} is VALID [2022-04-27 21:24:57,037 INFO L290 TraceCheckUtils]: 47: Hoare triple {6892#(and (<= main_~x~0 40) (<= 40 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} is VALID [2022-04-27 21:24:57,038 INFO L290 TraceCheckUtils]: 48: Hoare triple {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} is VALID [2022-04-27 21:24:57,038 INFO L290 TraceCheckUtils]: 49: Hoare triple {6893#(and (<= main_~x~0 42) (<= 42 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} is VALID [2022-04-27 21:24:57,038 INFO L290 TraceCheckUtils]: 50: Hoare triple {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} is VALID [2022-04-27 21:24:57,039 INFO L290 TraceCheckUtils]: 51: Hoare triple {6894#(and (<= 44 main_~x~0) (<= main_~x~0 44))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} is VALID [2022-04-27 21:24:57,039 INFO L290 TraceCheckUtils]: 52: Hoare triple {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} is VALID [2022-04-27 21:24:57,040 INFO L290 TraceCheckUtils]: 53: Hoare triple {6895#(and (<= 46 main_~x~0) (<= main_~x~0 46))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} is VALID [2022-04-27 21:24:57,040 INFO L290 TraceCheckUtils]: 54: Hoare triple {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} is VALID [2022-04-27 21:24:57,041 INFO L290 TraceCheckUtils]: 55: Hoare triple {6896#(and (<= main_~x~0 48) (<= 48 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} is VALID [2022-04-27 21:24:57,041 INFO L290 TraceCheckUtils]: 56: Hoare triple {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} is VALID [2022-04-27 21:24:57,041 INFO L290 TraceCheckUtils]: 57: Hoare triple {6897#(and (<= main_~x~0 50) (<= 50 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} is VALID [2022-04-27 21:24:57,042 INFO L290 TraceCheckUtils]: 58: Hoare triple {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} is VALID [2022-04-27 21:24:57,042 INFO L290 TraceCheckUtils]: 59: Hoare triple {6898#(and (<= main_~x~0 52) (<= 52 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} is VALID [2022-04-27 21:24:57,043 INFO L290 TraceCheckUtils]: 60: Hoare triple {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} is VALID [2022-04-27 21:24:57,043 INFO L290 TraceCheckUtils]: 61: Hoare triple {6899#(and (<= main_~x~0 54) (<= 54 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} is VALID [2022-04-27 21:24:57,043 INFO L290 TraceCheckUtils]: 62: Hoare triple {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} is VALID [2022-04-27 21:24:57,044 INFO L290 TraceCheckUtils]: 63: Hoare triple {6900#(and (<= main_~x~0 56) (<= 56 main_~x~0))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} is VALID [2022-04-27 21:24:57,044 INFO L290 TraceCheckUtils]: 64: Hoare triple {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} is VALID [2022-04-27 21:24:57,045 INFO L290 TraceCheckUtils]: 65: Hoare triple {6901#(and (<= 58 main_~x~0) (<= main_~x~0 58))} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7102#(and (<= main_~x~0 60) (<= 60 main_~x~0))} is VALID [2022-04-27 21:24:57,045 INFO L290 TraceCheckUtils]: 66: Hoare triple {7102#(and (<= main_~x~0 60) (<= 60 main_~x~0))} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:57,045 INFO L272 TraceCheckUtils]: 67: Hoare triple {6868#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {6868#false} is VALID [2022-04-27 21:24:57,045 INFO L290 TraceCheckUtils]: 68: Hoare triple {6868#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6868#false} is VALID [2022-04-27 21:24:57,045 INFO L290 TraceCheckUtils]: 69: Hoare triple {6868#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:57,046 INFO L290 TraceCheckUtils]: 70: Hoare triple {6868#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:57,046 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:24:57,046 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:24:58,640 INFO L290 TraceCheckUtils]: 70: Hoare triple {6868#false} [61] L8-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:58,641 INFO L290 TraceCheckUtils]: 69: Hoare triple {6868#false} [59] L7-->L8: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:58,641 INFO L290 TraceCheckUtils]: 68: Hoare triple {6868#false} [58] __VERIFIER_assertENTRY-->L7: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6868#false} is VALID [2022-04-27 21:24:58,641 INFO L272 TraceCheckUtils]: 67: Hoare triple {6868#false} [54] L17-2-->__VERIFIER_assertENTRY: Formula: (= |v___VERIFIER_assert_#in~condInParam_1| (ite (= (mod v_main_~x~0_9 2) (mod v_main_~y~0_5 2)) 1 0)) InVars {main_~x~0=v_main_~x~0_9, main_~y~0=v_main_~y~0_5} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[__VERIFIER_assert_#in~cond, main_~x~0, main_~y~0] {6868#false} is VALID [2022-04-27 21:24:58,641 INFO L290 TraceCheckUtils]: 66: Hoare triple {7130#(< (mod main_~x~0 4294967296) 99)} [52] L18-2-->L17-2: Formula: (not (< (mod v_main_~x~0_5 4294967296) 99)) InVars {main_~x~0=v_main_~x~0_5} OutVars{main_~x~0=v_main_~x~0_5} AuxVars[] AssignedVars[] {6868#false} is VALID [2022-04-27 21:24:58,642 INFO L290 TraceCheckUtils]: 65: Hoare triple {7134#(< (mod (+ main_~x~0 2) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7130#(< (mod main_~x~0 4294967296) 99)} is VALID [2022-04-27 21:24:58,642 INFO L290 TraceCheckUtils]: 64: Hoare triple {7134#(< (mod (+ main_~x~0 2) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7134#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:24:58,643 INFO L290 TraceCheckUtils]: 63: Hoare triple {7141#(< (mod (+ main_~x~0 4) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7134#(< (mod (+ main_~x~0 2) 4294967296) 99)} is VALID [2022-04-27 21:24:58,644 INFO L290 TraceCheckUtils]: 62: Hoare triple {7141#(< (mod (+ main_~x~0 4) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7141#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:24:58,644 INFO L290 TraceCheckUtils]: 61: Hoare triple {7148#(< (mod (+ main_~x~0 6) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7141#(< (mod (+ main_~x~0 4) 4294967296) 99)} is VALID [2022-04-27 21:24:58,645 INFO L290 TraceCheckUtils]: 60: Hoare triple {7148#(< (mod (+ main_~x~0 6) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7148#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:24:58,645 INFO L290 TraceCheckUtils]: 59: Hoare triple {7155#(< (mod (+ main_~x~0 8) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7148#(< (mod (+ main_~x~0 6) 4294967296) 99)} is VALID [2022-04-27 21:24:58,646 INFO L290 TraceCheckUtils]: 58: Hoare triple {7155#(< (mod (+ main_~x~0 8) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7155#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:24:58,646 INFO L290 TraceCheckUtils]: 57: Hoare triple {7162#(< (mod (+ main_~x~0 10) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7155#(< (mod (+ main_~x~0 8) 4294967296) 99)} is VALID [2022-04-27 21:24:58,647 INFO L290 TraceCheckUtils]: 56: Hoare triple {7162#(< (mod (+ main_~x~0 10) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7162#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:24:58,647 INFO L290 TraceCheckUtils]: 55: Hoare triple {7169#(< (mod (+ main_~x~0 12) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7162#(< (mod (+ main_~x~0 10) 4294967296) 99)} is VALID [2022-04-27 21:24:58,648 INFO L290 TraceCheckUtils]: 54: Hoare triple {7169#(< (mod (+ main_~x~0 12) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7169#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:24:58,649 INFO L290 TraceCheckUtils]: 53: Hoare triple {7176#(< (mod (+ main_~x~0 14) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7169#(< (mod (+ main_~x~0 12) 4294967296) 99)} is VALID [2022-04-27 21:24:58,649 INFO L290 TraceCheckUtils]: 52: Hoare triple {7176#(< (mod (+ main_~x~0 14) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7176#(< (mod (+ main_~x~0 14) 4294967296) 99)} is VALID [2022-04-27 21:24:58,650 INFO L290 TraceCheckUtils]: 51: Hoare triple {7183#(< (mod (+ main_~x~0 16) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7176#(< (mod (+ main_~x~0 14) 4294967296) 99)} is VALID [2022-04-27 21:24:58,650 INFO L290 TraceCheckUtils]: 50: Hoare triple {7183#(< (mod (+ main_~x~0 16) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7183#(< (mod (+ main_~x~0 16) 4294967296) 99)} is VALID [2022-04-27 21:24:58,651 INFO L290 TraceCheckUtils]: 49: Hoare triple {7190#(< (mod (+ main_~x~0 18) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7183#(< (mod (+ main_~x~0 16) 4294967296) 99)} is VALID [2022-04-27 21:24:58,651 INFO L290 TraceCheckUtils]: 48: Hoare triple {7190#(< (mod (+ main_~x~0 18) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7190#(< (mod (+ main_~x~0 18) 4294967296) 99)} is VALID [2022-04-27 21:24:58,652 INFO L290 TraceCheckUtils]: 47: Hoare triple {7197#(< (mod (+ main_~x~0 20) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7190#(< (mod (+ main_~x~0 18) 4294967296) 99)} is VALID [2022-04-27 21:24:58,652 INFO L290 TraceCheckUtils]: 46: Hoare triple {7197#(< (mod (+ main_~x~0 20) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7197#(< (mod (+ main_~x~0 20) 4294967296) 99)} is VALID [2022-04-27 21:24:58,653 INFO L290 TraceCheckUtils]: 45: Hoare triple {7204#(< (mod (+ main_~x~0 22) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7197#(< (mod (+ main_~x~0 20) 4294967296) 99)} is VALID [2022-04-27 21:24:58,653 INFO L290 TraceCheckUtils]: 44: Hoare triple {7204#(< (mod (+ main_~x~0 22) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7204#(< (mod (+ main_~x~0 22) 4294967296) 99)} is VALID [2022-04-27 21:24:58,654 INFO L290 TraceCheckUtils]: 43: Hoare triple {7211#(< (mod (+ main_~x~0 24) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7204#(< (mod (+ main_~x~0 22) 4294967296) 99)} is VALID [2022-04-27 21:24:58,654 INFO L290 TraceCheckUtils]: 42: Hoare triple {7211#(< (mod (+ main_~x~0 24) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7211#(< (mod (+ main_~x~0 24) 4294967296) 99)} is VALID [2022-04-27 21:24:58,655 INFO L290 TraceCheckUtils]: 41: Hoare triple {7218#(< (mod (+ main_~x~0 26) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7211#(< (mod (+ main_~x~0 24) 4294967296) 99)} is VALID [2022-04-27 21:24:58,655 INFO L290 TraceCheckUtils]: 40: Hoare triple {7218#(< (mod (+ main_~x~0 26) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7218#(< (mod (+ main_~x~0 26) 4294967296) 99)} is VALID [2022-04-27 21:24:58,656 INFO L290 TraceCheckUtils]: 39: Hoare triple {7225#(< (mod (+ main_~x~0 28) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7218#(< (mod (+ main_~x~0 26) 4294967296) 99)} is VALID [2022-04-27 21:24:58,657 INFO L290 TraceCheckUtils]: 38: Hoare triple {7225#(< (mod (+ main_~x~0 28) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7225#(< (mod (+ main_~x~0 28) 4294967296) 99)} is VALID [2022-04-27 21:24:58,657 INFO L290 TraceCheckUtils]: 37: Hoare triple {7232#(< (mod (+ 30 main_~x~0) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7225#(< (mod (+ main_~x~0 28) 4294967296) 99)} is VALID [2022-04-27 21:24:58,658 INFO L290 TraceCheckUtils]: 36: Hoare triple {7232#(< (mod (+ 30 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7232#(< (mod (+ 30 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,658 INFO L290 TraceCheckUtils]: 35: Hoare triple {7239#(< (mod (+ 32 main_~x~0) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7232#(< (mod (+ 30 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,659 INFO L290 TraceCheckUtils]: 34: Hoare triple {7239#(< (mod (+ 32 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7239#(< (mod (+ 32 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,659 INFO L290 TraceCheckUtils]: 33: Hoare triple {7246#(< (mod (+ main_~x~0 34) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7239#(< (mod (+ 32 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,660 INFO L290 TraceCheckUtils]: 32: Hoare triple {7246#(< (mod (+ main_~x~0 34) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7246#(< (mod (+ main_~x~0 34) 4294967296) 99)} is VALID [2022-04-27 21:24:58,660 INFO L290 TraceCheckUtils]: 31: Hoare triple {7253#(< (mod (+ main_~x~0 36) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7246#(< (mod (+ main_~x~0 34) 4294967296) 99)} is VALID [2022-04-27 21:24:58,661 INFO L290 TraceCheckUtils]: 30: Hoare triple {7253#(< (mod (+ main_~x~0 36) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7253#(< (mod (+ main_~x~0 36) 4294967296) 99)} is VALID [2022-04-27 21:24:58,661 INFO L290 TraceCheckUtils]: 29: Hoare triple {7260#(< (mod (+ main_~x~0 38) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7253#(< (mod (+ main_~x~0 36) 4294967296) 99)} is VALID [2022-04-27 21:24:58,662 INFO L290 TraceCheckUtils]: 28: Hoare triple {7260#(< (mod (+ main_~x~0 38) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7260#(< (mod (+ main_~x~0 38) 4294967296) 99)} is VALID [2022-04-27 21:24:58,663 INFO L290 TraceCheckUtils]: 27: Hoare triple {7267#(< (mod (+ 40 main_~x~0) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7260#(< (mod (+ main_~x~0 38) 4294967296) 99)} is VALID [2022-04-27 21:24:58,663 INFO L290 TraceCheckUtils]: 26: Hoare triple {7267#(< (mod (+ 40 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7267#(< (mod (+ 40 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,664 INFO L290 TraceCheckUtils]: 25: Hoare triple {7274#(< (mod (+ 42 main_~x~0) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7267#(< (mod (+ 40 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,664 INFO L290 TraceCheckUtils]: 24: Hoare triple {7274#(< (mod (+ 42 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7274#(< (mod (+ 42 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,665 INFO L290 TraceCheckUtils]: 23: Hoare triple {7281#(< (mod (+ 44 main_~x~0) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7274#(< (mod (+ 42 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,665 INFO L290 TraceCheckUtils]: 22: Hoare triple {7281#(< (mod (+ 44 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7281#(< (mod (+ 44 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,666 INFO L290 TraceCheckUtils]: 21: Hoare triple {7288#(< (mod (+ main_~x~0 46) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7281#(< (mod (+ 44 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,666 INFO L290 TraceCheckUtils]: 20: Hoare triple {7288#(< (mod (+ main_~x~0 46) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7288#(< (mod (+ main_~x~0 46) 4294967296) 99)} is VALID [2022-04-27 21:24:58,667 INFO L290 TraceCheckUtils]: 19: Hoare triple {7295#(< (mod (+ main_~x~0 48) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7288#(< (mod (+ main_~x~0 46) 4294967296) 99)} is VALID [2022-04-27 21:24:58,667 INFO L290 TraceCheckUtils]: 18: Hoare triple {7295#(< (mod (+ main_~x~0 48) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7295#(< (mod (+ main_~x~0 48) 4294967296) 99)} is VALID [2022-04-27 21:24:58,668 INFO L290 TraceCheckUtils]: 17: Hoare triple {7302#(< (mod (+ main_~x~0 50) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7295#(< (mod (+ main_~x~0 48) 4294967296) 99)} is VALID [2022-04-27 21:24:58,668 INFO L290 TraceCheckUtils]: 16: Hoare triple {7302#(< (mod (+ main_~x~0 50) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7302#(< (mod (+ main_~x~0 50) 4294967296) 99)} is VALID [2022-04-27 21:24:58,669 INFO L290 TraceCheckUtils]: 15: Hoare triple {7309#(< (mod (+ main_~x~0 52) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7302#(< (mod (+ main_~x~0 50) 4294967296) 99)} is VALID [2022-04-27 21:24:58,669 INFO L290 TraceCheckUtils]: 14: Hoare triple {7309#(< (mod (+ main_~x~0 52) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7309#(< (mod (+ main_~x~0 52) 4294967296) 99)} is VALID [2022-04-27 21:24:58,670 INFO L290 TraceCheckUtils]: 13: Hoare triple {7316#(< (mod (+ main_~x~0 54) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7309#(< (mod (+ main_~x~0 52) 4294967296) 99)} is VALID [2022-04-27 21:24:58,670 INFO L290 TraceCheckUtils]: 12: Hoare triple {7316#(< (mod (+ main_~x~0 54) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7316#(< (mod (+ main_~x~0 54) 4294967296) 99)} is VALID [2022-04-27 21:24:58,671 INFO L290 TraceCheckUtils]: 11: Hoare triple {7323#(< (mod (+ 56 main_~x~0) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7316#(< (mod (+ main_~x~0 54) 4294967296) 99)} is VALID [2022-04-27 21:24:58,671 INFO L290 TraceCheckUtils]: 10: Hoare triple {7323#(< (mod (+ 56 main_~x~0) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7323#(< (mod (+ 56 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,672 INFO L290 TraceCheckUtils]: 9: Hoare triple {7330#(< (mod (+ main_~x~0 58) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7323#(< (mod (+ 56 main_~x~0) 4294967296) 99)} is VALID [2022-04-27 21:24:58,673 INFO L290 TraceCheckUtils]: 8: Hoare triple {7330#(< (mod (+ main_~x~0 58) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7330#(< (mod (+ main_~x~0 58) 4294967296) 99)} is VALID [2022-04-27 21:24:58,673 INFO L290 TraceCheckUtils]: 7: Hoare triple {7337#(< (mod (+ main_~x~0 60) 4294967296) 99)} [56] L18-->L18-2: Formula: (and (not (= (mod v_main_~y~0_1 2) 0)) (= v_main_~x~0_1 (+ v_main_~x~0_2 2))) InVars {main_~x~0=v_main_~x~0_2, main_~y~0=v_main_~y~0_1} OutVars{main_~x~0=v_main_~x~0_1, main_~y~0=v_main_~y~0_1} AuxVars[] AssignedVars[main_~x~0] {7330#(< (mod (+ main_~x~0 58) 4294967296) 99)} is VALID [2022-04-27 21:24:58,674 INFO L290 TraceCheckUtils]: 6: Hoare triple {7337#(< (mod (+ main_~x~0 60) 4294967296) 99)} [53] L18-2-->L18: Formula: (< (mod v_main_~x~0_6 4294967296) 99) InVars {main_~x~0=v_main_~x~0_6} OutVars{main_~x~0=v_main_~x~0_6} AuxVars[] AssignedVars[] {7337#(< (mod (+ main_~x~0 60) 4294967296) 99)} is VALID [2022-04-27 21:24:58,674 INFO L290 TraceCheckUtils]: 5: Hoare triple {6867#true} [49] mainENTRY-->L18-2: Formula: (and (= v_main_~y~0_2 |v_main_#t~nondet4_2|) (= v_main_~x~0_3 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|} OutVars{main_~x~0=v_main_~x~0_3, main_~y~0=v_main_~y~0_2} AuxVars[] AssignedVars[main_#t~nondet4, main_~x~0, main_~y~0] {7337#(< (mod (+ main_~x~0 60) 4294967296) 99)} is VALID [2022-04-27 21:24:58,674 INFO L272 TraceCheckUtils]: 4: Hoare triple {6867#true} [46] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:58,674 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6867#true} {6867#true} [64] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:58,674 INFO L290 TraceCheckUtils]: 2: Hoare triple {6867#true} [50] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:58,675 INFO L290 TraceCheckUtils]: 1: Hoare triple {6867#true} [47] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_1| 1))) (and (= 48 (select .cse0 0)) (= (select |v_#valid_1| 2) 1) (= (select |v_#valid_1| 0) 0) (< 0 |v_#StackHeapBarrier_1|) (= |v_#NULL.base_1| 0) (= 1 (select |v_#valid_1| 3)) (= (select |v_#length_1| 3) 12) (= (select |v_#valid_1| 1) 1) (= 2 (select |v_#length_1| 1)) (= (select |v_#length_1| 2) 14) (= (select .cse0 1) 0) (= |v_#NULL.offset_1| 0))) InVars {#memory_int=|v_#memory_int_1|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_1|, #valid=|v_#valid_1|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_1|, #valid=|v_#valid_1|, #memory_int=|v_#memory_int_1|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_1|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6867#true} is VALID [2022-04-27 21:24:58,675 INFO L272 TraceCheckUtils]: 0: Hoare triple {6867#true} [45] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6867#true} is VALID [2022-04-27 21:24:58,675 INFO L134 CoverageAnalysis]: Checked inductivity of 900 backedges. 0 proven. 900 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:24:58,676 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [259882986] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:24:58,676 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:24:58,676 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33, 33] total 66 [2022-04-27 21:24:58,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418695093] [2022-04-27 21:24:58,676 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:24:58,677 INFO L78 Accepts]: Start accepts. Automaton has has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 71 [2022-04-27 21:24:58,677 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:24:58,677 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:24:58,792 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 137 edges. 137 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:24:58,792 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 66 states [2022-04-27 21:24:58,792 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:24:58,793 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2022-04-27 21:24:58,795 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1075, Invalid=3215, Unknown=0, NotChecked=0, Total=4290 [2022-04-27 21:24:58,795 INFO L87 Difference]: Start difference. First operand 193 states and 195 transitions. Second operand has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:25:59,873 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:25:59,873 INFO L93 Difference]: Finished difference Result 238 states and 259 transitions. [2022-04-27 21:25:59,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2022-04-27 21:25:59,874 INFO L78 Accepts]: Start accepts. Automaton has has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 71 [2022-04-27 21:25:59,874 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:25:59,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:25:59,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 180 transitions. [2022-04-27 21:25:59,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:25:59,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 180 transitions. [2022-04-27 21:25:59,877 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 65 states and 180 transitions. [2022-04-27 21:26:00,236 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 180 edges. 180 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:26:00,239 INFO L225 Difference]: With dead ends: 238 [2022-04-27 21:26:00,240 INFO L226 Difference]: Without dead ends: 233 [2022-04-27 21:26:00,242 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 239 GetRequests, 112 SyntacticMatches, 1 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2686 ImplicationChecksByTransitivity, 58.1s TimeCoverageRelationStatistics Valid=4086, Invalid=12170, Unknown=0, NotChecked=0, Total=16256 [2022-04-27 21:26:00,243 INFO L413 NwaCegarLoop]: 11 mSDtfsCounter, 71 mSDsluCounter, 157 mSDsCounter, 0 mSdLazyCounter, 1858 mSolverCounterSat, 490 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 2.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 71 SdHoareTripleChecker+Valid, 168 SdHoareTripleChecker+Invalid, 2348 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 490 IncrementalHoareTripleChecker+Valid, 1858 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 2.3s IncrementalHoareTripleChecker+Time [2022-04-27 21:26:00,243 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [71 Valid, 168 Invalid, 2348 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [490 Valid, 1858 Invalid, 0 Unknown, 0 Unchecked, 2.3s Time] [2022-04-27 21:26:00,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2022-04-27 21:26:00,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 233. [2022-04-27 21:26:00,520 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:26:00,527 INFO L82 GeneralOperation]: Start isEquivalent. First operand 233 states. Second operand has 233 states, 228 states have (on average 1.013157894736842) internal successors, (231), 228 states have internal predecessors, (231), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:26:00,528 INFO L74 IsIncluded]: Start isIncluded. First operand 233 states. Second operand has 233 states, 228 states have (on average 1.013157894736842) internal successors, (231), 228 states have internal predecessors, (231), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:26:00,528 INFO L87 Difference]: Start difference. First operand 233 states. Second operand has 233 states, 228 states have (on average 1.013157894736842) internal successors, (231), 228 states have internal predecessors, (231), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:26:00,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:26:00,531 INFO L93 Difference]: Finished difference Result 233 states and 235 transitions. [2022-04-27 21:26:00,531 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 235 transitions. [2022-04-27 21:26:00,531 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:26:00,531 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:26:00,532 INFO L74 IsIncluded]: Start isIncluded. First operand has 233 states, 228 states have (on average 1.013157894736842) internal successors, (231), 228 states have internal predecessors, (231), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 233 states. [2022-04-27 21:26:00,532 INFO L87 Difference]: Start difference. First operand has 233 states, 228 states have (on average 1.013157894736842) internal successors, (231), 228 states have internal predecessors, (231), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Second operand 233 states. [2022-04-27 21:26:00,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:26:00,535 INFO L93 Difference]: Finished difference Result 233 states and 235 transitions. [2022-04-27 21:26:00,535 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 235 transitions. [2022-04-27 21:26:00,535 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:26:00,535 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:26:00,535 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:26:00,535 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:26:00,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 233 states, 228 states have (on average 1.013157894736842) internal successors, (231), 228 states have internal predecessors, (231), 3 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:26:00,539 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 235 transitions. [2022-04-27 21:26:00,539 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 235 transitions. Word has length 71 [2022-04-27 21:26:00,539 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:26:00,539 INFO L495 AbstractCegarLoop]: Abstraction has 233 states and 235 transitions. [2022-04-27 21:26:00,543 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 66 states, 66 states have (on average 2.0) internal successors, (132), 65 states have internal predecessors, (132), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:26:00,543 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 235 transitions. [2022-04-27 21:26:00,544 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2022-04-27 21:26:00,544 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:26:00,544 INFO L195 NwaCegarLoop]: trace histogram [50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:26:00,562 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2022-04-27 21:26:00,754 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-04-27 21:26:00,755 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:26:00,755 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:26:00,755 INFO L85 PathProgramCache]: Analyzing trace with hash 843717136, now seen corresponding path program 5 times [2022-04-27 21:26:00,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:26:00,755 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1436103388] [2022-04-27 21:26:00,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:26:00,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:26:00,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-04-27 21:26:00,817 INFO L352 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2022-04-27 21:26:00,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2022-04-27 21:26:00,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2022-04-27 21:26:00,873 INFO L271 BasicCegarLoop]: Counterexample is feasible [2022-04-27 21:26:00,874 INFO L805 garLoopResultBuilder]: Registering result UNSAFE for location __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION (0 of 1 remaining) [2022-04-27 21:26:00,875 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable13 [2022-04-27 21:26:00,877 INFO L356 BasicCegarLoop]: Path program histogram: [5, 5, 2, 1, 1] [2022-04-27 21:26:00,880 INFO L176 ceAbstractionStarter]: Computing trace abstraction results [2022-04-27 21:26:00,938 WARN L170 areAnnotationChecker]: ULTIMATE.startENTRY has no Hoare annotation [2022-04-27 21:26:00,938 WARN L170 areAnnotationChecker]: ULTIMATE.initENTRY has no Hoare annotation [2022-04-27 21:26:00,938 WARN L170 areAnnotationChecker]: mainENTRY has no Hoare annotation [2022-04-27 21:26:00,938 WARN L170 areAnnotationChecker]: __VERIFIER_assertENTRY has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: ULTIMATE.initFINAL has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L18-2 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L18-2 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L18-2 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L7 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L7 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: ULTIMATE.initEXIT has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L17-2 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L18 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L18 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L8 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L8 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L7-2 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: L-1 has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: __VERIFIER_assertEXIT has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: mainFINAL has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: mainEXIT has no Hoare annotation [2022-04-27 21:26:00,939 WARN L170 areAnnotationChecker]: ULTIMATE.startFINAL has no Hoare annotation [2022-04-27 21:26:00,939 INFO L163 areAnnotationChecker]: CFG has 0 edges. 0 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. 0 times interpolants missing. [2022-04-27 21:26:00,940 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 09:26:00 BasicIcfg [2022-04-27 21:26:00,940 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2022-04-27 21:26:00,941 INFO L158 Benchmark]: Toolchain (without parser) took 339601.44ms. Allocated memory was 217.1MB in the beginning and 331.4MB in the end (delta: 114.3MB). Free memory was 164.6MB in the beginning and 157.8MB in the end (delta: 6.8MB). Peak memory consumption was 122.0MB. Max. memory is 8.0GB. [2022-04-27 21:26:00,941 INFO L158 Benchmark]: CDTParser took 0.09ms. Allocated memory is still 217.1MB. Free memory was 180.8MB in the beginning and 180.6MB in the end (delta: 151.8kB). There was no memory consumed. Max. memory is 8.0GB. [2022-04-27 21:26:00,941 INFO L158 Benchmark]: CACSL2BoogieTranslator took 194.71ms. Allocated memory is still 217.1MB. Free memory was 164.3MB in the beginning and 193.0MB in the end (delta: -28.8MB). Peak memory consumption was 11.5MB. Max. memory is 8.0GB. [2022-04-27 21:26:00,941 INFO L158 Benchmark]: Boogie Preprocessor took 27.70ms. Allocated memory is still 217.1MB. Free memory was 193.0MB in the beginning and 191.8MB in the end (delta: 1.3MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. [2022-04-27 21:26:00,941 INFO L158 Benchmark]: RCFGBuilder took 231.61ms. Allocated memory is still 217.1MB. Free memory was 191.8MB in the beginning and 181.3MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 8.0GB. [2022-04-27 21:26:00,941 INFO L158 Benchmark]: IcfgTransformer took 36.38ms. Allocated memory is still 217.1MB. Free memory was 181.3MB in the beginning and 179.8MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. [2022-04-27 21:26:00,941 INFO L158 Benchmark]: TraceAbstraction took 339106.40ms. Allocated memory was 217.1MB in the beginning and 331.4MB in the end (delta: 114.3MB). Free memory was 179.4MB in the beginning and 157.8MB in the end (delta: 21.6MB). Peak memory consumption was 136.7MB. Max. memory is 8.0GB. [2022-04-27 21:26:00,942 INFO L339 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - AssertionsEnabledResult: Assertions are enabled Assertions are enabled - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09ms. Allocated memory is still 217.1MB. Free memory was 180.8MB in the beginning and 180.6MB in the end (delta: 151.8kB). There was no memory consumed. Max. memory is 8.0GB. * CACSL2BoogieTranslator took 194.71ms. Allocated memory is still 217.1MB. Free memory was 164.3MB in the beginning and 193.0MB in the end (delta: -28.8MB). Peak memory consumption was 11.5MB. Max. memory is 8.0GB. * Boogie Preprocessor took 27.70ms. Allocated memory is still 217.1MB. Free memory was 193.0MB in the beginning and 191.8MB in the end (delta: 1.3MB). Peak memory consumption was 1.0MB. Max. memory is 8.0GB. * RCFGBuilder took 231.61ms. Allocated memory is still 217.1MB. Free memory was 191.8MB in the beginning and 181.3MB in the end (delta: 10.5MB). Peak memory consumption was 10.5MB. Max. memory is 8.0GB. * IcfgTransformer took 36.38ms. Allocated memory is still 217.1MB. Free memory was 181.3MB in the beginning and 179.8MB in the end (delta: 1.5MB). Peak memory consumption was 2.1MB. Max. memory is 8.0GB. * TraceAbstraction took 339106.40ms. Allocated memory was 217.1MB in the beginning and 331.4MB in the end (delta: 114.3MB). Free memory was 179.4MB in the beginning and 157.8MB in the end (delta: 21.6MB). Peak memory consumption was 136.7MB. Max. memory is 8.0GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: ErrorAutomatonStatistics NumberErrorTraces: 0, NumberStatementsAllTraces: 0, NumberRelevantStatements: 0, 0.0s ErrorAutomatonConstructionTimeTotal, 0.0s FaulLocalizationTime, NumberStatementsFirstTrace: -1, TraceLengthAvg: 0, 0.0s ErrorAutomatonConstructionTimeAvg, 0.0s ErrorAutomatonDifferenceTimeAvg, 0.0s ErrorAutomatonDifferenceTimeTotal, NumberOfNoEnhancement: 0, NumberOfFiniteEnhancement: 0, NumberOfInfiniteEnhancement: 0 - CounterExampleResult [Line: 8]: a call to reach_error is reachable a call to reach_error is reachable We found a FailurePath: [L14] unsigned int x = 0; [L15] unsigned int y = __VERIFIER_nondet_uint(); [L17] COND TRUE x < 99 VAL [x=0, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=2, y=4294967295] [L17] COND TRUE x < 99 VAL [x=2, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=4, y=4294967295] [L17] COND TRUE x < 99 VAL [x=4, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=6, y=4294967295] [L17] COND TRUE x < 99 VAL [x=6, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=8, y=4294967295] [L17] COND TRUE x < 99 VAL [x=8, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=10, y=4294967295] [L17] COND TRUE x < 99 VAL [x=10, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=12, y=4294967295] [L17] COND TRUE x < 99 VAL [x=12, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=14, y=4294967295] [L17] COND TRUE x < 99 VAL [x=14, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=16, y=4294967295] [L17] COND TRUE x < 99 VAL [x=16, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=18, y=4294967295] [L17] COND TRUE x < 99 VAL [x=18, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=20, y=4294967295] [L17] COND TRUE x < 99 VAL [x=20, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=22, y=4294967295] [L17] COND TRUE x < 99 VAL [x=22, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=24, y=4294967295] [L17] COND TRUE x < 99 VAL [x=24, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=26, y=4294967295] [L17] COND TRUE x < 99 VAL [x=26, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=28, y=4294967295] [L17] COND TRUE x < 99 VAL [x=28, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=30, y=4294967295] [L17] COND TRUE x < 99 VAL [x=30, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=32, y=4294967295] [L17] COND TRUE x < 99 VAL [x=32, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=34, y=4294967295] [L17] COND TRUE x < 99 VAL [x=34, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=36, y=4294967295] [L17] COND TRUE x < 99 VAL [x=36, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=38, y=4294967295] [L17] COND TRUE x < 99 VAL [x=38, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=40, y=4294967295] [L17] COND TRUE x < 99 VAL [x=40, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=42, y=4294967295] [L17] COND TRUE x < 99 VAL [x=42, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=44, y=4294967295] [L17] COND TRUE x < 99 VAL [x=44, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=46, y=4294967295] [L17] COND TRUE x < 99 VAL [x=46, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=48, y=4294967295] [L17] COND TRUE x < 99 VAL [x=48, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=50, y=4294967295] [L17] COND TRUE x < 99 VAL [x=50, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=52, y=4294967295] [L17] COND TRUE x < 99 VAL [x=52, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=54, y=4294967295] [L17] COND TRUE x < 99 VAL [x=54, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=56, y=4294967295] [L17] COND TRUE x < 99 VAL [x=56, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=58, y=4294967295] [L17] COND TRUE x < 99 VAL [x=58, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=60, y=4294967295] [L17] COND TRUE x < 99 VAL [x=60, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=62, y=4294967295] [L17] COND TRUE x < 99 VAL [x=62, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=64, y=4294967295] [L17] COND TRUE x < 99 VAL [x=64, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=66, y=4294967295] [L17] COND TRUE x < 99 VAL [x=66, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=68, y=4294967295] [L17] COND TRUE x < 99 VAL [x=68, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=70, y=4294967295] [L17] COND TRUE x < 99 VAL [x=70, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=72, y=4294967295] [L17] COND TRUE x < 99 VAL [x=72, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=74, y=4294967295] [L17] COND TRUE x < 99 VAL [x=74, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=76, y=4294967295] [L17] COND TRUE x < 99 VAL [x=76, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=78, y=4294967295] [L17] COND TRUE x < 99 VAL [x=78, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=80, y=4294967295] [L17] COND TRUE x < 99 VAL [x=80, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=82, y=4294967295] [L17] COND TRUE x < 99 VAL [x=82, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=84, y=4294967295] [L17] COND TRUE x < 99 VAL [x=84, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=86, y=4294967295] [L17] COND TRUE x < 99 VAL [x=86, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=88, y=4294967295] [L17] COND TRUE x < 99 VAL [x=88, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=90, y=4294967295] [L17] COND TRUE x < 99 VAL [x=90, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=92, y=4294967295] [L17] COND TRUE x < 99 VAL [x=92, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=94, y=4294967295] [L17] COND TRUE x < 99 VAL [x=94, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=96, y=4294967295] [L17] COND TRUE x < 99 VAL [x=96, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=98, y=4294967295] [L17] COND TRUE x < 99 VAL [x=98, y=4294967295] [L18] COND FALSE !(y % 2 == 0) [L21] x += 2 VAL [x=100, y=4294967295] [L17] COND FALSE !(x < 99) VAL [x=100, y=4294967295] [L25] CALL __VERIFIER_assert((x % 2) == (y % 2)) VAL [\old(cond)=0] [L7] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L8] reach_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 19 locations, 1 error locations. Started 1 CEGAR loops. OverallTime: 339.0s, OverallIterations: 14, TraceHistogramMax: 50, PathProgramHistogramMax: 5, EmptinessCheckTime: 0.0s, AutomataDifference: 311.9s, DeadEndRemovalTime: 0.0s, HoareAnnotationTime: 0.0s, InitialAbstractionConstructionTime: 0.0s, HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 554 SdHoareTripleChecker+Valid, 8.9s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 553 mSDsluCounter, 861 SdHoareTripleChecker+Invalid, 8.9s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 702 mSDsCounter, 1690 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 6912 IncrementalHoareTripleChecker+Invalid, 8602 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 1690 mSolverCounterUnsat, 159 mSDtfsCounter, 6912 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown, PredicateUnifierStatistics: 0 DeclaredPredicates, 1075 GetRequests, 554 SyntacticMatches, 9 SemanticMatches, 512 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6645 ImplicationChecksByTransitivity, 295.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=233occurred in iteration=13, InterpolantAutomatonStates: 289, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s DumpTime, AutomataMinimizationStatistics: 1.3s AutomataMinimizationTime, 13 MinimizatonAttempts, 136 StatesRemovedByMinimization, 9 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TRACE_CHECK: 0.0s SsaConstructionTime, 11.3s SatisfiabilityAnalysisTime, 11.3s InterpolantComputationTime, 841 NumberOfCodeBlocks, 841 NumberOfCodeBlocksAsserted, 82 NumberOfCheckSat, 1022 ConstructedInterpolants, 0 QuantifiedInterpolants, 5490 SizeOfPredicates, 10 NumberOfNonLiveVariables, 985 ConjunctsInSsa, 258 ConjunctsInUnsatCore, 31 InterpolantComputations, 4 PerfectInterpolantSequences, 262/7150 InterpolantCoveringCapability, INVARIANT_SYNTHESIS: No data available, INTERPOLANT_CONSOLIDATION: No data available, ABSTRACT_INTERPRETATION: No data available, PDR: No data available, ACCELERATED_INTERPOLATION: No data available, SIFA: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! [2022-04-27 21:26:00,962 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Forceful destruction successful, exit code 0 Received shutdown request...