/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loops/insertion_sort-1.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 21:05:31,578 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 21:05:31,580 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 21:05:31,617 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 21:05:31,618 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 21:05:31,619 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 21:05:31,621 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 21:05:31,623 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 21:05:31,624 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 21:05:31,629 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 21:05:31,629 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 21:05:31,631 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 21:05:31,631 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 21:05:31,633 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 21:05:31,633 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 21:05:31,636 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 21:05:31,637 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 21:05:31,637 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 21:05:31,639 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 21:05:31,640 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 21:05:31,641 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 21:05:31,642 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 21:05:31,642 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 21:05:31,643 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 21:05:31,644 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 21:05:31,650 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 21:05:31,655 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 21:05:31,656 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 21:05:31,658 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 21:05:31,658 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-27 21:05:31,682 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 21:05:31,683 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 21:05:31,684 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-27 21:05:31,684 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-27 21:05:31,685 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-27 21:05:31,685 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-27 21:05:31,685 INFO L138 SettingsManager]: * Use SBE=true [2022-04-27 21:05:31,685 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 21:05:31,686 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 21:05:31,686 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 21:05:31,686 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 21:05:31,686 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 21:05:31,687 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:05:31,687 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-27 21:05:31,687 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-27 21:05:31,688 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 21:05:31,688 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-27 21:05:31,688 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-27 21:05:31,688 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-27 21:05:31,688 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-27 21:05:31,689 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 21:05:31,689 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 21:05:31,862 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 21:05:31,882 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 21:05:31,900 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 21:05:31,901 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 21:05:31,902 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 21:05:31,903 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops/insertion_sort-1.c [2022-04-27 21:05:31,966 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ce77ea31a/0d9f44524f2d4acd9090c89c55a63d06/FLAG6bf4be24c [2022-04-27 21:05:32,330 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 21:05:32,330 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c [2022-04-27 21:05:32,334 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ce77ea31a/0d9f44524f2d4acd9090c89c55a63d06/FLAG6bf4be24c [2022-04-27 21:05:32,341 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/ce77ea31a/0d9f44524f2d4acd9090c89c55a63d06 [2022-04-27 21:05:32,343 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 21:05:32,344 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 21:05:32,355 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 21:05:32,355 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 21:05:32,358 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 21:05:32,359 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,360 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46b440c1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32, skipping insertion in model container [2022-04-27 21:05:32,360 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,364 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 21:05:32,375 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 21:05:32,494 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c[328,341] [2022-04-27 21:05:32,543 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:05:32,561 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 21:05:32,571 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-1.c[328,341] [2022-04-27 21:05:32,579 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:05:32,587 INFO L208 MainTranslator]: Completed translation [2022-04-27 21:05:32,587 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32 WrapperNode [2022-04-27 21:05:32,587 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 21:05:32,591 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 21:05:32,592 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 21:05:32,592 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 21:05:32,609 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,609 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,621 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,621 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,651 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,654 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,655 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,656 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 21:05:32,657 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 21:05:32,657 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 21:05:32,657 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 21:05:32,660 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,670 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:05:32,676 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:32,686 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 21:05:32,695 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 21:05:32,720 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 21:05:32,720 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 21:05:32,720 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 21:05:32,720 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 21:05:32,720 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 21:05:32,720 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 21:05:32,721 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 21:05:32,721 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 21:05:32,723 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 21:05:32,723 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 21:05:32,723 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 21:05:32,723 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2022-04-27 21:05:32,723 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 21:05:32,724 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 21:05:32,807 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 21:05:32,809 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 21:05:32,968 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 21:05:32,972 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 21:05:32,972 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-27 21:05:32,974 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:05:32 BoogieIcfgContainer [2022-04-27 21:05:32,974 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 21:05:32,974 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 21:05:32,974 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 21:05:32,975 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 21:05:32,984 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:05:32" (1/1) ... [2022-04-27 21:05:32,985 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-27 21:05:33,005 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:05:33 BasicIcfg [2022-04-27 21:05:33,005 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 21:05:33,006 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 21:05:33,006 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 21:05:33,008 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 21:05:33,008 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 09:05:32" (1/4) ... [2022-04-27 21:05:33,009 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7a8a4591 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,009 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:32" (2/4) ... [2022-04-27 21:05:33,009 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7a8a4591 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,009 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:05:32" (3/4) ... [2022-04-27 21:05:33,009 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7a8a4591 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,009 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:05:33" (4/4) ... [2022-04-27 21:05:33,010 INFO L111 eAbstractionObserver]: Analyzing ICFG insertion_sort-1.cqvasr [2022-04-27 21:05:33,019 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-27 21:05:33,019 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 21:05:33,045 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 21:05:33,054 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@52514a6d, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@501a6b64 [2022-04-27 21:05:33,054 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 21:05:33,073 INFO L276 IsEmpty]: Start isEmpty. Operand has 33 states, 25 states have (on average 1.48) internal successors, (37), 26 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:33,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 21:05:33,079 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:33,080 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:33,080 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:33,088 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:33,091 INFO L85 PathProgramCache]: Analyzing trace with hash -1926103570, now seen corresponding path program 1 times [2022-04-27 21:05:33,097 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:33,097 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325075938] [2022-04-27 21:05:33,097 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:33,098 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:33,163 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:33,231 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:33,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:33,259 INFO L290 TraceCheckUtils]: 0: Hoare triple {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {36#true} is VALID [2022-04-27 21:05:33,259 INFO L290 TraceCheckUtils]: 1: Hoare triple {36#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-27 21:05:33,259 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {36#true} {36#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-27 21:05:33,264 INFO L272 TraceCheckUtils]: 0: Hoare triple {36#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:33,265 INFO L290 TraceCheckUtils]: 1: Hoare triple {41#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {36#true} is VALID [2022-04-27 21:05:33,265 INFO L290 TraceCheckUtils]: 2: Hoare triple {36#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-27 21:05:33,265 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {36#true} {36#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-27 21:05:33,265 INFO L272 TraceCheckUtils]: 4: Hoare triple {36#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {36#true} is VALID [2022-04-27 21:05:33,266 INFO L290 TraceCheckUtils]: 5: Hoare triple {36#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {36#true} is VALID [2022-04-27 21:05:33,268 INFO L290 TraceCheckUtils]: 6: Hoare triple {36#true} [103] L17-3-->L17-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-27 21:05:33,268 INFO L290 TraceCheckUtils]: 7: Hoare triple {37#false} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {37#false} is VALID [2022-04-27 21:05:33,268 INFO L290 TraceCheckUtils]: 8: Hoare triple {37#false} [108] L19-3-->L19-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-27 21:05:33,268 INFO L290 TraceCheckUtils]: 9: Hoare triple {37#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {37#false} is VALID [2022-04-27 21:05:33,268 INFO L290 TraceCheckUtils]: 10: Hoare triple {37#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {37#false} is VALID [2022-04-27 21:05:33,269 INFO L272 TraceCheckUtils]: 11: Hoare triple {37#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {37#false} is VALID [2022-04-27 21:05:33,269 INFO L290 TraceCheckUtils]: 12: Hoare triple {37#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {37#false} is VALID [2022-04-27 21:05:33,269 INFO L290 TraceCheckUtils]: 13: Hoare triple {37#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-27 21:05:33,269 INFO L290 TraceCheckUtils]: 14: Hoare triple {37#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {37#false} is VALID [2022-04-27 21:05:33,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:33,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:33,270 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325075938] [2022-04-27 21:05:33,270 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325075938] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:33,271 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:05:33,271 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 21:05:33,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422455406] [2022-04-27 21:05:33,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:33,275 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:33,277 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:33,278 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:33,302 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:33,302 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 21:05:33,303 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:33,332 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 21:05:33,332 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:05:33,334 INFO L87 Difference]: Start difference. First operand has 33 states, 25 states have (on average 1.48) internal successors, (37), 26 states have internal predecessors, (37), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:33,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:33,439 INFO L93 Difference]: Finished difference Result 58 states and 77 transitions. [2022-04-27 21:05:33,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 21:05:33,439 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:33,440 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:33,441 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:33,457 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 77 transitions. [2022-04-27 21:05:33,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:33,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 77 transitions. [2022-04-27 21:05:33,462 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 77 transitions. [2022-04-27 21:05:33,567 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 77 edges. 77 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:33,574 INFO L225 Difference]: With dead ends: 58 [2022-04-27 21:05:33,574 INFO L226 Difference]: Without dead ends: 28 [2022-04-27 21:05:33,576 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:05:33,581 INFO L413 NwaCegarLoop]: 37 mSDtfsCounter, 29 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 30 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:33,582 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [30 Valid, 40 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:05:33,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-27 21:05:33,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2022-04-27 21:05:33,607 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:33,607 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:33,608 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:33,608 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:33,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:33,610 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-27 21:05:33,610 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-27 21:05:33,611 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:33,611 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:33,611 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-27 21:05:33,611 INFO L87 Difference]: Start difference. First operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-27 21:05:33,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:33,614 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2022-04-27 21:05:33,614 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-27 21:05:33,614 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:33,614 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:33,614 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:33,614 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:33,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 22 states have (on average 1.2727272727272727) internal successors, (28), 22 states have internal predecessors, (28), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:33,635 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 33 transitions. [2022-04-27 21:05:33,637 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 33 transitions. Word has length 15 [2022-04-27 21:05:33,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:33,637 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 33 transitions. [2022-04-27 21:05:33,637 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:33,637 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 33 transitions. [2022-04-27 21:05:33,638 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 21:05:33,638 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:33,638 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:33,638 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 21:05:33,639 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:33,640 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:33,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1448912944, now seen corresponding path program 1 times [2022-04-27 21:05:33,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:33,640 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421029776] [2022-04-27 21:05:33,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:33,641 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:33,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:33,818 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:33,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:33,824 INFO L290 TraceCheckUtils]: 0: Hoare triple {219#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {211#true} is VALID [2022-04-27 21:05:33,825 INFO L290 TraceCheckUtils]: 1: Hoare triple {211#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-27 21:05:33,825 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {211#true} {211#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-27 21:05:33,826 INFO L272 TraceCheckUtils]: 0: Hoare triple {211#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {219#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:33,826 INFO L290 TraceCheckUtils]: 1: Hoare triple {219#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {211#true} is VALID [2022-04-27 21:05:33,826 INFO L290 TraceCheckUtils]: 2: Hoare triple {211#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-27 21:05:33,826 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {211#true} {211#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-27 21:05:33,826 INFO L272 TraceCheckUtils]: 4: Hoare triple {211#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {211#true} is VALID [2022-04-27 21:05:33,827 INFO L290 TraceCheckUtils]: 5: Hoare triple {211#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {216#(= main_~j~0 0)} is VALID [2022-04-27 21:05:33,827 INFO L290 TraceCheckUtils]: 6: Hoare triple {216#(= main_~j~0 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 21:05:33,828 INFO L290 TraceCheckUtils]: 7: Hoare triple {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 21:05:33,828 INFO L290 TraceCheckUtils]: 8: Hoare triple {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 21:05:33,829 INFO L290 TraceCheckUtils]: 9: Hoare triple {217#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {218#(and (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:33,830 INFO L290 TraceCheckUtils]: 10: Hoare triple {218#(and (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {212#false} is VALID [2022-04-27 21:05:33,830 INFO L272 TraceCheckUtils]: 11: Hoare triple {212#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {212#false} is VALID [2022-04-27 21:05:33,830 INFO L290 TraceCheckUtils]: 12: Hoare triple {212#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {212#false} is VALID [2022-04-27 21:05:33,830 INFO L290 TraceCheckUtils]: 13: Hoare triple {212#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {212#false} is VALID [2022-04-27 21:05:33,831 INFO L290 TraceCheckUtils]: 14: Hoare triple {212#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {212#false} is VALID [2022-04-27 21:05:33,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:33,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:33,831 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421029776] [2022-04-27 21:05:33,831 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421029776] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:33,831 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:05:33,831 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 21:05:33,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1035477883] [2022-04-27 21:05:33,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:33,833 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:33,833 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:33,833 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:33,845 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:33,845 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 21:05:33,845 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:33,846 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 21:05:33,849 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-04-27 21:05:33,850 INFO L87 Difference]: Start difference. First operand 28 states and 33 transitions. Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,116 INFO L93 Difference]: Finished difference Result 53 states and 64 transitions. [2022-04-27 21:05:34,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:05:34,117 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:34,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:34,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,119 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 64 transitions. [2022-04-27 21:05:34,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 64 transitions. [2022-04-27 21:05:34,120 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 64 transitions. [2022-04-27 21:05:34,173 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:34,175 INFO L225 Difference]: With dead ends: 53 [2022-04-27 21:05:34,175 INFO L226 Difference]: Without dead ends: 30 [2022-04-27 21:05:34,176 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:34,177 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 34 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 89 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 35 SdHoareTripleChecker+Valid, 45 SdHoareTripleChecker+Invalid, 93 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 89 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:34,178 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [35 Valid, 45 Invalid, 93 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 89 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:05:34,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2022-04-27 21:05:34,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 29. [2022-04-27 21:05:34,184 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:34,185 INFO L82 GeneralOperation]: Start isEquivalent. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,186 INFO L74 IsIncluded]: Start isIncluded. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,187 INFO L87 Difference]: Start difference. First operand 30 states. Second operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,189 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-27 21:05:34,189 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-27 21:05:34,190 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:34,190 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:34,190 INFO L74 IsIncluded]: Start isIncluded. First operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 30 states. [2022-04-27 21:05:34,190 INFO L87 Difference]: Start difference. First operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 30 states. [2022-04-27 21:05:34,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,191 INFO L93 Difference]: Finished difference Result 30 states and 35 transitions. [2022-04-27 21:05:34,191 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-27 21:05:34,192 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:34,192 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:34,192 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:34,192 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:34,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29 states, 23 states have (on average 1.2608695652173914) internal successors, (29), 23 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 34 transitions. [2022-04-27 21:05:34,193 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 34 transitions. Word has length 15 [2022-04-27 21:05:34,193 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:34,193 INFO L495 AbstractCegarLoop]: Abstraction has 29 states and 34 transitions. [2022-04-27 21:05:34,194 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,194 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 34 transitions. [2022-04-27 21:05:34,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 21:05:34,194 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:34,194 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:34,194 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 21:05:34,194 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:34,195 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:34,195 INFO L85 PathProgramCache]: Analyzing trace with hash 1246349198, now seen corresponding path program 1 times [2022-04-27 21:05:34,195 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:34,195 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390599897] [2022-04-27 21:05:34,195 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:34,195 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:34,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,283 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:34,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,289 INFO L290 TraceCheckUtils]: 0: Hoare triple {410#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {401#true} is VALID [2022-04-27 21:05:34,289 INFO L290 TraceCheckUtils]: 1: Hoare triple {401#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,289 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {401#true} {401#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,290 INFO L272 TraceCheckUtils]: 0: Hoare triple {401#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {410#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:34,290 INFO L290 TraceCheckUtils]: 1: Hoare triple {410#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {401#true} is VALID [2022-04-27 21:05:34,290 INFO L290 TraceCheckUtils]: 2: Hoare triple {401#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,290 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {401#true} {401#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,290 INFO L272 TraceCheckUtils]: 4: Hoare triple {401#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,291 INFO L290 TraceCheckUtils]: 5: Hoare triple {401#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {406#(= main_~j~0 0)} is VALID [2022-04-27 21:05:34,291 INFO L290 TraceCheckUtils]: 6: Hoare triple {406#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {406#(= main_~j~0 0)} is VALID [2022-04-27 21:05:34,292 INFO L290 TraceCheckUtils]: 7: Hoare triple {406#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {407#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:34,292 INFO L290 TraceCheckUtils]: 8: Hoare triple {407#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:34,293 INFO L290 TraceCheckUtils]: 9: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:34,293 INFO L290 TraceCheckUtils]: 10: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:34,294 INFO L290 TraceCheckUtils]: 11: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:34,294 INFO L290 TraceCheckUtils]: 12: Hoare triple {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {402#false} is VALID [2022-04-27 21:05:34,295 INFO L272 TraceCheckUtils]: 13: Hoare triple {402#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {402#false} is VALID [2022-04-27 21:05:34,295 INFO L290 TraceCheckUtils]: 14: Hoare triple {402#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {402#false} is VALID [2022-04-27 21:05:34,295 INFO L290 TraceCheckUtils]: 15: Hoare triple {402#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-27 21:05:34,295 INFO L290 TraceCheckUtils]: 16: Hoare triple {402#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-27 21:05:34,295 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:34,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:34,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390599897] [2022-04-27 21:05:34,296 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390599897] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:34,296 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1393970933] [2022-04-27 21:05:34,296 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:34,296 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:34,296 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:34,297 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:34,326 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 21:05:34,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,343 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 21:05:34,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,352 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:34,664 INFO L272 TraceCheckUtils]: 0: Hoare triple {401#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,665 INFO L290 TraceCheckUtils]: 1: Hoare triple {401#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {401#true} is VALID [2022-04-27 21:05:34,665 INFO L290 TraceCheckUtils]: 2: Hoare triple {401#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,665 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {401#true} {401#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,665 INFO L272 TraceCheckUtils]: 4: Hoare triple {401#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,665 INFO L290 TraceCheckUtils]: 5: Hoare triple {401#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {401#true} is VALID [2022-04-27 21:05:34,666 INFO L290 TraceCheckUtils]: 6: Hoare triple {401#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {401#true} is VALID [2022-04-27 21:05:34,666 INFO L290 TraceCheckUtils]: 7: Hoare triple {401#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {401#true} is VALID [2022-04-27 21:05:34,666 INFO L290 TraceCheckUtils]: 8: Hoare triple {401#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {401#true} is VALID [2022-04-27 21:05:34,666 INFO L290 TraceCheckUtils]: 9: Hoare triple {401#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {441#(= main_~j~0 1)} is VALID [2022-04-27 21:05:34,667 INFO L290 TraceCheckUtils]: 10: Hoare triple {441#(= main_~j~0 1)} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:34,668 INFO L290 TraceCheckUtils]: 11: Hoare triple {408#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:34,668 INFO L290 TraceCheckUtils]: 12: Hoare triple {409#(and (= (+ (- 1) main_~k~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {402#false} is VALID [2022-04-27 21:05:34,669 INFO L272 TraceCheckUtils]: 13: Hoare triple {402#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {402#false} is VALID [2022-04-27 21:05:34,669 INFO L290 TraceCheckUtils]: 14: Hoare triple {402#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {402#false} is VALID [2022-04-27 21:05:34,669 INFO L290 TraceCheckUtils]: 15: Hoare triple {402#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-27 21:05:34,669 INFO L290 TraceCheckUtils]: 16: Hoare triple {402#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {402#false} is VALID [2022-04-27 21:05:34,669 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:05:34,669 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 21:05:34,670 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1393970933] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:34,670 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 21:05:34,670 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 8 [2022-04-27 21:05:34,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1064589296] [2022-04-27 21:05:34,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:34,670 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 21:05:34,671 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:34,671 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,682 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:34,683 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-04-27 21:05:34,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:34,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-04-27 21:05:34,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2022-04-27 21:05:34,684 INFO L87 Difference]: Start difference. First operand 29 states and 34 transitions. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,760 INFO L93 Difference]: Finished difference Result 49 states and 58 transitions. [2022-04-27 21:05:34,760 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-04-27 21:05:34,760 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 21:05:34,760 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:34,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 57 transitions. [2022-04-27 21:05:34,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 57 transitions. [2022-04-27 21:05:34,763 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 5 states and 57 transitions. [2022-04-27 21:05:34,803 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 57 edges. 57 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:34,804 INFO L225 Difference]: With dead ends: 49 [2022-04-27 21:05:34,804 INFO L226 Difference]: Without dead ends: 37 [2022-04-27 21:05:34,804 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 16 SyntacticMatches, 2 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=62, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:34,805 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 13 mSDsluCounter, 51 mSDsCounter, 0 mSdLazyCounter, 18 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 13 SdHoareTripleChecker+Valid, 81 SdHoareTripleChecker+Invalid, 18 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 18 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:34,805 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [13 Valid, 81 Invalid, 18 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 18 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:05:34,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2022-04-27 21:05:34,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 30. [2022-04-27 21:05:34,808 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:34,808 INFO L82 GeneralOperation]: Start isEquivalent. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,808 INFO L74 IsIncluded]: Start isIncluded. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,808 INFO L87 Difference]: Start difference. First operand 37 states. Second operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,809 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2022-04-27 21:05:34,809 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-27 21:05:34,810 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:34,810 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:34,810 INFO L74 IsIncluded]: Start isIncluded. First operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-27 21:05:34,810 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 37 states. [2022-04-27 21:05:34,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,811 INFO L93 Difference]: Finished difference Result 37 states and 45 transitions. [2022-04-27 21:05:34,811 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 45 transitions. [2022-04-27 21:05:34,812 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:34,812 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:34,812 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:34,812 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:34,812 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 24 states have (on average 1.25) internal successors, (30), 24 states have internal predecessors, (30), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 35 transitions. [2022-04-27 21:05:34,813 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 35 transitions. Word has length 17 [2022-04-27 21:05:34,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:34,813 INFO L495 AbstractCegarLoop]: Abstraction has 30 states and 35 transitions. [2022-04-27 21:05:34,813 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,813 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 35 transitions. [2022-04-27 21:05:34,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 21:05:34,814 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:34,814 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:34,830 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Ended with exit code 0 [2022-04-27 21:05:35,031 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:35,032 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:35,032 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:35,032 INFO L85 PathProgramCache]: Analyzing trace with hash 931318849, now seen corresponding path program 1 times [2022-04-27 21:05:35,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:35,032 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054436035] [2022-04-27 21:05:35,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:35,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:35,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,321 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:35,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,326 INFO L290 TraceCheckUtils]: 0: Hoare triple {657#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-27 21:05:35,326 INFO L290 TraceCheckUtils]: 1: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,326 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,327 INFO L272 TraceCheckUtils]: 0: Hoare triple {648#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {657#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:35,327 INFO L290 TraceCheckUtils]: 1: Hoare triple {657#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-27 21:05:35,327 INFO L290 TraceCheckUtils]: 2: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,327 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,328 INFO L272 TraceCheckUtils]: 4: Hoare triple {648#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,328 INFO L290 TraceCheckUtils]: 5: Hoare triple {648#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {653#(= main_~j~0 0)} is VALID [2022-04-27 21:05:35,328 INFO L290 TraceCheckUtils]: 6: Hoare triple {653#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {653#(= main_~j~0 0)} is VALID [2022-04-27 21:05:35,329 INFO L290 TraceCheckUtils]: 7: Hoare triple {653#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {654#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:35,329 INFO L290 TraceCheckUtils]: 8: Hoare triple {654#(and (not (<= (+ (div main_~j~0 4294967296) 1) 0)) (<= main_~j~0 1))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:35,330 INFO L290 TraceCheckUtils]: 9: Hoare triple {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:35,336 INFO L290 TraceCheckUtils]: 10: Hoare triple {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {649#false} is VALID [2022-04-27 21:05:35,336 INFO L290 TraceCheckUtils]: 11: Hoare triple {649#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {649#false} is VALID [2022-04-27 21:05:35,336 INFO L290 TraceCheckUtils]: 12: Hoare triple {649#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-27 21:05:35,336 INFO L290 TraceCheckUtils]: 13: Hoare triple {649#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-27 21:05:35,336 INFO L290 TraceCheckUtils]: 14: Hoare triple {649#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {649#false} is VALID [2022-04-27 21:05:35,336 INFO L290 TraceCheckUtils]: 15: Hoare triple {649#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L290 TraceCheckUtils]: 17: Hoare triple {649#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L290 TraceCheckUtils]: 18: Hoare triple {649#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L272 TraceCheckUtils]: 19: Hoare triple {649#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L290 TraceCheckUtils]: 20: Hoare triple {649#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L290 TraceCheckUtils]: 21: Hoare triple {649#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:35,337 INFO L290 TraceCheckUtils]: 22: Hoare triple {649#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:35,338 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:35,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:35,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1054436035] [2022-04-27 21:05:35,338 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1054436035] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:35,338 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [422632246] [2022-04-27 21:05:35,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:35,338 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:35,338 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:35,350 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:35,351 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 21:05:35,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,397 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 21:05:35,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,404 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:35,813 INFO L272 TraceCheckUtils]: 0: Hoare triple {648#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,814 INFO L290 TraceCheckUtils]: 1: Hoare triple {648#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-27 21:05:35,814 INFO L290 TraceCheckUtils]: 2: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,816 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,816 INFO L272 TraceCheckUtils]: 4: Hoare triple {648#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:35,816 INFO L290 TraceCheckUtils]: 5: Hoare triple {648#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {653#(= main_~j~0 0)} is VALID [2022-04-27 21:05:35,817 INFO L290 TraceCheckUtils]: 6: Hoare triple {653#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {653#(= main_~j~0 0)} is VALID [2022-04-27 21:05:35,817 INFO L290 TraceCheckUtils]: 7: Hoare triple {653#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {682#(= main_~j~0 1)} is VALID [2022-04-27 21:05:35,818 INFO L290 TraceCheckUtils]: 8: Hoare triple {682#(= main_~j~0 1)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:35,818 INFO L290 TraceCheckUtils]: 9: Hoare triple {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:35,819 INFO L290 TraceCheckUtils]: 10: Hoare triple {656#(and (= (+ (- 1) main_~j~0) 0) (<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {649#false} is VALID [2022-04-27 21:05:35,819 INFO L290 TraceCheckUtils]: 11: Hoare triple {649#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {649#false} is VALID [2022-04-27 21:05:35,821 INFO L290 TraceCheckUtils]: 12: Hoare triple {649#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-27 21:05:35,821 INFO L290 TraceCheckUtils]: 13: Hoare triple {649#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-27 21:05:35,822 INFO L290 TraceCheckUtils]: 14: Hoare triple {649#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {649#false} is VALID [2022-04-27 21:05:35,822 INFO L290 TraceCheckUtils]: 15: Hoare triple {649#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {649#false} is VALID [2022-04-27 21:05:35,823 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:35,830 INFO L290 TraceCheckUtils]: 17: Hoare triple {649#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {649#false} is VALID [2022-04-27 21:05:35,832 INFO L290 TraceCheckUtils]: 18: Hoare triple {649#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {649#false} is VALID [2022-04-27 21:05:35,832 INFO L272 TraceCheckUtils]: 19: Hoare triple {649#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {649#false} is VALID [2022-04-27 21:05:35,832 INFO L290 TraceCheckUtils]: 20: Hoare triple {649#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {649#false} is VALID [2022-04-27 21:05:35,832 INFO L290 TraceCheckUtils]: 21: Hoare triple {649#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:35,832 INFO L290 TraceCheckUtils]: 22: Hoare triple {649#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:35,833 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:35,833 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:36,215 INFO L290 TraceCheckUtils]: 22: Hoare triple {649#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 21: Hoare triple {649#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 20: Hoare triple {649#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L272 TraceCheckUtils]: 19: Hoare triple {649#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 18: Hoare triple {649#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 17: Hoare triple {649#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 16: Hoare triple {649#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 15: Hoare triple {649#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 14: Hoare triple {649#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {649#false} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 13: Hoare triple {649#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-27 21:05:36,217 INFO L290 TraceCheckUtils]: 12: Hoare triple {649#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {649#false} is VALID [2022-04-27 21:05:36,217 INFO L290 TraceCheckUtils]: 11: Hoare triple {649#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {649#false} is VALID [2022-04-27 21:05:36,218 INFO L290 TraceCheckUtils]: 10: Hoare triple {764#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {649#false} is VALID [2022-04-27 21:05:36,218 INFO L290 TraceCheckUtils]: 9: Hoare triple {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {764#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 21:05:36,219 INFO L290 TraceCheckUtils]: 8: Hoare triple {771#(<= 0 (div (+ (* (- 1) (mod main_~j~0 4294967296)) 1) 4294967296))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {655#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:36,220 INFO L290 TraceCheckUtils]: 7: Hoare triple {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {771#(<= 0 (div (+ (* (- 1) (mod main_~j~0 4294967296)) 1) 4294967296))} is VALID [2022-04-27 21:05:36,220 INFO L290 TraceCheckUtils]: 6: Hoare triple {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} is VALID [2022-04-27 21:05:36,221 INFO L290 TraceCheckUtils]: 5: Hoare triple {648#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {775#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} is VALID [2022-04-27 21:05:36,221 INFO L272 TraceCheckUtils]: 4: Hoare triple {648#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:36,221 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {648#true} {648#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:36,221 INFO L290 TraceCheckUtils]: 2: Hoare triple {648#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:36,221 INFO L290 TraceCheckUtils]: 1: Hoare triple {648#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {648#true} is VALID [2022-04-27 21:05:36,221 INFO L272 TraceCheckUtils]: 0: Hoare triple {648#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {648#true} is VALID [2022-04-27 21:05:36,222 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:36,222 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [422632246] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:36,224 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:36,224 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 11 [2022-04-27 21:05:36,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1961205715] [2022-04-27 21:05:36,224 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:36,224 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:05:36,226 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:36,226 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,251 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 33 edges. 33 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:36,251 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-04-27 21:05:36,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:36,252 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-04-27 21:05:36,252 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2022-04-27 21:05:36,252 INFO L87 Difference]: Start difference. First operand 30 states and 35 transitions. Second operand has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:36,555 INFO L93 Difference]: Finished difference Result 61 states and 74 transitions. [2022-04-27 21:05:36,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:05:36,555 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:05:36,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:36,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,557 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 74 transitions. [2022-04-27 21:05:36,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 74 transitions. [2022-04-27 21:05:36,558 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 74 transitions. [2022-04-27 21:05:36,612 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 74 edges. 74 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:36,613 INFO L225 Difference]: With dead ends: 61 [2022-04-27 21:05:36,613 INFO L226 Difference]: Without dead ends: 40 [2022-04-27 21:05:36,613 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 42 SyntacticMatches, 3 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 37 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=58, Invalid=152, Unknown=0, NotChecked=0, Total=210 [2022-04-27 21:05:36,614 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 70 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 145 mSolverCounterSat, 15 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 53 SdHoareTripleChecker+Invalid, 160 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 15 IncrementalHoareTripleChecker+Valid, 145 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:36,614 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [70 Valid, 53 Invalid, 160 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [15 Valid, 145 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:05:36,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2022-04-27 21:05:36,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 32. [2022-04-27 21:05:36,618 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:36,618 INFO L82 GeneralOperation]: Start isEquivalent. First operand 40 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,618 INFO L74 IsIncluded]: Start isIncluded. First operand 40 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,618 INFO L87 Difference]: Start difference. First operand 40 states. Second operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:36,619 INFO L93 Difference]: Finished difference Result 40 states and 48 transitions. [2022-04-27 21:05:36,619 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 48 transitions. [2022-04-27 21:05:36,619 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:36,620 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:36,620 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 40 states. [2022-04-27 21:05:36,620 INFO L87 Difference]: Start difference. First operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 40 states. [2022-04-27 21:05:36,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:36,621 INFO L93 Difference]: Finished difference Result 40 states and 48 transitions. [2022-04-27 21:05:36,621 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 48 transitions. [2022-04-27 21:05:36,621 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:36,621 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:36,621 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:36,621 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:36,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 26 states have internal predecessors, (32), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 37 transitions. [2022-04-27 21:05:36,622 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 37 transitions. Word has length 23 [2022-04-27 21:05:36,622 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:36,622 INFO L495 AbstractCegarLoop]: Abstraction has 32 states and 37 transitions. [2022-04-27 21:05:36,623 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 2.5454545454545454) internal successors, (28), 10 states have internal predecessors, (28), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,623 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 37 transitions. [2022-04-27 21:05:36,623 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-27 21:05:36,623 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:36,623 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:36,639 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Ended with exit code 0 [2022-04-27 21:05:36,839 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable3 [2022-04-27 21:05:36,840 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:36,840 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:36,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1459507809, now seen corresponding path program 2 times [2022-04-27 21:05:36,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:36,840 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184102059] [2022-04-27 21:05:36,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:36,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:36,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,219 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:37,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,224 INFO L290 TraceCheckUtils]: 0: Hoare triple {1031#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-27 21:05:37,225 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,225 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,225 INFO L272 TraceCheckUtils]: 0: Hoare triple {1013#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1031#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:37,226 INFO L290 TraceCheckUtils]: 1: Hoare triple {1031#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-27 21:05:37,226 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,226 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,226 INFO L272 TraceCheckUtils]: 4: Hoare triple {1013#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,226 INFO L290 TraceCheckUtils]: 5: Hoare triple {1013#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:37,227 INFO L290 TraceCheckUtils]: 6: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:37,227 INFO L290 TraceCheckUtils]: 7: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:37,228 INFO L290 TraceCheckUtils]: 8: Hoare triple {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:37,228 INFO L290 TraceCheckUtils]: 9: Hoare triple {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:37,229 INFO L290 TraceCheckUtils]: 10: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:37,229 INFO L290 TraceCheckUtils]: 11: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:37,230 INFO L290 TraceCheckUtils]: 12: Hoare triple {1019#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1021#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:37,231 INFO L290 TraceCheckUtils]: 13: Hoare triple {1021#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1022#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-27 21:05:37,231 INFO L290 TraceCheckUtils]: 14: Hoare triple {1022#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1023#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:05:37,232 INFO L290 TraceCheckUtils]: 15: Hoare triple {1023#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1024#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:37,233 INFO L290 TraceCheckUtils]: 16: Hoare triple {1024#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1025#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:37,233 INFO L290 TraceCheckUtils]: 17: Hoare triple {1025#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:37,234 INFO L290 TraceCheckUtils]: 18: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:37,234 INFO L290 TraceCheckUtils]: 19: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:05:37,235 INFO L290 TraceCheckUtils]: 20: Hoare triple {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1028#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:37,235 INFO L272 TraceCheckUtils]: 21: Hoare triple {1028#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1029#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:05:37,236 INFO L290 TraceCheckUtils]: 22: Hoare triple {1029#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1030#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:05:37,236 INFO L290 TraceCheckUtils]: 23: Hoare triple {1030#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-27 21:05:37,236 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-27 21:05:37,237 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:37,237 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:37,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184102059] [2022-04-27 21:05:37,237 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184102059] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:37,237 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1386527120] [2022-04-27 21:05:37,237 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:05:37,237 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:37,237 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:37,238 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:37,239 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 21:05:37,280 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:05:37,280 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:05:37,281 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 26 conjunts are in the unsatisfiable core [2022-04-27 21:05:37,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,294 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:37,334 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-04-27 21:05:37,379 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-04-27 21:05:37,756 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:05:37,757 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 21:05:37,883 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:05:37,883 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 21:05:37,950 INFO L272 TraceCheckUtils]: 0: Hoare triple {1013#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,951 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-27 21:05:37,951 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,951 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,951 INFO L272 TraceCheckUtils]: 4: Hoare triple {1013#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:37,952 INFO L290 TraceCheckUtils]: 5: Hoare triple {1013#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:37,953 INFO L290 TraceCheckUtils]: 6: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:37,953 INFO L290 TraceCheckUtils]: 7: Hoare triple {1018#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1056#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0))} is VALID [2022-04-27 21:05:37,953 INFO L290 TraceCheckUtils]: 8: Hoare triple {1056#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:37,953 INFO L290 TraceCheckUtils]: 9: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:37,954 INFO L290 TraceCheckUtils]: 10: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1020#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:37,954 INFO L290 TraceCheckUtils]: 11: Hoare triple {1020#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1069#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:37,955 INFO L290 TraceCheckUtils]: 12: Hoare triple {1069#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1073#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-27 21:05:37,955 INFO L290 TraceCheckUtils]: 13: Hoare triple {1073#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1077#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:05:37,956 INFO L290 TraceCheckUtils]: 14: Hoare triple {1077#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1081#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:05:37,956 INFO L290 TraceCheckUtils]: 15: Hoare triple {1081#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1085#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:37,957 INFO L290 TraceCheckUtils]: 16: Hoare triple {1085#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:37,957 INFO L290 TraceCheckUtils]: 17: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:37,958 INFO L290 TraceCheckUtils]: 18: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:37,958 INFO L290 TraceCheckUtils]: 19: Hoare triple {1026#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:05:37,959 INFO L290 TraceCheckUtils]: 20: Hoare triple {1027#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1028#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:37,959 INFO L272 TraceCheckUtils]: 21: Hoare triple {1028#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:37,959 INFO L290 TraceCheckUtils]: 22: Hoare triple {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1108#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:37,960 INFO L290 TraceCheckUtils]: 23: Hoare triple {1108#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-27 21:05:37,960 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-27 21:05:37,960 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:37,960 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:39,007 INFO L290 TraceCheckUtils]: 24: Hoare triple {1014#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-27 21:05:39,007 INFO L290 TraceCheckUtils]: 23: Hoare triple {1108#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1014#false} is VALID [2022-04-27 21:05:39,008 INFO L290 TraceCheckUtils]: 22: Hoare triple {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1108#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:39,012 INFO L272 TraceCheckUtils]: 21: Hoare triple {1028#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1104#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:39,012 INFO L290 TraceCheckUtils]: 20: Hoare triple {1127#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1028#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:39,013 INFO L290 TraceCheckUtils]: 19: Hoare triple {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1127#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:05:39,013 INFO L290 TraceCheckUtils]: 18: Hoare triple {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:39,013 INFO L290 TraceCheckUtils]: 17: Hoare triple {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:39,014 INFO L290 TraceCheckUtils]: 16: Hoare triple {1141#(forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1131#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:39,015 INFO L290 TraceCheckUtils]: 15: Hoare triple {1145#(or (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45)))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1141#(forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45))))} is VALID [2022-04-27 21:05:39,015 INFO L290 TraceCheckUtils]: 14: Hoare triple {1149#(or (not |main_#t~short10|) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1145#(or (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (not (<= main_~key~0 v_ArrVal_45)))) |main_#t~short10|)} is VALID [2022-04-27 21:05:39,016 INFO L290 TraceCheckUtils]: 13: Hoare triple {1153#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1149#(or (not |main_#t~short10|) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-27 21:05:39,021 INFO L290 TraceCheckUtils]: 12: Hoare triple {1157#(forall ((v_main_~i~0_12 Int)) (or (not (<= 0 v_main_~i~0_12)) (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4)))))) (not (<= (+ v_main_~i~0_12 1) main_~j~0))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1153#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_45 Int)) (or (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_45) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-27 21:05:39,022 INFO L290 TraceCheckUtils]: 11: Hoare triple {1013#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1157#(forall ((v_main_~i~0_12 Int)) (or (not (<= 0 v_main_~i~0_12)) (forall ((v_ArrVal_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_45) (+ |main_~#v~0.offset| 4))) (< v_ArrVal_45 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4)))))) (not (<= (+ v_main_~i~0_12 1) main_~j~0))))} is VALID [2022-04-27 21:05:39,022 INFO L290 TraceCheckUtils]: 10: Hoare triple {1013#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:39,022 INFO L290 TraceCheckUtils]: 9: Hoare triple {1013#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L290 TraceCheckUtils]: 8: Hoare triple {1013#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L290 TraceCheckUtils]: 7: Hoare triple {1013#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L290 TraceCheckUtils]: 6: Hoare triple {1013#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L290 TraceCheckUtils]: 5: Hoare triple {1013#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L272 TraceCheckUtils]: 4: Hoare triple {1013#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1013#true} {1013#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L290 TraceCheckUtils]: 2: Hoare triple {1013#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L290 TraceCheckUtils]: 1: Hoare triple {1013#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1013#true} is VALID [2022-04-27 21:05:39,023 INFO L272 TraceCheckUtils]: 0: Hoare triple {1013#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1013#true} is VALID [2022-04-27 21:05:39,024 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:39,024 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1386527120] provided 1 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:39,024 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-04-27 21:05:39,024 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [16, 15] total 31 [2022-04-27 21:05:39,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908224679] [2022-04-27 21:05:39,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:39,025 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 21:05:39,025 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:39,025 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,048 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:39,048 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-04-27 21:05:39,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:39,049 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-04-27 21:05:39,049 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=775, Unknown=0, NotChecked=0, Total=930 [2022-04-27 21:05:39,049 INFO L87 Difference]: Start difference. First operand 32 states and 37 transitions. Second operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,283 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:39,283 INFO L93 Difference]: Finished difference Result 49 states and 57 transitions. [2022-04-27 21:05:39,283 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2022-04-27 21:05:39,283 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 21:05:39,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:39,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 54 transitions. [2022-04-27 21:05:39,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 54 transitions. [2022-04-27 21:05:39,286 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 14 states and 54 transitions. [2022-04-27 21:05:39,328 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 54 edges. 54 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:39,329 INFO L225 Difference]: With dead ends: 49 [2022-04-27 21:05:39,329 INFO L226 Difference]: Without dead ends: 47 [2022-04-27 21:05:39,330 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 36 SyntacticMatches, 4 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 450 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=181, Invalid=1009, Unknown=0, NotChecked=0, Total=1190 [2022-04-27 21:05:39,330 INFO L413 NwaCegarLoop]: 22 mSDtfsCounter, 15 mSDsluCounter, 144 mSDsCounter, 0 mSdLazyCounter, 33 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 15 SdHoareTripleChecker+Valid, 166 SdHoareTripleChecker+Invalid, 85 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 33 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 50 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:39,331 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [15 Valid, 166 Invalid, 85 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 33 Invalid, 0 Unknown, 50 Unchecked, 0.0s Time] [2022-04-27 21:05:39,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2022-04-27 21:05:39,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 45. [2022-04-27 21:05:39,348 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:39,348 INFO L82 GeneralOperation]: Start isEquivalent. First operand 47 states. Second operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,348 INFO L74 IsIncluded]: Start isIncluded. First operand 47 states. Second operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,348 INFO L87 Difference]: Start difference. First operand 47 states. Second operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:39,349 INFO L93 Difference]: Finished difference Result 47 states and 55 transitions. [2022-04-27 21:05:39,349 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 55 transitions. [2022-04-27 21:05:39,350 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:39,350 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:39,350 INFO L74 IsIncluded]: Start isIncluded. First operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 47 states. [2022-04-27 21:05:39,350 INFO L87 Difference]: Start difference. First operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 47 states. [2022-04-27 21:05:39,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:39,351 INFO L93 Difference]: Finished difference Result 47 states and 55 transitions. [2022-04-27 21:05:39,351 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 55 transitions. [2022-04-27 21:05:39,351 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:39,351 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:39,351 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:39,351 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:39,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 37 states have (on average 1.2432432432432432) internal successors, (46), 38 states have internal predecessors, (46), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,353 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2022-04-27 21:05:39,353 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 53 transitions. Word has length 25 [2022-04-27 21:05:39,353 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:39,353 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 53 transitions. [2022-04-27 21:05:39,353 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,353 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 53 transitions. [2022-04-27 21:05:39,354 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-27 21:05:39,354 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:39,354 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:39,371 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Ended with exit code 0 [2022-04-27 21:05:39,566 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:39,567 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:39,567 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:39,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1038508128, now seen corresponding path program 1 times [2022-04-27 21:05:39,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:39,567 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681380778] [2022-04-27 21:05:39,567 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:39,568 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:39,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,649 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:39,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,654 INFO L290 TraceCheckUtils]: 0: Hoare triple {1436#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1428#true} is VALID [2022-04-27 21:05:39,654 INFO L290 TraceCheckUtils]: 1: Hoare triple {1428#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-27 21:05:39,654 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1428#true} {1428#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-27 21:05:39,654 INFO L272 TraceCheckUtils]: 0: Hoare triple {1428#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1436#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 1: Hoare triple {1436#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 2: Hoare triple {1428#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1428#true} {1428#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L272 TraceCheckUtils]: 4: Hoare triple {1428#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 5: Hoare triple {1428#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 6: Hoare triple {1428#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 7: Hoare triple {1428#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 8: Hoare triple {1428#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 9: Hoare triple {1428#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1428#true} is VALID [2022-04-27 21:05:39,655 INFO L290 TraceCheckUtils]: 10: Hoare triple {1428#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1428#true} is VALID [2022-04-27 21:05:39,656 INFO L290 TraceCheckUtils]: 11: Hoare triple {1428#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1433#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:39,656 INFO L290 TraceCheckUtils]: 12: Hoare triple {1433#(= (+ (- 1) main_~j~0) 0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1434#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 21:05:39,658 INFO L290 TraceCheckUtils]: 13: Hoare triple {1434#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1435#(and (= (+ (- 1) main_~j~0) 0) |main_#t~short10|)} is VALID [2022-04-27 21:05:39,662 INFO L290 TraceCheckUtils]: 14: Hoare triple {1435#(and (= (+ (- 1) main_~j~0) 0) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-27 21:05:39,662 INFO L290 TraceCheckUtils]: 15: Hoare triple {1429#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 16: Hoare triple {1429#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 17: Hoare triple {1429#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 18: Hoare triple {1429#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 19: Hoare triple {1429#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 20: Hoare triple {1429#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L272 TraceCheckUtils]: 21: Hoare triple {1429#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 22: Hoare triple {1429#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 23: Hoare triple {1429#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L290 TraceCheckUtils]: 24: Hoare triple {1429#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1429#false} is VALID [2022-04-27 21:05:39,663 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:39,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:39,664 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681380778] [2022-04-27 21:05:39,664 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681380778] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:39,664 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:05:39,664 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 21:05:39,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1437602666] [2022-04-27 21:05:39,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:39,664 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 21:05:39,664 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:39,664 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,678 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:39,678 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 21:05:39,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:39,678 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 21:05:39,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2022-04-27 21:05:39,679 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. Second operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,853 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:39,853 INFO L93 Difference]: Finished difference Result 78 states and 96 transitions. [2022-04-27 21:05:39,854 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 21:05:39,854 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 21:05:39,854 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:39,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 77 transitions. [2022-04-27 21:05:39,855 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,856 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 77 transitions. [2022-04-27 21:05:39,856 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 77 transitions. [2022-04-27 21:05:39,911 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 77 edges. 77 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:39,912 INFO L225 Difference]: With dead ends: 78 [2022-04-27 21:05:39,912 INFO L226 Difference]: Without dead ends: 59 [2022-04-27 21:05:39,912 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2022-04-27 21:05:39,913 INFO L413 NwaCegarLoop]: 24 mSDtfsCounter, 64 mSDsluCounter, 7 mSDsCounter, 0 mSdLazyCounter, 57 mSolverCounterSat, 10 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 65 SdHoareTripleChecker+Valid, 31 SdHoareTripleChecker+Invalid, 67 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 10 IncrementalHoareTripleChecker+Valid, 57 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:39,913 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [65 Valid, 31 Invalid, 67 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [10 Valid, 57 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:05:39,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2022-04-27 21:05:39,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 47. [2022-04-27 21:05:39,935 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:39,936 INFO L82 GeneralOperation]: Start isEquivalent. First operand 59 states. Second operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,936 INFO L74 IsIncluded]: Start isIncluded. First operand 59 states. Second operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,936 INFO L87 Difference]: Start difference. First operand 59 states. Second operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:39,937 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2022-04-27 21:05:39,937 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 72 transitions. [2022-04-27 21:05:39,937 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:39,937 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:39,938 INFO L74 IsIncluded]: Start isIncluded. First operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 59 states. [2022-04-27 21:05:39,938 INFO L87 Difference]: Start difference. First operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 59 states. [2022-04-27 21:05:39,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:39,939 INFO L93 Difference]: Finished difference Result 59 states and 72 transitions. [2022-04-27 21:05:39,939 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 72 transitions. [2022-04-27 21:05:39,939 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:39,939 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:39,939 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:39,939 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:39,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 47 states, 39 states have (on average 1.2307692307692308) internal successors, (48), 40 states have internal predecessors, (48), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:39,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 55 transitions. [2022-04-27 21:05:39,940 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 55 transitions. Word has length 25 [2022-04-27 21:05:39,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:39,941 INFO L495 AbstractCegarLoop]: Abstraction has 47 states and 55 transitions. [2022-04-27 21:05:39,941 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:39,941 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 55 transitions. [2022-04-27 21:05:39,941 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-04-27 21:05:39,941 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:39,941 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:39,941 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5 [2022-04-27 21:05:39,941 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:39,942 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:39,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1031689277, now seen corresponding path program 1 times [2022-04-27 21:05:39,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:39,942 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652162467] [2022-04-27 21:05:39,942 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:39,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:39,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,995 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:39,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,999 INFO L290 TraceCheckUtils]: 0: Hoare triple {1741#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-27 21:05:39,999 INFO L290 TraceCheckUtils]: 1: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:39,999 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:39,999 INFO L272 TraceCheckUtils]: 0: Hoare triple {1732#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1741#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:39,999 INFO L290 TraceCheckUtils]: 1: Hoare triple {1741#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 2: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L272 TraceCheckUtils]: 4: Hoare triple {1732#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 5: Hoare triple {1732#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 6: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 7: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 8: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 9: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-27 21:05:40,000 INFO L290 TraceCheckUtils]: 10: Hoare triple {1732#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,001 INFO L290 TraceCheckUtils]: 11: Hoare triple {1732#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1737#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:40,001 INFO L290 TraceCheckUtils]: 12: Hoare triple {1737#(= (+ (- 1) main_~j~0) 0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:40,002 INFO L290 TraceCheckUtils]: 13: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:40,002 INFO L290 TraceCheckUtils]: 14: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:40,002 INFO L290 TraceCheckUtils]: 15: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:40,003 INFO L290 TraceCheckUtils]: 16: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:40,004 INFO L290 TraceCheckUtils]: 17: Hoare triple {1738#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1739#(and (<= (+ main_~i~0 2) main_~j~0) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 21:05:40,004 INFO L290 TraceCheckUtils]: 18: Hoare triple {1739#(and (<= (+ main_~i~0 2) main_~j~0) (= (+ (- 1) main_~j~0) 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1740#(not |main_#t~short10|)} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 19: Hoare triple {1740#(not |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 20: Hoare triple {1733#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 21: Hoare triple {1733#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 22: Hoare triple {1733#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 23: Hoare triple {1733#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 24: Hoare triple {1733#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 25: Hoare triple {1733#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L272 TraceCheckUtils]: 26: Hoare triple {1733#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 27: Hoare triple {1733#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 28: Hoare triple {1733#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,005 INFO L290 TraceCheckUtils]: 29: Hoare triple {1733#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,006 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:40,006 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:40,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652162467] [2022-04-27 21:05:40,006 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652162467] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:40,006 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1263710033] [2022-04-27 21:05:40,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:40,006 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:40,006 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:40,007 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:40,008 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 21:05:40,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:40,052 INFO L263 TraceCheckSpWp]: Trace formula consists of 127 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 21:05:40,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:40,061 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:40,142 INFO L272 TraceCheckUtils]: 0: Hoare triple {1732#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,142 INFO L290 TraceCheckUtils]: 1: Hoare triple {1732#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-27 21:05:40,142 INFO L290 TraceCheckUtils]: 2: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,142 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,142 INFO L272 TraceCheckUtils]: 4: Hoare triple {1732#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,142 INFO L290 TraceCheckUtils]: 5: Hoare triple {1732#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1732#true} is VALID [2022-04-27 21:05:40,143 INFO L290 TraceCheckUtils]: 6: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-27 21:05:40,143 INFO L290 TraceCheckUtils]: 7: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-27 21:05:40,143 INFO L290 TraceCheckUtils]: 8: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-27 21:05:40,143 INFO L290 TraceCheckUtils]: 9: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-27 21:05:40,143 INFO L290 TraceCheckUtils]: 10: Hoare triple {1732#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,143 INFO L290 TraceCheckUtils]: 11: Hoare triple {1732#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1778#(<= main_~j~0 1)} is VALID [2022-04-27 21:05:40,144 INFO L290 TraceCheckUtils]: 12: Hoare triple {1778#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,144 INFO L290 TraceCheckUtils]: 13: Hoare triple {1782#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,144 INFO L290 TraceCheckUtils]: 14: Hoare triple {1782#(<= main_~i~0 0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,145 INFO L290 TraceCheckUtils]: 15: Hoare triple {1782#(<= main_~i~0 0)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,145 INFO L290 TraceCheckUtils]: 16: Hoare triple {1782#(<= main_~i~0 0)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,145 INFO L290 TraceCheckUtils]: 17: Hoare triple {1782#(<= main_~i~0 0)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1798#(<= (+ main_~i~0 1) 0)} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 18: Hoare triple {1798#(<= (+ main_~i~0 1) 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1740#(not |main_#t~short10|)} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 19: Hoare triple {1740#(not |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 20: Hoare triple {1733#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 21: Hoare triple {1733#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1733#false} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 22: Hoare triple {1733#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1733#false} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 23: Hoare triple {1733#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,146 INFO L290 TraceCheckUtils]: 24: Hoare triple {1733#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1733#false} is VALID [2022-04-27 21:05:40,147 INFO L290 TraceCheckUtils]: 25: Hoare triple {1733#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1733#false} is VALID [2022-04-27 21:05:40,147 INFO L272 TraceCheckUtils]: 26: Hoare triple {1733#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1733#false} is VALID [2022-04-27 21:05:40,147 INFO L290 TraceCheckUtils]: 27: Hoare triple {1733#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1733#false} is VALID [2022-04-27 21:05:40,147 INFO L290 TraceCheckUtils]: 28: Hoare triple {1733#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,147 INFO L290 TraceCheckUtils]: 29: Hoare triple {1733#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,147 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:40,147 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:40,218 INFO L290 TraceCheckUtils]: 29: Hoare triple {1733#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 28: Hoare triple {1733#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 27: Hoare triple {1733#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L272 TraceCheckUtils]: 26: Hoare triple {1733#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 25: Hoare triple {1733#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 24: Hoare triple {1733#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 23: Hoare triple {1733#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 22: Hoare triple {1733#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 21: Hoare triple {1733#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {1733#false} is VALID [2022-04-27 21:05:40,219 INFO L290 TraceCheckUtils]: 20: Hoare triple {1733#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-27 21:05:40,220 INFO L290 TraceCheckUtils]: 19: Hoare triple {1740#(not |main_#t~short10|)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1733#false} is VALID [2022-04-27 21:05:40,220 INFO L290 TraceCheckUtils]: 18: Hoare triple {1798#(<= (+ main_~i~0 1) 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1740#(not |main_#t~short10|)} is VALID [2022-04-27 21:05:40,220 INFO L290 TraceCheckUtils]: 17: Hoare triple {1782#(<= main_~i~0 0)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {1798#(<= (+ main_~i~0 1) 0)} is VALID [2022-04-27 21:05:40,221 INFO L290 TraceCheckUtils]: 16: Hoare triple {1782#(<= main_~i~0 0)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,221 INFO L290 TraceCheckUtils]: 15: Hoare triple {1782#(<= main_~i~0 0)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,221 INFO L290 TraceCheckUtils]: 14: Hoare triple {1782#(<= main_~i~0 0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,222 INFO L290 TraceCheckUtils]: 13: Hoare triple {1782#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,222 INFO L290 TraceCheckUtils]: 12: Hoare triple {1778#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1782#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 11: Hoare triple {1732#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1778#(<= main_~j~0 1)} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 10: Hoare triple {1732#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 9: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 8: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 7: Hoare triple {1732#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 6: Hoare triple {1732#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 5: Hoare triple {1732#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L272 TraceCheckUtils]: 4: Hoare triple {1732#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1732#true} {1732#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,223 INFO L290 TraceCheckUtils]: 2: Hoare triple {1732#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,224 INFO L290 TraceCheckUtils]: 1: Hoare triple {1732#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1732#true} is VALID [2022-04-27 21:05:40,224 INFO L272 TraceCheckUtils]: 0: Hoare triple {1732#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1732#true} is VALID [2022-04-27 21:05:40,224 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:40,224 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1263710033] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:40,224 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:40,224 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 21:05:40,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1914581830] [2022-04-27 21:05:40,224 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:40,224 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-27 21:05:40,225 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:40,225 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:40,247 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 38 edges. 38 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:40,248 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 21:05:40,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:40,248 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 21:05:40,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:40,248 INFO L87 Difference]: Start difference. First operand 47 states and 55 transitions. Second operand has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:40,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:40,653 INFO L93 Difference]: Finished difference Result 91 states and 113 transitions. [2022-04-27 21:05:40,653 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-27 21:05:40,653 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-27 21:05:40,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:40,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:40,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 93 transitions. [2022-04-27 21:05:40,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:40,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 93 transitions. [2022-04-27 21:05:40,657 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 93 transitions. [2022-04-27 21:05:40,732 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 93 edges. 93 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:40,733 INFO L225 Difference]: With dead ends: 91 [2022-04-27 21:05:40,733 INFO L226 Difference]: Without dead ends: 72 [2022-04-27 21:05:40,733 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 59 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 50 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=92, Invalid=214, Unknown=0, NotChecked=0, Total=306 [2022-04-27 21:05:40,734 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 69 mSDsluCounter, 22 mSDsCounter, 0 mSdLazyCounter, 188 mSolverCounterSat, 20 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 70 SdHoareTripleChecker+Valid, 52 SdHoareTripleChecker+Invalid, 208 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 20 IncrementalHoareTripleChecker+Valid, 188 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:40,734 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [70 Valid, 52 Invalid, 208 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [20 Valid, 188 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:05:40,734 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2022-04-27 21:05:40,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 53. [2022-04-27 21:05:40,759 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:40,759 INFO L82 GeneralOperation]: Start isEquivalent. First operand 72 states. Second operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:40,759 INFO L74 IsIncluded]: Start isIncluded. First operand 72 states. Second operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:40,759 INFO L87 Difference]: Start difference. First operand 72 states. Second operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:40,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:40,761 INFO L93 Difference]: Finished difference Result 72 states and 86 transitions. [2022-04-27 21:05:40,761 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 86 transitions. [2022-04-27 21:05:40,762 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:40,762 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:40,762 INFO L74 IsIncluded]: Start isIncluded. First operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 72 states. [2022-04-27 21:05:40,762 INFO L87 Difference]: Start difference. First operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 72 states. [2022-04-27 21:05:40,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:40,764 INFO L93 Difference]: Finished difference Result 72 states and 86 transitions. [2022-04-27 21:05:40,764 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 86 transitions. [2022-04-27 21:05:40,764 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:40,764 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:40,764 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:40,764 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:40,764 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 45 states have (on average 1.2222222222222223) internal successors, (55), 46 states have internal predecessors, (55), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:40,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 62 transitions. [2022-04-27 21:05:40,765 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 62 transitions. Word has length 30 [2022-04-27 21:05:40,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:40,765 INFO L495 AbstractCegarLoop]: Abstraction has 53 states and 62 transitions. [2022-04-27 21:05:40,765 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 3.3) internal successors, (33), 9 states have internal predecessors, (33), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:40,765 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 62 transitions. [2022-04-27 21:05:40,766 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2022-04-27 21:05:40,766 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:40,766 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:40,793 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:40,982 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:40,982 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:40,982 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:40,982 INFO L85 PathProgramCache]: Analyzing trace with hash -765262082, now seen corresponding path program 1 times [2022-04-27 21:05:40,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:40,982 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1292011245] [2022-04-27 21:05:40,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:40,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:41,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:41,339 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:41,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:41,343 INFO L290 TraceCheckUtils]: 0: Hoare triple {2302#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-27 21:05:41,344 INFO L290 TraceCheckUtils]: 1: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:41,344 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:41,344 INFO L272 TraceCheckUtils]: 0: Hoare triple {2281#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2302#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:41,344 INFO L290 TraceCheckUtils]: 1: Hoare triple {2302#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-27 21:05:41,344 INFO L290 TraceCheckUtils]: 2: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:41,345 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:41,345 INFO L272 TraceCheckUtils]: 4: Hoare triple {2281#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:41,345 INFO L290 TraceCheckUtils]: 5: Hoare triple {2281#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:41,346 INFO L290 TraceCheckUtils]: 6: Hoare triple {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:41,346 INFO L290 TraceCheckUtils]: 7: Hoare triple {2286#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:41,347 INFO L290 TraceCheckUtils]: 8: Hoare triple {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:41,347 INFO L290 TraceCheckUtils]: 9: Hoare triple {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2288#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:41,347 INFO L290 TraceCheckUtils]: 10: Hoare triple {2288#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2288#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:41,348 INFO L290 TraceCheckUtils]: 11: Hoare triple {2288#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:41,349 INFO L290 TraceCheckUtils]: 12: Hoare triple {2287#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2289#(and (= |main_~#v~0.offset| 0) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (and (<= (+ main_~i~0 1) 0) (= (+ (- 1) main_~j~0) 0))))} is VALID [2022-04-27 21:05:41,349 INFO L290 TraceCheckUtils]: 13: Hoare triple {2289#(and (= |main_~#v~0.offset| 0) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (and (<= (+ main_~i~0 1) 0) (= (+ (- 1) main_~j~0) 0))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2290#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:41,350 INFO L290 TraceCheckUtils]: 14: Hoare triple {2290#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2291#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:05:41,350 INFO L290 TraceCheckUtils]: 15: Hoare triple {2291#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2292#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:05:41,351 INFO L290 TraceCheckUtils]: 16: Hoare triple {2292#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {2293#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:05:41,352 INFO L290 TraceCheckUtils]: 17: Hoare triple {2293#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {2294#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:05:41,352 INFO L290 TraceCheckUtils]: 18: Hoare triple {2294#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2295#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} is VALID [2022-04-27 21:05:41,353 INFO L290 TraceCheckUtils]: 19: Hoare triple {2295#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:05:41,353 INFO L290 TraceCheckUtils]: 20: Hoare triple {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:05:41,355 INFO L290 TraceCheckUtils]: 21: Hoare triple {2296#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:41,355 INFO L290 TraceCheckUtils]: 22: Hoare triple {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:41,356 INFO L290 TraceCheckUtils]: 23: Hoare triple {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:41,356 INFO L290 TraceCheckUtils]: 24: Hoare triple {2297#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2298#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:05:41,361 INFO L290 TraceCheckUtils]: 25: Hoare triple {2298#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:05:41,362 INFO L272 TraceCheckUtils]: 26: Hoare triple {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2300#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:05:41,362 INFO L290 TraceCheckUtils]: 27: Hoare triple {2300#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2301#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:05:41,362 INFO L290 TraceCheckUtils]: 28: Hoare triple {2301#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-27 21:05:41,363 INFO L290 TraceCheckUtils]: 29: Hoare triple {2282#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-27 21:05:41,363 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:41,363 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:41,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1292011245] [2022-04-27 21:05:41,363 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1292011245] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:41,363 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1719717612] [2022-04-27 21:05:41,363 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:41,363 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:41,363 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:41,364 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:41,365 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 21:05:41,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:41,407 INFO L263 TraceCheckSpWp]: Trace formula consists of 124 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-27 21:05:41,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:41,420 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:41,679 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-27 21:05:41,679 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-27 21:05:42,422 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-27 21:05:42,422 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-27 21:05:43,656 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-27 21:05:43,656 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-27 21:05:43,834 INFO L272 TraceCheckUtils]: 0: Hoare triple {2281#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:43,835 INFO L290 TraceCheckUtils]: 1: Hoare triple {2281#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-27 21:05:43,835 INFO L290 TraceCheckUtils]: 2: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:43,835 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:43,835 INFO L272 TraceCheckUtils]: 4: Hoare triple {2281#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:43,835 INFO L290 TraceCheckUtils]: 5: Hoare triple {2281#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2281#true} is VALID [2022-04-27 21:05:43,836 INFO L290 TraceCheckUtils]: 6: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-27 21:05:43,836 INFO L290 TraceCheckUtils]: 7: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-27 21:05:43,836 INFO L290 TraceCheckUtils]: 8: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-27 21:05:43,836 INFO L290 TraceCheckUtils]: 9: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-27 21:05:43,836 INFO L290 TraceCheckUtils]: 10: Hoare triple {2281#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:43,836 INFO L290 TraceCheckUtils]: 11: Hoare triple {2281#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2339#(<= main_~j~0 1)} is VALID [2022-04-27 21:05:43,837 INFO L290 TraceCheckUtils]: 12: Hoare triple {2339#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2343#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:43,837 INFO L290 TraceCheckUtils]: 13: Hoare triple {2343#(<= main_~i~0 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2347#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:05:43,838 INFO L290 TraceCheckUtils]: 14: Hoare triple {2347#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2351#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:43,838 INFO L290 TraceCheckUtils]: 15: Hoare triple {2351#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2355#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:43,839 INFO L290 TraceCheckUtils]: 16: Hoare triple {2355#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= 0 main_~i~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {2359#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:43,840 INFO L290 TraceCheckUtils]: 17: Hoare triple {2359#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {2363#(exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-27 21:05:43,841 INFO L290 TraceCheckUtils]: 18: Hoare triple {2363#(exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2367#(and (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:05:43,843 INFO L290 TraceCheckUtils]: 19: Hoare triple {2367#(and (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 0) (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} is VALID [2022-04-27 21:05:43,844 INFO L290 TraceCheckUtils]: 20: Hoare triple {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} is VALID [2022-04-27 21:05:43,846 INFO L290 TraceCheckUtils]: 21: Hoare triple {2371#(and (< main_~i~0 0) (exists ((v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_16 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-27 21:05:43,846 INFO L290 TraceCheckUtils]: 22: Hoare triple {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-27 21:05:43,846 INFO L290 TraceCheckUtils]: 23: Hoare triple {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} is VALID [2022-04-27 21:05:43,847 INFO L290 TraceCheckUtils]: 24: Hoare triple {2378#(exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2388#(and (exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (= main_~k~0 1))} is VALID [2022-04-27 21:05:43,848 INFO L290 TraceCheckUtils]: 25: Hoare triple {2388#(and (exists ((main_~i~0 Int) (v_main_~i~0_16 Int)) (and (<= v_main_~i~0_16 (+ main_~i~0 1)) (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* v_main_~i~0_16 4)))) (<= 0 v_main_~i~0_16))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:05:43,848 INFO L272 TraceCheckUtils]: 26: Hoare triple {2299#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:43,848 INFO L290 TraceCheckUtils]: 27: Hoare triple {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2399#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:43,849 INFO L290 TraceCheckUtils]: 28: Hoare triple {2399#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-27 21:05:43,849 INFO L290 TraceCheckUtils]: 29: Hoare triple {2282#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-27 21:05:43,849 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:43,849 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:46,435 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 61 [2022-04-27 21:05:46,532 INFO L356 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-04-27 21:05:46,532 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 771 treesize of output 711 [2022-04-27 21:05:48,264 INFO L290 TraceCheckUtils]: 29: Hoare triple {2282#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-27 21:05:48,267 INFO L290 TraceCheckUtils]: 28: Hoare triple {2399#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {2282#false} is VALID [2022-04-27 21:05:48,268 INFO L290 TraceCheckUtils]: 27: Hoare triple {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2399#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:48,268 INFO L272 TraceCheckUtils]: 26: Hoare triple {2415#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2395#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:48,269 INFO L290 TraceCheckUtils]: 25: Hoare triple {2419#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2415#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:48,269 INFO L290 TraceCheckUtils]: 24: Hoare triple {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {2419#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:05:48,269 INFO L290 TraceCheckUtils]: 23: Hoare triple {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:48,269 INFO L290 TraceCheckUtils]: 22: Hoare triple {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:48,270 INFO L290 TraceCheckUtils]: 21: Hoare triple {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {2423#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:48,271 INFO L290 TraceCheckUtils]: 20: Hoare triple {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:05:48,271 INFO L290 TraceCheckUtils]: 19: Hoare triple {2440#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2433#(forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:05:48,272 INFO L290 TraceCheckUtils]: 18: Hoare triple {2444#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2440#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 21:05:48,273 INFO L290 TraceCheckUtils]: 17: Hoare triple {2448#(forall ((v_main_~i~0_17 Int)) (or (<= 0 v_main_~i~0_17) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {2444#(or (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_98) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:48,274 INFO L290 TraceCheckUtils]: 16: Hoare triple {2452#(forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {2448#(forall ((v_main_~i~0_17 Int)) (or (<= 0 v_main_~i~0_17) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (forall ((v_ArrVal_98 Int)) (or (not (<= v_ArrVal_98 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4)))))))} is VALID [2022-04-27 21:05:48,275 INFO L290 TraceCheckUtils]: 15: Hoare triple {2456#(or (not |main_#t~short10|) (forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0)))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2452#(forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0))))} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 14: Hoare triple {2460#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2456#(or (not |main_#t~short10|) (forall ((v_main_~i~0_17 Int) (v_ArrVal_98 Int) (v_ArrVal_95 Int)) (or (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_95) (+ |main_~#v~0.offset| (* v_main_~i~0_17 4) 4) v_ArrVal_98) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_17) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_95)) (not (<= main_~i~0 (+ v_main_~i~0_17 1))) (not (<= v_ArrVal_98 main_~key~0)))))} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 13: Hoare triple {2281#true} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2460#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 12: Hoare triple {2281#true} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 11: Hoare triple {2281#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 10: Hoare triple {2281#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 9: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 8: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 7: Hoare triple {2281#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 6: Hoare triple {2281#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2281#true} is VALID [2022-04-27 21:05:48,276 INFO L290 TraceCheckUtils]: 5: Hoare triple {2281#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2281#true} is VALID [2022-04-27 21:05:48,277 INFO L272 TraceCheckUtils]: 4: Hoare triple {2281#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:48,277 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2281#true} {2281#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:48,277 INFO L290 TraceCheckUtils]: 2: Hoare triple {2281#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:48,277 INFO L290 TraceCheckUtils]: 1: Hoare triple {2281#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2281#true} is VALID [2022-04-27 21:05:48,277 INFO L272 TraceCheckUtils]: 0: Hoare triple {2281#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2281#true} is VALID [2022-04-27 21:05:48,277 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:48,277 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1719717612] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:48,278 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:48,278 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 16, 14] total 42 [2022-04-27 21:05:48,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563416046] [2022-04-27 21:05:48,278 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:48,278 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-27 21:05:48,279 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:48,279 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:48,353 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 70 edges. 70 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:48,353 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-04-27 21:05:48,353 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:48,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-04-27 21:05:48,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=187, Invalid=1532, Unknown=3, NotChecked=0, Total=1722 [2022-04-27 21:05:48,355 INFO L87 Difference]: Start difference. First operand 53 states and 62 transitions. Second operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:56,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:56,461 INFO L93 Difference]: Finished difference Result 115 states and 140 transitions. [2022-04-27 21:05:56,461 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2022-04-27 21:05:56,461 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 30 [2022-04-27 21:05:56,461 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:56,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:56,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 116 transitions. [2022-04-27 21:05:56,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:56,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 116 transitions. [2022-04-27 21:05:56,476 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 44 states and 116 transitions. [2022-04-27 21:05:56,563 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 116 edges. 116 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:56,565 INFO L225 Difference]: With dead ends: 115 [2022-04-27 21:05:56,565 INFO L226 Difference]: Without dead ends: 113 [2022-04-27 21:05:56,567 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 43 SyntacticMatches, 3 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1743 ImplicationChecksByTransitivity, 9.8s TimeCoverageRelationStatistics Valid=591, Invalid=5106, Unknown=3, NotChecked=0, Total=5700 [2022-04-27 21:05:56,568 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 121 mSDsluCounter, 122 mSDsCounter, 0 mSdLazyCounter, 685 mSolverCounterSat, 84 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 122 SdHoareTripleChecker+Valid, 148 SdHoareTripleChecker+Invalid, 1082 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 84 IncrementalHoareTripleChecker+Valid, 685 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 313 IncrementalHoareTripleChecker+Unchecked, 0.6s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:56,575 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [122 Valid, 148 Invalid, 1082 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [84 Valid, 685 Invalid, 0 Unknown, 313 Unchecked, 0.6s Time] [2022-04-27 21:05:56,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2022-04-27 21:05:56,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 60. [2022-04-27 21:05:56,603 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:56,603 INFO L82 GeneralOperation]: Start isEquivalent. First operand 113 states. Second operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:56,610 INFO L74 IsIncluded]: Start isIncluded. First operand 113 states. Second operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:56,611 INFO L87 Difference]: Start difference. First operand 113 states. Second operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:56,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:56,625 INFO L93 Difference]: Finished difference Result 113 states and 138 transitions. [2022-04-27 21:05:56,625 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 138 transitions. [2022-04-27 21:05:56,625 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:56,625 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:56,625 INFO L74 IsIncluded]: Start isIncluded. First operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 113 states. [2022-04-27 21:05:56,625 INFO L87 Difference]: Start difference. First operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 113 states. [2022-04-27 21:05:56,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:56,628 INFO L93 Difference]: Finished difference Result 113 states and 138 transitions. [2022-04-27 21:05:56,628 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 138 transitions. [2022-04-27 21:05:56,628 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:56,628 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:56,628 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:56,628 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:56,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60 states, 52 states have (on average 1.2307692307692308) internal successors, (64), 53 states have internal predecessors, (64), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:56,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 71 transitions. [2022-04-27 21:05:56,629 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 71 transitions. Word has length 30 [2022-04-27 21:05:56,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:56,629 INFO L495 AbstractCegarLoop]: Abstraction has 60 states and 71 transitions. [2022-04-27 21:05:56,630 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 40 states have (on average 1.575) internal successors, (63), 39 states have internal predecessors, (63), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:56,630 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 71 transitions. [2022-04-27 21:05:56,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-27 21:05:56,630 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:56,630 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:56,647 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:56,830 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:56,830 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:56,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:56,831 INFO L85 PathProgramCache]: Analyzing trace with hash 1650775123, now seen corresponding path program 1 times [2022-04-27 21:05:56,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:56,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [269866878] [2022-04-27 21:05:56,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:56,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:56,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:56,888 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:56,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:56,892 INFO L290 TraceCheckUtils]: 0: Hoare triple {3051#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-27 21:05:56,892 INFO L290 TraceCheckUtils]: 1: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:56,892 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:56,892 INFO L272 TraceCheckUtils]: 0: Hoare triple {3042#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3051#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 1: Hoare triple {3051#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 2: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L272 TraceCheckUtils]: 4: Hoare triple {3042#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 5: Hoare triple {3042#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 6: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 7: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 8: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 9: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 10: Hoare triple {3042#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:56,893 INFO L290 TraceCheckUtils]: 11: Hoare triple {3042#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:56,894 INFO L290 TraceCheckUtils]: 12: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:56,894 INFO L290 TraceCheckUtils]: 13: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:56,895 INFO L290 TraceCheckUtils]: 14: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:56,895 INFO L290 TraceCheckUtils]: 15: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:56,895 INFO L290 TraceCheckUtils]: 16: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3047#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:56,895 INFO L290 TraceCheckUtils]: 17: Hoare triple {3047#(= (+ (- 1) main_~j~0) 0)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3048#(<= 2 main_~j~0)} is VALID [2022-04-27 21:05:56,896 INFO L290 TraceCheckUtils]: 18: Hoare triple {3048#(<= 2 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3049#(<= 1 main_~i~0)} is VALID [2022-04-27 21:05:56,896 INFO L290 TraceCheckUtils]: 19: Hoare triple {3049#(<= 1 main_~i~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3050#|main_#t~short10|} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 20: Hoare triple {3050#|main_#t~short10|} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 21: Hoare triple {3043#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 22: Hoare triple {3043#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 23: Hoare triple {3043#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 24: Hoare triple {3043#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 25: Hoare triple {3043#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 26: Hoare triple {3043#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L272 TraceCheckUtils]: 27: Hoare triple {3043#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 28: Hoare triple {3043#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 29: Hoare triple {3043#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L290 TraceCheckUtils]: 30: Hoare triple {3043#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:56,897 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:56,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:56,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [269866878] [2022-04-27 21:05:56,898 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [269866878] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:56,898 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1228959781] [2022-04-27 21:05:56,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:56,898 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:56,898 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:56,899 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:56,900 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 21:05:56,943 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:56,944 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 21:05:56,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:56,951 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:57,036 INFO L272 TraceCheckUtils]: 0: Hoare triple {3042#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 1: Hoare triple {3042#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 2: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L272 TraceCheckUtils]: 4: Hoare triple {3042#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 5: Hoare triple {3042#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 6: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 7: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 8: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 9: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-27 21:05:57,037 INFO L290 TraceCheckUtils]: 10: Hoare triple {3042#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,038 INFO L290 TraceCheckUtils]: 11: Hoare triple {3042#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,038 INFO L290 TraceCheckUtils]: 12: Hoare triple {3088#(<= 1 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,038 INFO L290 TraceCheckUtils]: 13: Hoare triple {3088#(<= 1 main_~j~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,038 INFO L290 TraceCheckUtils]: 14: Hoare triple {3088#(<= 1 main_~j~0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,039 INFO L290 TraceCheckUtils]: 15: Hoare triple {3088#(<= 1 main_~j~0)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,039 INFO L290 TraceCheckUtils]: 16: Hoare triple {3088#(<= 1 main_~j~0)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,040 INFO L290 TraceCheckUtils]: 17: Hoare triple {3088#(<= 1 main_~j~0)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3048#(<= 2 main_~j~0)} is VALID [2022-04-27 21:05:57,040 INFO L290 TraceCheckUtils]: 18: Hoare triple {3048#(<= 2 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3049#(<= 1 main_~i~0)} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 19: Hoare triple {3049#(<= 1 main_~i~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3050#|main_#t~short10|} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 20: Hoare triple {3050#|main_#t~short10|} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 21: Hoare triple {3043#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 22: Hoare triple {3043#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 23: Hoare triple {3043#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 24: Hoare triple {3043#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 25: Hoare triple {3043#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 26: Hoare triple {3043#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L272 TraceCheckUtils]: 27: Hoare triple {3043#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 28: Hoare triple {3043#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3043#false} is VALID [2022-04-27 21:05:57,041 INFO L290 TraceCheckUtils]: 29: Hoare triple {3043#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,042 INFO L290 TraceCheckUtils]: 30: Hoare triple {3043#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,042 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:57,042 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 30: Hoare triple {3043#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 29: Hoare triple {3043#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 28: Hoare triple {3043#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L272 TraceCheckUtils]: 27: Hoare triple {3043#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 26: Hoare triple {3043#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 25: Hoare triple {3043#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 24: Hoare triple {3043#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 23: Hoare triple {3043#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 22: Hoare triple {3043#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3043#false} is VALID [2022-04-27 21:05:57,147 INFO L290 TraceCheckUtils]: 21: Hoare triple {3043#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3043#false} is VALID [2022-04-27 21:05:57,148 INFO L290 TraceCheckUtils]: 20: Hoare triple {3050#|main_#t~short10|} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {3043#false} is VALID [2022-04-27 21:05:57,148 INFO L290 TraceCheckUtils]: 19: Hoare triple {3179#(<= 0 main_~i~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3050#|main_#t~short10|} is VALID [2022-04-27 21:05:57,149 INFO L290 TraceCheckUtils]: 18: Hoare triple {3088#(<= 1 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3179#(<= 0 main_~i~0)} is VALID [2022-04-27 21:05:57,149 INFO L290 TraceCheckUtils]: 17: Hoare triple {3186#(<= 0 main_~j~0)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3088#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:57,149 INFO L290 TraceCheckUtils]: 16: Hoare triple {3186#(<= 0 main_~j~0)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3186#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:57,150 INFO L290 TraceCheckUtils]: 15: Hoare triple {3186#(<= 0 main_~j~0)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3186#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:57,150 INFO L290 TraceCheckUtils]: 14: Hoare triple {3186#(<= 0 main_~j~0)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3186#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:57,150 INFO L290 TraceCheckUtils]: 13: Hoare triple {3186#(<= 0 main_~j~0)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3186#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 12: Hoare triple {3186#(<= 0 main_~j~0)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3186#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 11: Hoare triple {3042#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3186#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 10: Hoare triple {3042#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 9: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 8: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 7: Hoare triple {3042#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3042#true} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 6: Hoare triple {3042#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3042#true} is VALID [2022-04-27 21:05:57,151 INFO L290 TraceCheckUtils]: 5: Hoare triple {3042#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3042#true} is VALID [2022-04-27 21:05:57,151 INFO L272 TraceCheckUtils]: 4: Hoare triple {3042#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,152 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3042#true} {3042#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,152 INFO L290 TraceCheckUtils]: 2: Hoare triple {3042#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,152 INFO L290 TraceCheckUtils]: 1: Hoare triple {3042#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3042#true} is VALID [2022-04-27 21:05:57,152 INFO L272 TraceCheckUtils]: 0: Hoare triple {3042#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3042#true} is VALID [2022-04-27 21:05:57,152 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:57,152 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1228959781] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:57,152 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:57,152 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 21:05:57,152 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [94424375] [2022-04-27 21:05:57,152 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:57,153 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 21:05:57,153 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:57,153 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,186 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:57,186 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 21:05:57,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:57,186 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 21:05:57,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:57,187 INFO L87 Difference]: Start difference. First operand 60 states and 71 transitions. Second operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:57,708 INFO L93 Difference]: Finished difference Result 132 states and 162 transitions. [2022-04-27 21:05:57,708 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 21:05:57,709 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 21:05:57,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:57,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 110 transitions. [2022-04-27 21:05:57,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 110 transitions. [2022-04-27 21:05:57,712 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 110 transitions. [2022-04-27 21:05:57,795 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 110 edges. 110 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:57,796 INFO L225 Difference]: With dead ends: 132 [2022-04-27 21:05:57,796 INFO L226 Difference]: Without dead ends: 98 [2022-04-27 21:05:57,796 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=260, Unknown=0, NotChecked=0, Total=380 [2022-04-27 21:05:57,797 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 141 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 219 mSolverCounterSat, 53 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 141 SdHoareTripleChecker+Valid, 55 SdHoareTripleChecker+Invalid, 272 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 53 IncrementalHoareTripleChecker+Valid, 219 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:57,798 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [141 Valid, 55 Invalid, 272 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [53 Valid, 219 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 21:05:57,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2022-04-27 21:05:57,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 63. [2022-04-27 21:05:57,874 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:57,874 INFO L82 GeneralOperation]: Start isEquivalent. First operand 98 states. Second operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,874 INFO L74 IsIncluded]: Start isIncluded. First operand 98 states. Second operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,874 INFO L87 Difference]: Start difference. First operand 98 states. Second operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:57,877 INFO L93 Difference]: Finished difference Result 98 states and 118 transitions. [2022-04-27 21:05:57,877 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 118 transitions. [2022-04-27 21:05:57,877 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:57,878 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:57,878 INFO L74 IsIncluded]: Start isIncluded. First operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 98 states. [2022-04-27 21:05:57,883 INFO L87 Difference]: Start difference. First operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 98 states. [2022-04-27 21:05:57,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:57,886 INFO L93 Difference]: Finished difference Result 98 states and 118 transitions. [2022-04-27 21:05:57,886 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 118 transitions. [2022-04-27 21:05:57,886 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:57,886 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:57,886 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:57,886 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:57,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 63 states, 55 states have (on average 1.2181818181818183) internal successors, (67), 56 states have internal predecessors, (67), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 74 transitions. [2022-04-27 21:05:57,889 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 74 transitions. Word has length 31 [2022-04-27 21:05:57,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:57,889 INFO L495 AbstractCegarLoop]: Abstraction has 63 states and 74 transitions. [2022-04-27 21:05:57,889 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,889 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 74 transitions. [2022-04-27 21:05:57,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-27 21:05:57,889 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:57,889 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:57,906 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Ended with exit code 0 [2022-04-27 21:05:58,105 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:58,105 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:58,106 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:58,106 INFO L85 PathProgramCache]: Analyzing trace with hash -547485170, now seen corresponding path program 1 times [2022-04-27 21:05:58,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:58,106 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324380997] [2022-04-27 21:05:58,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:58,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:58,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,305 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:58,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,309 INFO L290 TraceCheckUtils]: 0: Hoare triple {3735#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-27 21:05:58,309 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,309 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,310 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-04-27 21:05:58,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,315 INFO L290 TraceCheckUtils]: 0: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-27 21:05:58,315 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,315 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,316 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:58,316 INFO L272 TraceCheckUtils]: 0: Hoare triple {3720#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3735#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:58,317 INFO L290 TraceCheckUtils]: 1: Hoare triple {3735#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-27 21:05:58,317 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,317 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,317 INFO L272 TraceCheckUtils]: 4: Hoare triple {3720#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,317 INFO L290 TraceCheckUtils]: 5: Hoare triple {3720#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3725#(= main_~j~0 0)} is VALID [2022-04-27 21:05:58,317 INFO L290 TraceCheckUtils]: 6: Hoare triple {3725#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3725#(= main_~j~0 0)} is VALID [2022-04-27 21:05:58,318 INFO L290 TraceCheckUtils]: 7: Hoare triple {3725#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:58,318 INFO L290 TraceCheckUtils]: 8: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:58,319 INFO L290 TraceCheckUtils]: 9: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:05:58,319 INFO L290 TraceCheckUtils]: 10: Hoare triple {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,320 INFO L290 TraceCheckUtils]: 11: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,320 INFO L290 TraceCheckUtils]: 12: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,320 INFO L290 TraceCheckUtils]: 13: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,321 INFO L290 TraceCheckUtils]: 14: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,321 INFO L290 TraceCheckUtils]: 15: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,321 INFO L290 TraceCheckUtils]: 16: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,321 INFO L290 TraceCheckUtils]: 17: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,322 INFO L290 TraceCheckUtils]: 18: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:58,322 INFO L290 TraceCheckUtils]: 19: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:58,323 INFO L290 TraceCheckUtils]: 20: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:58,323 INFO L272 TraceCheckUtils]: 21: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3720#true} is VALID [2022-04-27 21:05:58,323 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-27 21:05:58,323 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,323 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:58,323 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3720#true} {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:58,324 INFO L290 TraceCheckUtils]: 26: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:58,324 INFO L290 TraceCheckUtils]: 27: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:05:58,325 INFO L290 TraceCheckUtils]: 28: Hoare triple {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3721#false} is VALID [2022-04-27 21:05:58,325 INFO L272 TraceCheckUtils]: 29: Hoare triple {3721#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3721#false} is VALID [2022-04-27 21:05:58,325 INFO L290 TraceCheckUtils]: 30: Hoare triple {3721#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3721#false} is VALID [2022-04-27 21:05:58,325 INFO L290 TraceCheckUtils]: 31: Hoare triple {3721#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-27 21:05:58,325 INFO L290 TraceCheckUtils]: 32: Hoare triple {3721#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-27 21:05:58,325 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:05:58,326 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:58,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1324380997] [2022-04-27 21:05:58,326 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1324380997] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:58,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [689730785] [2022-04-27 21:05:58,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:58,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:58,326 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:58,340 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:58,439 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 21:05:58,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,481 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 21:05:58,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,489 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:59,496 INFO L272 TraceCheckUtils]: 0: Hoare triple {3720#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:59,496 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-27 21:05:59,496 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:59,496 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:59,496 INFO L272 TraceCheckUtils]: 4: Hoare triple {3720#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:59,497 INFO L290 TraceCheckUtils]: 5: Hoare triple {3720#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3725#(= main_~j~0 0)} is VALID [2022-04-27 21:05:59,497 INFO L290 TraceCheckUtils]: 6: Hoare triple {3725#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3725#(= main_~j~0 0)} is VALID [2022-04-27 21:05:59,497 INFO L290 TraceCheckUtils]: 7: Hoare triple {3725#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:59,498 INFO L290 TraceCheckUtils]: 8: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:59,498 INFO L290 TraceCheckUtils]: 9: Hoare triple {3726#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:05:59,499 INFO L290 TraceCheckUtils]: 10: Hoare triple {3727#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,499 INFO L290 TraceCheckUtils]: 11: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,500 INFO L290 TraceCheckUtils]: 12: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,500 INFO L290 TraceCheckUtils]: 13: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,500 INFO L290 TraceCheckUtils]: 14: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,501 INFO L290 TraceCheckUtils]: 15: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,501 INFO L290 TraceCheckUtils]: 16: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,501 INFO L290 TraceCheckUtils]: 17: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,502 INFO L290 TraceCheckUtils]: 18: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:05:59,502 INFO L290 TraceCheckUtils]: 19: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:59,502 INFO L290 TraceCheckUtils]: 20: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:59,503 INFO L272 TraceCheckUtils]: 21: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3720#true} is VALID [2022-04-27 21:05:59,503 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-27 21:05:59,503 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:59,503 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:05:59,503 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3720#true} {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:59,504 INFO L290 TraceCheckUtils]: 26: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:59,504 INFO L290 TraceCheckUtils]: 27: Hoare triple {3729#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3820#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= main_~k~0 2))} is VALID [2022-04-27 21:05:59,505 INFO L290 TraceCheckUtils]: 28: Hoare triple {3820#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= main_~k~0 2))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3721#false} is VALID [2022-04-27 21:05:59,505 INFO L272 TraceCheckUtils]: 29: Hoare triple {3721#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3721#false} is VALID [2022-04-27 21:05:59,505 INFO L290 TraceCheckUtils]: 30: Hoare triple {3721#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3721#false} is VALID [2022-04-27 21:05:59,505 INFO L290 TraceCheckUtils]: 31: Hoare triple {3721#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-27 21:05:59,505 INFO L290 TraceCheckUtils]: 32: Hoare triple {3721#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-27 21:05:59,505 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:05:59,505 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:06:04,152 INFO L290 TraceCheckUtils]: 32: Hoare triple {3721#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-27 21:06:04,153 INFO L290 TraceCheckUtils]: 31: Hoare triple {3721#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {3721#false} is VALID [2022-04-27 21:06:04,153 INFO L290 TraceCheckUtils]: 30: Hoare triple {3721#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3721#false} is VALID [2022-04-27 21:06:04,153 INFO L272 TraceCheckUtils]: 29: Hoare triple {3721#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3721#false} is VALID [2022-04-27 21:06:04,154 INFO L290 TraceCheckUtils]: 28: Hoare triple {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3721#false} is VALID [2022-04-27 21:06:04,154 INFO L290 TraceCheckUtils]: 27: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3734#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:06:04,155 INFO L290 TraceCheckUtils]: 26: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:04,155 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3720#true} {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:04,155 INFO L290 TraceCheckUtils]: 24: Hoare triple {3720#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:06:04,156 INFO L290 TraceCheckUtils]: 23: Hoare triple {3720#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:06:04,156 INFO L290 TraceCheckUtils]: 22: Hoare triple {3720#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3720#true} is VALID [2022-04-27 21:06:04,156 INFO L272 TraceCheckUtils]: 21: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3720#true} is VALID [2022-04-27 21:06:04,156 INFO L290 TraceCheckUtils]: 20: Hoare triple {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:04,157 INFO L290 TraceCheckUtils]: 19: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {3851#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:04,157 INFO L290 TraceCheckUtils]: 18: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,157 INFO L290 TraceCheckUtils]: 17: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,158 INFO L290 TraceCheckUtils]: 16: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,158 INFO L290 TraceCheckUtils]: 15: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,158 INFO L290 TraceCheckUtils]: 14: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,159 INFO L290 TraceCheckUtils]: 13: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,159 INFO L290 TraceCheckUtils]: 12: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,159 INFO L290 TraceCheckUtils]: 11: Hoare triple {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,160 INFO L290 TraceCheckUtils]: 10: Hoare triple {3903#(<= 0 (+ 1 (div (+ (- 4294967294) (* (- 1) (mod main_~j~0 4294967296))) 4294967296)))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3728#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:04,161 INFO L290 TraceCheckUtils]: 9: Hoare triple {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3903#(<= 0 (+ 1 (div (+ (- 4294967294) (* (- 1) (mod main_~j~0 4294967296))) 4294967296)))} is VALID [2022-04-27 21:06:04,161 INFO L290 TraceCheckUtils]: 8: Hoare triple {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:04,162 INFO L290 TraceCheckUtils]: 7: Hoare triple {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3907#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:04,162 INFO L290 TraceCheckUtils]: 6: Hoare triple {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:04,163 INFO L290 TraceCheckUtils]: 5: Hoare triple {3720#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3914#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:04,163 INFO L272 TraceCheckUtils]: 4: Hoare triple {3720#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:06:04,163 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3720#true} {3720#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:06:04,163 INFO L290 TraceCheckUtils]: 2: Hoare triple {3720#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:06:04,163 INFO L290 TraceCheckUtils]: 1: Hoare triple {3720#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3720#true} is VALID [2022-04-27 21:06:04,163 INFO L272 TraceCheckUtils]: 0: Hoare triple {3720#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3720#true} is VALID [2022-04-27 21:06:04,163 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:04,163 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [689730785] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:06:04,163 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:06:04,163 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 14 [2022-04-27 21:06:04,164 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [944883148] [2022-04-27 21:06:04,164 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:06:04,164 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-27 21:06:04,164 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:06:04,164 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:04,208 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:04,209 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 21:06:04,209 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:06:04,209 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 21:06:04,209 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2022-04-27 21:06:04,209 INFO L87 Difference]: Start difference. First operand 63 states and 74 transitions. Second operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:05,089 INFO L93 Difference]: Finished difference Result 160 states and 193 transitions. [2022-04-27 21:06:05,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 21:06:05,089 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-27 21:06:05,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:06:05,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 105 transitions. [2022-04-27 21:06:05,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 105 transitions. [2022-04-27 21:06:05,091 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 105 transitions. [2022-04-27 21:06:05,175 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 105 edges. 105 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:05,176 INFO L225 Difference]: With dead ends: 160 [2022-04-27 21:06:05,176 INFO L226 Difference]: Without dead ends: 95 [2022-04-27 21:06:05,176 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 60 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=90, Invalid=330, Unknown=0, NotChecked=0, Total=420 [2022-04-27 21:06:05,177 INFO L413 NwaCegarLoop]: 32 mSDtfsCounter, 126 mSDsluCounter, 42 mSDsCounter, 0 mSdLazyCounter, 314 mSolverCounterSat, 26 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 127 SdHoareTripleChecker+Valid, 74 SdHoareTripleChecker+Invalid, 340 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 26 IncrementalHoareTripleChecker+Valid, 314 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 21:06:05,177 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [127 Valid, 74 Invalid, 340 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [26 Valid, 314 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 21:06:05,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 95 states. [2022-04-27 21:06:05,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 72. [2022-04-27 21:06:05,219 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:06:05,219 INFO L82 GeneralOperation]: Start isEquivalent. First operand 95 states. Second operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,219 INFO L74 IsIncluded]: Start isIncluded. First operand 95 states. Second operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,219 INFO L87 Difference]: Start difference. First operand 95 states. Second operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:05,227 INFO L93 Difference]: Finished difference Result 95 states and 112 transitions. [2022-04-27 21:06:05,227 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 112 transitions. [2022-04-27 21:06:05,227 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:05,227 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:05,228 INFO L74 IsIncluded]: Start isIncluded. First operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 95 states. [2022-04-27 21:06:05,228 INFO L87 Difference]: Start difference. First operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 95 states. [2022-04-27 21:06:05,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:05,232 INFO L93 Difference]: Finished difference Result 95 states and 112 transitions. [2022-04-27 21:06:05,232 INFO L276 IsEmpty]: Start isEmpty. Operand 95 states and 112 transitions. [2022-04-27 21:06:05,232 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:05,232 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:05,233 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:06:05,233 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:06:05,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 72 states, 64 states have (on average 1.1875) internal successors, (76), 65 states have internal predecessors, (76), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 83 transitions. [2022-04-27 21:06:05,234 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 83 transitions. Word has length 33 [2022-04-27 21:06:05,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:06:05,235 INFO L495 AbstractCegarLoop]: Abstraction has 72 states and 83 transitions. [2022-04-27 21:06:05,235 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:05,235 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 83 transitions. [2022-04-27 21:06:05,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-04-27 21:06:05,236 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:06:05,237 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:06:05,255 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-27 21:06:05,448 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:05,449 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:06:05,449 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:06:05,449 INFO L85 PathProgramCache]: Analyzing trace with hash 1553999756, now seen corresponding path program 2 times [2022-04-27 21:06:05,449 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:06:05,449 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649841187] [2022-04-27 21:06:05,449 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:06:05,449 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:06:05,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:05,824 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:06:05,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:05,827 INFO L290 TraceCheckUtils]: 0: Hoare triple {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-27 21:06:05,827 INFO L290 TraceCheckUtils]: 1: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:05,827 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:05,828 INFO L272 TraceCheckUtils]: 0: Hoare triple {4451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:06:05,828 INFO L290 TraceCheckUtils]: 1: Hoare triple {4469#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-27 21:06:05,828 INFO L290 TraceCheckUtils]: 2: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:05,828 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:05,828 INFO L272 TraceCheckUtils]: 4: Hoare triple {4451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:05,828 INFO L290 TraceCheckUtils]: 5: Hoare triple {4451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:05,829 INFO L290 TraceCheckUtils]: 6: Hoare triple {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:05,829 INFO L290 TraceCheckUtils]: 7: Hoare triple {4456#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,830 INFO L290 TraceCheckUtils]: 8: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,830 INFO L290 TraceCheckUtils]: 9: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,830 INFO L290 TraceCheckUtils]: 10: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,830 INFO L290 TraceCheckUtils]: 11: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,831 INFO L290 TraceCheckUtils]: 12: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,831 INFO L290 TraceCheckUtils]: 13: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,831 INFO L290 TraceCheckUtils]: 14: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,832 INFO L290 TraceCheckUtils]: 15: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,832 INFO L290 TraceCheckUtils]: 16: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,833 INFO L290 TraceCheckUtils]: 17: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,833 INFO L290 TraceCheckUtils]: 18: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,834 INFO L290 TraceCheckUtils]: 19: Hoare triple {4457#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4459#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} is VALID [2022-04-27 21:06:05,834 INFO L290 TraceCheckUtils]: 20: Hoare triple {4459#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,834 INFO L290 TraceCheckUtils]: 21: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,835 INFO L290 TraceCheckUtils]: 22: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,835 INFO L290 TraceCheckUtils]: 23: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,836 INFO L290 TraceCheckUtils]: 24: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,836 INFO L290 TraceCheckUtils]: 25: Hoare triple {4460#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,836 INFO L290 TraceCheckUtils]: 26: Hoare triple {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,837 INFO L290 TraceCheckUtils]: 27: Hoare triple {4461#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:06:05,837 INFO L290 TraceCheckUtils]: 28: Hoare triple {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:06:05,840 INFO L290 TraceCheckUtils]: 29: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:05,841 INFO L290 TraceCheckUtils]: 30: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:05,841 INFO L290 TraceCheckUtils]: 31: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:05,841 INFO L290 TraceCheckUtils]: 32: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:06:05,842 INFO L290 TraceCheckUtils]: 33: Hoare triple {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:05,842 INFO L272 TraceCheckUtils]: 34: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4467#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:06:05,843 INFO L290 TraceCheckUtils]: 35: Hoare triple {4467#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4468#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:06:05,843 INFO L290 TraceCheckUtils]: 36: Hoare triple {4468#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-27 21:06:05,843 INFO L290 TraceCheckUtils]: 37: Hoare triple {4452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-27 21:06:05,843 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:05,843 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:06:05,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [649841187] [2022-04-27 21:06:05,844 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [649841187] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:06:05,844 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2135168185] [2022-04-27 21:06:05,844 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:06:05,844 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:05,844 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:06:05,847 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:06:05,872 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 21:06:05,919 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:06:05,920 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:06:05,920 INFO L263 TraceCheckSpWp]: Trace formula consists of 153 conjuncts, 21 conjunts are in the unsatisfiable core [2022-04-27 21:06:05,933 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:05,934 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:06:06,348 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:06:06,350 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 21:06:06,456 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:06:06,456 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 21:06:06,534 INFO L272 TraceCheckUtils]: 0: Hoare triple {4451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:06,534 INFO L290 TraceCheckUtils]: 1: Hoare triple {4451#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-27 21:06:06,534 INFO L290 TraceCheckUtils]: 2: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:06,534 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:06,534 INFO L272 TraceCheckUtils]: 4: Hoare triple {4451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:06,535 INFO L290 TraceCheckUtils]: 5: Hoare triple {4451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,535 INFO L290 TraceCheckUtils]: 6: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,535 INFO L290 TraceCheckUtils]: 7: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,536 INFO L290 TraceCheckUtils]: 8: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,536 INFO L290 TraceCheckUtils]: 9: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,536 INFO L290 TraceCheckUtils]: 10: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,536 INFO L290 TraceCheckUtils]: 11: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,537 INFO L290 TraceCheckUtils]: 12: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4458#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:06,537 INFO L290 TraceCheckUtils]: 13: Hoare triple {4458#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:06,537 INFO L290 TraceCheckUtils]: 14: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:06,538 INFO L290 TraceCheckUtils]: 15: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:06,538 INFO L290 TraceCheckUtils]: 16: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:06,539 INFO L290 TraceCheckUtils]: 17: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:06,539 INFO L290 TraceCheckUtils]: 18: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:06,539 INFO L290 TraceCheckUtils]: 19: Hoare triple {4512#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4531#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} is VALID [2022-04-27 21:06:06,540 INFO L290 TraceCheckUtils]: 20: Hoare triple {4531#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:06,540 INFO L290 TraceCheckUtils]: 21: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:06,547 INFO L290 TraceCheckUtils]: 22: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:06,552 INFO L290 TraceCheckUtils]: 23: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:06,553 INFO L290 TraceCheckUtils]: 24: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:06,553 INFO L290 TraceCheckUtils]: 25: Hoare triple {4535#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4551#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-27 21:06:06,553 INFO L290 TraceCheckUtils]: 26: Hoare triple {4551#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4555#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:06:06,554 INFO L290 TraceCheckUtils]: 27: Hoare triple {4555#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:06:06,554 INFO L290 TraceCheckUtils]: 28: Hoare triple {4462#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:06:06,555 INFO L290 TraceCheckUtils]: 29: Hoare triple {4463#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:06,556 INFO L290 TraceCheckUtils]: 30: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:06,556 INFO L290 TraceCheckUtils]: 31: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:06,556 INFO L290 TraceCheckUtils]: 32: Hoare triple {4464#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:06:06,557 INFO L290 TraceCheckUtils]: 33: Hoare triple {4465#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:06,557 INFO L272 TraceCheckUtils]: 34: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:06:06,558 INFO L290 TraceCheckUtils]: 35: Hoare triple {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4584#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:06:06,558 INFO L290 TraceCheckUtils]: 36: Hoare triple {4584#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-27 21:06:06,558 INFO L290 TraceCheckUtils]: 37: Hoare triple {4452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-27 21:06:06,558 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:06:06,558 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:06:06,886 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-27 21:06:06,913 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-27 21:06:06,914 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-27 21:06:07,182 INFO L290 TraceCheckUtils]: 37: Hoare triple {4452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-27 21:06:07,183 INFO L290 TraceCheckUtils]: 36: Hoare triple {4584#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {4452#false} is VALID [2022-04-27 21:06:07,187 INFO L290 TraceCheckUtils]: 35: Hoare triple {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4584#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:06:07,188 INFO L272 TraceCheckUtils]: 34: Hoare triple {4466#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4580#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:06:07,188 INFO L290 TraceCheckUtils]: 33: Hoare triple {4603#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4466#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:07,189 INFO L290 TraceCheckUtils]: 32: Hoare triple {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {4603#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:06:07,189 INFO L290 TraceCheckUtils]: 31: Hoare triple {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:06:07,189 INFO L290 TraceCheckUtils]: 30: Hoare triple {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:06:07,190 INFO L290 TraceCheckUtils]: 29: Hoare triple {4617#(forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4607#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:06:07,191 INFO L290 TraceCheckUtils]: 28: Hoare triple {4621#(or (forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4617#(forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:06:07,192 INFO L290 TraceCheckUtils]: 27: Hoare triple {4625#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4621#(or (forall ((v_ArrVal_164 Int)) (or (not (<= main_~key~0 v_ArrVal_164)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_164) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 21:06:07,192 INFO L290 TraceCheckUtils]: 26: Hoare triple {4629#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4625#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:07,192 INFO L290 TraceCheckUtils]: 25: Hoare triple {4633#(<= main_~i~0 1)} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {4629#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:07,194 INFO L290 TraceCheckUtils]: 24: Hoare triple {4633#(<= main_~i~0 1)} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {4633#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:07,194 INFO L290 TraceCheckUtils]: 23: Hoare triple {4633#(<= main_~i~0 1)} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4633#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:07,194 INFO L290 TraceCheckUtils]: 22: Hoare triple {4633#(<= main_~i~0 1)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4633#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:07,194 INFO L290 TraceCheckUtils]: 21: Hoare triple {4633#(<= main_~i~0 1)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4633#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:07,195 INFO L290 TraceCheckUtils]: 20: Hoare triple {4649#(<= main_~j~0 2)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4633#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:07,195 INFO L290 TraceCheckUtils]: 19: Hoare triple {4653#(<= main_~j~0 1)} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4649#(<= main_~j~0 2)} is VALID [2022-04-27 21:06:07,195 INFO L290 TraceCheckUtils]: 18: Hoare triple {4653#(<= main_~j~0 1)} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {4653#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:07,196 INFO L290 TraceCheckUtils]: 17: Hoare triple {4653#(<= main_~j~0 1)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4653#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:07,196 INFO L290 TraceCheckUtils]: 16: Hoare triple {4653#(<= main_~j~0 1)} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4653#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:07,196 INFO L290 TraceCheckUtils]: 15: Hoare triple {4653#(<= main_~j~0 1)} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4653#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:07,196 INFO L290 TraceCheckUtils]: 14: Hoare triple {4653#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4653#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 13: Hoare triple {4451#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4653#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 12: Hoare triple {4451#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 11: Hoare triple {4451#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 10: Hoare triple {4451#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 9: Hoare triple {4451#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 8: Hoare triple {4451#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 7: Hoare triple {4451#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 6: Hoare triple {4451#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 5: Hoare triple {4451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L272 TraceCheckUtils]: 4: Hoare triple {4451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4451#true} {4451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 2: Hoare triple {4451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L290 TraceCheckUtils]: 1: Hoare triple {4451#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4451#true} is VALID [2022-04-27 21:06:07,197 INFO L272 TraceCheckUtils]: 0: Hoare triple {4451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4451#true} is VALID [2022-04-27 21:06:07,198 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:06:07,198 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2135168185] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:06:07,198 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:06:07,198 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 14] total 32 [2022-04-27 21:06:07,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48208643] [2022-04-27 21:06:07,198 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:06:07,199 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-27 21:06:07,200 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:06:07,200 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:07,249 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:07,249 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-04-27 21:06:07,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:06:07,250 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-04-27 21:06:07,250 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=862, Unknown=0, NotChecked=0, Total=992 [2022-04-27 21:06:07,250 INFO L87 Difference]: Start difference. First operand 72 states and 83 transitions. Second operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:09,839 INFO L93 Difference]: Finished difference Result 211 states and 257 transitions. [2022-04-27 21:06:09,839 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2022-04-27 21:06:09,840 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-27 21:06:09,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:06:09,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 195 transitions. [2022-04-27 21:06:09,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 195 transitions. [2022-04-27 21:06:09,844 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 50 states and 195 transitions. [2022-04-27 21:06:09,968 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 195 edges. 195 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:09,970 INFO L225 Difference]: With dead ends: 211 [2022-04-27 21:06:09,970 INFO L226 Difference]: Without dead ends: 174 [2022-04-27 21:06:09,972 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 65 SyntacticMatches, 7 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1703 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1045, Invalid=5117, Unknown=0, NotChecked=0, Total=6162 [2022-04-27 21:06:09,972 INFO L413 NwaCegarLoop]: 22 mSDtfsCounter, 317 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 823 mSolverCounterSat, 290 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.8s Time, 0 mProtectedPredicate, 0 mProtectedAction, 317 SdHoareTripleChecker+Valid, 79 SdHoareTripleChecker+Invalid, 1224 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 290 IncrementalHoareTripleChecker+Valid, 823 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 111 IncrementalHoareTripleChecker+Unchecked, 0.8s IncrementalHoareTripleChecker+Time [2022-04-27 21:06:09,972 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [317 Valid, 79 Invalid, 1224 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [290 Valid, 823 Invalid, 0 Unknown, 111 Unchecked, 0.8s Time] [2022-04-27 21:06:09,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2022-04-27 21:06:10,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 84. [2022-04-27 21:06:10,069 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:06:10,069 INFO L82 GeneralOperation]: Start isEquivalent. First operand 174 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:10,070 INFO L74 IsIncluded]: Start isIncluded. First operand 174 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:10,070 INFO L87 Difference]: Start difference. First operand 174 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:10,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:10,074 INFO L93 Difference]: Finished difference Result 174 states and 206 transitions. [2022-04-27 21:06:10,074 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 206 transitions. [2022-04-27 21:06:10,074 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:10,074 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:10,074 INFO L74 IsIncluded]: Start isIncluded. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 174 states. [2022-04-27 21:06:10,075 INFO L87 Difference]: Start difference. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 174 states. [2022-04-27 21:06:10,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:10,077 INFO L93 Difference]: Finished difference Result 174 states and 206 transitions. [2022-04-27 21:06:10,078 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 206 transitions. [2022-04-27 21:06:10,079 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:10,079 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:10,079 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:06:10,079 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:06:10,080 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:10,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 98 transitions. [2022-04-27 21:06:10,084 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 98 transitions. Word has length 38 [2022-04-27 21:06:10,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:06:10,084 INFO L495 AbstractCegarLoop]: Abstraction has 84 states and 98 transitions. [2022-04-27 21:06:10,084 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 31 states have (on average 2.5161290322580645) internal successors, (78), 29 states have internal predecessors, (78), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:10,085 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 98 transitions. [2022-04-27 21:06:10,085 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2022-04-27 21:06:10,085 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:06:10,085 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:06:10,104 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2022-04-27 21:06:10,299 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable10 [2022-04-27 21:06:10,299 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:06:10,300 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:06:10,300 INFO L85 PathProgramCache]: Analyzing trace with hash -1626243309, now seen corresponding path program 2 times [2022-04-27 21:06:10,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:06:10,300 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221577098] [2022-04-27 21:06:10,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:06:10,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:06:10,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:10,884 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:06:10,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:10,888 INFO L290 TraceCheckUtils]: 0: Hoare triple {5578#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-27 21:06:10,889 INFO L290 TraceCheckUtils]: 1: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:10,889 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:10,889 INFO L272 TraceCheckUtils]: 0: Hoare triple {5553#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5578#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:06:10,889 INFO L290 TraceCheckUtils]: 1: Hoare triple {5578#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-27 21:06:10,889 INFO L290 TraceCheckUtils]: 2: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:10,889 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:10,889 INFO L272 TraceCheckUtils]: 4: Hoare triple {5553#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:10,890 INFO L290 TraceCheckUtils]: 5: Hoare triple {5553#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:10,890 INFO L290 TraceCheckUtils]: 6: Hoare triple {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:10,891 INFO L290 TraceCheckUtils]: 7: Hoare triple {5558#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:10,891 INFO L290 TraceCheckUtils]: 8: Hoare triple {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:10,892 INFO L290 TraceCheckUtils]: 9: Hoare triple {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:06:10,892 INFO L290 TraceCheckUtils]: 10: Hoare triple {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:06:10,892 INFO L290 TraceCheckUtils]: 11: Hoare triple {5560#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5561#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:10,893 INFO L290 TraceCheckUtils]: 12: Hoare triple {5561#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5561#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:10,893 INFO L290 TraceCheckUtils]: 13: Hoare triple {5561#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:10,894 INFO L290 TraceCheckUtils]: 14: Hoare triple {5559#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5562#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 21:06:10,894 INFO L290 TraceCheckUtils]: 15: Hoare triple {5562#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5563#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 21:06:10,895 INFO L290 TraceCheckUtils]: 16: Hoare triple {5563#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5564#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:10,895 INFO L290 TraceCheckUtils]: 17: Hoare triple {5564#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5565#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:10,896 INFO L290 TraceCheckUtils]: 18: Hoare triple {5565#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5566#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:10,897 INFO L290 TraceCheckUtils]: 19: Hoare triple {5566#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5567#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} is VALID [2022-04-27 21:06:10,897 INFO L290 TraceCheckUtils]: 20: Hoare triple {5567#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5568#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} is VALID [2022-04-27 21:06:10,898 INFO L290 TraceCheckUtils]: 21: Hoare triple {5568#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,898 INFO L290 TraceCheckUtils]: 22: Hoare triple {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,899 INFO L290 TraceCheckUtils]: 23: Hoare triple {5569#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5570#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,899 INFO L290 TraceCheckUtils]: 24: Hoare triple {5570#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5571#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,900 INFO L290 TraceCheckUtils]: 25: Hoare triple {5571#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,901 INFO L290 TraceCheckUtils]: 26: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,901 INFO L290 TraceCheckUtils]: 27: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,902 INFO L290 TraceCheckUtils]: 28: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,902 INFO L290 TraceCheckUtils]: 29: Hoare triple {5572#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,903 INFO L290 TraceCheckUtils]: 30: Hoare triple {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,903 INFO L290 TraceCheckUtils]: 31: Hoare triple {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,904 INFO L290 TraceCheckUtils]: 32: Hoare triple {5573#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5574#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:06:10,904 INFO L290 TraceCheckUtils]: 33: Hoare triple {5574#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5575#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:10,905 INFO L272 TraceCheckUtils]: 34: Hoare triple {5575#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5576#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:06:10,905 INFO L290 TraceCheckUtils]: 35: Hoare triple {5576#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5577#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:06:10,906 INFO L290 TraceCheckUtils]: 36: Hoare triple {5577#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-27 21:06:10,906 INFO L290 TraceCheckUtils]: 37: Hoare triple {5554#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-27 21:06:10,906 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:06:10,906 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:06:10,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221577098] [2022-04-27 21:06:10,906 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221577098] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:06:10,906 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2069486055] [2022-04-27 21:06:10,906 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:06:10,906 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:10,906 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:06:10,907 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:06:10,908 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 21:06:10,956 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:06:10,956 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:06:10,957 INFO L263 TraceCheckSpWp]: Trace formula consists of 150 conjuncts, 30 conjunts are in the unsatisfiable core [2022-04-27 21:06:10,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:10,970 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:06:11,263 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-27 21:06:11,264 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-27 21:06:12,070 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-27 21:06:12,071 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-27 21:06:13,349 INFO L356 Elim1Store]: treesize reduction 88, result has 22.1 percent of original size [2022-04-27 21:06:13,350 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 37 [2022-04-27 21:06:14,811 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-27 21:06:14,811 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-27 21:06:15,044 INFO L272 TraceCheckUtils]: 0: Hoare triple {5553#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 1: Hoare triple {5553#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 2: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L272 TraceCheckUtils]: 4: Hoare triple {5553#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 5: Hoare triple {5553#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 6: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 7: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 8: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 9: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-27 21:06:15,044 INFO L290 TraceCheckUtils]: 10: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-27 21:06:15,045 INFO L290 TraceCheckUtils]: 11: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-27 21:06:15,045 INFO L290 TraceCheckUtils]: 12: Hoare triple {5553#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:06:15,045 INFO L290 TraceCheckUtils]: 13: Hoare triple {5553#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5621#(= main_~j~0 1)} is VALID [2022-04-27 21:06:15,045 INFO L290 TraceCheckUtils]: 14: Hoare triple {5621#(= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5625#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:06:15,046 INFO L290 TraceCheckUtils]: 15: Hoare triple {5625#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5629#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:06:15,047 INFO L290 TraceCheckUtils]: 16: Hoare triple {5629#(and (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5633#(and (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:06:15,047 INFO L290 TraceCheckUtils]: 17: Hoare triple {5633#(and (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5637#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:06:15,048 INFO L290 TraceCheckUtils]: 18: Hoare triple {5637#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5641#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:06:15,049 INFO L290 TraceCheckUtils]: 19: Hoare triple {5641#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5645#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))))} is VALID [2022-04-27 21:06:15,051 INFO L290 TraceCheckUtils]: 20: Hoare triple {5645#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5649#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:06:15,052 INFO L290 TraceCheckUtils]: 21: Hoare triple {5649#(and (= main_~j~0 1) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (<= (+ v_main_~i~0_26 1) main_~j~0))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} is VALID [2022-04-27 21:06:15,054 INFO L290 TraceCheckUtils]: 22: Hoare triple {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} is VALID [2022-04-27 21:06:15,056 INFO L290 TraceCheckUtils]: 23: Hoare triple {5653#(and (= main_~j~0 1) (< main_~i~0 0) (exists ((v_main_~i~0_26 Int)) (and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4)))) (<= v_main_~i~0_26 (+ main_~i~0 1)) (<= 0 v_main_~i~0_26) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5660#(and (= main_~j~0 1) (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} is VALID [2022-04-27 21:06:15,056 INFO L290 TraceCheckUtils]: 24: Hoare triple {5660#(and (= main_~j~0 1) (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5664#(and (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:06:15,059 INFO L290 TraceCheckUtils]: 25: Hoare triple {5664#(and (exists ((main_~i~0 Int) (v_main_~i~0_26 Int)) (and (<= v_main_~i~0_26 (+ main_~i~0 1)) (< main_~i~0 0) (<= 0 v_main_~i~0_26) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))))) (= (+ (- 1) main_~j~0) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-27 21:06:15,061 INFO L290 TraceCheckUtils]: 26: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-27 21:06:15,063 INFO L290 TraceCheckUtils]: 27: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-27 21:06:15,065 INFO L290 TraceCheckUtils]: 28: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} is VALID [2022-04-27 21:06:15,067 INFO L290 TraceCheckUtils]: 29: Hoare triple {5668#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~i~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} is VALID [2022-04-27 21:06:15,069 INFO L290 TraceCheckUtils]: 30: Hoare triple {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} is VALID [2022-04-27 21:06:15,071 INFO L290 TraceCheckUtils]: 31: Hoare triple {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} is VALID [2022-04-27 21:06:15,072 INFO L290 TraceCheckUtils]: 32: Hoare triple {5681#(exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5691#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~k~0 1))} is VALID [2022-04-27 21:06:15,073 INFO L290 TraceCheckUtils]: 33: Hoare triple {5691#(and (exists ((v_main_~i~0_27 Int) (v_main_~i~0_26 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_27 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_26 4) 4))) (< v_main_~i~0_27 0) (<= 0 v_main_~i~0_26) (<= v_main_~i~0_26 (+ v_main_~i~0_27 1)))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5695#(< |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:15,074 INFO L272 TraceCheckUtils]: 34: Hoare triple {5695#(< |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:06:15,074 INFO L290 TraceCheckUtils]: 35: Hoare triple {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5703#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:06:15,075 INFO L290 TraceCheckUtils]: 36: Hoare triple {5703#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-27 21:06:15,075 INFO L290 TraceCheckUtils]: 37: Hoare triple {5554#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-27 21:06:15,075 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:06:15,075 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:06:35,838 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 77 [2022-04-27 21:06:35,926 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-27 21:06:35,927 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 5803 treesize of output 5609 [2022-04-27 21:07:55,016 INFO L290 TraceCheckUtils]: 37: Hoare triple {5554#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-27 21:07:55,017 INFO L290 TraceCheckUtils]: 36: Hoare triple {5703#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {5554#false} is VALID [2022-04-27 21:07:55,017 INFO L290 TraceCheckUtils]: 35: Hoare triple {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5703#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:07:55,018 INFO L272 TraceCheckUtils]: 34: Hoare triple {5575#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5699#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:07:55,018 INFO L290 TraceCheckUtils]: 33: Hoare triple {5722#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5575#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:07:55,019 INFO L290 TraceCheckUtils]: 32: Hoare triple {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {5722#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:07:55,019 INFO L290 TraceCheckUtils]: 31: Hoare triple {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:07:55,020 INFO L290 TraceCheckUtils]: 30: Hoare triple {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:07:55,021 INFO L290 TraceCheckUtils]: 29: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5726#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:07:55,021 INFO L290 TraceCheckUtils]: 28: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:07:55,022 INFO L290 TraceCheckUtils]: 27: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:07:55,022 INFO L290 TraceCheckUtils]: 26: Hoare triple {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:07:55,024 INFO L290 TraceCheckUtils]: 25: Hoare triple {5749#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5736#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:07:55,027 INFO L290 TraceCheckUtils]: 24: Hoare triple {5753#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5749#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:07:55,030 INFO L290 TraceCheckUtils]: 23: Hoare triple {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {5753#(forall ((v_ArrVal_198 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:07:55,031 INFO L290 TraceCheckUtils]: 22: Hoare triple {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:07:55,032 INFO L290 TraceCheckUtils]: 21: Hoare triple {5764#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5757#(forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:07:55,032 INFO L290 TraceCheckUtils]: 20: Hoare triple {5768#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5764#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 21:07:55,034 INFO L290 TraceCheckUtils]: 19: Hoare triple {5772#(forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {5768#(or (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (<= 0 main_~i~0))} is VALID [2022-04-27 21:07:55,036 INFO L290 TraceCheckUtils]: 18: Hoare triple {5776#(forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {5772#(forall ((v_main_~i~0_29 Int)) (or (<= 0 v_main_~i~0_29) (forall ((v_ArrVal_198 Int) (v_ArrVal_195 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))))) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} is VALID [2022-04-27 21:07:55,036 INFO L290 TraceCheckUtils]: 17: Hoare triple {5780#(or (forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1))))) (not |main_#t~short10|))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5776#(forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1)))))} is VALID [2022-04-27 21:07:55,037 INFO L290 TraceCheckUtils]: 16: Hoare triple {5784#(or (not |main_#t~short10|) (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0)) (= 0 (* main_~i~0 4))) (<= 1 main_~i~0))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5780#(or (forall ((v_main_~i~0_29 Int) (v_ArrVal_198 Int) (v_ArrVal_195 Int) (v_ArrVal_193 Int)) (or (not (<= v_ArrVal_195 main_~key~0)) (<= (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) |main_~#v~0.offset|) (select (store (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_193) (+ |main_~#v~0.offset| (* v_main_~i~0_29 4) 4) v_ArrVal_195) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_198) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_29) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_193)) (not (<= main_~i~0 (+ v_main_~i~0_29 1))))) (not |main_#t~short10|))} is VALID [2022-04-27 21:07:55,038 INFO L290 TraceCheckUtils]: 15: Hoare triple {5788#(or (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0))) (not (<= 0 main_~i~0)) (<= 1 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5784#(or (not |main_#t~short10|) (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0)) (= 0 (* main_~i~0 4))) (<= 1 main_~i~0))} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 14: Hoare triple {5553#true} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5788#(or (and (not (= (* main_~j~0 4) 0)) (not (= (+ (* main_~j~0 4) 4) 0))) (not (<= 0 main_~i~0)) (<= 1 main_~i~0))} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 13: Hoare triple {5553#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 12: Hoare triple {5553#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 11: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 10: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 9: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 8: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 7: Hoare triple {5553#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 6: Hoare triple {5553#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5553#true} is VALID [2022-04-27 21:07:55,039 INFO L290 TraceCheckUtils]: 5: Hoare triple {5553#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5553#true} is VALID [2022-04-27 21:07:55,040 INFO L272 TraceCheckUtils]: 4: Hoare triple {5553#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:07:55,040 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5553#true} {5553#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:07:55,040 INFO L290 TraceCheckUtils]: 2: Hoare triple {5553#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:07:55,040 INFO L290 TraceCheckUtils]: 1: Hoare triple {5553#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5553#true} is VALID [2022-04-27 21:07:55,040 INFO L272 TraceCheckUtils]: 0: Hoare triple {5553#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5553#true} is VALID [2022-04-27 21:07:55,040 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 2 proven. 11 refuted. 1 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:07:55,040 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2069486055] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:07:55,040 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:07:55,040 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 19, 18] total 53 [2022-04-27 21:07:55,040 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862363103] [2022-04-27 21:07:55,040 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:07:55,041 INFO L78 Accepts]: Start accepts. Automaton has has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-27 21:07:55,041 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:07:55,041 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:07:57,171 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 90 edges. 89 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-27 21:07:57,171 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 53 states [2022-04-27 21:07:57,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:07:57,172 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2022-04-27 21:07:57,172 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=292, Invalid=2449, Unknown=15, NotChecked=0, Total=2756 [2022-04-27 21:07:57,188 INFO L87 Difference]: Start difference. First operand 84 states and 98 transitions. Second operand has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:00,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:00,966 INFO L93 Difference]: Finished difference Result 131 states and 151 transitions. [2022-04-27 21:08:00,966 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2022-04-27 21:08:00,966 INFO L78 Accepts]: Start accepts. Automaton has has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 38 [2022-04-27 21:08:00,966 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:08:00,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:00,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 114 transitions. [2022-04-27 21:08:00,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:00,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 114 transitions. [2022-04-27 21:08:00,969 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 51 states and 114 transitions. [2022-04-27 21:08:02,431 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 114 edges. 113 inductive. 0 not inductive. 1 times theorem prover too weak to decide inductivity. [2022-04-27 21:08:02,432 INFO L225 Difference]: With dead ends: 131 [2022-04-27 21:08:02,432 INFO L226 Difference]: Without dead ends: 129 [2022-04-27 21:08:02,435 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 144 GetRequests, 52 SyntacticMatches, 2 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2632 ImplicationChecksByTransitivity, 34.8s TimeCoverageRelationStatistics Valid=807, Invalid=7549, Unknown=16, NotChecked=0, Total=8372 [2022-04-27 21:08:02,435 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 59 mSDsluCounter, 112 mSDsCounter, 0 mSdLazyCounter, 374 mSolverCounterSat, 41 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.4s Time, 0 mProtectedPredicate, 0 mProtectedAction, 60 SdHoareTripleChecker+Valid, 140 SdHoareTripleChecker+Invalid, 660 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 41 IncrementalHoareTripleChecker+Valid, 374 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 245 IncrementalHoareTripleChecker+Unchecked, 0.4s IncrementalHoareTripleChecker+Time [2022-04-27 21:08:02,435 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [60 Valid, 140 Invalid, 660 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [41 Valid, 374 Invalid, 0 Unknown, 245 Unchecked, 0.4s Time] [2022-04-27 21:08:02,435 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2022-04-27 21:08:02,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 84. [2022-04-27 21:08:02,523 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:08:02,524 INFO L82 GeneralOperation]: Start isEquivalent. First operand 129 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:08:02,524 INFO L74 IsIncluded]: Start isIncluded. First operand 129 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:08:02,524 INFO L87 Difference]: Start difference. First operand 129 states. Second operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:08:02,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:02,526 INFO L93 Difference]: Finished difference Result 129 states and 149 transitions. [2022-04-27 21:08:02,526 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 149 transitions. [2022-04-27 21:08:02,526 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:08:02,526 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:08:02,526 INFO L74 IsIncluded]: Start isIncluded. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 129 states. [2022-04-27 21:08:02,526 INFO L87 Difference]: Start difference. First operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 129 states. [2022-04-27 21:08:02,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:02,528 INFO L93 Difference]: Finished difference Result 129 states and 149 transitions. [2022-04-27 21:08:02,528 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 149 transitions. [2022-04-27 21:08:02,528 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:08:02,528 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:08:02,528 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:08:02,528 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:08:02,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84 states, 76 states have (on average 1.1973684210526316) internal successors, (91), 77 states have internal predecessors, (91), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:08:02,529 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 98 transitions. [2022-04-27 21:08:02,529 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 98 transitions. Word has length 38 [2022-04-27 21:08:02,530 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:08:02,530 INFO L495 AbstractCegarLoop]: Abstraction has 84 states and 98 transitions. [2022-04-27 21:08:02,530 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 53 states, 51 states have (on average 1.6274509803921569) internal successors, (83), 50 states have internal predecessors, (83), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:02,530 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 98 transitions. [2022-04-27 21:08:02,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2022-04-27 21:08:02,530 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:08:02,530 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:08:02,547 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Forceful destruction successful, exit code 0 [2022-04-27 21:08:02,734 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable11,10 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:08:02,735 INFO L420 AbstractCegarLoop]: === Iteration 13 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:08:02,735 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:08:02,735 INFO L85 PathProgramCache]: Analyzing trace with hash -1062518689, now seen corresponding path program 2 times [2022-04-27 21:08:02,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:08:02,735 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099991300] [2022-04-27 21:08:02,735 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:08:02,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:08:02,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:02,972 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:08:02,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:02,977 INFO L290 TraceCheckUtils]: 0: Hoare triple {6485#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6464#true} is VALID [2022-04-27 21:08:02,977 INFO L290 TraceCheckUtils]: 1: Hoare triple {6464#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,977 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {6464#true} {6464#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,978 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 29 [2022-04-27 21:08:02,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:02,982 INFO L290 TraceCheckUtils]: 0: Hoare triple {6464#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6464#true} is VALID [2022-04-27 21:08:02,982 INFO L290 TraceCheckUtils]: 1: Hoare triple {6464#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,983 INFO L290 TraceCheckUtils]: 2: Hoare triple {6464#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,983 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6464#true} {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:02,984 INFO L272 TraceCheckUtils]: 0: Hoare triple {6464#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6485#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:08:02,984 INFO L290 TraceCheckUtils]: 1: Hoare triple {6485#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6464#true} is VALID [2022-04-27 21:08:02,984 INFO L290 TraceCheckUtils]: 2: Hoare triple {6464#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,984 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6464#true} {6464#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,984 INFO L272 TraceCheckUtils]: 4: Hoare triple {6464#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,984 INFO L290 TraceCheckUtils]: 5: Hoare triple {6464#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6469#(= main_~j~0 0)} is VALID [2022-04-27 21:08:02,985 INFO L290 TraceCheckUtils]: 6: Hoare triple {6469#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6469#(= main_~j~0 0)} is VALID [2022-04-27 21:08:02,985 INFO L290 TraceCheckUtils]: 7: Hoare triple {6469#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,985 INFO L290 TraceCheckUtils]: 8: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,986 INFO L290 TraceCheckUtils]: 9: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:02,986 INFO L290 TraceCheckUtils]: 10: Hoare triple {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:02,986 INFO L290 TraceCheckUtils]: 11: Hoare triple {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:02,986 INFO L290 TraceCheckUtils]: 12: Hoare triple {6464#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,987 INFO L290 TraceCheckUtils]: 13: Hoare triple {6464#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,987 INFO L290 TraceCheckUtils]: 14: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,987 INFO L290 TraceCheckUtils]: 15: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,988 INFO L290 TraceCheckUtils]: 16: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,988 INFO L290 TraceCheckUtils]: 17: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,989 INFO L290 TraceCheckUtils]: 18: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:02,989 INFO L290 TraceCheckUtils]: 19: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:02,990 INFO L290 TraceCheckUtils]: 20: Hoare triple {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6472#(= 4 (* main_~i~0 4))} is VALID [2022-04-27 21:08:02,990 INFO L290 TraceCheckUtils]: 21: Hoare triple {6472#(= 4 (* main_~i~0 4))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6472#(= 4 (* main_~i~0 4))} is VALID [2022-04-27 21:08:02,991 INFO L290 TraceCheckUtils]: 22: Hoare triple {6472#(= 4 (* main_~i~0 4))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6473#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:08:02,991 INFO L290 TraceCheckUtils]: 23: Hoare triple {6473#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6474#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:08:02,992 INFO L290 TraceCheckUtils]: 24: Hoare triple {6474#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:02,992 INFO L290 TraceCheckUtils]: 25: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:02,992 INFO L290 TraceCheckUtils]: 26: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:02,993 INFO L290 TraceCheckUtils]: 27: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:02,993 INFO L290 TraceCheckUtils]: 28: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:02,993 INFO L272 TraceCheckUtils]: 29: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6464#true} is VALID [2022-04-27 21:08:02,994 INFO L290 TraceCheckUtils]: 30: Hoare triple {6464#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6464#true} is VALID [2022-04-27 21:08:02,994 INFO L290 TraceCheckUtils]: 31: Hoare triple {6464#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,994 INFO L290 TraceCheckUtils]: 32: Hoare triple {6464#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:02,994 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {6464#true} {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:02,995 INFO L290 TraceCheckUtils]: 34: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:02,995 INFO L290 TraceCheckUtils]: 35: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {6481#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:08:02,995 INFO L290 TraceCheckUtils]: 36: Hoare triple {6481#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6482#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:08:02,996 INFO L272 TraceCheckUtils]: 37: Hoare triple {6482#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6483#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:08:02,996 INFO L290 TraceCheckUtils]: 38: Hoare triple {6483#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6484#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:08:02,997 INFO L290 TraceCheckUtils]: 39: Hoare triple {6484#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6465#false} is VALID [2022-04-27 21:08:02,997 INFO L290 TraceCheckUtils]: 40: Hoare triple {6465#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6465#false} is VALID [2022-04-27 21:08:02,997 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 19 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:08:02,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:08:02,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099991300] [2022-04-27 21:08:02,997 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099991300] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:08:02,997 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1330159418] [2022-04-27 21:08:02,998 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:08:02,998 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:08:02,998 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:08:03,013 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:08:03,053 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2022-04-27 21:08:03,072 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:08:03,072 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:08:03,073 INFO L263 TraceCheckSpWp]: Trace formula consists of 157 conjuncts, 26 conjunts are in the unsatisfiable core [2022-04-27 21:08:03,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:03,087 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:08:03,279 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 12 [2022-04-27 21:08:03,463 INFO L356 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2022-04-27 21:08:03,464 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 23 treesize of output 22 [2022-04-27 21:08:05,517 WARN L855 $PredicateComparison]: unable to prove that (exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (let ((.cse0 (select |c_#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|))) (<= (select .cse0 (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select .cse0 (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))) is different from true [2022-04-27 21:08:05,720 INFO L356 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2022-04-27 21:08:05,721 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 34 treesize of output 10 [2022-04-27 21:08:05,801 INFO L272 TraceCheckUtils]: 0: Hoare triple {6464#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 1: Hoare triple {6464#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 2: Hoare triple {6464#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6464#true} {6464#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L272 TraceCheckUtils]: 4: Hoare triple {6464#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 5: Hoare triple {6464#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 6: Hoare triple {6464#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 7: Hoare triple {6464#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 8: Hoare triple {6464#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#true} is VALID [2022-04-27 21:08:05,801 INFO L290 TraceCheckUtils]: 9: Hoare triple {6464#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:05,802 INFO L290 TraceCheckUtils]: 10: Hoare triple {6464#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#true} is VALID [2022-04-27 21:08:05,802 INFO L290 TraceCheckUtils]: 11: Hoare triple {6464#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:05,802 INFO L290 TraceCheckUtils]: 12: Hoare triple {6464#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:05,802 INFO L290 TraceCheckUtils]: 13: Hoare triple {6464#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:05,802 INFO L290 TraceCheckUtils]: 14: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6531#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:05,803 INFO L290 TraceCheckUtils]: 15: Hoare triple {6531#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6535#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:08:05,803 INFO L290 TraceCheckUtils]: 16: Hoare triple {6535#(and (<= 1 main_~j~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6539#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:05,804 INFO L290 TraceCheckUtils]: 17: Hoare triple {6539#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6539#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:05,804 INFO L290 TraceCheckUtils]: 18: Hoare triple {6539#(and (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:05,805 INFO L290 TraceCheckUtils]: 19: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:05,806 INFO L290 TraceCheckUtils]: 20: Hoare triple {6471#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6472#(= 4 (* main_~i~0 4))} is VALID [2022-04-27 21:08:05,806 INFO L290 TraceCheckUtils]: 21: Hoare triple {6472#(= 4 (* main_~i~0 4))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6472#(= 4 (* main_~i~0 4))} is VALID [2022-04-27 21:08:05,807 INFO L290 TraceCheckUtils]: 22: Hoare triple {6472#(= 4 (* main_~i~0 4))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6473#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:08:05,807 INFO L290 TraceCheckUtils]: 23: Hoare triple {6473#(and (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 8)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6474#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:08:05,808 INFO L290 TraceCheckUtils]: 24: Hoare triple {6474#(and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:05,808 INFO L290 TraceCheckUtils]: 25: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:05,808 INFO L290 TraceCheckUtils]: 26: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:05,809 INFO L290 TraceCheckUtils]: 27: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:05,809 INFO L290 TraceCheckUtils]: 28: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:05,810 INFO L272 TraceCheckUtils]: 29: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-27 21:08:05,811 INFO L290 TraceCheckUtils]: 30: Hoare triple {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-27 21:08:05,811 INFO L290 TraceCheckUtils]: 31: Hoare triple {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-27 21:08:05,811 INFO L290 TraceCheckUtils]: 32: Hoare triple {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} is VALID [2022-04-27 21:08:05,812 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {6579#(exists ((|v_main_~#v~0.base_BEFORE_CALL_1| Int) (|v_main_~#v~0.offset_BEFORE_CALL_1| Int)) (<= (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ |v_main_~#v~0.offset_BEFORE_CALL_1| 4)) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_1|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_1|))))} {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:05,812 INFO L290 TraceCheckUtils]: 34: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:05,813 INFO L290 TraceCheckUtils]: 35: Hoare triple {6476#(and (= main_~k~0 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {6598#(and (= (+ (- 1) main_~k~0) 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} is VALID [2022-04-27 21:08:05,813 INFO L290 TraceCheckUtils]: 36: Hoare triple {6598#(and (= (+ (- 1) main_~k~0) 1) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6482#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:08:05,814 INFO L272 TraceCheckUtils]: 37: Hoare triple {6482#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6605#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:08:05,814 INFO L290 TraceCheckUtils]: 38: Hoare triple {6605#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6609#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:08:05,814 INFO L290 TraceCheckUtils]: 39: Hoare triple {6609#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6465#false} is VALID [2022-04-27 21:08:05,814 INFO L290 TraceCheckUtils]: 40: Hoare triple {6465#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6465#false} is VALID [2022-04-27 21:08:05,815 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 9 trivial. 2 not checked. [2022-04-27 21:08:05,815 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:08:08,532 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 61 [2022-04-27 21:08:08,590 INFO L356 Elim1Store]: treesize reduction 25, result has 39.0 percent of original size [2022-04-27 21:08:08,591 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 903 treesize of output 848 [2022-04-27 21:08:09,446 INFO L290 TraceCheckUtils]: 40: Hoare triple {6465#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6465#false} is VALID [2022-04-27 21:08:09,446 INFO L290 TraceCheckUtils]: 39: Hoare triple {6609#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {6465#false} is VALID [2022-04-27 21:08:09,447 INFO L290 TraceCheckUtils]: 38: Hoare triple {6605#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6609#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:08:09,447 INFO L272 TraceCheckUtils]: 37: Hoare triple {6482#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6605#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:08:09,447 INFO L290 TraceCheckUtils]: 36: Hoare triple {6481#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6482#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:08:09,448 INFO L290 TraceCheckUtils]: 35: Hoare triple {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {6481#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:08:09,449 INFO L290 TraceCheckUtils]: 34: Hoare triple {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:08:09,449 INFO L284 TraceCheckUtils]: 33: Hoare quadruple {6464#true} {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:08:09,449 INFO L290 TraceCheckUtils]: 32: Hoare triple {6464#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,449 INFO L290 TraceCheckUtils]: 31: Hoare triple {6464#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,449 INFO L290 TraceCheckUtils]: 30: Hoare triple {6464#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {6464#true} is VALID [2022-04-27 21:08:09,449 INFO L272 TraceCheckUtils]: 29: Hoare triple {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {6464#true} is VALID [2022-04-27 21:08:09,450 INFO L290 TraceCheckUtils]: 28: Hoare triple {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:08:09,451 INFO L290 TraceCheckUtils]: 27: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {6631#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:08:09,451 INFO L290 TraceCheckUtils]: 26: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:09,451 INFO L290 TraceCheckUtils]: 25: Hoare triple {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:09,452 INFO L290 TraceCheckUtils]: 24: Hoare triple {6665#(forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6475#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:09,453 INFO L290 TraceCheckUtils]: 23: Hoare triple {6669#(or (forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))))) |main_#t~short10|)} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6665#(forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8)))))} is VALID [2022-04-27 21:08:09,454 INFO L290 TraceCheckUtils]: 22: Hoare triple {6673#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6669#(or (forall ((v_ArrVal_225 Int)) (or (not (<= main_~key~0 v_ArrVal_225)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))))) |main_#t~short10|)} is VALID [2022-04-27 21:08:09,455 INFO L290 TraceCheckUtils]: 21: Hoare triple {6673#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6673#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} is VALID [2022-04-27 21:08:09,458 INFO L290 TraceCheckUtils]: 20: Hoare triple {6680#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6673#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))))} is VALID [2022-04-27 21:08:09,461 INFO L290 TraceCheckUtils]: 19: Hoare triple {6684#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4))))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {6680#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))))))} is VALID [2022-04-27 21:08:09,462 INFO L290 TraceCheckUtils]: 18: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {6684#(forall ((v_ArrVal_225 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) 4) v_ArrVal_225) (+ |main_~#v~0.offset| 8))) (< v_ArrVal_225 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4))))))} is VALID [2022-04-27 21:08:09,462 INFO L290 TraceCheckUtils]: 17: Hoare triple {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:09,463 INFO L290 TraceCheckUtils]: 16: Hoare triple {6694#(or (not |main_#t~short10|) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {6470#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:09,463 INFO L290 TraceCheckUtils]: 15: Hoare triple {6698#(or (not (<= 0 main_~i~0)) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {6694#(or (not |main_#t~short10|) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} is VALID [2022-04-27 21:08:09,464 INFO L290 TraceCheckUtils]: 14: Hoare triple {6702#(<= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {6698#(or (not (<= 0 main_~i~0)) (and (<= 1 main_~j~0) (<= main_~j~0 1)))} is VALID [2022-04-27 21:08:09,464 INFO L290 TraceCheckUtils]: 13: Hoare triple {6464#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {6702#(<= main_~j~0 1)} is VALID [2022-04-27 21:08:09,464 INFO L290 TraceCheckUtils]: 12: Hoare triple {6464#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,464 INFO L290 TraceCheckUtils]: 11: Hoare triple {6464#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:09,464 INFO L290 TraceCheckUtils]: 10: Hoare triple {6464#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#true} is VALID [2022-04-27 21:08:09,464 INFO L290 TraceCheckUtils]: 9: Hoare triple {6464#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L290 TraceCheckUtils]: 8: Hoare triple {6464#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L290 TraceCheckUtils]: 7: Hoare triple {6464#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L290 TraceCheckUtils]: 6: Hoare triple {6464#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L290 TraceCheckUtils]: 5: Hoare triple {6464#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L272 TraceCheckUtils]: 4: Hoare triple {6464#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {6464#true} {6464#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L290 TraceCheckUtils]: 2: Hoare triple {6464#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L290 TraceCheckUtils]: 1: Hoare triple {6464#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L272 TraceCheckUtils]: 0: Hoare triple {6464#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {6464#true} is VALID [2022-04-27 21:08:09,465 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 2 proven. 10 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:08:09,465 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1330159418] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:08:09,465 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:08:09,466 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 17, 17] total 31 [2022-04-27 21:08:09,466 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1428066171] [2022-04-27 21:08:09,466 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:08:09,466 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 41 [2022-04-27 21:08:09,471 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:08:09,471 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:08:09,534 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:08:09,535 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 31 states [2022-04-27 21:08:09,535 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:08:09,535 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2022-04-27 21:08:09,535 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=773, Unknown=2, NotChecked=56, Total=930 [2022-04-27 21:08:09,537 INFO L87 Difference]: Start difference. First operand 84 states and 98 transitions. Second operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:08:46,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:46,365 INFO L93 Difference]: Finished difference Result 148 states and 174 transitions. [2022-04-27 21:08:46,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2022-04-27 21:08:46,366 INFO L78 Accepts]: Start accepts. Automaton has has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 41 [2022-04-27 21:08:46,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:08:46,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:08:46,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 117 transitions. [2022-04-27 21:08:46,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:08:46,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 117 transitions. [2022-04-27 21:08:46,368 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 32 states and 117 transitions. [2022-04-27 21:08:46,469 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 117 edges. 117 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:08:46,471 INFO L225 Difference]: With dead ends: 148 [2022-04-27 21:08:46,471 INFO L226 Difference]: Without dead ends: 146 [2022-04-27 21:08:46,472 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 70 SyntacticMatches, 10 SemanticMatches, 54 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 39.4s TimeCoverageRelationStatistics Valid=339, Invalid=2617, Unknown=18, NotChecked=106, Total=3080 [2022-04-27 21:08:46,472 INFO L413 NwaCegarLoop]: 30 mSDtfsCounter, 120 mSDsluCounter, 133 mSDsCounter, 0 mSdLazyCounter, 780 mSolverCounterSat, 72 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.9s Time, 0 mProtectedPredicate, 0 mProtectedAction, 121 SdHoareTripleChecker+Valid, 163 SdHoareTripleChecker+Invalid, 1262 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 72 IncrementalHoareTripleChecker+Valid, 780 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 410 IncrementalHoareTripleChecker+Unchecked, 0.9s IncrementalHoareTripleChecker+Time [2022-04-27 21:08:46,472 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [121 Valid, 163 Invalid, 1262 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [72 Valid, 780 Invalid, 0 Unknown, 410 Unchecked, 0.9s Time] [2022-04-27 21:08:46,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2022-04-27 21:08:46,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 118. [2022-04-27 21:08:46,605 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:08:46,606 INFO L82 GeneralOperation]: Start isEquivalent. First operand 146 states. Second operand has 118 states, 106 states have (on average 1.2075471698113207) internal successors, (128), 108 states have internal predecessors, (128), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:46,606 INFO L74 IsIncluded]: Start isIncluded. First operand 146 states. Second operand has 118 states, 106 states have (on average 1.2075471698113207) internal successors, (128), 108 states have internal predecessors, (128), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:46,606 INFO L87 Difference]: Start difference. First operand 146 states. Second operand has 118 states, 106 states have (on average 1.2075471698113207) internal successors, (128), 108 states have internal predecessors, (128), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:46,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:46,608 INFO L93 Difference]: Finished difference Result 146 states and 172 transitions. [2022-04-27 21:08:46,608 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 172 transitions. [2022-04-27 21:08:46,608 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:08:46,608 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:08:46,608 INFO L74 IsIncluded]: Start isIncluded. First operand has 118 states, 106 states have (on average 1.2075471698113207) internal successors, (128), 108 states have internal predecessors, (128), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 146 states. [2022-04-27 21:08:46,608 INFO L87 Difference]: Start difference. First operand has 118 states, 106 states have (on average 1.2075471698113207) internal successors, (128), 108 states have internal predecessors, (128), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 146 states. [2022-04-27 21:08:46,611 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:46,611 INFO L93 Difference]: Finished difference Result 146 states and 172 transitions. [2022-04-27 21:08:46,611 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 172 transitions. [2022-04-27 21:08:46,611 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:08:46,611 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:08:46,611 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:08:46,611 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:08:46,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 106 states have (on average 1.2075471698113207) internal successors, (128), 108 states have internal predecessors, (128), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:46,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 139 transitions. [2022-04-27 21:08:46,613 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 139 transitions. Word has length 41 [2022-04-27 21:08:46,613 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:08:46,613 INFO L495 AbstractCegarLoop]: Abstraction has 118 states and 139 transitions. [2022-04-27 21:08:46,613 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 31 states, 30 states have (on average 2.2) internal successors, (66), 28 states have internal predecessors, (66), 4 states have call successors, (8), 5 states have call predecessors, (8), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:08:46,614 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 139 transitions. [2022-04-27 21:08:46,614 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2022-04-27 21:08:46,614 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:08:46,614 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:08:46,633 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Forceful destruction successful, exit code 0 [2022-04-27 21:08:46,830 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 11 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable12 [2022-04-27 21:08:46,831 INFO L420 AbstractCegarLoop]: === Iteration 14 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:08:46,831 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:08:46,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1915025960, now seen corresponding path program 1 times [2022-04-27 21:08:46,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:08:46,831 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304133214] [2022-04-27 21:08:46,831 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:08:46,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:08:46,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:47,032 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:08:47,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:47,036 INFO L290 TraceCheckUtils]: 0: Hoare triple {7464#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7451#true} is VALID [2022-04-27 21:08:47,036 INFO L290 TraceCheckUtils]: 1: Hoare triple {7451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,036 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {7451#true} {7451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,037 INFO L272 TraceCheckUtils]: 0: Hoare triple {7451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7464#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:08:47,037 INFO L290 TraceCheckUtils]: 1: Hoare triple {7464#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7451#true} is VALID [2022-04-27 21:08:47,037 INFO L290 TraceCheckUtils]: 2: Hoare triple {7451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,037 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {7451#true} {7451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,037 INFO L272 TraceCheckUtils]: 4: Hoare triple {7451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,037 INFO L290 TraceCheckUtils]: 5: Hoare triple {7451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {7456#(= main_~j~0 0)} is VALID [2022-04-27 21:08:47,038 INFO L290 TraceCheckUtils]: 6: Hoare triple {7456#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7456#(= main_~j~0 0)} is VALID [2022-04-27 21:08:47,038 INFO L290 TraceCheckUtils]: 7: Hoare triple {7456#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:47,038 INFO L290 TraceCheckUtils]: 8: Hoare triple {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:47,039 INFO L290 TraceCheckUtils]: 9: Hoare triple {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:47,039 INFO L290 TraceCheckUtils]: 10: Hoare triple {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:47,040 INFO L290 TraceCheckUtils]: 11: Hoare triple {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7459#(and (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-27 21:08:47,041 INFO L290 TraceCheckUtils]: 12: Hoare triple {7459#(and (<= 3 main_~j~0) (<= main_~j~0 3))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {7460#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,041 INFO L290 TraceCheckUtils]: 13: Hoare triple {7460#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,041 INFO L290 TraceCheckUtils]: 14: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,042 INFO L290 TraceCheckUtils]: 15: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,042 INFO L290 TraceCheckUtils]: 16: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,043 INFO L290 TraceCheckUtils]: 17: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,043 INFO L290 TraceCheckUtils]: 18: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,044 INFO L290 TraceCheckUtils]: 19: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,044 INFO L290 TraceCheckUtils]: 20: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,045 INFO L290 TraceCheckUtils]: 21: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,045 INFO L290 TraceCheckUtils]: 22: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,045 INFO L290 TraceCheckUtils]: 23: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,046 INFO L290 TraceCheckUtils]: 24: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,047 INFO L290 TraceCheckUtils]: 25: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7463#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 26: Hoare triple {7463#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 27: Hoare triple {7452#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 28: Hoare triple {7452#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 29: Hoare triple {7452#false} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 30: Hoare triple {7452#false} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 31: Hoare triple {7452#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 32: Hoare triple {7452#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 33: Hoare triple {7452#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 34: Hoare triple {7452#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 35: Hoare triple {7452#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 36: Hoare triple {7452#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 37: Hoare triple {7452#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 38: Hoare triple {7452#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {7452#false} is VALID [2022-04-27 21:08:47,048 INFO L290 TraceCheckUtils]: 39: Hoare triple {7452#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {7452#false} is VALID [2022-04-27 21:08:47,049 INFO L272 TraceCheckUtils]: 40: Hoare triple {7452#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {7452#false} is VALID [2022-04-27 21:08:47,049 INFO L290 TraceCheckUtils]: 41: Hoare triple {7452#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {7452#false} is VALID [2022-04-27 21:08:47,049 INFO L290 TraceCheckUtils]: 42: Hoare triple {7452#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,049 INFO L290 TraceCheckUtils]: 43: Hoare triple {7452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,049 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 19 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-27 21:08:47,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:08:47,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304133214] [2022-04-27 21:08:47,049 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304133214] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:08:47,049 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [542090035] [2022-04-27 21:08:47,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:08:47,049 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:08:47,049 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:08:47,064 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:08:47,080 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2022-04-27 21:08:47,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:47,144 INFO L263 TraceCheckSpWp]: Trace formula consists of 166 conjuncts, 16 conjunts are in the unsatisfiable core [2022-04-27 21:08:47,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:47,152 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:08:47,672 INFO L272 TraceCheckUtils]: 0: Hoare triple {7451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,672 INFO L290 TraceCheckUtils]: 1: Hoare triple {7451#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7451#true} is VALID [2022-04-27 21:08:47,672 INFO L290 TraceCheckUtils]: 2: Hoare triple {7451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,672 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {7451#true} {7451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,672 INFO L272 TraceCheckUtils]: 4: Hoare triple {7451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:47,672 INFO L290 TraceCheckUtils]: 5: Hoare triple {7451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {7456#(= main_~j~0 0)} is VALID [2022-04-27 21:08:47,673 INFO L290 TraceCheckUtils]: 6: Hoare triple {7456#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7456#(= main_~j~0 0)} is VALID [2022-04-27 21:08:47,673 INFO L290 TraceCheckUtils]: 7: Hoare triple {7456#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:47,674 INFO L290 TraceCheckUtils]: 8: Hoare triple {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:47,674 INFO L290 TraceCheckUtils]: 9: Hoare triple {7457#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:47,675 INFO L290 TraceCheckUtils]: 10: Hoare triple {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:47,675 INFO L290 TraceCheckUtils]: 11: Hoare triple {7458#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7459#(and (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-27 21:08:47,676 INFO L290 TraceCheckUtils]: 12: Hoare triple {7459#(and (<= 3 main_~j~0) (<= main_~j~0 3))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {7460#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:47,676 INFO L290 TraceCheckUtils]: 13: Hoare triple {7460#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,677 INFO L290 TraceCheckUtils]: 14: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,677 INFO L290 TraceCheckUtils]: 15: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,678 INFO L290 TraceCheckUtils]: 16: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,678 INFO L290 TraceCheckUtils]: 17: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,678 INFO L290 TraceCheckUtils]: 18: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} is VALID [2022-04-27 21:08:47,679 INFO L290 TraceCheckUtils]: 19: Hoare triple {7461#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,679 INFO L290 TraceCheckUtils]: 20: Hoare triple {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,680 INFO L290 TraceCheckUtils]: 21: Hoare triple {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,680 INFO L290 TraceCheckUtils]: 22: Hoare triple {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,680 INFO L290 TraceCheckUtils]: 23: Hoare triple {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,681 INFO L290 TraceCheckUtils]: 24: Hoare triple {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,681 INFO L290 TraceCheckUtils]: 25: Hoare triple {7525#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 1) main_~j~0) 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7544#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 2) main_~j~0) 1))} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 26: Hoare triple {7544#(and (<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296))) (= (+ (- 2) main_~j~0) 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 27: Hoare triple {7452#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 28: Hoare triple {7452#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 29: Hoare triple {7452#false} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 30: Hoare triple {7452#false} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 31: Hoare triple {7452#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 32: Hoare triple {7452#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 33: Hoare triple {7452#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 34: Hoare triple {7452#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 35: Hoare triple {7452#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 36: Hoare triple {7452#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7452#false} is VALID [2022-04-27 21:08:47,682 INFO L290 TraceCheckUtils]: 37: Hoare triple {7452#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L290 TraceCheckUtils]: 38: Hoare triple {7452#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L290 TraceCheckUtils]: 39: Hoare triple {7452#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L272 TraceCheckUtils]: 40: Hoare triple {7452#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L290 TraceCheckUtils]: 41: Hoare triple {7452#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L290 TraceCheckUtils]: 42: Hoare triple {7452#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L290 TraceCheckUtils]: 43: Hoare triple {7452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:47,683 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 19 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-27 21:08:47,683 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:08:48,136 INFO L290 TraceCheckUtils]: 43: Hoare triple {7452#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:48,136 INFO L290 TraceCheckUtils]: 42: Hoare triple {7452#false} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:48,136 INFO L290 TraceCheckUtils]: 41: Hoare triple {7452#false} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {7452#false} is VALID [2022-04-27 21:08:48,136 INFO L272 TraceCheckUtils]: 40: Hoare triple {7452#false} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {7452#false} is VALID [2022-04-27 21:08:48,136 INFO L290 TraceCheckUtils]: 39: Hoare triple {7452#false} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 38: Hoare triple {7452#false} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 37: Hoare triple {7452#false} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 36: Hoare triple {7452#false} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 35: Hoare triple {7452#false} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 34: Hoare triple {7452#false} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 33: Hoare triple {7452#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 32: Hoare triple {7452#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 31: Hoare triple {7452#false} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 30: Hoare triple {7452#false} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 29: Hoare triple {7452#false} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 28: Hoare triple {7452#false} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7452#false} is VALID [2022-04-27 21:08:48,137 INFO L290 TraceCheckUtils]: 27: Hoare triple {7452#false} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7452#false} is VALID [2022-04-27 21:08:48,138 INFO L290 TraceCheckUtils]: 26: Hoare triple {7463#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7452#false} is VALID [2022-04-27 21:08:48,139 INFO L290 TraceCheckUtils]: 25: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7463#(<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,139 INFO L290 TraceCheckUtils]: 24: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,140 INFO L290 TraceCheckUtils]: 23: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,140 INFO L290 TraceCheckUtils]: 22: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,141 INFO L290 TraceCheckUtils]: 21: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,141 INFO L290 TraceCheckUtils]: 20: Hoare triple {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,142 INFO L290 TraceCheckUtils]: 19: Hoare triple {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {7462#(<= main_~j~0 (+ 4294967294 (* (div (+ main_~j~0 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,143 INFO L290 TraceCheckUtils]: 18: Hoare triple {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-27 21:08:48,143 INFO L290 TraceCheckUtils]: 17: Hoare triple {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-27 21:08:48,143 INFO L290 TraceCheckUtils]: 16: Hoare triple {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-27 21:08:48,144 INFO L290 TraceCheckUtils]: 15: Hoare triple {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-27 21:08:48,144 INFO L290 TraceCheckUtils]: 14: Hoare triple {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-27 21:08:48,145 INFO L290 TraceCheckUtils]: 13: Hoare triple {7460#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {7671#(<= main_~j~0 (+ (* (div (+ main_~j~0 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296) 4294967296) 4294967293))} is VALID [2022-04-27 21:08:48,146 INFO L290 TraceCheckUtils]: 12: Hoare triple {7693#(<= 0 (div (+ 3 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {7460#(<= main_~SIZE~0 (+ 3 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:08:48,147 INFO L290 TraceCheckUtils]: 11: Hoare triple {7697#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7693#(<= 0 (div (+ 3 (* (- 1) (mod main_~j~0 4294967296))) 4294967296))} is VALID [2022-04-27 21:08:48,147 INFO L290 TraceCheckUtils]: 10: Hoare triple {7697#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7697#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} is VALID [2022-04-27 21:08:48,148 INFO L290 TraceCheckUtils]: 9: Hoare triple {7704#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7697#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 3) 4294967296))} is VALID [2022-04-27 21:08:48,148 INFO L290 TraceCheckUtils]: 8: Hoare triple {7704#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7704#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-27 21:08:48,149 INFO L290 TraceCheckUtils]: 7: Hoare triple {7711#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {7704#(<= 0 (div (+ 3 (* (- 1) (mod (+ main_~j~0 2) 4294967296))) 4294967296))} is VALID [2022-04-27 21:08:48,150 INFO L290 TraceCheckUtils]: 6: Hoare triple {7711#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {7711#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} is VALID [2022-04-27 21:08:48,150 INFO L290 TraceCheckUtils]: 5: Hoare triple {7451#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {7711#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 3) 4294967296)) 3) 4294967296))} is VALID [2022-04-27 21:08:48,150 INFO L272 TraceCheckUtils]: 4: Hoare triple {7451#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:48,150 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {7451#true} {7451#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:48,150 INFO L290 TraceCheckUtils]: 2: Hoare triple {7451#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:48,150 INFO L290 TraceCheckUtils]: 1: Hoare triple {7451#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {7451#true} is VALID [2022-04-27 21:08:48,150 INFO L272 TraceCheckUtils]: 0: Hoare triple {7451#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {7451#true} is VALID [2022-04-27 21:08:48,151 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 19 proven. 17 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2022-04-27 21:08:48,151 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [542090035] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:08:48,151 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:08:48,151 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 18 [2022-04-27 21:08:48,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [729180081] [2022-04-27 21:08:48,151 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:08:48,151 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 44 [2022-04-27 21:08:48,152 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:08:48,152 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:48,205 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 67 edges. 67 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:08:48,205 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 18 states [2022-04-27 21:08:48,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:08:48,205 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2022-04-27 21:08:48,205 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=245, Unknown=0, NotChecked=0, Total=306 [2022-04-27 21:08:48,206 INFO L87 Difference]: Start difference. First operand 118 states and 139 transitions. Second operand has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:49,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:49,958 INFO L93 Difference]: Finished difference Result 284 states and 341 transitions. [2022-04-27 21:08:49,958 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-27 21:08:49,959 INFO L78 Accepts]: Start accepts. Automaton has has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 44 [2022-04-27 21:08:49,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:08:49,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:49,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 126 transitions. [2022-04-27 21:08:49,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:49,962 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 126 transitions. [2022-04-27 21:08:49,962 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 126 transitions. [2022-04-27 21:08:50,066 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 126 edges. 126 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:08:50,069 INFO L225 Difference]: With dead ends: 284 [2022-04-27 21:08:50,069 INFO L226 Difference]: Without dead ends: 208 [2022-04-27 21:08:50,069 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 78 SyntacticMatches, 6 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 100 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=125, Invalid=525, Unknown=0, NotChecked=0, Total=650 [2022-04-27 21:08:50,069 INFO L413 NwaCegarLoop]: 41 mSDtfsCounter, 192 mSDsluCounter, 57 mSDsCounter, 0 mSdLazyCounter, 543 mSolverCounterSat, 35 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.6s Time, 0 mProtectedPredicate, 0 mProtectedAction, 192 SdHoareTripleChecker+Valid, 98 SdHoareTripleChecker+Invalid, 578 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 35 IncrementalHoareTripleChecker+Valid, 543 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.7s IncrementalHoareTripleChecker+Time [2022-04-27 21:08:50,070 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [192 Valid, 98 Invalid, 578 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [35 Valid, 543 Invalid, 0 Unknown, 0 Unchecked, 0.7s Time] [2022-04-27 21:08:50,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2022-04-27 21:08:50,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 152. [2022-04-27 21:08:50,281 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:08:50,282 INFO L82 GeneralOperation]: Start isEquivalent. First operand 208 states. Second operand has 152 states, 140 states have (on average 1.1928571428571428) internal successors, (167), 142 states have internal predecessors, (167), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:50,282 INFO L74 IsIncluded]: Start isIncluded. First operand 208 states. Second operand has 152 states, 140 states have (on average 1.1928571428571428) internal successors, (167), 142 states have internal predecessors, (167), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:50,282 INFO L87 Difference]: Start difference. First operand 208 states. Second operand has 152 states, 140 states have (on average 1.1928571428571428) internal successors, (167), 142 states have internal predecessors, (167), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:50,285 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:50,285 INFO L93 Difference]: Finished difference Result 208 states and 247 transitions. [2022-04-27 21:08:50,286 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 247 transitions. [2022-04-27 21:08:50,286 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:08:50,286 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:08:50,286 INFO L74 IsIncluded]: Start isIncluded. First operand has 152 states, 140 states have (on average 1.1928571428571428) internal successors, (167), 142 states have internal predecessors, (167), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 208 states. [2022-04-27 21:08:50,287 INFO L87 Difference]: Start difference. First operand has 152 states, 140 states have (on average 1.1928571428571428) internal successors, (167), 142 states have internal predecessors, (167), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 208 states. [2022-04-27 21:08:50,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:08:50,292 INFO L93 Difference]: Finished difference Result 208 states and 247 transitions. [2022-04-27 21:08:50,292 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 247 transitions. [2022-04-27 21:08:50,292 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:08:50,292 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:08:50,292 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:08:50,292 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:08:50,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152 states, 140 states have (on average 1.1928571428571428) internal successors, (167), 142 states have internal predecessors, (167), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:08:50,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 178 transitions. [2022-04-27 21:08:50,296 INFO L78 Accepts]: Start accepts. Automaton has 152 states and 178 transitions. Word has length 44 [2022-04-27 21:08:50,296 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:08:50,296 INFO L495 AbstractCegarLoop]: Abstraction has 152 states and 178 transitions. [2022-04-27 21:08:50,297 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 18 states, 18 states have (on average 3.4444444444444446) internal successors, (62), 17 states have internal predecessors, (62), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:08:50,297 INFO L276 IsEmpty]: Start isEmpty. Operand 152 states and 178 transitions. [2022-04-27 21:08:50,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-04-27 21:08:50,297 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:08:50,297 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:08:50,327 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2022-04-27 21:08:50,513 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 12 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable13 [2022-04-27 21:08:50,514 INFO L420 AbstractCegarLoop]: === Iteration 15 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:08:50,514 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:08:50,514 INFO L85 PathProgramCache]: Analyzing trace with hash -1328658693, now seen corresponding path program 1 times [2022-04-27 21:08:50,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:08:50,514 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542537134] [2022-04-27 21:08:50,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:08:50,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:08:50,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:50,912 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:08:50,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:50,915 INFO L290 TraceCheckUtils]: 0: Hoare triple {8771#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8745#true} is VALID [2022-04-27 21:08:50,915 INFO L290 TraceCheckUtils]: 1: Hoare triple {8745#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,915 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {8745#true} {8745#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,915 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 34 [2022-04-27 21:08:50,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:50,918 INFO L290 TraceCheckUtils]: 0: Hoare triple {8745#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8745#true} is VALID [2022-04-27 21:08:50,918 INFO L290 TraceCheckUtils]: 1: Hoare triple {8745#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,918 INFO L290 TraceCheckUtils]: 2: Hoare triple {8745#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,918 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8745#true} {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:08:50,919 INFO L272 TraceCheckUtils]: 0: Hoare triple {8745#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8771#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:08:50,919 INFO L290 TraceCheckUtils]: 1: Hoare triple {8771#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8745#true} is VALID [2022-04-27 21:08:50,919 INFO L290 TraceCheckUtils]: 2: Hoare triple {8745#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,919 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8745#true} {8745#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,919 INFO L272 TraceCheckUtils]: 4: Hoare triple {8745#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,919 INFO L290 TraceCheckUtils]: 5: Hoare triple {8745#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {8750#(= main_~j~0 0)} is VALID [2022-04-27 21:08:50,920 INFO L290 TraceCheckUtils]: 6: Hoare triple {8750#(= main_~j~0 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8750#(= main_~j~0 0)} is VALID [2022-04-27 21:08:50,920 INFO L290 TraceCheckUtils]: 7: Hoare triple {8750#(= main_~j~0 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,921 INFO L290 TraceCheckUtils]: 8: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,921 INFO L290 TraceCheckUtils]: 9: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8752#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:50,922 INFO L290 TraceCheckUtils]: 10: Hoare triple {8752#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8752#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:08:50,922 INFO L290 TraceCheckUtils]: 11: Hoare triple {8752#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:08:50,922 INFO L290 TraceCheckUtils]: 12: Hoare triple {8745#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,922 INFO L290 TraceCheckUtils]: 13: Hoare triple {8745#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,922 INFO L290 TraceCheckUtils]: 14: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,923 INFO L290 TraceCheckUtils]: 15: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,923 INFO L290 TraceCheckUtils]: 16: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,923 INFO L290 TraceCheckUtils]: 17: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,924 INFO L290 TraceCheckUtils]: 18: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:08:50,924 INFO L290 TraceCheckUtils]: 19: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8753#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} is VALID [2022-04-27 21:08:50,925 INFO L290 TraceCheckUtils]: 20: Hoare triple {8753#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:08:50,926 INFO L290 TraceCheckUtils]: 21: Hoare triple {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:08:50,926 INFO L290 TraceCheckUtils]: 22: Hoare triple {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8755#(or (< main_~i~0 1) (and (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 4 (* main_~i~0 4))))} is VALID [2022-04-27 21:08:50,927 INFO L290 TraceCheckUtils]: 23: Hoare triple {8755#(or (< main_~i~0 1) (and (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 4 (* main_~i~0 4))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8756#(or (< main_~i~0 1) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4))))} is VALID [2022-04-27 21:08:50,927 INFO L290 TraceCheckUtils]: 24: Hoare triple {8756#(or (< main_~i~0 1) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {8757#(and (or (< main_~i~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))))) (<= main_~i~0 1))} is VALID [2022-04-27 21:08:50,928 INFO L290 TraceCheckUtils]: 25: Hoare triple {8757#(and (or (< main_~i~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))))) (<= main_~i~0 1))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {8758#(or (<= (+ main_~i~0 1) 0) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 21:08:50,929 INFO L290 TraceCheckUtils]: 26: Hoare triple {8758#(or (<= (+ main_~i~0 1) 0) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8759#(or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 21:08:50,929 INFO L290 TraceCheckUtils]: 27: Hoare triple {8759#(or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8760#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:08:50,929 INFO L290 TraceCheckUtils]: 28: Hoare triple {8760#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8760#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:08:50,930 INFO L290 TraceCheckUtils]: 29: Hoare triple {8760#(and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= 0 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:50,931 INFO L290 TraceCheckUtils]: 30: Hoare triple {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:50,931 INFO L290 TraceCheckUtils]: 31: Hoare triple {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:08:50,931 INFO L290 TraceCheckUtils]: 32: Hoare triple {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:08:50,932 INFO L290 TraceCheckUtils]: 33: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:08:50,932 INFO L272 TraceCheckUtils]: 34: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8745#true} is VALID [2022-04-27 21:08:50,932 INFO L290 TraceCheckUtils]: 35: Hoare triple {8745#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8745#true} is VALID [2022-04-27 21:08:50,932 INFO L290 TraceCheckUtils]: 36: Hoare triple {8745#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,932 INFO L290 TraceCheckUtils]: 37: Hoare triple {8745#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:08:50,933 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {8745#true} {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:08:50,933 INFO L290 TraceCheckUtils]: 39: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:08:50,933 INFO L290 TraceCheckUtils]: 40: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {8767#(<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:08:50,934 INFO L290 TraceCheckUtils]: 41: Hoare triple {8767#(<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8768#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:08:50,935 INFO L272 TraceCheckUtils]: 42: Hoare triple {8768#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8769#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:08:50,935 INFO L290 TraceCheckUtils]: 43: Hoare triple {8769#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8770#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:08:50,935 INFO L290 TraceCheckUtils]: 44: Hoare triple {8770#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {8746#false} is VALID [2022-04-27 21:08:50,935 INFO L290 TraceCheckUtils]: 45: Hoare triple {8746#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8746#false} is VALID [2022-04-27 21:08:50,936 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 4 proven. 23 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:08:50,936 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:08:50,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [542537134] [2022-04-27 21:08:50,936 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [542537134] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:08:50,936 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [68515760] [2022-04-27 21:08:50,936 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:08:50,936 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:08:50,936 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:08:50,937 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:08:50,938 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2022-04-27 21:08:50,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:50,992 INFO L263 TraceCheckSpWp]: Trace formula consists of 170 conjuncts, 27 conjunts are in the unsatisfiable core [2022-04-27 21:08:51,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:08:51,006 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:08:51,313 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-27 21:08:51,314 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-27 21:08:52,068 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-27 21:08:52,069 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-27 21:09:02,525 INFO L356 Elim1Store]: treesize reduction 11, result has 8.3 percent of original size [2022-04-27 21:09:02,526 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 36 treesize of output 12 [2022-04-27 21:09:02,619 INFO L272 TraceCheckUtils]: 0: Hoare triple {8745#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L290 TraceCheckUtils]: 1: Hoare triple {8745#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L290 TraceCheckUtils]: 2: Hoare triple {8745#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8745#true} {8745#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L272 TraceCheckUtils]: 4: Hoare triple {8745#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L290 TraceCheckUtils]: 5: Hoare triple {8745#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L290 TraceCheckUtils]: 6: Hoare triple {8745#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L290 TraceCheckUtils]: 7: Hoare triple {8745#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:09:02,619 INFO L290 TraceCheckUtils]: 8: Hoare triple {8745#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8745#true} is VALID [2022-04-27 21:09:02,620 INFO L290 TraceCheckUtils]: 9: Hoare triple {8745#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:09:02,620 INFO L290 TraceCheckUtils]: 10: Hoare triple {8745#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8745#true} is VALID [2022-04-27 21:09:02,620 INFO L290 TraceCheckUtils]: 11: Hoare triple {8745#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:09:02,620 INFO L290 TraceCheckUtils]: 12: Hoare triple {8745#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:02,620 INFO L290 TraceCheckUtils]: 13: Hoare triple {8745#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:02,620 INFO L290 TraceCheckUtils]: 14: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:02,621 INFO L290 TraceCheckUtils]: 15: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:02,621 INFO L290 TraceCheckUtils]: 16: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:02,621 INFO L290 TraceCheckUtils]: 17: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:02,622 INFO L290 TraceCheckUtils]: 18: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:02,622 INFO L290 TraceCheckUtils]: 19: Hoare triple {8751#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8752#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:09:02,624 INFO L290 TraceCheckUtils]: 20: Hoare triple {8752#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8835#(and (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-27 21:09:02,624 INFO L290 TraceCheckUtils]: 21: Hoare triple {8835#(and (<= main_~i~0 1) (<= 1 main_~i~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8835#(and (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-27 21:09:02,625 INFO L290 TraceCheckUtils]: 22: Hoare triple {8835#(and (<= main_~i~0 1) (<= 1 main_~i~0))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8842#(and (<= main_~i~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 1 main_~i~0))} is VALID [2022-04-27 21:09:02,625 INFO L290 TraceCheckUtils]: 23: Hoare triple {8842#(and (<= main_~i~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 1 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8846#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-27 21:09:02,626 INFO L290 TraceCheckUtils]: 24: Hoare triple {8846#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {8850#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} is VALID [2022-04-27 21:09:02,627 INFO L290 TraceCheckUtils]: 25: Hoare triple {8850#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (<= main_~i~0 1) (<= 1 main_~i~0))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {8854#(exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1)))} is VALID [2022-04-27 21:09:02,630 INFO L290 TraceCheckUtils]: 26: Hoare triple {8854#(exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8858#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:09:02,633 INFO L290 TraceCheckUtils]: 27: Hoare triple {8858#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= 1 v_main_~i~0_38) (<= v_main_~i~0_38 1))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8862#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} is VALID [2022-04-27 21:09:02,636 INFO L290 TraceCheckUtils]: 28: Hoare triple {8862#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8862#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} is VALID [2022-04-27 21:09:02,638 INFO L290 TraceCheckUtils]: 29: Hoare triple {8862#(and (exists ((v_main_~i~0_38 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4) 4))) (<= (+ main_~i~0 1) v_main_~i~0_38) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_38 4)))) (<= v_main_~i~0_38 1))) (<= 0 main_~i~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:09:02,663 INFO L290 TraceCheckUtils]: 30: Hoare triple {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:09:02,664 INFO L290 TraceCheckUtils]: 31: Hoare triple {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:09:02,664 INFO L290 TraceCheckUtils]: 32: Hoare triple {8761#(<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:09:02,665 INFO L290 TraceCheckUtils]: 33: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:09:02,666 INFO L272 TraceCheckUtils]: 34: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-27 21:09:02,666 INFO L290 TraceCheckUtils]: 35: Hoare triple {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-27 21:09:02,667 INFO L290 TraceCheckUtils]: 36: Hoare triple {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-27 21:09:02,667 INFO L290 TraceCheckUtils]: 37: Hoare triple {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} is VALID [2022-04-27 21:09:02,667 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {8884#(exists ((|v_main_~#v~0.base_BEFORE_CALL_3| Int) (|v_main_~#v~0.offset_BEFORE_CALL_3| Int)) (<= (+ (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ |v_main_~#v~0.offset_BEFORE_CALL_3| 4)) 1) (select (select |#memory_int| |v_main_~#v~0.base_BEFORE_CALL_3|) (+ 8 |v_main_~#v~0.offset_BEFORE_CALL_3|))))} {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:09:02,668 INFO L290 TraceCheckUtils]: 39: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:09:02,668 INFO L290 TraceCheckUtils]: 40: Hoare triple {8762#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 1) main_~k~0) 0))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {8903#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 2) main_~k~0) 0))} is VALID [2022-04-27 21:09:02,669 INFO L290 TraceCheckUtils]: 41: Hoare triple {8903#(and (<= (+ 1 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8))) (= (+ (- 2) main_~k~0) 0))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8768#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:09:02,670 INFO L272 TraceCheckUtils]: 42: Hoare triple {8768#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8910#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:09:02,670 INFO L290 TraceCheckUtils]: 43: Hoare triple {8910#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8914#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:09:02,670 INFO L290 TraceCheckUtils]: 44: Hoare triple {8914#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {8746#false} is VALID [2022-04-27 21:09:02,670 INFO L290 TraceCheckUtils]: 45: Hoare triple {8746#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8746#false} is VALID [2022-04-27 21:09:02,671 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:09:02,671 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:09:23,178 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 63 [2022-04-27 21:09:23,276 INFO L356 Elim1Store]: treesize reduction 31, result has 24.4 percent of original size [2022-04-27 21:09:23,278 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1679 treesize of output 1549 [2022-04-27 21:09:24,336 INFO L290 TraceCheckUtils]: 45: Hoare triple {8746#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8746#false} is VALID [2022-04-27 21:09:24,336 INFO L290 TraceCheckUtils]: 44: Hoare triple {8914#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {8746#false} is VALID [2022-04-27 21:09:24,337 INFO L290 TraceCheckUtils]: 43: Hoare triple {8910#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8914#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:09:24,337 INFO L272 TraceCheckUtils]: 42: Hoare triple {8930#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8910#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:09:24,338 INFO L290 TraceCheckUtils]: 41: Hoare triple {8934#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8930#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:09:24,339 INFO L290 TraceCheckUtils]: 40: Hoare triple {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [130] L29-2-->L29-3: Formula: (= v_main_~k~0_3 (+ v_main_~k~0_4 1)) InVars {main_~k~0=v_main_~k~0_4} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_3} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {8934#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:09:24,339 INFO L290 TraceCheckUtils]: 39: Hoare triple {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [126] L30-1-->L29-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:09:24,340 INFO L284 TraceCheckUtils]: 38: Hoare quadruple {8745#true} {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [139] __VERIFIER_assertEXIT-->L30-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:09:24,340 INFO L290 TraceCheckUtils]: 37: Hoare triple {8745#true} [136] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,340 INFO L290 TraceCheckUtils]: 36: Hoare triple {8745#true} [132] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_3 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,340 INFO L290 TraceCheckUtils]: 35: Hoare triple {8745#true} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {8745#true} is VALID [2022-04-27 21:09:24,340 INFO L272 TraceCheckUtils]: 34: Hoare triple {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {8745#true} is VALID [2022-04-27 21:09:24,340 INFO L290 TraceCheckUtils]: 33: Hoare triple {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:09:24,341 INFO L290 TraceCheckUtils]: 32: Hoare triple {8963#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {8938#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) 4)))} is VALID [2022-04-27 21:09:24,341 INFO L290 TraceCheckUtils]: 31: Hoare triple {8963#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {8963#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:09:24,341 INFO L290 TraceCheckUtils]: 30: Hoare triple {8963#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8963#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:09:24,342 INFO L290 TraceCheckUtils]: 29: Hoare triple {8973#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {8963#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 8)))} is VALID [2022-04-27 21:09:24,343 INFO L290 TraceCheckUtils]: 28: Hoare triple {8973#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8973#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} is VALID [2022-04-27 21:09:24,343 INFO L290 TraceCheckUtils]: 27: Hoare triple {8980#(or (not |main_#t~short10|) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8973#(forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0))))} is VALID [2022-04-27 21:09:24,344 INFO L290 TraceCheckUtils]: 26: Hoare triple {8984#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8980#(or (not |main_#t~short10|) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} is VALID [2022-04-27 21:09:24,345 INFO L290 TraceCheckUtils]: 25: Hoare triple {8988#(forall ((v_main_~i~0_39 Int)) (or (not (<= 0 v_main_~i~0_39)) (forall ((v_ArrVal_286 Int)) (or (not (<= v_ArrVal_286 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))))) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {8984#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_286 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)))))} is VALID [2022-04-27 21:09:24,346 INFO L290 TraceCheckUtils]: 24: Hoare triple {8992#(forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {8988#(forall ((v_main_~i~0_39 Int)) (or (not (<= 0 v_main_~i~0_39)) (forall ((v_ArrVal_286 Int)) (or (not (<= v_ArrVal_286 main_~key~0)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))))) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} is VALID [2022-04-27 21:09:24,347 INFO L290 TraceCheckUtils]: 23: Hoare triple {8996#(or (forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0)))) (not |main_#t~short10|))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8992#(forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0))))} is VALID [2022-04-27 21:09:24,348 INFO L290 TraceCheckUtils]: 22: Hoare triple {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {8996#(or (forall ((v_main_~i~0_39 Int) (v_ArrVal_286 Int) (v_ArrVal_283 Int)) (or (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_283)) (not (<= 0 v_main_~i~0_39)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 4)) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_283) (+ |main_~#v~0.offset| (* v_main_~i~0_39 4) 4) v_ArrVal_286) (+ |main_~#v~0.offset| 8))) (not (<= v_ArrVal_286 main_~key~0)) (not (<= (+ v_main_~i~0_39 1) main_~i~0)))) (not |main_#t~short10|))} is VALID [2022-04-27 21:09:24,349 INFO L290 TraceCheckUtils]: 21: Hoare triple {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:09:24,349 INFO L290 TraceCheckUtils]: 20: Hoare triple {8753#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {8754#(or (< main_~i~0 1) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:09:24,350 INFO L290 TraceCheckUtils]: 19: Hoare triple {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {8753#(or (= (* main_~j~0 4) 8) (< main_~j~0 2))} is VALID [2022-04-27 21:09:24,350 INFO L290 TraceCheckUtils]: 18: Hoare triple {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-27 21:09:24,351 INFO L290 TraceCheckUtils]: 17: Hoare triple {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-27 21:09:24,351 INFO L290 TraceCheckUtils]: 16: Hoare triple {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-27 21:09:24,351 INFO L290 TraceCheckUtils]: 15: Hoare triple {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-27 21:09:24,352 INFO L290 TraceCheckUtils]: 14: Hoare triple {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-27 21:09:24,352 INFO L290 TraceCheckUtils]: 13: Hoare triple {8745#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {9009#(or (< main_~j~0 1) (= 8 (+ (* main_~j~0 4) 4)))} is VALID [2022-04-27 21:09:24,352 INFO L290 TraceCheckUtils]: 12: Hoare triple {8745#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,352 INFO L290 TraceCheckUtils]: 11: Hoare triple {8745#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:09:24,352 INFO L290 TraceCheckUtils]: 10: Hoare triple {8745#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8745#true} is VALID [2022-04-27 21:09:24,352 INFO L290 TraceCheckUtils]: 9: Hoare triple {8745#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L290 TraceCheckUtils]: 8: Hoare triple {8745#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L290 TraceCheckUtils]: 7: Hoare triple {8745#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L290 TraceCheckUtils]: 6: Hoare triple {8745#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L290 TraceCheckUtils]: 5: Hoare triple {8745#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L272 TraceCheckUtils]: 4: Hoare triple {8745#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {8745#true} {8745#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L290 TraceCheckUtils]: 2: Hoare triple {8745#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L290 TraceCheckUtils]: 1: Hoare triple {8745#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L272 TraceCheckUtils]: 0: Hoare triple {8745#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {8745#true} is VALID [2022-04-27 21:09:24,353 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 2 proven. 16 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:09:24,353 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [68515760] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:09:24,353 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:09:24,353 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 18, 17] total 42 [2022-04-27 21:09:24,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465712801] [2022-04-27 21:09:24,354 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:09:24,354 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 46 [2022-04-27 21:09:24,355 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:09:24,355 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:09:24,440 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 97 edges. 97 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:09:24,440 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 42 states [2022-04-27 21:09:24,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:09:24,440 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2022-04-27 21:09:24,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=199, Invalid=1508, Unknown=15, NotChecked=0, Total=1722 [2022-04-27 21:09:24,441 INFO L87 Difference]: Start difference. First operand 152 states and 178 transitions. Second operand has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:09:36,726 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:09:36,726 INFO L93 Difference]: Finished difference Result 237 states and 280 transitions. [2022-04-27 21:09:36,726 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2022-04-27 21:09:36,727 INFO L78 Accepts]: Start accepts. Automaton has has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) Word has length 46 [2022-04-27 21:09:36,727 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:09:36,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:09:36,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 147 transitions. [2022-04-27 21:09:36,729 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:09:36,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 147 transitions. [2022-04-27 21:09:36,731 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 47 states and 147 transitions. [2022-04-27 21:09:36,847 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 147 edges. 147 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:09:36,850 INFO L225 Difference]: With dead ends: 237 [2022-04-27 21:09:36,850 INFO L226 Difference]: Without dead ends: 235 [2022-04-27 21:09:36,852 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 159 GetRequests, 72 SyntacticMatches, 9 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1708 ImplicationChecksByTransitivity, 38.9s TimeCoverageRelationStatistics Valid=737, Invalid=5564, Unknown=19, NotChecked=0, Total=6320 [2022-04-27 21:09:36,852 INFO L413 NwaCegarLoop]: 45 mSDtfsCounter, 149 mSDsluCounter, 159 mSDsCounter, 0 mSdLazyCounter, 1173 mSolverCounterSat, 102 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 150 SdHoareTripleChecker+Valid, 204 SdHoareTripleChecker+Invalid, 1825 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 102 IncrementalHoareTripleChecker+Valid, 1173 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 550 IncrementalHoareTripleChecker+Unchecked, 1.3s IncrementalHoareTripleChecker+Time [2022-04-27 21:09:36,853 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [150 Valid, 204 Invalid, 1825 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [102 Valid, 1173 Invalid, 0 Unknown, 550 Unchecked, 1.3s Time] [2022-04-27 21:09:36,853 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2022-04-27 21:09:37,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 162. [2022-04-27 21:09:37,120 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:09:37,120 INFO L82 GeneralOperation]: Start isEquivalent. First operand 235 states. Second operand has 162 states, 150 states have (on average 1.2) internal successors, (180), 152 states have internal predecessors, (180), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:09:37,120 INFO L74 IsIncluded]: Start isIncluded. First operand 235 states. Second operand has 162 states, 150 states have (on average 1.2) internal successors, (180), 152 states have internal predecessors, (180), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:09:37,120 INFO L87 Difference]: Start difference. First operand 235 states. Second operand has 162 states, 150 states have (on average 1.2) internal successors, (180), 152 states have internal predecessors, (180), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:09:37,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:09:37,124 INFO L93 Difference]: Finished difference Result 235 states and 278 transitions. [2022-04-27 21:09:37,124 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 278 transitions. [2022-04-27 21:09:37,124 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:09:37,124 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:09:37,125 INFO L74 IsIncluded]: Start isIncluded. First operand has 162 states, 150 states have (on average 1.2) internal successors, (180), 152 states have internal predecessors, (180), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 235 states. [2022-04-27 21:09:37,125 INFO L87 Difference]: Start difference. First operand has 162 states, 150 states have (on average 1.2) internal successors, (180), 152 states have internal predecessors, (180), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 235 states. [2022-04-27 21:09:37,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:09:37,130 INFO L93 Difference]: Finished difference Result 235 states and 278 transitions. [2022-04-27 21:09:37,130 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 278 transitions. [2022-04-27 21:09:37,130 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:09:37,130 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:09:37,130 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:09:37,130 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:09:37,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 162 states, 150 states have (on average 1.2) internal successors, (180), 152 states have internal predecessors, (180), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:09:37,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 191 transitions. [2022-04-27 21:09:37,132 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 191 transitions. Word has length 46 [2022-04-27 21:09:37,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:09:37,133 INFO L495 AbstractCegarLoop]: Abstraction has 162 states and 191 transitions. [2022-04-27 21:09:37,133 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 42 states, 40 states have (on average 2.1) internal successors, (84), 39 states have internal predecessors, (84), 5 states have call successors, (9), 5 states have call predecessors, (9), 2 states have return successors, (4), 3 states have call predecessors, (4), 3 states have call successors, (4) [2022-04-27 21:09:37,133 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 191 transitions. [2022-04-27 21:09:37,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-04-27 21:09:37,134 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:09:37,134 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:09:37,153 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Forceful destruction successful, exit code 0 [2022-04-27 21:09:37,347 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 13 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable14 [2022-04-27 21:09:37,347 INFO L420 AbstractCegarLoop]: === Iteration 16 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:09:37,348 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:09:37,348 INFO L85 PathProgramCache]: Analyzing trace with hash -2059580614, now seen corresponding path program 2 times [2022-04-27 21:09:37,348 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:09:37,348 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1257687004] [2022-04-27 21:09:37,348 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:09:37,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:09:37,381 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:09:38,170 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:09:38,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:09:38,174 INFO L290 TraceCheckUtils]: 0: Hoare triple {10177#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {10153#true} is VALID [2022-04-27 21:09:38,174 INFO L290 TraceCheckUtils]: 1: Hoare triple {10153#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:38,174 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {10153#true} {10153#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:38,174 INFO L272 TraceCheckUtils]: 0: Hoare triple {10153#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10177#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:09:38,175 INFO L290 TraceCheckUtils]: 1: Hoare triple {10177#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {10153#true} is VALID [2022-04-27 21:09:38,175 INFO L290 TraceCheckUtils]: 2: Hoare triple {10153#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:38,175 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {10153#true} {10153#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:38,175 INFO L272 TraceCheckUtils]: 4: Hoare triple {10153#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:38,175 INFO L290 TraceCheckUtils]: 5: Hoare triple {10153#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {10158#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:09:38,176 INFO L290 TraceCheckUtils]: 6: Hoare triple {10158#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10158#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:09:38,176 INFO L290 TraceCheckUtils]: 7: Hoare triple {10158#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:38,177 INFO L290 TraceCheckUtils]: 8: Hoare triple {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:38,177 INFO L290 TraceCheckUtils]: 9: Hoare triple {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10160#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} is VALID [2022-04-27 21:09:38,178 INFO L290 TraceCheckUtils]: 10: Hoare triple {10160#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10160#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} is VALID [2022-04-27 21:09:38,178 INFO L290 TraceCheckUtils]: 11: Hoare triple {10160#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10161#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| (* main_~j~0 4)) 0)))} is VALID [2022-04-27 21:09:38,178 INFO L290 TraceCheckUtils]: 12: Hoare triple {10161#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| (* main_~j~0 4)) 0)))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:38,179 INFO L290 TraceCheckUtils]: 13: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:38,179 INFO L290 TraceCheckUtils]: 14: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:38,179 INFO L290 TraceCheckUtils]: 15: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:38,180 INFO L290 TraceCheckUtils]: 16: Hoare triple {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10163#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:09:38,181 INFO L290 TraceCheckUtils]: 17: Hoare triple {10163#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10164#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-27 21:09:38,181 INFO L290 TraceCheckUtils]: 18: Hoare triple {10164#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10165#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:09:38,182 INFO L290 TraceCheckUtils]: 19: Hoare triple {10165#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10166#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:09:38,183 INFO L290 TraceCheckUtils]: 20: Hoare triple {10166#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10167#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,183 INFO L290 TraceCheckUtils]: 21: Hoare triple {10167#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10168#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-27 21:09:38,184 INFO L290 TraceCheckUtils]: 22: Hoare triple {10168#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:09:38,184 INFO L290 TraceCheckUtils]: 23: Hoare triple {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:09:38,185 INFO L290 TraceCheckUtils]: 24: Hoare triple {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:09:38,185 INFO L290 TraceCheckUtils]: 25: Hoare triple {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:09:38,186 INFO L290 TraceCheckUtils]: 26: Hoare triple {10169#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,186 INFO L290 TraceCheckUtils]: 27: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,187 INFO L290 TraceCheckUtils]: 28: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,187 INFO L290 TraceCheckUtils]: 29: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,188 INFO L290 TraceCheckUtils]: 30: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,188 INFO L290 TraceCheckUtils]: 31: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,188 INFO L290 TraceCheckUtils]: 32: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {10171#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,189 INFO L290 TraceCheckUtils]: 33: Hoare triple {10171#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,190 INFO L290 TraceCheckUtils]: 34: Hoare triple {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,190 INFO L290 TraceCheckUtils]: 35: Hoare triple {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,191 INFO L290 TraceCheckUtils]: 36: Hoare triple {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,192 INFO L290 TraceCheckUtils]: 37: Hoare triple {10172#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,192 INFO L290 TraceCheckUtils]: 38: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,192 INFO L290 TraceCheckUtils]: 39: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:38,193 INFO L290 TraceCheckUtils]: 40: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {10173#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:09:38,193 INFO L290 TraceCheckUtils]: 41: Hoare triple {10173#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {10174#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:09:38,194 INFO L272 TraceCheckUtils]: 42: Hoare triple {10174#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {10175#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:09:38,194 INFO L290 TraceCheckUtils]: 43: Hoare triple {10175#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {10176#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:09:38,194 INFO L290 TraceCheckUtils]: 44: Hoare triple {10176#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {10154#false} is VALID [2022-04-27 21:09:38,195 INFO L290 TraceCheckUtils]: 45: Hoare triple {10154#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10154#false} is VALID [2022-04-27 21:09:38,195 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 3 proven. 41 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2022-04-27 21:09:38,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:09:38,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1257687004] [2022-04-27 21:09:38,195 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1257687004] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:09:38,195 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1857759323] [2022-04-27 21:09:38,195 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:09:38,195 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:09:38,195 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:09:38,196 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:09:38,197 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2022-04-27 21:09:38,260 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:09:38,260 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:09:38,261 INFO L263 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 27 conjunts are in the unsatisfiable core [2022-04-27 21:09:38,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:09:38,276 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:09:38,606 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:38,606 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 21:09:38,825 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:38,826 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:38,827 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:38,829 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:09:38,829 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 32 [2022-04-27 21:09:39,033 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:39,034 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:39,035 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:09:39,037 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:09:39,037 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 30 treesize of output 32 [2022-04-27 21:09:39,122 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:09:39,122 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 21:09:39,204 INFO L272 TraceCheckUtils]: 0: Hoare triple {10153#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:39,205 INFO L290 TraceCheckUtils]: 1: Hoare triple {10153#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {10153#true} is VALID [2022-04-27 21:09:39,205 INFO L290 TraceCheckUtils]: 2: Hoare triple {10153#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:39,205 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {10153#true} {10153#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:39,205 INFO L272 TraceCheckUtils]: 4: Hoare triple {10153#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:09:39,205 INFO L290 TraceCheckUtils]: 5: Hoare triple {10153#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,205 INFO L290 TraceCheckUtils]: 6: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,206 INFO L290 TraceCheckUtils]: 7: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,206 INFO L290 TraceCheckUtils]: 8: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,206 INFO L290 TraceCheckUtils]: 9: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,207 INFO L290 TraceCheckUtils]: 10: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,207 INFO L290 TraceCheckUtils]: 11: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,207 INFO L290 TraceCheckUtils]: 12: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,207 INFO L290 TraceCheckUtils]: 13: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,208 INFO L290 TraceCheckUtils]: 14: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {10162#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:09:39,208 INFO L290 TraceCheckUtils]: 15: Hoare triple {10162#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:39,208 INFO L290 TraceCheckUtils]: 16: Hoare triple {10159#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10229#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:39,209 INFO L290 TraceCheckUtils]: 17: Hoare triple {10229#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10229#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:09:39,210 INFO L290 TraceCheckUtils]: 18: Hoare triple {10229#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) main_~i~0) (<= 1 main_~j~0) (<= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10165#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:09:39,210 INFO L290 TraceCheckUtils]: 19: Hoare triple {10165#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10166#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:09:39,211 INFO L290 TraceCheckUtils]: 20: Hoare triple {10166#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10167#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,212 INFO L290 TraceCheckUtils]: 21: Hoare triple {10167#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10245#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,212 INFO L290 TraceCheckUtils]: 22: Hoare triple {10245#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,213 INFO L290 TraceCheckUtils]: 23: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,213 INFO L290 TraceCheckUtils]: 24: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,214 INFO L290 TraceCheckUtils]: 25: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,214 INFO L290 TraceCheckUtils]: 26: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,215 INFO L290 TraceCheckUtils]: 27: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,215 INFO L290 TraceCheckUtils]: 28: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,216 INFO L290 TraceCheckUtils]: 29: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,216 INFO L290 TraceCheckUtils]: 30: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,217 INFO L290 TraceCheckUtils]: 31: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,217 INFO L290 TraceCheckUtils]: 32: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {10171#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,218 INFO L290 TraceCheckUtils]: 33: Hoare triple {10171#(and (= |main_~#v~0.offset| 0) (<= (+ (div (* (- 1) |main_~#v~0.offset|) 4) 2) main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,218 INFO L290 TraceCheckUtils]: 34: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,218 INFO L290 TraceCheckUtils]: 35: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,219 INFO L290 TraceCheckUtils]: 36: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,220 INFO L290 TraceCheckUtils]: 37: Hoare triple {10249#(and (= |main_~#v~0.offset| 0) (<= 1 main_~i~0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,220 INFO L290 TraceCheckUtils]: 38: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,220 INFO L290 TraceCheckUtils]: 39: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:09:39,221 INFO L290 TraceCheckUtils]: 40: Hoare triple {10170#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {10173#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:09:39,221 INFO L290 TraceCheckUtils]: 41: Hoare triple {10173#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {10174#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:09:39,222 INFO L272 TraceCheckUtils]: 42: Hoare triple {10174#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {10310#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:09:39,222 INFO L290 TraceCheckUtils]: 43: Hoare triple {10310#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {10314#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:09:39,222 INFO L290 TraceCheckUtils]: 44: Hoare triple {10314#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {10154#false} is VALID [2022-04-27 21:09:39,223 INFO L290 TraceCheckUtils]: 45: Hoare triple {10154#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10154#false} is VALID [2022-04-27 21:09:39,223 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 3 proven. 21 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-04-27 21:09:39,223 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:10:13,687 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 51 [2022-04-27 21:10:13,768 INFO L356 Elim1Store]: treesize reduction 16, result has 56.8 percent of original size [2022-04-27 21:10:13,768 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 1429 treesize of output 1347 [2022-04-27 21:10:23,410 INFO L290 TraceCheckUtils]: 45: Hoare triple {10154#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10154#false} is VALID [2022-04-27 21:10:23,410 INFO L290 TraceCheckUtils]: 44: Hoare triple {10314#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {10154#false} is VALID [2022-04-27 21:10:23,410 INFO L290 TraceCheckUtils]: 43: Hoare triple {10310#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {10314#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:10:23,411 INFO L272 TraceCheckUtils]: 42: Hoare triple {10174#(<= |main_#t~mem13| |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {10310#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:10:23,411 INFO L290 TraceCheckUtils]: 41: Hoare triple {10333#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {10174#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:10:23,412 INFO L290 TraceCheckUtils]: 40: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {10333#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:10:23,412 INFO L290 TraceCheckUtils]: 39: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,412 INFO L290 TraceCheckUtils]: 38: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,413 INFO L290 TraceCheckUtils]: 37: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,413 INFO L290 TraceCheckUtils]: 36: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,414 INFO L290 TraceCheckUtils]: 35: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,414 INFO L290 TraceCheckUtils]: 34: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,415 INFO L290 TraceCheckUtils]: 33: Hoare triple {10360#(forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))) (not (<= main_~i~0 (+ v_main_~i~0_43 1)))))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,416 INFO L290 TraceCheckUtils]: 32: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [129] L23-->L23-2: Formula: (not (< v_main_~i~0_6 2)) InVars {main_~i~0=v_main_~i~0_6} OutVars{main_~i~0=v_main_~i~0_6} AuxVars[] AssignedVars[] {10360#(forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))) (not (<= main_~i~0 (+ v_main_~i~0_43 1)))))} is VALID [2022-04-27 21:10:23,416 INFO L290 TraceCheckUtils]: 31: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,416 INFO L290 TraceCheckUtils]: 30: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,416 INFO L290 TraceCheckUtils]: 29: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,416 INFO L290 TraceCheckUtils]: 28: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,417 INFO L290 TraceCheckUtils]: 27: Hoare triple {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,417 INFO L290 TraceCheckUtils]: 26: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10337#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:10:23,417 INFO L290 TraceCheckUtils]: 25: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,418 INFO L290 TraceCheckUtils]: 24: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,418 INFO L290 TraceCheckUtils]: 23: Hoare triple {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:23,420 INFO L290 TraceCheckUtils]: 22: Hoare triple {10394#(forall ((v_main_~i~0_45 Int)) (or (not (<= main_~j~0 (+ v_main_~i~0_45 1))) (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10347#(forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:10:24,228 WARN L290 TraceCheckUtils]: 21: Hoare triple {10398#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))) (< v_main_~i~0_45 main_~j~0)))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {10394#(forall ((v_main_~i~0_45 Int)) (or (not (<= main_~j~0 (+ v_main_~i~0_45 1))) (forall ((v_ArrVal_324 Int)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} is UNKNOWN [2022-04-27 21:10:25,496 WARN L290 TraceCheckUtils]: 20: Hoare triple {10402#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {10398#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))) (< v_main_~i~0_45 main_~j~0)))} is UNKNOWN [2022-04-27 21:10:26,567 WARN L290 TraceCheckUtils]: 19: Hoare triple {10406#(or |main_#t~short10| (forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10402#(forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4)))))} is UNKNOWN [2022-04-27 21:10:26,569 INFO L290 TraceCheckUtils]: 18: Hoare triple {10410#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {10406#(or |main_#t~short10| (forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (< v_main_~i~0_45 main_~j~0) (not (<= main_~key~0 v_ArrVal_319)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_319) (+ |main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-27 21:10:26,569 INFO L290 TraceCheckUtils]: 17: Hoare triple {10410#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {10410#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:10:26,569 INFO L290 TraceCheckUtils]: 16: Hoare triple {10417#(= (* main_~j~0 4) 4)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {10410#(and (< 0 main_~j~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 15: Hoare triple {10153#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {10417#(= (* main_~j~0 4) 4)} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 14: Hoare triple {10153#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 13: Hoare triple {10153#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 12: Hoare triple {10153#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 11: Hoare triple {10153#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 10: Hoare triple {10153#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 9: Hoare triple {10153#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 8: Hoare triple {10153#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 7: Hoare triple {10153#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 6: Hoare triple {10153#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L290 TraceCheckUtils]: 5: Hoare triple {10153#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {10153#true} is VALID [2022-04-27 21:10:26,570 INFO L272 TraceCheckUtils]: 4: Hoare triple {10153#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:10:26,571 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {10153#true} {10153#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:10:26,571 INFO L290 TraceCheckUtils]: 2: Hoare triple {10153#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:10:26,571 INFO L290 TraceCheckUtils]: 1: Hoare triple {10153#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {10153#true} is VALID [2022-04-27 21:10:26,571 INFO L272 TraceCheckUtils]: 0: Hoare triple {10153#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {10153#true} is VALID [2022-04-27 21:10:26,571 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 3 proven. 21 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2022-04-27 21:10:26,571 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1857759323] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:10:26,571 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:10:26,571 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 16, 15] total 37 [2022-04-27 21:10:26,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180751268] [2022-04-27 21:10:26,571 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:10:26,580 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 46 [2022-04-27 21:10:26,585 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:10:26,585 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:10:29,953 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 88 edges. 85 inductive. 0 not inductive. 3 times theorem prover too weak to decide inductivity. [2022-04-27 21:10:29,953 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 37 states [2022-04-27 21:10:29,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:10:29,954 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2022-04-27 21:10:29,954 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=1141, Unknown=20, NotChecked=0, Total=1332 [2022-04-27 21:10:29,954 INFO L87 Difference]: Start difference. First operand 162 states and 191 transitions. Second operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:10:38,485 WARN L232 SmtUtils]: Spent 6.82s on a formula simplification. DAG size of input: 55 DAG size of output: 28 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 21:10:47,541 WARN L232 SmtUtils]: Spent 8.85s on a formula simplification. DAG size of input: 58 DAG size of output: 31 (called from [L 360] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2022-04-27 21:10:48,724 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (<= 2 c_main_~j~0) (<= 1 c_main_~i~0) (let ((.cse0 (select |c_#memory_int| |c_main_~#v~0.base|))) (<= (select .cse0 0) (select .cse0 (+ |c_main_~#v~0.offset| 4)))) (forall ((v_ArrVal_324 Int) (v_main_~i~0_45 Int) (v_ArrVal_319 Int)) (or (let ((.cse1 (store (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ (* c_main_~i~0 4) |c_main_~#v~0.offset| 4) v_ArrVal_319) (+ |c_main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324))) (<= (select .cse1 |c_main_~#v~0.offset|) (select .cse1 (+ |c_main_~#v~0.offset| 4)))) (< v_main_~i~0_45 c_main_~j~0) (not (<= c_main_~key~0 v_ArrVal_319)))) (= |c_main_~#v~0.offset| 0) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 21:10:56,934 WARN L833 $PredicateComparison]: unable to prove that (and (let ((.cse0 (select |c_#memory_int| |c_main_~#v~0.base|)) (.cse1 (* 4 c_main_~k~0))) (<= (select .cse0 (+ |c_main_~#v~0.offset| (- 4) .cse1)) (select .cse0 (+ |c_main_~#v~0.offset| .cse1)))) (forall ((v_main_~i~0_45 Int)) (or (not (<= c_main_~j~0 (+ v_main_~i~0_45 1))) (forall ((v_ArrVal_324 Int)) (let ((.cse2 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_45 4) 4) v_ArrVal_324))) (<= (select .cse2 |c_main_~#v~0.offset|) (select .cse2 (+ |c_main_~#v~0.offset| 4)))))))) is different from false [2022-04-27 21:11:59,102 WARN L833 $PredicateComparison]: unable to prove that (and (= |c_#NULL.base| |c_old(#NULL.base)|) (forall ((v_main_~i~0_43 Int)) (or (forall ((v_ArrVal_324 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_43 4) 4) v_ArrVal_324))) (<= (select .cse0 |c_main_~#v~0.offset|) (select .cse0 (+ |c_main_~#v~0.offset| 4))))) (not (<= c_main_~i~0 (+ v_main_~i~0_43 1))))) (= |c_#NULL.offset| |c_old(#NULL.offset)|)) is different from false [2022-04-27 21:12:01,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:01,572 INFO L93 Difference]: Finished difference Result 295 states and 357 transitions. [2022-04-27 21:12:01,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2022-04-27 21:12:01,572 INFO L78 Accepts]: Start accepts. Automaton has has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 46 [2022-04-27 21:12:01,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:12:01,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:01,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 178 transitions. [2022-04-27 21:12:01,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:01,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 178 transitions. [2022-04-27 21:12:01,576 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 49 states and 178 transitions. [2022-04-27 21:12:04,385 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 178 edges. 176 inductive. 0 not inductive. 2 times theorem prover too weak to decide inductivity. [2022-04-27 21:12:04,389 INFO L225 Difference]: With dead ends: 295 [2022-04-27 21:12:04,389 INFO L226 Difference]: Without dead ends: 293 [2022-04-27 21:12:04,390 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 77 SyntacticMatches, 14 SemanticMatches, 72 ConstructedPredicates, 3 IntricatePredicates, 0 DeprecatedPredicates, 1698 ImplicationChecksByTransitivity, 102.2s TimeCoverageRelationStatistics Valid=674, Invalid=4270, Unknown=38, NotChecked=420, Total=5402 [2022-04-27 21:12:04,390 INFO L413 NwaCegarLoop]: 15 mSDtfsCounter, 219 mSDsluCounter, 97 mSDsCounter, 0 mSdLazyCounter, 810 mSolverCounterSat, 153 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 221 SdHoareTripleChecker+Valid, 112 SdHoareTripleChecker+Invalid, 1386 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 153 IncrementalHoareTripleChecker+Valid, 810 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 423 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:12:04,390 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [221 Valid, 112 Invalid, 1386 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [153 Valid, 810 Invalid, 0 Unknown, 423 Unchecked, 1.1s Time] [2022-04-27 21:12:04,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 293 states. [2022-04-27 21:12:04,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 293 to 188. [2022-04-27 21:12:04,739 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:12:04,739 INFO L82 GeneralOperation]: Start isEquivalent. First operand 293 states. Second operand has 188 states, 176 states have (on average 1.2215909090909092) internal successors, (215), 178 states have internal predecessors, (215), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:12:04,740 INFO L74 IsIncluded]: Start isIncluded. First operand 293 states. Second operand has 188 states, 176 states have (on average 1.2215909090909092) internal successors, (215), 178 states have internal predecessors, (215), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:12:04,740 INFO L87 Difference]: Start difference. First operand 293 states. Second operand has 188 states, 176 states have (on average 1.2215909090909092) internal successors, (215), 178 states have internal predecessors, (215), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:12:04,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:04,746 INFO L93 Difference]: Finished difference Result 293 states and 355 transitions. [2022-04-27 21:12:04,746 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 355 transitions. [2022-04-27 21:12:04,746 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:12:04,746 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:12:04,747 INFO L74 IsIncluded]: Start isIncluded. First operand has 188 states, 176 states have (on average 1.2215909090909092) internal successors, (215), 178 states have internal predecessors, (215), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 293 states. [2022-04-27 21:12:04,747 INFO L87 Difference]: Start difference. First operand has 188 states, 176 states have (on average 1.2215909090909092) internal successors, (215), 178 states have internal predecessors, (215), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) Second operand 293 states. [2022-04-27 21:12:04,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:12:04,752 INFO L93 Difference]: Finished difference Result 293 states and 355 transitions. [2022-04-27 21:12:04,753 INFO L276 IsEmpty]: Start isEmpty. Operand 293 states and 355 transitions. [2022-04-27 21:12:04,753 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:12:04,753 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:12:04,753 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:12:04,753 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:12:04,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 188 states, 176 states have (on average 1.2215909090909092) internal successors, (215), 178 states have internal predecessors, (215), 6 states have call successors, (6), 6 states have call predecessors, (6), 5 states have return successors, (5), 3 states have call predecessors, (5), 5 states have call successors, (5) [2022-04-27 21:12:04,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 226 transitions. [2022-04-27 21:12:04,756 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 226 transitions. Word has length 46 [2022-04-27 21:12:04,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:12:04,757 INFO L495 AbstractCegarLoop]: Abstraction has 188 states and 226 transitions. [2022-04-27 21:12:04,757 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 34 states have internal predecessors, (82), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:12:04,757 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 226 transitions. [2022-04-27 21:12:04,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2022-04-27 21:12:04,757 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:12:04,757 INFO L195 NwaCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:12:04,774 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2022-04-27 21:12:04,974 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 14 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable15 [2022-04-27 21:12:04,974 INFO L420 AbstractCegarLoop]: === Iteration 17 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:12:04,974 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:12:04,974 INFO L85 PathProgramCache]: Analyzing trace with hash -1570483864, now seen corresponding path program 3 times [2022-04-27 21:12:04,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:12:04,974 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1995341930] [2022-04-27 21:12:04,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:12:04,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:12:05,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:05,908 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:12:05,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:05,911 INFO L290 TraceCheckUtils]: 0: Hoare triple {11803#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {11775#true} is VALID [2022-04-27 21:12:05,912 INFO L290 TraceCheckUtils]: 1: Hoare triple {11775#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:05,912 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {11775#true} {11775#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:05,912 INFO L272 TraceCheckUtils]: 0: Hoare triple {11775#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11803#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:12:05,912 INFO L290 TraceCheckUtils]: 1: Hoare triple {11803#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {11775#true} is VALID [2022-04-27 21:12:05,912 INFO L290 TraceCheckUtils]: 2: Hoare triple {11775#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:05,912 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {11775#true} {11775#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:05,912 INFO L272 TraceCheckUtils]: 4: Hoare triple {11775#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:05,913 INFO L290 TraceCheckUtils]: 5: Hoare triple {11775#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {11780#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:12:05,913 INFO L290 TraceCheckUtils]: 6: Hoare triple {11780#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11780#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:12:05,914 INFO L290 TraceCheckUtils]: 7: Hoare triple {11780#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11781#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:12:05,914 INFO L290 TraceCheckUtils]: 8: Hoare triple {11781#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11781#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:12:05,915 INFO L290 TraceCheckUtils]: 9: Hoare triple {11781#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11782#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:12:05,915 INFO L290 TraceCheckUtils]: 10: Hoare triple {11782#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11782#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:12:05,916 INFO L290 TraceCheckUtils]: 11: Hoare triple {11782#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2) (<= 2 main_~j~0))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11783#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-27 21:12:05,916 INFO L290 TraceCheckUtils]: 12: Hoare triple {11783#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11783#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} is VALID [2022-04-27 21:12:05,916 INFO L290 TraceCheckUtils]: 13: Hoare triple {11783#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= main_~j~0 3))} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11784#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:12:05,917 INFO L290 TraceCheckUtils]: 14: Hoare triple {11784#(= |main_~#v~0.offset| 0)} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {11784#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:12:05,917 INFO L290 TraceCheckUtils]: 15: Hoare triple {11784#(= |main_~#v~0.offset| 0)} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {11781#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:12:05,918 INFO L290 TraceCheckUtils]: 16: Hoare triple {11781#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11785#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 21:12:05,918 INFO L290 TraceCheckUtils]: 17: Hoare triple {11785#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (or (<= (+ main_~i~0 1) 0) (= 0 (* main_~i~0 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11786#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} is VALID [2022-04-27 21:12:05,919 INFO L290 TraceCheckUtils]: 18: Hoare triple {11786#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (= 0 (* main_~i~0 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11787#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (<= 0 main_~i~0))} is VALID [2022-04-27 21:12:05,920 INFO L290 TraceCheckUtils]: 19: Hoare triple {11787#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (and (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)))) (<= 0 main_~i~0))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11788#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:12:05,920 INFO L290 TraceCheckUtils]: 20: Hoare triple {11788#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {11789#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:12:05,921 INFO L290 TraceCheckUtils]: 21: Hoare triple {11789#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= 0 (* main_~i~0 4)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {11790#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} is VALID [2022-04-27 21:12:05,921 INFO L290 TraceCheckUtils]: 22: Hoare triple {11790#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 main_~i~0)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11791#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} is VALID [2022-04-27 21:12:05,922 INFO L290 TraceCheckUtils]: 23: Hoare triple {11791#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))) |main_#t~short10|))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {11792#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,922 INFO L290 TraceCheckUtils]: 24: Hoare triple {11792#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11792#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,923 INFO L290 TraceCheckUtils]: 25: Hoare triple {11792#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11793#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,924 INFO L290 TraceCheckUtils]: 26: Hoare triple {11793#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11794#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-27 21:12:05,924 INFO L290 TraceCheckUtils]: 27: Hoare triple {11794#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:12:05,925 INFO L290 TraceCheckUtils]: 28: Hoare triple {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:12:05,925 INFO L290 TraceCheckUtils]: 29: Hoare triple {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:12:05,926 INFO L290 TraceCheckUtils]: 30: Hoare triple {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:12:05,927 INFO L290 TraceCheckUtils]: 31: Hoare triple {11795#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= main_~j~0 2) (<= (+ main_~i~0 1) main_~j~0) (= 4 (* main_~i~0 4)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11794#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} is VALID [2022-04-27 21:12:05,927 INFO L290 TraceCheckUtils]: 32: Hoare triple {11794#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11796#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= main_~j~0 3))} is VALID [2022-04-27 21:12:05,928 INFO L290 TraceCheckUtils]: 33: Hoare triple {11796#(and (= |main_~#v~0.offset| 0) (<= 3 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= main_~j~0 3))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,929 INFO L290 TraceCheckUtils]: 34: Hoare triple {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,929 INFO L290 TraceCheckUtils]: 35: Hoare triple {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,930 INFO L290 TraceCheckUtils]: 36: Hoare triple {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,931 INFO L290 TraceCheckUtils]: 37: Hoare triple {11797#(and (= |main_~#v~0.offset| 0) (not (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 7)) (<= (+ |main_~#v~0.offset| (* main_~i~0 4)) 8) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11798#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,931 INFO L290 TraceCheckUtils]: 38: Hoare triple {11798#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11798#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,932 INFO L290 TraceCheckUtils]: 39: Hoare triple {11798#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {11798#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:12:05,932 INFO L290 TraceCheckUtils]: 40: Hoare triple {11798#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {11799#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:12:05,933 INFO L290 TraceCheckUtils]: 41: Hoare triple {11799#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {11800#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:12:05,933 INFO L272 TraceCheckUtils]: 42: Hoare triple {11800#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {11801#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:12:05,934 INFO L290 TraceCheckUtils]: 43: Hoare triple {11801#(not (= |__VERIFIER_assert_#in~cond| 0))} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {11802#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:12:05,934 INFO L290 TraceCheckUtils]: 44: Hoare triple {11802#(not (= __VERIFIER_assert_~cond 0))} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {11776#false} is VALID [2022-04-27 21:12:05,934 INFO L290 TraceCheckUtils]: 45: Hoare triple {11776#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11776#false} is VALID [2022-04-27 21:12:05,934 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:12:05,934 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:12:05,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1995341930] [2022-04-27 21:12:05,935 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1995341930] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:12:05,935 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1959087307] [2022-04-27 21:12:05,935 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2022-04-27 21:12:05,935 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:12:05,935 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:12:05,936 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:12:05,937 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2022-04-27 21:12:06,034 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2022-04-27 21:12:06,034 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:12:06,035 INFO L263 TraceCheckSpWp]: Trace formula consists of 176 conjuncts, 33 conjunts are in the unsatisfiable core [2022-04-27 21:12:06,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:12:06,052 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:12:06,328 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-27 21:12:06,328 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-27 21:12:06,680 INFO L356 Elim1Store]: treesize reduction 109, result has 9.2 percent of original size [2022-04-27 21:12:06,681 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 30 [2022-04-27 21:12:07,193 INFO L356 Elim1Store]: treesize reduction 96, result has 20.7 percent of original size [2022-04-27 21:12:07,194 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 37 treesize of output 39 [2022-04-27 21:12:07,798 INFO L356 Elim1Store]: treesize reduction 88, result has 20.0 percent of original size [2022-04-27 21:12:07,798 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 37 [2022-04-27 21:12:08,199 INFO L356 Elim1Store]: treesize reduction 36, result has 7.7 percent of original size [2022-04-27 21:12:08,200 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2022-04-27 21:12:08,330 INFO L272 TraceCheckUtils]: 0: Hoare triple {11775#true} [97] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:08,330 INFO L290 TraceCheckUtils]: 1: Hoare triple {11775#true} [99] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {11775#true} is VALID [2022-04-27 21:12:08,330 INFO L290 TraceCheckUtils]: 2: Hoare triple {11775#true} [102] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:08,330 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {11775#true} {11775#true} [137] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:08,330 INFO L272 TraceCheckUtils]: 4: Hoare triple {11775#true} [98] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:08,330 INFO L290 TraceCheckUtils]: 5: Hoare triple {11775#true} [101] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_2| 1)) (= v_main_~j~0_1 0) (= |v_main_~#v~0.offset_2| 0) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_2|) (= |v_#length_1| (store |v_#length_2| |v_main_~#v~0.base_2| (* (mod v_main_~SIZE~0_2 4294967296) 4))) (= (select |v_#valid_2| |v_main_~#v~0.base_2|) 0) (not (= |v_main_~#v~0.base_2| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_2)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_2|, main_~SIZE~0=v_main_~SIZE~0_2, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_2, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_2|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {11775#true} is VALID [2022-04-27 21:12:08,330 INFO L290 TraceCheckUtils]: 6: Hoare triple {11775#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 7: Hoare triple {11775#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 8: Hoare triple {11775#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 9: Hoare triple {11775#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 10: Hoare triple {11775#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 11: Hoare triple {11775#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 12: Hoare triple {11775#true} [105] L17-3-->L17-2: Formula: (and (= (store |v_#memory_int_3| |v_main_~#v~0.base_5| (store (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_5|) |v_main_#t~nondet6_2|)) |v_#memory_int_2|) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_4 4294967296)) (<= |v_main_#t~nondet6_2| 2147483647) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_4, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_3|, main_~#v~0.offset=|v_main_~#v~0.offset_5|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_2|, main_~SIZE~0=v_main_~SIZE~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 13: Hoare triple {11775#true} [107] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 14: Hoare triple {11775#true} [104] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_3 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_3, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {11775#true} is VALID [2022-04-27 21:12:08,331 INFO L290 TraceCheckUtils]: 15: Hoare triple {11775#true} [106] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {11852#(= main_~j~0 1)} is VALID [2022-04-27 21:12:08,332 INFO L290 TraceCheckUtils]: 16: Hoare triple {11852#(= main_~j~0 1)} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11856#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-27 21:12:08,332 INFO L290 TraceCheckUtils]: 17: Hoare triple {11856#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11856#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-27 21:12:08,333 INFO L290 TraceCheckUtils]: 18: Hoare triple {11856#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11863#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} is VALID [2022-04-27 21:12:08,333 INFO L290 TraceCheckUtils]: 19: Hoare triple {11863#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)))} [124] L22-3-->L23: Formula: |v_main_#t~short10_8| InVars {main_#t~short10=|v_main_#t~short10_8|} OutVars{main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11867#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:12:08,334 INFO L290 TraceCheckUtils]: 20: Hoare triple {11867#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} [128] L23-->L23-2: Formula: (and (= (store |v_#memory_int_7| |v_main_~#v~0.base_8| (let ((.cse0 (select |v_#memory_int_7| |v_main_~#v~0.base_8|)) (.cse1 (* v_main_~i~0_5 4))) (store .cse0 (+ |v_main_~#v~0.offset_8| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_8| .cse1))))) |v_#memory_int_6|) (< v_main_~i~0_5 2)) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_6|, main_~i~0=v_main_~i~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_8|, main_#t~mem11=|v_main_#t~mem11_1|} AuxVars[] AssignedVars[main_#t~mem11, #memory_int] {11871#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:12:08,335 INFO L290 TraceCheckUtils]: 21: Hoare triple {11871#(and (= main_~j~0 1) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)))) (= main_~j~0 (+ main_~i~0 1)))} [133] L23-2-->L22-5: Formula: (= v_main_~i~0_7 (+ (- 1) v_main_~i~0_8)) InVars {main_~i~0=v_main_~i~0_8} OutVars{main_~i~0=v_main_~i~0_7} AuxVars[] AssignedVars[main_~i~0] {11875#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 21:12:08,335 INFO L290 TraceCheckUtils]: 22: Hoare triple {11875#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11879#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:12:08,336 INFO L290 TraceCheckUtils]: 23: Hoare triple {11879#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [119] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {11879#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:12:08,336 INFO L290 TraceCheckUtils]: 24: Hoare triple {11879#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11886#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 21:12:08,337 INFO L290 TraceCheckUtils]: 25: Hoare triple {11886#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 2)))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11890#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} is VALID [2022-04-27 21:12:08,339 INFO L290 TraceCheckUtils]: 26: Hoare triple {11890#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11894#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-27 21:12:08,342 INFO L290 TraceCheckUtils]: 27: Hoare triple {11894#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-27 21:12:08,344 INFO L290 TraceCheckUtils]: 28: Hoare triple {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-27 21:12:08,346 INFO L290 TraceCheckUtils]: 29: Hoare triple {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-27 21:12:08,347 INFO L290 TraceCheckUtils]: 30: Hoare triple {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-27 21:12:08,350 INFO L290 TraceCheckUtils]: 31: Hoare triple {11898#(and (= (+ (- 1) main_~j~0) main_~i~0) (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11894#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} is VALID [2022-04-27 21:12:08,350 INFO L290 TraceCheckUtils]: 32: Hoare triple {11894#(and (= (+ (- 1) main_~j~0) 1) (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11914#(and (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))) (<= 3 main_~j~0))} is VALID [2022-04-27 21:12:08,353 INFO L290 TraceCheckUtils]: 33: Hoare triple {11914#(and (exists ((main_~i~0 Int)) (and (not (<= 0 main_~i~0)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))) (<= 3 main_~j~0))} [110] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_6 4294967296)) (= v_main_~key~0_2 (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_6|))) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, #memory_int=|v_#memory_int_4|, main_~SIZE~0=v_main_~SIZE~0_6, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_~SIZE~0=v_main_~SIZE~0_6, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_4|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_6|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-27 21:12:08,355 INFO L290 TraceCheckUtils]: 34: Hoare triple {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [113] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-27 21:12:08,357 INFO L290 TraceCheckUtils]: 35: Hoare triple {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [118] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) (= |v_main_#t~mem9_1| (select (select |v_#memory_int_5| |v_main_~#v~0.base_7|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_7|))) |v_main_#t~short10_3|) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_5|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-27 21:12:08,358 INFO L290 TraceCheckUtils]: 36: Hoare triple {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [123] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} is VALID [2022-04-27 21:12:08,361 INFO L290 TraceCheckUtils]: 37: Hoare triple {11918#(and (<= 2 main_~i~0) (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))))} [117] L22-6-->L19-2: Formula: (= (store |v_#memory_int_9| |v_main_~#v~0.base_9| (store (select |v_#memory_int_9| |v_main_~#v~0.base_9|) (+ (* v_main_~i~0_9 4) |v_main_~#v~0.offset_9| 4) v_main_~key~0_4)) |v_#memory_int_8|) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_9, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[#memory_int] {11931#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} is VALID [2022-04-27 21:12:08,362 INFO L290 TraceCheckUtils]: 38: Hoare triple {11931#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} [122] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {11931#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} is VALID [2022-04-27 21:12:08,364 INFO L290 TraceCheckUtils]: 39: Hoare triple {11931#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} [109] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_5 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {11931#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} is VALID [2022-04-27 21:12:08,366 INFO L290 TraceCheckUtils]: 40: Hoare triple {11931#(exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49))))} [111] L19-4-->L29-3: Formula: (= v_main_~k~0_5 1) InVars {} OutVars{main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0] {11941#(and (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))) (= main_~k~0 1))} is VALID [2022-04-27 21:12:08,367 INFO L290 TraceCheckUtils]: 41: Hoare triple {11941#(and (exists ((v_main_~i~0_49 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_49 4) 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_49 1)) (not (<= 0 v_main_~i~0_49)))) (= main_~k~0 1))} [116] L29-3-->L30: Formula: (let ((.cse0 (select |v_#memory_int_1| |v_main_~#v~0.base_1|)) (.cse1 (* v_main_~k~0_1 4))) (and (< (mod v_main_~k~0_1 4294967296) (mod v_main_~SIZE~0_1 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem13_1|) (= (select .cse0 (+ |v_main_~#v~0.offset_1| .cse1)) |v_main_#t~mem14_1|))) InVars {main_~#v~0.base=|v_main_~#v~0.base_1|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, main_~k~0=v_main_~k~0_1} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_1, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_1, #memory_int=|v_#memory_int_1|, main_~#v~0.offset=|v_main_~#v~0.offset_1|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {11800#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:12:08,368 INFO L272 TraceCheckUtils]: 42: Hoare triple {11800#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [121] L30-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {11948#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:12:08,368 INFO L290 TraceCheckUtils]: 43: Hoare triple {11948#(<= 1 |__VERIFIER_assert_#in~cond|)} [127] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_1 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {11952#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:12:08,368 INFO L290 TraceCheckUtils]: 44: Hoare triple {11952#(<= 1 __VERIFIER_assert_~cond)} [131] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_2 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[] {11776#false} is VALID [2022-04-27 21:12:08,369 INFO L290 TraceCheckUtils]: 45: Hoare triple {11776#false} [134] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {11776#false} is VALID [2022-04-27 21:12:08,369 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2022-04-27 21:12:08,369 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:12:12,751 WARN L833 $PredicateComparison]: unable to prove that (forall ((v_main_~i~0_50 Int)) (or (forall ((v_ArrVal_368 Int)) (let ((.cse0 (store (select |c_#memory_int| |c_main_~#v~0.base|) (+ |c_main_~#v~0.offset| (* v_main_~i~0_50 4) 4) v_ArrVal_368))) (<= (select .cse0 |c_main_~#v~0.offset|) (select .cse0 (+ |c_main_~#v~0.offset| 4))))) (not (<= c_main_~j~0 (+ v_main_~i~0_50 1))))) is different from false [2022-04-27 21:13:52,081 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 93 [2022-04-27 21:13:52,359 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-27 21:13:52,360 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 2679803 treesize of output 2630649 [2022-04-27 21:15:58,149 WARN L232 SmtUtils]: Spent 2.10m on a formula simplification. DAG size of input: 927 DAG size of output: 851 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:16:18,122 WARN L232 SmtUtils]: Spent 15.79s on a formula simplification. DAG size of input: 836 DAG size of output: 836 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:16:38,411 WARN L232 SmtUtils]: Spent 8.78s on a formula simplification. DAG size of input: 704 DAG size of output: 704 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:17:04,536 WARN L232 SmtUtils]: Spent 8.64s on a formula simplification. DAG size of input: 681 DAG size of output: 681 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:17:18,711 WARN L232 SmtUtils]: Spent 7.51s on a formula simplification. DAG size of input: 670 DAG size of output: 670 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:17:38,725 WARN L232 SmtUtils]: Spent 6.30s on a formula simplification. DAG size of input: 640 DAG size of output: 640 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:17:50,690 WARN L232 SmtUtils]: Spent 6.38s on a formula simplification. DAG size of input: 638 DAG size of output: 638 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:18:01,011 WARN L232 SmtUtils]: Spent 6.48s on a formula simplification. DAG size of input: 636 DAG size of output: 636 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2022-04-27 21:18:19,200 WARN L232 SmtUtils]: Spent 6.34s on a formula simplification. DAG size of input: 519 DAG size of output: 519 (called from [L 988] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)