/usr/bin/java -ea -Xmx8000000000 -Xss4m -jar ./plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata ./data --core.log.level.for.class de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN -tc ../../../trunk/examples/toolchains/AutomizerCTransformed.xml -s ../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf -i ../../../trunk/examples/svcomp/loops/insertion_sort-2.c -------------------------------------------------------------------------------- This is Ultimate 0.2.2-dev-fb4f59a-m [2022-04-27 21:05:32,034 INFO L177 SettingsManager]: Resetting all preferences to default values... [2022-04-27 21:05:32,047 INFO L181 SettingsManager]: Resetting UltimateCore preferences to default values [2022-04-27 21:05:32,093 INFO L184 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2022-04-27 21:05:32,094 INFO L181 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2022-04-27 21:05:32,095 INFO L181 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2022-04-27 21:05:32,098 INFO L181 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2022-04-27 21:05:32,100 INFO L181 SettingsManager]: Resetting LassoRanker preferences to default values [2022-04-27 21:05:32,102 INFO L181 SettingsManager]: Resetting Reaching Definitions preferences to default values [2022-04-27 21:05:32,106 INFO L181 SettingsManager]: Resetting SyntaxChecker preferences to default values [2022-04-27 21:05:32,107 INFO L181 SettingsManager]: Resetting Sifa preferences to default values [2022-04-27 21:05:32,108 INFO L184 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2022-04-27 21:05:32,108 INFO L181 SettingsManager]: Resetting LTL2Aut preferences to default values [2022-04-27 21:05:32,110 INFO L181 SettingsManager]: Resetting PEA to Boogie preferences to default values [2022-04-27 21:05:32,111 INFO L181 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2022-04-27 21:05:32,113 INFO L181 SettingsManager]: Resetting ChcToBoogie preferences to default values [2022-04-27 21:05:32,114 INFO L181 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2022-04-27 21:05:32,114 INFO L181 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2022-04-27 21:05:32,116 INFO L181 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2022-04-27 21:05:32,118 INFO L181 SettingsManager]: Resetting CodeCheck preferences to default values [2022-04-27 21:05:32,119 INFO L181 SettingsManager]: Resetting HornVerifier preferences to default values [2022-04-27 21:05:32,121 INFO L181 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2022-04-27 21:05:32,122 INFO L181 SettingsManager]: Resetting RCFGBuilder preferences to default values [2022-04-27 21:05:32,122 INFO L181 SettingsManager]: Resetting Referee preferences to default values [2022-04-27 21:05:32,124 INFO L181 SettingsManager]: Resetting TraceAbstraction preferences to default values [2022-04-27 21:05:32,126 INFO L184 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2022-04-27 21:05:32,134 INFO L181 SettingsManager]: Resetting SmtParser preferences to default values [2022-04-27 21:05:32,134 INFO L181 SettingsManager]: Resetting Witness Parser preferences to default values [2022-04-27 21:05:32,136 INFO L188 SettingsManager]: Finished resetting all preferences to default values... [2022-04-27 21:05:32,136 INFO L101 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/loopacceleration/qvasr/qvasr_64.epf [2022-04-27 21:05:32,160 INFO L113 SettingsManager]: Loading preferences was successful [2022-04-27 21:05:32,161 INFO L115 SettingsManager]: Preferences different from defaults after loading the file: [2022-04-27 21:05:32,161 INFO L136 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2022-04-27 21:05:32,161 INFO L138 SettingsManager]: * Ignore calls to procedures called more than once=ONLY_FOR_SEQUENTIAL_PROGRAMS [2022-04-27 21:05:32,162 INFO L136 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2022-04-27 21:05:32,162 INFO L138 SettingsManager]: * Create parallel compositions if possible=false [2022-04-27 21:05:32,163 INFO L138 SettingsManager]: * Use SBE=true [2022-04-27 21:05:32,163 INFO L136 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2022-04-27 21:05:32,163 INFO L138 SettingsManager]: * Overapproximate operations on floating types=true [2022-04-27 21:05:32,163 INFO L138 SettingsManager]: * Check division by zero=IGNORE [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * Check if freed pointer was valid=false [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * Use constant arrays=true [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2022-04-27 21:05:32,164 INFO L136 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2022-04-27 21:05:32,164 INFO L138 SettingsManager]: * Size of a code block=SequenceOfStatements [2022-04-27 21:05:32,165 INFO L138 SettingsManager]: * SMT solver=External_DefaultMode [2022-04-27 21:05:32,165 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:05:32,165 INFO L136 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2022-04-27 21:05:32,165 INFO L138 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2022-04-27 21:05:32,165 INFO L138 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2022-04-27 21:05:32,165 INFO L138 SettingsManager]: * Trace refinement strategy=CAMEL [2022-04-27 21:05:32,166 INFO L138 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2022-04-27 21:05:32,166 INFO L138 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2022-04-27 21:05:32,166 INFO L138 SettingsManager]: * Trace refinement exception blacklist=NONE [2022-04-27 21:05:32,166 INFO L138 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2022-04-27 21:05:32,167 INFO L136 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2022-04-27 21:05:32,167 INFO L138 SettingsManager]: * TransformationType=LOOP_ACCELERATION_QVASR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.core: Log level for class -> de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=WARN; [2022-04-27 21:05:32,387 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2022-04-27 21:05:32,412 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2022-04-27 21:05:32,414 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2022-04-27 21:05:32,415 INFO L271 PluginConnector]: Initializing CDTParser... [2022-04-27 21:05:32,415 INFO L275 PluginConnector]: CDTParser initialized [2022-04-27 21:05:32,416 INFO L432 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loops/insertion_sort-2.c [2022-04-27 21:05:32,481 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f69e44c0d/7f90652e79244aa4b7b5627299d9fc4a/FLAG61fb081d9 [2022-04-27 21:05:32,798 INFO L306 CDTParser]: Found 1 translation units. [2022-04-27 21:05:32,798 INFO L160 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-2.c [2022-04-27 21:05:32,803 INFO L349 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f69e44c0d/7f90652e79244aa4b7b5627299d9fc4a/FLAG61fb081d9 [2022-04-27 21:05:33,223 INFO L357 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f69e44c0d/7f90652e79244aa4b7b5627299d9fc4a [2022-04-27 21:05:33,227 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2022-04-27 21:05:33,228 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2022-04-27 21:05:33,231 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2022-04-27 21:05:33,231 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2022-04-27 21:05:33,235 INFO L275 PluginConnector]: CACSL2BoogieTranslator initialized [2022-04-27 21:05:33,236 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,237 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@22ecc7c5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,237 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,242 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2022-04-27 21:05:33,258 INFO L178 MainTranslator]: Built tables and reachable declarations [2022-04-27 21:05:33,396 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-2.c[328,341] [2022-04-27 21:05:33,433 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:05:33,439 INFO L203 MainTranslator]: Completed pre-run [2022-04-27 21:05:33,455 WARN L230 ndardFunctionHandler]: Function reach_error is already implemented but we override the implementation for the call at /storage/repos/ultimate/trunk/examples/svcomp/loops/insertion_sort-2.c[328,341] [2022-04-27 21:05:33,463 INFO L210 PostProcessor]: Analyzing one entry point: main [2022-04-27 21:05:33,472 INFO L208 MainTranslator]: Completed translation [2022-04-27 21:05:33,473 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33 WrapperNode [2022-04-27 21:05:33,473 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2022-04-27 21:05:33,474 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2022-04-27 21:05:33,475 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2022-04-27 21:05:33,475 INFO L275 PluginConnector]: Boogie Preprocessor initialized [2022-04-27 21:05:33,483 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,483 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,488 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,488 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,496 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,500 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,501 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,502 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2022-04-27 21:05:33,503 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2022-04-27 21:05:33,503 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2022-04-27 21:05:33,503 INFO L275 PluginConnector]: RCFGBuilder initialized [2022-04-27 21:05:33,504 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,513 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2022-04-27 21:05:33,523 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:33,533 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) [2022-04-27 21:05:33,538 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (1)] Waiting until timeout for monitored process [2022-04-27 21:05:33,561 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2022-04-27 21:05:33,561 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2022-04-27 21:05:33,561 INFO L138 BoogieDeclarations]: Found implementation of procedure reach_error [2022-04-27 21:05:33,561 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2022-04-27 21:05:33,562 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure abort [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure __assert_fail [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure reach_error [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_uint [2022-04-27 21:05:33,562 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure main [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2022-04-27 21:05:33,563 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2022-04-27 21:05:33,618 INFO L234 CfgBuilder]: Building ICFG [2022-04-27 21:05:33,619 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2022-04-27 21:05:33,750 INFO L275 CfgBuilder]: Performing block encoding [2022-04-27 21:05:33,756 INFO L294 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2022-04-27 21:05:33,756 INFO L299 CfgBuilder]: Removed 4 assume(true) statements. [2022-04-27 21:05:33,757 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:05:33 BoogieIcfgContainer [2022-04-27 21:05:33,758 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2022-04-27 21:05:33,758 INFO L113 PluginConnector]: ------------------------IcfgTransformer---------------------------- [2022-04-27 21:05:33,758 INFO L271 PluginConnector]: Initializing IcfgTransformer... [2022-04-27 21:05:33,759 INFO L275 PluginConnector]: IcfgTransformer initialized [2022-04-27 21:05:33,762 INFO L185 PluginConnector]: Executing the observer IcfgTransformationObserver from plugin IcfgTransformer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:05:33" (1/1) ... [2022-04-27 21:05:33,763 INFO L168 ansformationObserver]: Applying ICFG transformation LOOP_ACCELERATION_QVASR [2022-04-27 21:05:33,788 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:05:33 BasicIcfg [2022-04-27 21:05:33,788 INFO L132 PluginConnector]: ------------------------ END IcfgTransformer---------------------------- [2022-04-27 21:05:33,789 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2022-04-27 21:05:33,790 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2022-04-27 21:05:33,796 INFO L275 PluginConnector]: TraceAbstraction initialized [2022-04-27 21:05:33,797 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 27.04 09:05:33" (1/4) ... [2022-04-27 21:05:33,797 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e532046 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,797 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 27.04 09:05:33" (2/4) ... [2022-04-27 21:05:33,797 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e532046 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 27.04 09:05:33" (3/4) ... [2022-04-27 21:05:33,798 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7e532046 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 27.04 09:05:33, skipping insertion in model container [2022-04-27 21:05:33,798 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.icfgtransformation CFG 27.04 09:05:33" (4/4) ... [2022-04-27 21:05:33,799 INFO L111 eAbstractionObserver]: Analyzing ICFG insertion_sort-2.cqvasr [2022-04-27 21:05:33,809 INFO L201 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2022-04-27 21:05:33,809 INFO L160 ceAbstractionStarter]: Applying trace abstraction to program that has 1 error locations. [2022-04-27 21:05:33,884 INFO L356 AbstractCegarLoop]: ======== Iteration 0 == of CEGAR loop == AllErrorsAtOnce ======== [2022-04-27 21:05:33,889 INFO L357 AbstractCegarLoop]: Settings: SEPARATE_VIOLATION_CHECK=true, mInterprocedural=true, mMaxIterations=1000000, mWatchIteration=1000000, mArtifact=RCFG, mInterpolation=FPandBP, mInterpolantAutomaton=STRAIGHT_LINE, mDumpAutomata=false, mAutomataFormat=ATS_NUMERATE, mDumpPath=., mDeterminiation=PREDICATE_ABSTRACTION, mMinimize=MINIMIZE_SEVPA, mHoare=true, mAutomataTypeConcurrency=FINITE_AUTOMATA, mHoareTripleChecks=INCREMENTAL, mHoareAnnotationPositions=LoopsAndPotentialCycles, mDumpOnlyReuseAutomata=false, mLimitTraceHistogram=0, mErrorLocTimeLimit=0, mLimitPathProgramCount=0, mCollectInterpolantStatistics=true, mHeuristicEmptinessCheck=false, mHeuristicEmptinessCheckAStarHeuristic=ZERO, mHeuristicEmptinessCheckAStarHeuristicRandomSeed=1337, mHeuristicEmptinessCheckSmtFeatureScoringMethod=DAGSIZE, mSMTFeatureExtraction=false, mSMTFeatureExtractionDumpPath=., mOverrideInterpolantAutomaton=false, mMcrInterpolantMethod=WP, mPorIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@1e35659f, mLbeIndependenceSettings=de.uni_freiburg.informatik.ultimate.lib.tracecheckerutils.partialorder.independence.IndependenceSettings@76906ca5 [2022-04-27 21:05:33,889 INFO L358 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2022-04-27 21:05:33,902 INFO L276 IsEmpty]: Start isEmpty. Operand has 31 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 24 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:33,909 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 21:05:33,910 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:33,910 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:33,911 INFO L420 AbstractCegarLoop]: === Iteration 1 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:33,918 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:33,918 INFO L85 PathProgramCache]: Analyzing trace with hash -189909079, now seen corresponding path program 1 times [2022-04-27 21:05:33,925 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:33,926 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395430578] [2022-04-27 21:05:33,926 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:33,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:34,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,146 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:34,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,176 INFO L290 TraceCheckUtils]: 0: Hoare triple {39#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {34#true} is VALID [2022-04-27 21:05:34,177 INFO L290 TraceCheckUtils]: 1: Hoare triple {34#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 21:05:34,177 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {34#true} {34#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 21:05:34,180 INFO L272 TraceCheckUtils]: 0: Hoare triple {34#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {39#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:34,181 INFO L290 TraceCheckUtils]: 1: Hoare triple {39#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {34#true} is VALID [2022-04-27 21:05:34,181 INFO L290 TraceCheckUtils]: 2: Hoare triple {34#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 21:05:34,181 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {34#true} {34#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 21:05:34,182 INFO L272 TraceCheckUtils]: 4: Hoare triple {34#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {34#true} is VALID [2022-04-27 21:05:34,183 INFO L290 TraceCheckUtils]: 5: Hoare triple {34#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {34#true} is VALID [2022-04-27 21:05:34,184 INFO L290 TraceCheckUtils]: 6: Hoare triple {34#true} [96] L17-3-->L17-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 21:05:34,185 INFO L290 TraceCheckUtils]: 7: Hoare triple {35#false} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {35#false} is VALID [2022-04-27 21:05:34,185 INFO L290 TraceCheckUtils]: 8: Hoare triple {35#false} [101] L19-3-->L19-4: Formula: false InVars {} OutVars{} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 21:05:34,185 INFO L290 TraceCheckUtils]: 9: Hoare triple {35#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {35#false} is VALID [2022-04-27 21:05:34,187 INFO L290 TraceCheckUtils]: 10: Hoare triple {35#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {35#false} is VALID [2022-04-27 21:05:34,188 INFO L272 TraceCheckUtils]: 11: Hoare triple {35#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {35#false} is VALID [2022-04-27 21:05:34,188 INFO L290 TraceCheckUtils]: 12: Hoare triple {35#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {35#false} is VALID [2022-04-27 21:05:34,189 INFO L290 TraceCheckUtils]: 13: Hoare triple {35#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 21:05:34,189 INFO L290 TraceCheckUtils]: 14: Hoare triple {35#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {35#false} is VALID [2022-04-27 21:05:34,189 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:34,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:34,190 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [395430578] [2022-04-27 21:05:34,191 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [395430578] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:34,191 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:05:34,191 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2022-04-27 21:05:34,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1333901638] [2022-04-27 21:05:34,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:34,198 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:34,200 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:34,202 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,228 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:34,228 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 3 states [2022-04-27 21:05:34,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:34,258 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2022-04-27 21:05:34,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:05:34,261 INFO L87 Difference]: Start difference. First operand has 31 states, 23 states have (on average 1.4782608695652173) internal successors, (34), 24 states have internal predecessors, (34), 3 states have call successors, (3), 3 states have call predecessors, (3), 3 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,364 INFO L93 Difference]: Finished difference Result 54 states and 71 transitions. [2022-04-27 21:05:34,364 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2022-04-27 21:05:34,364 INFO L78 Accepts]: Start accepts. Automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:34,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:34,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 71 transitions. [2022-04-27 21:05:34,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 71 transitions. [2022-04-27 21:05:34,384 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 3 states and 71 transitions. [2022-04-27 21:05:34,485 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 71 edges. 71 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:34,493 INFO L225 Difference]: With dead ends: 54 [2022-04-27 21:05:34,493 INFO L226 Difference]: Without dead ends: 26 [2022-04-27 21:05:34,496 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2022-04-27 21:05:34,500 INFO L413 NwaCegarLoop]: 34 mSDtfsCounter, 26 mSDsluCounter, 3 mSDsCounter, 0 mSdLazyCounter, 3 mSolverCounterSat, 2 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 27 SdHoareTripleChecker+Valid, 37 SdHoareTripleChecker+Invalid, 5 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 2 IncrementalHoareTripleChecker+Valid, 3 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:34,501 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [27 Valid, 37 Invalid, 5 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [2 Valid, 3 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:05:34,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2022-04-27 21:05:34,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2022-04-27 21:05:34,529 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:34,530 INFO L82 GeneralOperation]: Start isEquivalent. First operand 26 states. Second operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,531 INFO L74 IsIncluded]: Start isIncluded. First operand 26 states. Second operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,532 INFO L87 Difference]: Start difference. First operand 26 states. Second operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,536 INFO L93 Difference]: Finished difference Result 26 states and 30 transitions. [2022-04-27 21:05:34,536 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 21:05:34,536 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:34,537 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:34,537 INFO L74 IsIncluded]: Start isIncluded. First operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 26 states. [2022-04-27 21:05:34,537 INFO L87 Difference]: Start difference. First operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 26 states. [2022-04-27 21:05:34,540 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,540 INFO L93 Difference]: Finished difference Result 26 states and 30 transitions. [2022-04-27 21:05:34,540 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 21:05:34,543 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:34,544 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:34,545 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:34,545 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:34,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 20 states have (on average 1.25) internal successors, (25), 20 states have internal predecessors, (25), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:34,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 30 transitions. [2022-04-27 21:05:34,549 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 30 transitions. Word has length 15 [2022-04-27 21:05:34,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:34,550 INFO L495 AbstractCegarLoop]: Abstraction has 26 states and 30 transitions. [2022-04-27 21:05:34,550 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 2 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,550 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 30 transitions. [2022-04-27 21:05:34,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2022-04-27 21:05:34,550 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:34,551 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:34,551 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable0 [2022-04-27 21:05:34,551 INFO L420 AbstractCegarLoop]: === Iteration 2 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:34,552 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:34,552 INFO L85 PathProgramCache]: Analyzing trace with hash -1109859861, now seen corresponding path program 1 times [2022-04-27 21:05:34,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:34,552 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [702104216] [2022-04-27 21:05:34,552 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:34,553 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:34,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,678 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:34,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:34,695 INFO L290 TraceCheckUtils]: 0: Hoare triple {207#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {199#true} is VALID [2022-04-27 21:05:34,695 INFO L290 TraceCheckUtils]: 1: Hoare triple {199#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#true} is VALID [2022-04-27 21:05:34,695 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {199#true} {199#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#true} is VALID [2022-04-27 21:05:34,696 INFO L272 TraceCheckUtils]: 0: Hoare triple {199#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {207#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:34,697 INFO L290 TraceCheckUtils]: 1: Hoare triple {207#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {199#true} is VALID [2022-04-27 21:05:34,697 INFO L290 TraceCheckUtils]: 2: Hoare triple {199#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#true} is VALID [2022-04-27 21:05:34,697 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {199#true} {199#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#true} is VALID [2022-04-27 21:05:34,697 INFO L272 TraceCheckUtils]: 4: Hoare triple {199#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {199#true} is VALID [2022-04-27 21:05:34,699 INFO L290 TraceCheckUtils]: 5: Hoare triple {199#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {204#(= main_~j~0 0)} is VALID [2022-04-27 21:05:34,700 INFO L290 TraceCheckUtils]: 6: Hoare triple {204#(= main_~j~0 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {205#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 21:05:34,700 INFO L290 TraceCheckUtils]: 7: Hoare triple {205#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {205#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 21:05:34,701 INFO L290 TraceCheckUtils]: 8: Hoare triple {205#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {205#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} is VALID [2022-04-27 21:05:34,702 INFO L290 TraceCheckUtils]: 9: Hoare triple {205#(<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {206#(and (<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:05:34,703 INFO L290 TraceCheckUtils]: 10: Hoare triple {206#(and (<= main_~SIZE~0 (* (div main_~SIZE~0 4294967296) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {200#false} is VALID [2022-04-27 21:05:34,704 INFO L272 TraceCheckUtils]: 11: Hoare triple {200#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {200#false} is VALID [2022-04-27 21:05:34,704 INFO L290 TraceCheckUtils]: 12: Hoare triple {200#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {200#false} is VALID [2022-04-27 21:05:34,704 INFO L290 TraceCheckUtils]: 13: Hoare triple {200#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {200#false} is VALID [2022-04-27 21:05:34,704 INFO L290 TraceCheckUtils]: 14: Hoare triple {200#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {200#false} is VALID [2022-04-27 21:05:34,705 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:34,705 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:34,705 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [702104216] [2022-04-27 21:05:34,705 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [702104216] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:34,705 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:05:34,706 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 21:05:34,706 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [386428524] [2022-04-27 21:05:34,706 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:34,708 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:34,709 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:34,709 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,722 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 15 edges. 15 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:34,723 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 21:05:34,723 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:34,724 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 21:05:34,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-04-27 21:05:34,729 INFO L87 Difference]: Start difference. First operand 26 states and 30 transitions. Second operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,976 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:34,976 INFO L93 Difference]: Finished difference Result 49 states and 58 transitions. [2022-04-27 21:05:34,977 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:05:34,977 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 15 [2022-04-27 21:05:34,977 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:34,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 58 transitions. [2022-04-27 21:05:34,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:34,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 58 transitions. [2022-04-27 21:05:34,989 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 58 transitions. [2022-04-27 21:05:35,041 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 58 edges. 58 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:35,042 INFO L225 Difference]: With dead ends: 49 [2022-04-27 21:05:35,043 INFO L226 Difference]: Without dead ends: 28 [2022-04-27 21:05:35,043 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:35,046 INFO L413 NwaCegarLoop]: 25 mSDtfsCounter, 31 mSDsluCounter, 12 mSDsCounter, 0 mSdLazyCounter, 58 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 32 SdHoareTripleChecker+Valid, 37 SdHoareTripleChecker+Invalid, 62 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 58 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:35,046 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [32 Valid, 37 Invalid, 62 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 58 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:05:35,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2022-04-27 21:05:35,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2022-04-27 21:05:35,053 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:35,054 INFO L82 GeneralOperation]: Start isEquivalent. First operand 28 states. Second operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:35,055 INFO L74 IsIncluded]: Start isIncluded. First operand 28 states. Second operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:35,056 INFO L87 Difference]: Start difference. First operand 28 states. Second operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:35,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:35,058 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-04-27 21:05:35,059 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-04-27 21:05:35,059 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:35,059 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:35,059 INFO L74 IsIncluded]: Start isIncluded. First operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-27 21:05:35,060 INFO L87 Difference]: Start difference. First operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 28 states. [2022-04-27 21:05:35,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:35,067 INFO L93 Difference]: Finished difference Result 28 states and 32 transitions. [2022-04-27 21:05:35,067 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-04-27 21:05:35,067 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:35,067 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:35,068 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:35,068 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:35,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 21 states have (on average 1.2380952380952381) internal successors, (26), 21 states have internal predecessors, (26), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:35,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 31 transitions. [2022-04-27 21:05:35,070 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 31 transitions. Word has length 15 [2022-04-27 21:05:35,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:35,070 INFO L495 AbstractCegarLoop]: Abstraction has 27 states and 31 transitions. [2022-04-27 21:05:35,071 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 1.8333333333333333) internal successors, (11), 5 states have internal predecessors, (11), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:35,071 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 31 transitions. [2022-04-27 21:05:35,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2022-04-27 21:05:35,072 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:35,072 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:35,072 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable1 [2022-04-27 21:05:35,072 INFO L420 AbstractCegarLoop]: === Iteration 3 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:35,073 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:35,073 INFO L85 PathProgramCache]: Analyzing trace with hash -1012960919, now seen corresponding path program 1 times [2022-04-27 21:05:35,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:35,074 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1199804638] [2022-04-27 21:05:35,074 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:35,074 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:35,136 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,230 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:35,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,237 INFO L290 TraceCheckUtils]: 0: Hoare triple {388#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:05:35,237 INFO L290 TraceCheckUtils]: 1: Hoare triple {379#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:35,237 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {379#true} {379#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:35,238 INFO L272 TraceCheckUtils]: 0: Hoare triple {379#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {388#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:35,238 INFO L290 TraceCheckUtils]: 1: Hoare triple {388#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:05:35,238 INFO L290 TraceCheckUtils]: 2: Hoare triple {379#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:35,239 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {379#true} {379#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:35,239 INFO L272 TraceCheckUtils]: 4: Hoare triple {379#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:35,239 INFO L290 TraceCheckUtils]: 5: Hoare triple {379#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {384#(= main_~j~0 0)} is VALID [2022-04-27 21:05:35,240 INFO L290 TraceCheckUtils]: 6: Hoare triple {384#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {384#(= main_~j~0 0)} is VALID [2022-04-27 21:05:35,240 INFO L290 TraceCheckUtils]: 7: Hoare triple {384#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {385#(and (<= 0 (div (+ (- 1) main_~j~0) 4294967296)) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:35,242 INFO L290 TraceCheckUtils]: 8: Hoare triple {385#(and (<= 0 (div (+ (- 1) main_~j~0) 4294967296)) (<= main_~j~0 1))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 21:05:35,242 INFO L290 TraceCheckUtils]: 9: Hoare triple {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 21:05:35,242 INFO L290 TraceCheckUtils]: 10: Hoare triple {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 21:05:35,243 INFO L290 TraceCheckUtils]: 11: Hoare triple {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {387#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:35,244 INFO L290 TraceCheckUtils]: 12: Hoare triple {387#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {380#false} is VALID [2022-04-27 21:05:35,244 INFO L272 TraceCheckUtils]: 13: Hoare triple {380#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {380#false} is VALID [2022-04-27 21:05:35,245 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#false} is VALID [2022-04-27 21:05:35,245 INFO L290 TraceCheckUtils]: 15: Hoare triple {380#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:05:35,245 INFO L290 TraceCheckUtils]: 16: Hoare triple {380#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:05:35,245 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:35,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:35,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1199804638] [2022-04-27 21:05:35,246 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1199804638] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:35,246 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1050932633] [2022-04-27 21:05:35,246 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:35,246 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:35,247 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:35,248 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:35,260 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Waiting until timeout for monitored process [2022-04-27 21:05:35,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,312 INFO L263 TraceCheckSpWp]: Trace formula consists of 88 conjuncts, 6 conjunts are in the unsatisfiable core [2022-04-27 21:05:35,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:35,339 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:36,212 INFO L272 TraceCheckUtils]: 0: Hoare triple {379#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:36,212 INFO L290 TraceCheckUtils]: 1: Hoare triple {379#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {379#true} is VALID [2022-04-27 21:05:36,212 INFO L290 TraceCheckUtils]: 2: Hoare triple {379#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:36,213 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {379#true} {379#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:36,213 INFO L272 TraceCheckUtils]: 4: Hoare triple {379#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:36,213 INFO L290 TraceCheckUtils]: 5: Hoare triple {379#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {379#true} is VALID [2022-04-27 21:05:36,213 INFO L290 TraceCheckUtils]: 6: Hoare triple {379#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {379#true} is VALID [2022-04-27 21:05:36,213 INFO L290 TraceCheckUtils]: 7: Hoare triple {379#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {379#true} is VALID [2022-04-27 21:05:36,214 INFO L290 TraceCheckUtils]: 8: Hoare triple {379#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {379#true} is VALID [2022-04-27 21:05:36,215 INFO L290 TraceCheckUtils]: 9: Hoare triple {379#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {385#(and (<= 0 (div (+ (- 1) main_~j~0) 4294967296)) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:36,216 INFO L290 TraceCheckUtils]: 10: Hoare triple {385#(and (<= 0 (div (+ (- 1) main_~j~0) 4294967296)) (<= main_~j~0 1))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} is VALID [2022-04-27 21:05:36,217 INFO L290 TraceCheckUtils]: 11: Hoare triple {386#(<= 0 (div (+ (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0) 1) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {387#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:36,218 INFO L290 TraceCheckUtils]: 12: Hoare triple {387#(and (= (+ (- 1) main_~k~0) 0) (<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {380#false} is VALID [2022-04-27 21:05:36,218 INFO L272 TraceCheckUtils]: 13: Hoare triple {380#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {380#false} is VALID [2022-04-27 21:05:36,219 INFO L290 TraceCheckUtils]: 14: Hoare triple {380#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {380#false} is VALID [2022-04-27 21:05:36,219 INFO L290 TraceCheckUtils]: 15: Hoare triple {380#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:05:36,219 INFO L290 TraceCheckUtils]: 16: Hoare triple {380#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {380#false} is VALID [2022-04-27 21:05:36,219 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:05:36,220 INFO L324 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2022-04-27 21:05:36,222 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1050932633] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:36,222 INFO L184 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2022-04-27 21:05:36,222 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 7 [2022-04-27 21:05:36,224 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [623897653] [2022-04-27 21:05:36,224 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:36,225 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 21:05:36,225 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:36,225 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,242 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 17 edges. 17 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:36,242 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 5 states [2022-04-27 21:05:36,242 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:36,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2022-04-27 21:05:36,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2022-04-27 21:05:36,243 INFO L87 Difference]: Start difference. First operand 27 states and 31 transitions. Second operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:36,443 INFO L93 Difference]: Finished difference Result 45 states and 52 transitions. [2022-04-27 21:05:36,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2022-04-27 21:05:36,444 INFO L78 Accepts]: Start accepts. Automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 17 [2022-04-27 21:05:36,444 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:36,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 51 transitions. [2022-04-27 21:05:36,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5 states to 5 states and 51 transitions. [2022-04-27 21:05:36,448 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 5 states and 51 transitions. [2022-04-27 21:05:36,505 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 51 edges. 51 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:36,506 INFO L225 Difference]: With dead ends: 45 [2022-04-27 21:05:36,507 INFO L226 Difference]: Without dead ends: 33 [2022-04-27 21:05:36,508 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 17 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2022-04-27 21:05:36,508 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 10 mSDsluCounter, 66 mSDsCounter, 0 mSdLazyCounter, 26 mSolverCounterSat, 0 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.0s Time, 0 mProtectedPredicate, 0 mProtectedAction, 10 SdHoareTripleChecker+Valid, 93 SdHoareTripleChecker+Invalid, 26 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Valid, 26 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.0s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:36,509 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [10 Valid, 93 Invalid, 26 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [0 Valid, 26 Invalid, 0 Unknown, 0 Unchecked, 0.0s Time] [2022-04-27 21:05:36,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2022-04-27 21:05:36,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 28. [2022-04-27 21:05:36,517 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:36,518 INFO L82 GeneralOperation]: Start isEquivalent. First operand 33 states. Second operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,518 INFO L74 IsIncluded]: Start isIncluded. First operand 33 states. Second operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,519 INFO L87 Difference]: Start difference. First operand 33 states. Second operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:36,521 INFO L93 Difference]: Finished difference Result 33 states and 39 transitions. [2022-04-27 21:05:36,521 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 39 transitions. [2022-04-27 21:05:36,523 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:36,523 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:36,523 INFO L74 IsIncluded]: Start isIncluded. First operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-27 21:05:36,523 INFO L87 Difference]: Start difference. First operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 33 states. [2022-04-27 21:05:36,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:36,528 INFO L93 Difference]: Finished difference Result 33 states and 39 transitions. [2022-04-27 21:05:36,528 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 39 transitions. [2022-04-27 21:05:36,528 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:36,529 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:36,529 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:36,529 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:36,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 22 states have (on average 1.2272727272727273) internal successors, (27), 22 states have internal predecessors, (27), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:36,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 32 transitions. [2022-04-27 21:05:36,530 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 32 transitions. Word has length 17 [2022-04-27 21:05:36,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:36,531 INFO L495 AbstractCegarLoop]: Abstraction has 28 states and 32 transitions. [2022-04-27 21:05:36,531 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 5 states, 5 states have (on average 2.6) internal successors, (13), 5 states have internal predecessors, (13), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,531 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 32 transitions. [2022-04-27 21:05:36,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 21:05:36,536 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:36,536 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:36,562 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (2)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:36,759 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable2,2 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:36,759 INFO L420 AbstractCegarLoop]: === Iteration 4 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:36,760 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:36,760 INFO L85 PathProgramCache]: Analyzing trace with hash -768849603, now seen corresponding path program 1 times [2022-04-27 21:05:36,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:36,760 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655712135] [2022-04-27 21:05:36,760 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:36,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:36,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:36,828 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:36,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:36,836 INFO L290 TraceCheckUtils]: 0: Hoare triple {619#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {611#true} is VALID [2022-04-27 21:05:36,836 INFO L290 TraceCheckUtils]: 1: Hoare triple {611#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {611#true} is VALID [2022-04-27 21:05:36,836 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {611#true} {611#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {611#true} is VALID [2022-04-27 21:05:36,839 INFO L272 TraceCheckUtils]: 0: Hoare triple {611#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {619#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:36,839 INFO L290 TraceCheckUtils]: 1: Hoare triple {619#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {611#true} is VALID [2022-04-27 21:05:36,839 INFO L290 TraceCheckUtils]: 2: Hoare triple {611#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {611#true} is VALID [2022-04-27 21:05:36,839 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {611#true} {611#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {611#true} is VALID [2022-04-27 21:05:36,839 INFO L272 TraceCheckUtils]: 4: Hoare triple {611#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {611#true} is VALID [2022-04-27 21:05:36,840 INFO L290 TraceCheckUtils]: 5: Hoare triple {611#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {611#true} is VALID [2022-04-27 21:05:36,840 INFO L290 TraceCheckUtils]: 6: Hoare triple {611#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {611#true} is VALID [2022-04-27 21:05:36,840 INFO L290 TraceCheckUtils]: 7: Hoare triple {611#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {611#true} is VALID [2022-04-27 21:05:36,840 INFO L290 TraceCheckUtils]: 8: Hoare triple {611#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {611#true} is VALID [2022-04-27 21:05:36,841 INFO L290 TraceCheckUtils]: 9: Hoare triple {611#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {616#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:36,842 INFO L290 TraceCheckUtils]: 10: Hoare triple {616#(= (+ (- 1) main_~j~0) 0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {617#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 21:05:36,842 INFO L290 TraceCheckUtils]: 11: Hoare triple {617#(and (<= main_~j~0 (+ main_~i~0 1)) (= (+ (- 1) main_~j~0) 0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {618#|main_#t~short10|} is VALID [2022-04-27 21:05:36,843 INFO L290 TraceCheckUtils]: 12: Hoare triple {618#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {612#false} is VALID [2022-04-27 21:05:36,843 INFO L290 TraceCheckUtils]: 13: Hoare triple {612#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {612#false} is VALID [2022-04-27 21:05:36,843 INFO L290 TraceCheckUtils]: 14: Hoare triple {612#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {612#false} is VALID [2022-04-27 21:05:36,843 INFO L290 TraceCheckUtils]: 15: Hoare triple {612#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {612#false} is VALID [2022-04-27 21:05:36,844 INFO L290 TraceCheckUtils]: 16: Hoare triple {612#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {612#false} is VALID [2022-04-27 21:05:36,844 INFO L290 TraceCheckUtils]: 17: Hoare triple {612#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {612#false} is VALID [2022-04-27 21:05:36,844 INFO L290 TraceCheckUtils]: 18: Hoare triple {612#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {612#false} is VALID [2022-04-27 21:05:36,844 INFO L272 TraceCheckUtils]: 19: Hoare triple {612#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {612#false} is VALID [2022-04-27 21:05:36,844 INFO L290 TraceCheckUtils]: 20: Hoare triple {612#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {612#false} is VALID [2022-04-27 21:05:36,844 INFO L290 TraceCheckUtils]: 21: Hoare triple {612#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {612#false} is VALID [2022-04-27 21:05:36,845 INFO L290 TraceCheckUtils]: 22: Hoare triple {612#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {612#false} is VALID [2022-04-27 21:05:36,845 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:05:36,845 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:36,845 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1655712135] [2022-04-27 21:05:36,845 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1655712135] provided 1 perfect and 0 imperfect interpolant sequences [2022-04-27 21:05:36,846 INFO L184 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2022-04-27 21:05:36,846 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2022-04-27 21:05:36,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261245993] [2022-04-27 21:05:36,846 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:36,846 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:05:36,846 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:36,847 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:36,863 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:36,863 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 6 states [2022-04-27 21:05:36,864 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:36,864 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2022-04-27 21:05:36,864 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2022-04-27 21:05:36,864 INFO L87 Difference]: Start difference. First operand 28 states and 32 transitions. Second operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:37,096 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:37,097 INFO L93 Difference]: Finished difference Result 55 states and 66 transitions. [2022-04-27 21:05:37,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2022-04-27 21:05:37,097 INFO L78 Accepts]: Start accepts. Automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:05:37,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:37,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:37,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 65 transitions. [2022-04-27 21:05:37,100 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:37,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6 states to 6 states and 65 transitions. [2022-04-27 21:05:37,102 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 6 states and 65 transitions. [2022-04-27 21:05:37,167 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:37,168 INFO L225 Difference]: With dead ends: 55 [2022-04-27 21:05:37,169 INFO L226 Difference]: Without dead ends: 38 [2022-04-27 21:05:37,169 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2022-04-27 21:05:37,170 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 43 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 82 mSolverCounterSat, 8 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 44 SdHoareTripleChecker+Valid, 40 SdHoareTripleChecker+Invalid, 90 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 8 IncrementalHoareTripleChecker+Valid, 82 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:37,170 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [44 Valid, 40 Invalid, 90 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [8 Valid, 82 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:05:37,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2022-04-27 21:05:37,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 30. [2022-04-27 21:05:37,179 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:37,179 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:37,179 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:37,179 INFO L87 Difference]: Start difference. First operand 38 states. Second operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:37,181 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:37,181 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2022-04-27 21:05:37,181 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 45 transitions. [2022-04-27 21:05:37,181 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:37,182 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:37,182 INFO L74 IsIncluded]: Start isIncluded. First operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 38 states. [2022-04-27 21:05:37,182 INFO L87 Difference]: Start difference. First operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 38 states. [2022-04-27 21:05:37,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:37,184 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2022-04-27 21:05:37,184 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 45 transitions. [2022-04-27 21:05:37,184 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:37,184 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:37,184 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:37,184 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:37,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 24 states have internal predecessors, (29), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:37,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 34 transitions. [2022-04-27 21:05:37,186 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 34 transitions. Word has length 23 [2022-04-27 21:05:37,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:37,186 INFO L495 AbstractCegarLoop]: Abstraction has 30 states and 34 transitions. [2022-04-27 21:05:37,186 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 6 states, 6 states have (on average 3.1666666666666665) internal successors, (19), 5 states have internal predecessors, (19), 2 states have call successors, (3), 3 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:37,186 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 34 transitions. [2022-04-27 21:05:37,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2022-04-27 21:05:37,187 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:37,187 INFO L195 NwaCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:37,187 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable3 [2022-04-27 21:05:37,187 INFO L420 AbstractCegarLoop]: === Iteration 5 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:37,187 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:37,188 INFO L85 PathProgramCache]: Analyzing trace with hash 1028101756, now seen corresponding path program 1 times [2022-04-27 21:05:37,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:37,188 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146255032] [2022-04-27 21:05:37,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:37,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:37,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,350 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:37,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,359 INFO L290 TraceCheckUtils]: 0: Hoare triple {830#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {821#true} is VALID [2022-04-27 21:05:37,359 INFO L290 TraceCheckUtils]: 1: Hoare triple {821#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,359 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {821#true} {821#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,360 INFO L272 TraceCheckUtils]: 0: Hoare triple {821#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {830#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:37,360 INFO L290 TraceCheckUtils]: 1: Hoare triple {830#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {821#true} is VALID [2022-04-27 21:05:37,360 INFO L290 TraceCheckUtils]: 2: Hoare triple {821#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,360 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {821#true} {821#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,360 INFO L272 TraceCheckUtils]: 4: Hoare triple {821#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,362 INFO L290 TraceCheckUtils]: 5: Hoare triple {821#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {826#(= main_~j~0 0)} is VALID [2022-04-27 21:05:37,363 INFO L290 TraceCheckUtils]: 6: Hoare triple {826#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {826#(= main_~j~0 0)} is VALID [2022-04-27 21:05:37,363 INFO L290 TraceCheckUtils]: 7: Hoare triple {826#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {827#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:37,364 INFO L290 TraceCheckUtils]: 8: Hoare triple {827#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {828#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:37,365 INFO L290 TraceCheckUtils]: 9: Hoare triple {828#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {829#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:37,366 INFO L290 TraceCheckUtils]: 10: Hoare triple {829#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {822#false} is VALID [2022-04-27 21:05:37,366 INFO L290 TraceCheckUtils]: 11: Hoare triple {822#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {822#false} is VALID [2022-04-27 21:05:37,366 INFO L290 TraceCheckUtils]: 12: Hoare triple {822#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {822#false} is VALID [2022-04-27 21:05:37,366 INFO L290 TraceCheckUtils]: 13: Hoare triple {822#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {822#false} is VALID [2022-04-27 21:05:37,367 INFO L290 TraceCheckUtils]: 14: Hoare triple {822#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {822#false} is VALID [2022-04-27 21:05:37,367 INFO L290 TraceCheckUtils]: 15: Hoare triple {822#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {822#false} is VALID [2022-04-27 21:05:37,367 INFO L290 TraceCheckUtils]: 16: Hoare triple {822#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:37,367 INFO L290 TraceCheckUtils]: 17: Hoare triple {822#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {822#false} is VALID [2022-04-27 21:05:37,367 INFO L290 TraceCheckUtils]: 18: Hoare triple {822#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {822#false} is VALID [2022-04-27 21:05:37,367 INFO L272 TraceCheckUtils]: 19: Hoare triple {822#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {822#false} is VALID [2022-04-27 21:05:37,368 INFO L290 TraceCheckUtils]: 20: Hoare triple {822#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {822#false} is VALID [2022-04-27 21:05:37,368 INFO L290 TraceCheckUtils]: 21: Hoare triple {822#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:37,368 INFO L290 TraceCheckUtils]: 22: Hoare triple {822#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:37,368 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:37,368 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:37,368 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [146255032] [2022-04-27 21:05:37,368 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [146255032] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:37,369 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [544959295] [2022-04-27 21:05:37,369 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:37,369 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:37,369 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:37,370 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:37,411 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Waiting until timeout for monitored process [2022-04-27 21:05:37,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,430 INFO L263 TraceCheckSpWp]: Trace formula consists of 105 conjuncts, 8 conjunts are in the unsatisfiable core [2022-04-27 21:05:37,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:37,440 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:37,912 INFO L272 TraceCheckUtils]: 0: Hoare triple {821#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,912 INFO L290 TraceCheckUtils]: 1: Hoare triple {821#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {821#true} is VALID [2022-04-27 21:05:37,912 INFO L290 TraceCheckUtils]: 2: Hoare triple {821#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,912 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {821#true} {821#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,912 INFO L272 TraceCheckUtils]: 4: Hoare triple {821#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:37,913 INFO L290 TraceCheckUtils]: 5: Hoare triple {821#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {826#(= main_~j~0 0)} is VALID [2022-04-27 21:05:37,913 INFO L290 TraceCheckUtils]: 6: Hoare triple {826#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {826#(= main_~j~0 0)} is VALID [2022-04-27 21:05:37,914 INFO L290 TraceCheckUtils]: 7: Hoare triple {826#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {827#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:37,915 INFO L290 TraceCheckUtils]: 8: Hoare triple {827#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {828#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:37,916 INFO L290 TraceCheckUtils]: 9: Hoare triple {828#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {829#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} is VALID [2022-04-27 21:05:37,916 INFO L290 TraceCheckUtils]: 10: Hoare triple {829#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~SIZE~0 (* 4294967296 (div main_~j~0 4294967296))) (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {822#false} is VALID [2022-04-27 21:05:37,917 INFO L290 TraceCheckUtils]: 11: Hoare triple {822#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {822#false} is VALID [2022-04-27 21:05:37,917 INFO L290 TraceCheckUtils]: 12: Hoare triple {822#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {822#false} is VALID [2022-04-27 21:05:37,917 INFO L290 TraceCheckUtils]: 13: Hoare triple {822#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {822#false} is VALID [2022-04-27 21:05:37,917 INFO L290 TraceCheckUtils]: 14: Hoare triple {822#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {822#false} is VALID [2022-04-27 21:05:37,917 INFO L290 TraceCheckUtils]: 15: Hoare triple {822#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {822#false} is VALID [2022-04-27 21:05:37,917 INFO L290 TraceCheckUtils]: 16: Hoare triple {822#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L290 TraceCheckUtils]: 17: Hoare triple {822#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L290 TraceCheckUtils]: 18: Hoare triple {822#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L272 TraceCheckUtils]: 19: Hoare triple {822#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L290 TraceCheckUtils]: 20: Hoare triple {822#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L290 TraceCheckUtils]: 21: Hoare triple {822#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L290 TraceCheckUtils]: 22: Hoare triple {822#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:37,918 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:37,919 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:38,255 INFO L290 TraceCheckUtils]: 22: Hoare triple {822#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:38,256 INFO L290 TraceCheckUtils]: 21: Hoare triple {822#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:38,256 INFO L290 TraceCheckUtils]: 20: Hoare triple {822#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {822#false} is VALID [2022-04-27 21:05:38,256 INFO L272 TraceCheckUtils]: 19: Hoare triple {822#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {822#false} is VALID [2022-04-27 21:05:38,256 INFO L290 TraceCheckUtils]: 18: Hoare triple {822#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {822#false} is VALID [2022-04-27 21:05:38,256 INFO L290 TraceCheckUtils]: 17: Hoare triple {822#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {822#false} is VALID [2022-04-27 21:05:38,256 INFO L290 TraceCheckUtils]: 16: Hoare triple {822#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {822#false} is VALID [2022-04-27 21:05:38,257 INFO L290 TraceCheckUtils]: 15: Hoare triple {822#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {822#false} is VALID [2022-04-27 21:05:38,257 INFO L290 TraceCheckUtils]: 14: Hoare triple {822#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {822#false} is VALID [2022-04-27 21:05:38,257 INFO L290 TraceCheckUtils]: 13: Hoare triple {822#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {822#false} is VALID [2022-04-27 21:05:38,257 INFO L290 TraceCheckUtils]: 12: Hoare triple {822#false} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {822#false} is VALID [2022-04-27 21:05:38,257 INFO L290 TraceCheckUtils]: 11: Hoare triple {822#false} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {822#false} is VALID [2022-04-27 21:05:38,258 INFO L290 TraceCheckUtils]: 10: Hoare triple {936#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {822#false} is VALID [2022-04-27 21:05:38,258 INFO L290 TraceCheckUtils]: 9: Hoare triple {828#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {936#(not (< (mod main_~j~0 4294967296) (mod main_~SIZE~0 4294967296)))} is VALID [2022-04-27 21:05:38,259 INFO L290 TraceCheckUtils]: 8: Hoare triple {943#(<= 0 (div (+ (* (- 1) (mod main_~j~0 4294967296)) 1) 4294967296))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {828#(<= main_~SIZE~0 (+ (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:05:38,260 INFO L290 TraceCheckUtils]: 7: Hoare triple {947#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {943#(<= 0 (div (+ (* (- 1) (mod main_~j~0 4294967296)) 1) 4294967296))} is VALID [2022-04-27 21:05:38,260 INFO L290 TraceCheckUtils]: 6: Hoare triple {947#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {947#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} is VALID [2022-04-27 21:05:38,261 INFO L290 TraceCheckUtils]: 5: Hoare triple {821#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {947#(<= 0 (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) 1) 4294967296))} is VALID [2022-04-27 21:05:38,261 INFO L272 TraceCheckUtils]: 4: Hoare triple {821#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:38,261 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {821#true} {821#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:38,261 INFO L290 TraceCheckUtils]: 2: Hoare triple {821#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:38,261 INFO L290 TraceCheckUtils]: 1: Hoare triple {821#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {821#true} is VALID [2022-04-27 21:05:38,262 INFO L272 TraceCheckUtils]: 0: Hoare triple {821#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {821#true} is VALID [2022-04-27 21:05:38,262 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:38,262 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [544959295] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:38,262 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:38,262 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 21:05:38,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [389407359] [2022-04-27 21:05:38,263 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:38,263 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:05:38,264 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:38,264 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:38,288 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 31 edges. 31 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:38,288 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 21:05:38,288 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:38,288 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 21:05:38,289 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:38,289 INFO L87 Difference]: Start difference. First operand 30 states and 34 transitions. Second operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:38,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:38,802 INFO L93 Difference]: Finished difference Result 59 states and 69 transitions. [2022-04-27 21:05:38,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2022-04-27 21:05:38,803 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 23 [2022-04-27 21:05:38,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:38,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:38,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 65 transitions. [2022-04-27 21:05:38,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:38,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7 states to 7 states and 65 transitions. [2022-04-27 21:05:38,807 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 7 states and 65 transitions. [2022-04-27 21:05:38,867 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 65 edges. 65 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:38,868 INFO L225 Difference]: With dead ends: 59 [2022-04-27 21:05:38,868 INFO L226 Difference]: Without dead ends: 38 [2022-04-27 21:05:38,869 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 42 SyntacticMatches, 4 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=133, Unknown=0, NotChecked=0, Total=182 [2022-04-27 21:05:38,869 INFO L413 NwaCegarLoop]: 23 mSDtfsCounter, 49 mSDsluCounter, 32 mSDsCounter, 0 mSdLazyCounter, 154 mSolverCounterSat, 14 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 49 SdHoareTripleChecker+Valid, 55 SdHoareTripleChecker+Invalid, 168 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 14 IncrementalHoareTripleChecker+Valid, 154 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:38,870 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [49 Valid, 55 Invalid, 168 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [14 Valid, 154 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 21:05:38,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2022-04-27 21:05:38,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 32. [2022-04-27 21:05:38,881 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:38,882 INFO L82 GeneralOperation]: Start isEquivalent. First operand 38 states. Second operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:38,882 INFO L74 IsIncluded]: Start isIncluded. First operand 38 states. Second operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:38,882 INFO L87 Difference]: Start difference. First operand 38 states. Second operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:38,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:38,883 INFO L93 Difference]: Finished difference Result 38 states and 44 transitions. [2022-04-27 21:05:38,883 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 44 transitions. [2022-04-27 21:05:38,884 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:38,884 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:38,884 INFO L74 IsIncluded]: Start isIncluded. First operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 38 states. [2022-04-27 21:05:38,884 INFO L87 Difference]: Start difference. First operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) Second operand 38 states. [2022-04-27 21:05:38,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:38,885 INFO L93 Difference]: Finished difference Result 38 states and 44 transitions. [2022-04-27 21:05:38,885 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 44 transitions. [2022-04-27 21:05:38,885 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:38,886 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:38,886 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:38,886 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:38,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 26 states have (on average 1.1923076923076923) internal successors, (31), 26 states have internal predecessors, (31), 3 states have call successors, (3), 3 states have call predecessors, (3), 2 states have return successors, (2), 2 states have call predecessors, (2), 2 states have call successors, (2) [2022-04-27 21:05:38,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 36 transitions. [2022-04-27 21:05:38,887 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 36 transitions. Word has length 23 [2022-04-27 21:05:38,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:38,887 INFO L495 AbstractCegarLoop]: Abstraction has 32 states and 36 transitions. [2022-04-27 21:05:38,887 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 2.6) internal successors, (26), 9 states have internal predecessors, (26), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:38,887 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 36 transitions. [2022-04-27 21:05:38,888 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2022-04-27 21:05:38,888 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:38,888 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:38,914 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (3)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:39,103 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable4,3 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:39,104 INFO L420 AbstractCegarLoop]: === Iteration 6 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:39,104 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:39,104 INFO L85 PathProgramCache]: Analyzing trace with hash 1354614778, now seen corresponding path program 2 times [2022-04-27 21:05:39,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:39,104 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751528683] [2022-04-27 21:05:39,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:39,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:39,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,665 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:39,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,677 INFO L290 TraceCheckUtils]: 0: Hoare triple {1200#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1182#true} is VALID [2022-04-27 21:05:39,678 INFO L290 TraceCheckUtils]: 1: Hoare triple {1182#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:39,678 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1182#true} {1182#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:39,678 INFO L272 TraceCheckUtils]: 0: Hoare triple {1182#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1200#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:39,679 INFO L290 TraceCheckUtils]: 1: Hoare triple {1200#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1182#true} is VALID [2022-04-27 21:05:39,679 INFO L290 TraceCheckUtils]: 2: Hoare triple {1182#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:39,679 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1182#true} {1182#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:39,679 INFO L272 TraceCheckUtils]: 4: Hoare triple {1182#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:39,680 INFO L290 TraceCheckUtils]: 5: Hoare triple {1182#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:39,680 INFO L290 TraceCheckUtils]: 6: Hoare triple {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:39,681 INFO L290 TraceCheckUtils]: 7: Hoare triple {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:39,681 INFO L290 TraceCheckUtils]: 8: Hoare triple {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:39,682 INFO L290 TraceCheckUtils]: 9: Hoare triple {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1189#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:39,682 INFO L290 TraceCheckUtils]: 10: Hoare triple {1189#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1189#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:39,683 INFO L290 TraceCheckUtils]: 11: Hoare triple {1189#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:39,683 INFO L290 TraceCheckUtils]: 12: Hoare triple {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1190#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:39,684 INFO L290 TraceCheckUtils]: 13: Hoare triple {1190#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1191#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} is VALID [2022-04-27 21:05:39,685 INFO L290 TraceCheckUtils]: 14: Hoare triple {1191#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (= (+ |main_~#v~0.offset| (* main_~i~0 4)) 0) (and (not |main_#t~short10|) (<= (+ main_~i~0 1) main_~j~0))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1192#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:05:39,686 INFO L290 TraceCheckUtils]: 15: Hoare triple {1192#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1193#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:39,687 INFO L290 TraceCheckUtils]: 16: Hoare triple {1193#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1194#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:39,687 INFO L290 TraceCheckUtils]: 17: Hoare triple {1194#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:39,688 INFO L290 TraceCheckUtils]: 18: Hoare triple {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:39,688 INFO L290 TraceCheckUtils]: 19: Hoare triple {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1196#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:05:39,689 INFO L290 TraceCheckUtils]: 20: Hoare triple {1196#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1197#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:39,690 INFO L272 TraceCheckUtils]: 21: Hoare triple {1197#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1198#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:05:39,690 INFO L290 TraceCheckUtils]: 22: Hoare triple {1198#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1199#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:05:39,690 INFO L290 TraceCheckUtils]: 23: Hoare triple {1199#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1183#false} is VALID [2022-04-27 21:05:39,691 INFO L290 TraceCheckUtils]: 24: Hoare triple {1183#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#false} is VALID [2022-04-27 21:05:39,691 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:39,691 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:39,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751528683] [2022-04-27 21:05:39,691 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751528683] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:39,691 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [203031548] [2022-04-27 21:05:39,692 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:05:39,692 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:39,692 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:39,693 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:39,703 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Waiting until timeout for monitored process [2022-04-27 21:05:39,749 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:05:39,749 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:05:39,750 INFO L263 TraceCheckSpWp]: Trace formula consists of 114 conjuncts, 28 conjunts are in the unsatisfiable core [2022-04-27 21:05:39,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:39,772 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:39,819 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-04-27 21:05:39,872 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 11 [2022-04-27 21:05:40,221 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:05:40,222 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 21:05:40,342 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:05:40,342 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 21:05:40,416 INFO L272 TraceCheckUtils]: 0: Hoare triple {1182#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:40,416 INFO L290 TraceCheckUtils]: 1: Hoare triple {1182#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1182#true} is VALID [2022-04-27 21:05:40,416 INFO L290 TraceCheckUtils]: 2: Hoare triple {1182#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:40,416 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1182#true} {1182#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:40,416 INFO L272 TraceCheckUtils]: 4: Hoare triple {1182#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:40,420 INFO L290 TraceCheckUtils]: 5: Hoare triple {1182#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:40,420 INFO L290 TraceCheckUtils]: 6: Hoare triple {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:40,421 INFO L290 TraceCheckUtils]: 7: Hoare triple {1187#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1225#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0))} is VALID [2022-04-27 21:05:40,421 INFO L290 TraceCheckUtils]: 8: Hoare triple {1225#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1189#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:40,422 INFO L290 TraceCheckUtils]: 9: Hoare triple {1189#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1189#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:40,422 INFO L290 TraceCheckUtils]: 10: Hoare triple {1189#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1189#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:40,422 INFO L290 TraceCheckUtils]: 11: Hoare triple {1189#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:40,423 INFO L290 TraceCheckUtils]: 12: Hoare triple {1188#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1241#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:40,424 INFO L290 TraceCheckUtils]: 13: Hoare triple {1241#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1245#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) |main_#t~short10|)} is VALID [2022-04-27 21:05:40,424 INFO L290 TraceCheckUtils]: 14: Hoare triple {1245#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) |main_#t~short10|)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1249#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:05:40,425 INFO L290 TraceCheckUtils]: 15: Hoare triple {1249#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= 0 main_~i~0) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1253#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:40,426 INFO L290 TraceCheckUtils]: 16: Hoare triple {1253#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:40,426 INFO L290 TraceCheckUtils]: 17: Hoare triple {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:40,427 INFO L290 TraceCheckUtils]: 18: Hoare triple {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:40,427 INFO L290 TraceCheckUtils]: 19: Hoare triple {1195#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1196#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:05:40,428 INFO L290 TraceCheckUtils]: 20: Hoare triple {1196#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1197#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:40,428 INFO L272 TraceCheckUtils]: 21: Hoare triple {1197#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1272#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:40,429 INFO L290 TraceCheckUtils]: 22: Hoare triple {1272#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1276#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:40,429 INFO L290 TraceCheckUtils]: 23: Hoare triple {1276#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1183#false} is VALID [2022-04-27 21:05:40,429 INFO L290 TraceCheckUtils]: 24: Hoare triple {1183#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#false} is VALID [2022-04-27 21:05:40,429 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:40,430 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:41,127 INFO L290 TraceCheckUtils]: 24: Hoare triple {1183#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1183#false} is VALID [2022-04-27 21:05:41,128 INFO L290 TraceCheckUtils]: 23: Hoare triple {1276#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1183#false} is VALID [2022-04-27 21:05:41,128 INFO L290 TraceCheckUtils]: 22: Hoare triple {1272#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1276#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:41,129 INFO L272 TraceCheckUtils]: 21: Hoare triple {1197#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1272#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:41,130 INFO L290 TraceCheckUtils]: 20: Hoare triple {1295#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1197#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:41,130 INFO L290 TraceCheckUtils]: 19: Hoare triple {1299#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1295#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:05:41,131 INFO L290 TraceCheckUtils]: 18: Hoare triple {1299#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1299#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:41,131 INFO L290 TraceCheckUtils]: 17: Hoare triple {1299#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1299#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:41,132 INFO L290 TraceCheckUtils]: 16: Hoare triple {1309#(forall ((v_ArrVal_52 Int)) (or (not (<= main_~key~0 v_ArrVal_52)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4)))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1299#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:41,133 INFO L290 TraceCheckUtils]: 15: Hoare triple {1313#(or (forall ((v_ArrVal_52 Int)) (or (not (<= main_~key~0 v_ArrVal_52)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1309#(forall ((v_ArrVal_52 Int)) (or (not (<= main_~key~0 v_ArrVal_52)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:05:41,134 INFO L290 TraceCheckUtils]: 14: Hoare triple {1317#(or (not |main_#t~short10|) (forall ((v_ArrVal_52 Int)) (or (< v_ArrVal_52 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1313#(or (forall ((v_ArrVal_52 Int)) (or (not (<= main_~key~0 v_ArrVal_52)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 21:05:41,135 INFO L290 TraceCheckUtils]: 13: Hoare triple {1321#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_52 Int)) (or (< v_ArrVal_52 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1317#(or (not |main_#t~short10|) (forall ((v_ArrVal_52 Int)) (or (< v_ArrVal_52 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-27 21:05:41,137 INFO L290 TraceCheckUtils]: 12: Hoare triple {1325#(or (not (<= 1 main_~j~0)) (forall ((v_ArrVal_52 Int)) (or (< v_ArrVal_52 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1321#(or (not (<= 0 main_~i~0)) (forall ((v_ArrVal_52 Int)) (or (< v_ArrVal_52 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-27 21:05:41,138 INFO L290 TraceCheckUtils]: 11: Hoare triple {1182#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1325#(or (not (<= 1 main_~j~0)) (forall ((v_ArrVal_52 Int)) (or (< v_ArrVal_52 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_52) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)) v_ArrVal_52) (+ |main_~#v~0.offset| 4))))))} is VALID [2022-04-27 21:05:41,138 INFO L290 TraceCheckUtils]: 10: Hoare triple {1182#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:41,138 INFO L290 TraceCheckUtils]: 9: Hoare triple {1182#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1182#true} is VALID [2022-04-27 21:05:41,138 INFO L290 TraceCheckUtils]: 8: Hoare triple {1182#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1182#true} is VALID [2022-04-27 21:05:41,138 INFO L290 TraceCheckUtils]: 7: Hoare triple {1182#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L290 TraceCheckUtils]: 6: Hoare triple {1182#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L290 TraceCheckUtils]: 5: Hoare triple {1182#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L272 TraceCheckUtils]: 4: Hoare triple {1182#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1182#true} {1182#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L290 TraceCheckUtils]: 2: Hoare triple {1182#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L290 TraceCheckUtils]: 1: Hoare triple {1182#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1182#true} is VALID [2022-04-27 21:05:41,139 INFO L272 TraceCheckUtils]: 0: Hoare triple {1182#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1182#true} is VALID [2022-04-27 21:05:41,140 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:41,140 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [203031548] provided 1 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:41,140 INFO L184 FreeRefinementEngine]: Found 1 perfect and 2 imperfect interpolant sequences. [2022-04-27 21:05:41,140 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [16, 15] total 30 [2022-04-27 21:05:41,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1788408282] [2022-04-27 21:05:41,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2022-04-27 21:05:41,141 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 21:05:41,141 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:41,141 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:41,165 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 23 edges. 23 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:41,166 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 12 states [2022-04-27 21:05:41,166 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:41,166 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2022-04-27 21:05:41,167 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=145, Invalid=725, Unknown=0, NotChecked=0, Total=870 [2022-04-27 21:05:41,167 INFO L87 Difference]: Start difference. First operand 32 states and 36 transitions. Second operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:41,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:41,482 INFO L93 Difference]: Finished difference Result 53 states and 61 transitions. [2022-04-27 21:05:41,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2022-04-27 21:05:41,482 INFO L78 Accepts]: Start accepts. Automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 25 [2022-04-27 21:05:41,482 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:41,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:41,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 56 transitions. [2022-04-27 21:05:41,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:41,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 56 transitions. [2022-04-27 21:05:41,486 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 12 states and 56 transitions. [2022-04-27 21:05:41,557 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 56 edges. 56 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:41,558 INFO L225 Difference]: With dead ends: 53 [2022-04-27 21:05:41,558 INFO L226 Difference]: Without dead ends: 51 [2022-04-27 21:05:41,559 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 36 SyntacticMatches, 5 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 399 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=166, Invalid=890, Unknown=0, NotChecked=0, Total=1056 [2022-04-27 21:05:41,560 INFO L413 NwaCegarLoop]: 21 mSDtfsCounter, 17 mSDsluCounter, 172 mSDsCounter, 0 mSdLazyCounter, 43 mSolverCounterSat, 4 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 18 SdHoareTripleChecker+Valid, 193 SdHoareTripleChecker+Invalid, 104 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 4 IncrementalHoareTripleChecker+Valid, 43 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 57 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:41,560 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [18 Valid, 193 Invalid, 104 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [4 Valid, 43 Invalid, 0 Unknown, 57 Unchecked, 0.1s Time] [2022-04-27 21:05:41,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2022-04-27 21:05:41,589 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 45. [2022-04-27 21:05:41,589 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:41,590 INFO L82 GeneralOperation]: Start isEquivalent. First operand 51 states. Second operand has 45 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 38 states have internal predecessors, (45), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:41,590 INFO L74 IsIncluded]: Start isIncluded. First operand 51 states. Second operand has 45 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 38 states have internal predecessors, (45), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:41,590 INFO L87 Difference]: Start difference. First operand 51 states. Second operand has 45 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 38 states have internal predecessors, (45), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:41,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:41,593 INFO L93 Difference]: Finished difference Result 51 states and 59 transitions. [2022-04-27 21:05:41,593 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 59 transitions. [2022-04-27 21:05:41,593 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:41,593 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:41,593 INFO L74 IsIncluded]: Start isIncluded. First operand has 45 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 38 states have internal predecessors, (45), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 51 states. [2022-04-27 21:05:41,594 INFO L87 Difference]: Start difference. First operand has 45 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 38 states have internal predecessors, (45), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 51 states. [2022-04-27 21:05:41,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:41,596 INFO L93 Difference]: Finished difference Result 51 states and 59 transitions. [2022-04-27 21:05:41,596 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 59 transitions. [2022-04-27 21:05:41,596 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:41,596 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:41,596 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:41,596 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:41,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 37 states have (on average 1.2162162162162162) internal successors, (45), 38 states have internal predecessors, (45), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:41,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 52 transitions. [2022-04-27 21:05:41,598 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 52 transitions. Word has length 25 [2022-04-27 21:05:41,598 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:41,598 INFO L495 AbstractCegarLoop]: Abstraction has 45 states and 52 transitions. [2022-04-27 21:05:41,599 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 12 states, 11 states have (on average 1.7272727272727273) internal successors, (19), 11 states have internal predecessors, (19), 2 states have call successors, (3), 2 states have call predecessors, (3), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:41,599 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 52 transitions. [2022-04-27 21:05:41,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-04-27 21:05:41,599 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:41,599 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:41,624 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (4)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:41,819 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable5,4 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:41,820 INFO L420 AbstractCegarLoop]: === Iteration 7 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:41,820 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:41,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1272155915, now seen corresponding path program 1 times [2022-04-27 21:05:41,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:41,820 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326535491] [2022-04-27 21:05:41,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:41,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:41,875 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:42,299 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:42,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:42,307 INFO L290 TraceCheckUtils]: 0: Hoare triple {1629#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1610#true} is VALID [2022-04-27 21:05:42,307 INFO L290 TraceCheckUtils]: 1: Hoare triple {1610#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:42,307 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {1610#true} {1610#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:42,308 INFO L272 TraceCheckUtils]: 0: Hoare triple {1610#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1629#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:42,308 INFO L290 TraceCheckUtils]: 1: Hoare triple {1629#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1610#true} is VALID [2022-04-27 21:05:42,308 INFO L290 TraceCheckUtils]: 2: Hoare triple {1610#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:42,309 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1610#true} {1610#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:42,309 INFO L272 TraceCheckUtils]: 4: Hoare triple {1610#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:42,309 INFO L290 TraceCheckUtils]: 5: Hoare triple {1610#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1615#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:42,310 INFO L290 TraceCheckUtils]: 6: Hoare triple {1615#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1615#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:05:42,311 INFO L290 TraceCheckUtils]: 7: Hoare triple {1615#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1616#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:42,311 INFO L290 TraceCheckUtils]: 8: Hoare triple {1616#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1616#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:42,312 INFO L290 TraceCheckUtils]: 9: Hoare triple {1616#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1617#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:42,312 INFO L290 TraceCheckUtils]: 10: Hoare triple {1617#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1617#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:05:42,313 INFO L290 TraceCheckUtils]: 11: Hoare triple {1617#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1616#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:05:42,314 INFO L290 TraceCheckUtils]: 12: Hoare triple {1616#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1618#(and (= |main_~#v~0.offset| 0) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (and (<= (+ main_~i~0 1) 0) (= (+ (- 1) main_~j~0) 0))))} is VALID [2022-04-27 21:05:42,315 INFO L290 TraceCheckUtils]: 13: Hoare triple {1618#(and (= |main_~#v~0.offset| 0) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (and (<= (+ main_~i~0 1) 0) (= (+ (- 1) main_~j~0) 0))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1619#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:42,316 INFO L290 TraceCheckUtils]: 14: Hoare triple {1619#(or (not |main_#t~short10|) (and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1620#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:05:42,317 INFO L290 TraceCheckUtils]: 15: Hoare triple {1620#(and (= |main_~#v~0.offset| 0) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {1621#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:05:42,318 INFO L290 TraceCheckUtils]: 16: Hoare triple {1621#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ main_~i~0 1)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1622#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} is VALID [2022-04-27 21:05:42,318 INFO L290 TraceCheckUtils]: 17: Hoare triple {1622#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (or (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (and (<= 0 (+ main_~i~0 1)) |main_#t~short10|)))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1623#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:05:42,319 INFO L290 TraceCheckUtils]: 18: Hoare triple {1623#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1623#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:05:42,320 INFO L290 TraceCheckUtils]: 19: Hoare triple {1623#(and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1624#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:42,321 INFO L290 TraceCheckUtils]: 20: Hoare triple {1624#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1624#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:42,321 INFO L290 TraceCheckUtils]: 21: Hoare triple {1624#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1624#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:05:42,322 INFO L290 TraceCheckUtils]: 22: Hoare triple {1624#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1625#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:05:42,323 INFO L290 TraceCheckUtils]: 23: Hoare triple {1625#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1626#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:05:42,324 INFO L272 TraceCheckUtils]: 24: Hoare triple {1626#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1627#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:05:42,324 INFO L290 TraceCheckUtils]: 25: Hoare triple {1627#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1628#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:05:42,325 INFO L290 TraceCheckUtils]: 26: Hoare triple {1628#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1611#false} is VALID [2022-04-27 21:05:42,325 INFO L290 TraceCheckUtils]: 27: Hoare triple {1611#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1611#false} is VALID [2022-04-27 21:05:42,325 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2022-04-27 21:05:42,325 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:42,325 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326535491] [2022-04-27 21:05:42,326 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326535491] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:42,326 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [253160090] [2022-04-27 21:05:42,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:42,326 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:42,326 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:42,327 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:42,328 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Waiting until timeout for monitored process [2022-04-27 21:05:42,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:42,396 INFO L263 TraceCheckSpWp]: Trace formula consists of 123 conjuncts, 23 conjunts are in the unsatisfiable core [2022-04-27 21:05:42,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:42,412 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:42,819 INFO L356 Elim1Store]: treesize reduction 39, result has 22.0 percent of original size [2022-04-27 21:05:42,819 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 39 treesize of output 30 [2022-04-27 21:05:43,579 INFO L356 Elim1Store]: treesize reduction 108, result has 10.0 percent of original size [2022-04-27 21:05:43,580 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 48 treesize of output 31 [2022-04-27 21:05:44,623 INFO L356 Elim1Store]: treesize reduction 78, result has 8.2 percent of original size [2022-04-27 21:05:44,623 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 4 new quantified variables, introduced 6 case distinctions, treesize of input 38 treesize of output 16 [2022-04-27 21:05:44,765 INFO L272 TraceCheckUtils]: 0: Hoare triple {1610#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:44,766 INFO L290 TraceCheckUtils]: 1: Hoare triple {1610#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1610#true} is VALID [2022-04-27 21:05:44,766 INFO L290 TraceCheckUtils]: 2: Hoare triple {1610#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:44,766 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1610#true} {1610#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:44,766 INFO L272 TraceCheckUtils]: 4: Hoare triple {1610#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:44,766 INFO L290 TraceCheckUtils]: 5: Hoare triple {1610#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1610#true} is VALID [2022-04-27 21:05:44,767 INFO L290 TraceCheckUtils]: 6: Hoare triple {1610#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1610#true} is VALID [2022-04-27 21:05:44,767 INFO L290 TraceCheckUtils]: 7: Hoare triple {1610#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1610#true} is VALID [2022-04-27 21:05:44,767 INFO L290 TraceCheckUtils]: 8: Hoare triple {1610#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1610#true} is VALID [2022-04-27 21:05:44,767 INFO L290 TraceCheckUtils]: 9: Hoare triple {1610#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1610#true} is VALID [2022-04-27 21:05:44,767 INFO L290 TraceCheckUtils]: 10: Hoare triple {1610#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:44,768 INFO L290 TraceCheckUtils]: 11: Hoare triple {1610#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1666#(<= main_~j~0 1)} is VALID [2022-04-27 21:05:44,768 INFO L290 TraceCheckUtils]: 12: Hoare triple {1666#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1670#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:44,769 INFO L290 TraceCheckUtils]: 13: Hoare triple {1670#(<= main_~i~0 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1674#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:05:44,769 INFO L290 TraceCheckUtils]: 14: Hoare triple {1674#(and (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1678#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} is VALID [2022-04-27 21:05:44,771 INFO L290 TraceCheckUtils]: 15: Hoare triple {1678#(and (<= main_~i~0 0) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (<= 0 main_~i~0))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {1682#(exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))))))} is VALID [2022-04-27 21:05:44,773 INFO L290 TraceCheckUtils]: 16: Hoare triple {1682#(exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1686#(and (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:05:44,774 INFO L290 TraceCheckUtils]: 17: Hoare triple {1686#(and (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= v_main_~i~0_11 0) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1690#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} is VALID [2022-04-27 21:05:44,774 INFO L290 TraceCheckUtils]: 18: Hoare triple {1690#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1690#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} is VALID [2022-04-27 21:05:44,775 INFO L290 TraceCheckUtils]: 19: Hoare triple {1690#(and (< main_~i~0 0) (exists ((v_main_~i~0_11 Int)) (and (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= v_main_~i~0_11 (+ main_~i~0 1)) (<= 0 v_main_~i~0_11) (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4)))))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1697#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} is VALID [2022-04-27 21:05:44,777 INFO L290 TraceCheckUtils]: 20: Hoare triple {1697#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1697#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} is VALID [2022-04-27 21:05:44,778 INFO L290 TraceCheckUtils]: 21: Hoare triple {1697#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1697#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} is VALID [2022-04-27 21:05:44,780 INFO L290 TraceCheckUtils]: 22: Hoare triple {1697#(exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1707#(and (exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11))) (= main_~k~0 1))} is VALID [2022-04-27 21:05:44,781 INFO L290 TraceCheckUtils]: 23: Hoare triple {1707#(and (exists ((main_~i~0 Int) (v_main_~i~0_11 Int)) (and (< main_~i~0 0) (<= v_main_~i~0_11 (+ main_~i~0 1)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* v_main_~i~0_11 4) 4))) (<= 0 v_main_~i~0_11))) (= main_~k~0 1))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1626#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:05:44,788 INFO L272 TraceCheckUtils]: 24: Hoare triple {1626#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1714#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:44,788 INFO L290 TraceCheckUtils]: 25: Hoare triple {1714#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1718#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:44,789 INFO L290 TraceCheckUtils]: 26: Hoare triple {1718#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1611#false} is VALID [2022-04-27 21:05:44,789 INFO L290 TraceCheckUtils]: 27: Hoare triple {1611#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1611#false} is VALID [2022-04-27 21:05:44,789 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:44,789 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:46,022 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 61 [2022-04-27 21:05:46,110 INFO L356 Elim1Store]: treesize reduction 36, result has 2.7 percent of original size [2022-04-27 21:05:46,110 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 383 treesize of output 347 [2022-04-27 21:05:47,194 INFO L290 TraceCheckUtils]: 27: Hoare triple {1611#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1611#false} is VALID [2022-04-27 21:05:47,195 INFO L290 TraceCheckUtils]: 26: Hoare triple {1718#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {1611#false} is VALID [2022-04-27 21:05:47,195 INFO L290 TraceCheckUtils]: 25: Hoare triple {1714#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {1718#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:05:47,196 INFO L272 TraceCheckUtils]: 24: Hoare triple {1734#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {1714#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:05:47,196 INFO L290 TraceCheckUtils]: 23: Hoare triple {1738#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {1734#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:05:47,197 INFO L290 TraceCheckUtils]: 22: Hoare triple {1742#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {1738#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:05:47,197 INFO L290 TraceCheckUtils]: 21: Hoare triple {1742#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {1742#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:47,197 INFO L290 TraceCheckUtils]: 20: Hoare triple {1742#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {1742#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:47,198 INFO L290 TraceCheckUtils]: 19: Hoare triple {1752#(forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {1742#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:05:47,199 INFO L290 TraceCheckUtils]: 18: Hoare triple {1752#(forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1752#(forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0))))} is VALID [2022-04-27 21:05:47,199 INFO L290 TraceCheckUtils]: 17: Hoare triple {1759#(or (forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0)))) |main_#t~short10|)} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {1752#(forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0))))} is VALID [2022-04-27 21:05:47,200 INFO L290 TraceCheckUtils]: 16: Hoare triple {1763#(or (<= 0 main_~i~0) (forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0)))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1759#(or (forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0)))) |main_#t~short10|)} is VALID [2022-04-27 21:05:47,208 INFO L290 TraceCheckUtils]: 15: Hoare triple {1767#(or (not |main_#t~short10|) (forall ((v_main_~i~0_12 Int) (v_ArrVal_76 Int) (v_ArrVal_73 Int)) (or (not (<= v_ArrVal_76 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_12 1))) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_73)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_73) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_76) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_73) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_12))))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {1763#(or (<= 0 main_~i~0) (forall ((v_ArrVal_76 Int)) (or (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (not (<= v_ArrVal_76 main_~key~0)))))} is VALID [2022-04-27 21:05:47,210 INFO L290 TraceCheckUtils]: 14: Hoare triple {1771#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {1767#(or (not |main_#t~short10|) (forall ((v_main_~i~0_12 Int) (v_ArrVal_76 Int) (v_ArrVal_73 Int)) (or (not (<= v_ArrVal_76 main_~key~0)) (not (<= main_~i~0 (+ v_main_~i~0_12 1))) (not (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) v_ArrVal_73)) (<= (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_73) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_76) |main_~#v~0.offset|) (select (store (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_73) (+ |main_~#v~0.offset| (* v_main_~i~0_12 4) 4) v_ArrVal_76) (+ |main_~#v~0.offset| 4))) (<= 0 v_main_~i~0_12))))} is VALID [2022-04-27 21:05:47,210 INFO L290 TraceCheckUtils]: 13: Hoare triple {1610#true} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {1771#(or (not |main_#t~short10|) (<= 1 main_~i~0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:05:47,210 INFO L290 TraceCheckUtils]: 12: Hoare triple {1610#true} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {1610#true} is VALID [2022-04-27 21:05:47,211 INFO L290 TraceCheckUtils]: 11: Hoare triple {1610#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {1610#true} is VALID [2022-04-27 21:05:47,213 INFO L290 TraceCheckUtils]: 10: Hoare triple {1610#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:47,213 INFO L290 TraceCheckUtils]: 9: Hoare triple {1610#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1610#true} is VALID [2022-04-27 21:05:47,213 INFO L290 TraceCheckUtils]: 8: Hoare triple {1610#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1610#true} is VALID [2022-04-27 21:05:47,213 INFO L290 TraceCheckUtils]: 7: Hoare triple {1610#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {1610#true} is VALID [2022-04-27 21:05:47,213 INFO L290 TraceCheckUtils]: 6: Hoare triple {1610#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {1610#true} is VALID [2022-04-27 21:05:47,213 INFO L290 TraceCheckUtils]: 5: Hoare triple {1610#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {1610#true} is VALID [2022-04-27 21:05:47,214 INFO L272 TraceCheckUtils]: 4: Hoare triple {1610#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:47,214 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {1610#true} {1610#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:47,214 INFO L290 TraceCheckUtils]: 2: Hoare triple {1610#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:47,215 INFO L290 TraceCheckUtils]: 1: Hoare triple {1610#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {1610#true} is VALID [2022-04-27 21:05:47,215 INFO L272 TraceCheckUtils]: 0: Hoare triple {1610#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {1610#true} is VALID [2022-04-27 21:05:47,215 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:47,215 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [253160090] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:47,215 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:47,215 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 14, 12] total 36 [2022-04-27 21:05:47,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246175410] [2022-04-27 21:05:47,216 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:47,217 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2022-04-27 21:05:47,218 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:47,218 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:47,283 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 64 edges. 64 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:47,283 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 36 states [2022-04-27 21:05:47,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:47,283 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2022-04-27 21:05:47,284 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=135, Invalid=1124, Unknown=1, NotChecked=0, Total=1260 [2022-04-27 21:05:47,284 INFO L87 Difference]: Start difference. First operand 45 states and 52 transitions. Second operand has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:57,485 INFO L93 Difference]: Finished difference Result 103 states and 131 transitions. [2022-04-27 21:05:57,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2022-04-27 21:05:57,485 INFO L78 Accepts]: Start accepts. Automaton has has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2022-04-27 21:05:57,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:57,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 100 transitions. [2022-04-27 21:05:57,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 100 transitions. [2022-04-27 21:05:57,491 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 37 states and 100 transitions. [2022-04-27 21:05:57,595 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 100 edges. 100 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:57,598 INFO L225 Difference]: With dead ends: 103 [2022-04-27 21:05:57,598 INFO L226 Difference]: Without dead ends: 101 [2022-04-27 21:05:57,599 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 44 SyntacticMatches, 3 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1146 ImplicationChecksByTransitivity, 10.5s TimeCoverageRelationStatistics Valid=447, Invalid=3831, Unknown=12, NotChecked=0, Total=4290 [2022-04-27 21:05:57,599 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 81 mSDsluCounter, 107 mSDsCounter, 0 mSdLazyCounter, 463 mSolverCounterSat, 42 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.5s Time, 0 mProtectedPredicate, 0 mProtectedAction, 82 SdHoareTripleChecker+Valid, 133 SdHoareTripleChecker+Invalid, 720 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 42 IncrementalHoareTripleChecker+Valid, 463 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 215 IncrementalHoareTripleChecker+Unchecked, 0.5s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:57,600 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [82 Valid, 133 Invalid, 720 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [42 Valid, 463 Invalid, 0 Unknown, 215 Unchecked, 0.5s Time] [2022-04-27 21:05:57,600 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 101 states. [2022-04-27 21:05:57,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 101 to 52. [2022-04-27 21:05:57,644 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:57,644 INFO L82 GeneralOperation]: Start isEquivalent. First operand 101 states. Second operand has 52 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 45 states have internal predecessors, (56), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,645 INFO L74 IsIncluded]: Start isIncluded. First operand 101 states. Second operand has 52 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 45 states have internal predecessors, (56), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,645 INFO L87 Difference]: Start difference. First operand 101 states. Second operand has 52 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 45 states have internal predecessors, (56), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,652 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:57,652 INFO L93 Difference]: Finished difference Result 101 states and 129 transitions. [2022-04-27 21:05:57,652 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 129 transitions. [2022-04-27 21:05:57,653 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:57,653 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:57,653 INFO L74 IsIncluded]: Start isIncluded. First operand has 52 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 45 states have internal predecessors, (56), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 101 states. [2022-04-27 21:05:57,653 INFO L87 Difference]: Start difference. First operand has 52 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 45 states have internal predecessors, (56), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 101 states. [2022-04-27 21:05:57,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:57,658 INFO L93 Difference]: Finished difference Result 101 states and 129 transitions. [2022-04-27 21:05:57,658 INFO L276 IsEmpty]: Start isEmpty. Operand 101 states and 129 transitions. [2022-04-27 21:05:57,659 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:57,659 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:57,659 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:57,659 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:57,659 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 44 states have (on average 1.2727272727272727) internal successors, (56), 45 states have internal predecessors, (56), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:57,660 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 63 transitions. [2022-04-27 21:05:57,661 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 63 transitions. Word has length 28 [2022-04-27 21:05:57,661 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:57,661 INFO L495 AbstractCegarLoop]: Abstraction has 52 states and 63 transitions. [2022-04-27 21:05:57,661 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 36 states, 34 states have (on average 1.6764705882352942) internal successors, (57), 33 states have internal predecessors, (57), 3 states have call successors, (6), 4 states have call predecessors, (6), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:57,661 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 63 transitions. [2022-04-27 21:05:57,661 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2022-04-27 21:05:57,662 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:57,662 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:57,684 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (5)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:57,879 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable6,5 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:57,879 INFO L420 AbstractCegarLoop]: === Iteration 8 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:57,880 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:57,880 INFO L85 PathProgramCache]: Analyzing trace with hash 524795444, now seen corresponding path program 1 times [2022-04-27 21:05:57,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:57,880 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1556715253] [2022-04-27 21:05:57,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:57,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:57,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:57,966 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:57,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:57,971 INFO L290 TraceCheckUtils]: 0: Hoare triple {2308#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2299#true} is VALID [2022-04-27 21:05:57,971 INFO L290 TraceCheckUtils]: 1: Hoare triple {2299#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:57,976 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2299#true} {2299#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:57,976 INFO L272 TraceCheckUtils]: 0: Hoare triple {2299#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2308#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:57,976 INFO L290 TraceCheckUtils]: 1: Hoare triple {2308#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2299#true} is VALID [2022-04-27 21:05:57,976 INFO L290 TraceCheckUtils]: 2: Hoare triple {2299#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2299#true} {2299#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L272 TraceCheckUtils]: 4: Hoare triple {2299#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L290 TraceCheckUtils]: 5: Hoare triple {2299#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L290 TraceCheckUtils]: 6: Hoare triple {2299#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L290 TraceCheckUtils]: 7: Hoare triple {2299#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L290 TraceCheckUtils]: 8: Hoare triple {2299#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L290 TraceCheckUtils]: 9: Hoare triple {2299#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2299#true} is VALID [2022-04-27 21:05:57,977 INFO L290 TraceCheckUtils]: 10: Hoare triple {2299#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:57,978 INFO L290 TraceCheckUtils]: 11: Hoare triple {2299#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2304#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:57,978 INFO L290 TraceCheckUtils]: 12: Hoare triple {2304#(= (+ (- 1) main_~j~0) 0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2305#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:57,979 INFO L290 TraceCheckUtils]: 13: Hoare triple {2305#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2305#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:57,979 INFO L290 TraceCheckUtils]: 14: Hoare triple {2305#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2305#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:05:57,980 INFO L290 TraceCheckUtils]: 15: Hoare triple {2305#(and (= (+ (- 1) main_~j~0) 0) (<= (+ main_~i~0 1) main_~j~0))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {2306#(and (<= (+ main_~i~0 2) main_~j~0) (= (+ (- 1) main_~j~0) 0))} is VALID [2022-04-27 21:05:57,981 INFO L290 TraceCheckUtils]: 16: Hoare triple {2306#(and (<= (+ main_~i~0 2) main_~j~0) (= (+ (- 1) main_~j~0) 0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2307#(and (= (+ (- 1) main_~j~0) 0) (not |main_#t~short10|))} is VALID [2022-04-27 21:05:57,981 INFO L290 TraceCheckUtils]: 17: Hoare triple {2307#(and (= (+ (- 1) main_~j~0) 0) (not |main_#t~short10|))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2300#false} is VALID [2022-04-27 21:05:57,981 INFO L290 TraceCheckUtils]: 18: Hoare triple {2300#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2300#false} is VALID [2022-04-27 21:05:57,981 INFO L290 TraceCheckUtils]: 19: Hoare triple {2300#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2300#false} is VALID [2022-04-27 21:05:57,981 INFO L290 TraceCheckUtils]: 20: Hoare triple {2300#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L290 TraceCheckUtils]: 21: Hoare triple {2300#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L290 TraceCheckUtils]: 22: Hoare triple {2300#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L290 TraceCheckUtils]: 23: Hoare triple {2300#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L272 TraceCheckUtils]: 24: Hoare triple {2300#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L290 TraceCheckUtils]: 25: Hoare triple {2300#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L290 TraceCheckUtils]: 26: Hoare triple {2300#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:57,982 INFO L290 TraceCheckUtils]: 27: Hoare triple {2300#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:57,983 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:57,983 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:57,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1556715253] [2022-04-27 21:05:57,983 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1556715253] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:57,983 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [378504927] [2022-04-27 21:05:57,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:57,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:57,983 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:57,988 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:57,992 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Waiting until timeout for monitored process [2022-04-27 21:05:58,037 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,038 INFO L263 TraceCheckSpWp]: Trace formula consists of 126 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 21:05:58,048 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:58,048 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:58,146 INFO L272 TraceCheckUtils]: 0: Hoare triple {2299#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,146 INFO L290 TraceCheckUtils]: 1: Hoare triple {2299#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2299#true} is VALID [2022-04-27 21:05:58,146 INFO L290 TraceCheckUtils]: 2: Hoare triple {2299#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,146 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2299#true} {2299#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L272 TraceCheckUtils]: 4: Hoare triple {2299#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L290 TraceCheckUtils]: 5: Hoare triple {2299#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L290 TraceCheckUtils]: 6: Hoare triple {2299#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L290 TraceCheckUtils]: 7: Hoare triple {2299#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L290 TraceCheckUtils]: 8: Hoare triple {2299#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L290 TraceCheckUtils]: 9: Hoare triple {2299#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2299#true} is VALID [2022-04-27 21:05:58,147 INFO L290 TraceCheckUtils]: 10: Hoare triple {2299#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,148 INFO L290 TraceCheckUtils]: 11: Hoare triple {2299#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2345#(<= main_~j~0 1)} is VALID [2022-04-27 21:05:58,148 INFO L290 TraceCheckUtils]: 12: Hoare triple {2345#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2349#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:58,149 INFO L290 TraceCheckUtils]: 13: Hoare triple {2349#(<= main_~i~0 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2349#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:58,149 INFO L290 TraceCheckUtils]: 14: Hoare triple {2349#(<= main_~i~0 0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2349#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:58,150 INFO L290 TraceCheckUtils]: 15: Hoare triple {2349#(<= main_~i~0 0)} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {2359#(<= (+ main_~i~0 1) 0)} is VALID [2022-04-27 21:05:58,150 INFO L290 TraceCheckUtils]: 16: Hoare triple {2359#(<= (+ main_~i~0 1) 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2363#(not |main_#t~short10|)} is VALID [2022-04-27 21:05:58,151 INFO L290 TraceCheckUtils]: 17: Hoare triple {2363#(not |main_#t~short10|)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2300#false} is VALID [2022-04-27 21:05:58,151 INFO L290 TraceCheckUtils]: 18: Hoare triple {2300#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2300#false} is VALID [2022-04-27 21:05:58,151 INFO L290 TraceCheckUtils]: 19: Hoare triple {2300#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2300#false} is VALID [2022-04-27 21:05:58,151 INFO L290 TraceCheckUtils]: 20: Hoare triple {2300#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2300#false} is VALID [2022-04-27 21:05:58,151 INFO L290 TraceCheckUtils]: 21: Hoare triple {2300#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:58,151 INFO L290 TraceCheckUtils]: 22: Hoare triple {2300#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2300#false} is VALID [2022-04-27 21:05:58,152 INFO L290 TraceCheckUtils]: 23: Hoare triple {2300#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2300#false} is VALID [2022-04-27 21:05:58,152 INFO L272 TraceCheckUtils]: 24: Hoare triple {2300#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2300#false} is VALID [2022-04-27 21:05:58,152 INFO L290 TraceCheckUtils]: 25: Hoare triple {2300#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2300#false} is VALID [2022-04-27 21:05:58,152 INFO L290 TraceCheckUtils]: 26: Hoare triple {2300#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:58,152 INFO L290 TraceCheckUtils]: 27: Hoare triple {2300#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:58,152 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:58,152 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:58,260 INFO L290 TraceCheckUtils]: 27: Hoare triple {2300#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L290 TraceCheckUtils]: 26: Hoare triple {2300#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L290 TraceCheckUtils]: 25: Hoare triple {2300#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L272 TraceCheckUtils]: 24: Hoare triple {2300#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L290 TraceCheckUtils]: 23: Hoare triple {2300#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L290 TraceCheckUtils]: 22: Hoare triple {2300#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L290 TraceCheckUtils]: 21: Hoare triple {2300#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2300#false} is VALID [2022-04-27 21:05:58,261 INFO L290 TraceCheckUtils]: 20: Hoare triple {2300#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2300#false} is VALID [2022-04-27 21:05:58,262 INFO L290 TraceCheckUtils]: 19: Hoare triple {2300#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2300#false} is VALID [2022-04-27 21:05:58,262 INFO L290 TraceCheckUtils]: 18: Hoare triple {2300#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2300#false} is VALID [2022-04-27 21:05:58,262 INFO L290 TraceCheckUtils]: 17: Hoare triple {2363#(not |main_#t~short10|)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2300#false} is VALID [2022-04-27 21:05:58,263 INFO L290 TraceCheckUtils]: 16: Hoare triple {2359#(<= (+ main_~i~0 1) 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2363#(not |main_#t~short10|)} is VALID [2022-04-27 21:05:58,264 INFO L290 TraceCheckUtils]: 15: Hoare triple {2349#(<= main_~i~0 0)} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {2359#(<= (+ main_~i~0 1) 0)} is VALID [2022-04-27 21:05:58,265 INFO L290 TraceCheckUtils]: 14: Hoare triple {2349#(<= main_~i~0 0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2349#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:58,265 INFO L290 TraceCheckUtils]: 13: Hoare triple {2349#(<= main_~i~0 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2349#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:58,266 INFO L290 TraceCheckUtils]: 12: Hoare triple {2345#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2349#(<= main_~i~0 0)} is VALID [2022-04-27 21:05:58,266 INFO L290 TraceCheckUtils]: 11: Hoare triple {2299#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2345#(<= main_~j~0 1)} is VALID [2022-04-27 21:05:58,266 INFO L290 TraceCheckUtils]: 10: Hoare triple {2299#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,266 INFO L290 TraceCheckUtils]: 9: Hoare triple {2299#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2299#true} is VALID [2022-04-27 21:05:58,266 INFO L290 TraceCheckUtils]: 8: Hoare triple {2299#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2299#true} is VALID [2022-04-27 21:05:58,266 INFO L290 TraceCheckUtils]: 7: Hoare triple {2299#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L290 TraceCheckUtils]: 6: Hoare triple {2299#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L290 TraceCheckUtils]: 5: Hoare triple {2299#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L272 TraceCheckUtils]: 4: Hoare triple {2299#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2299#true} {2299#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L290 TraceCheckUtils]: 2: Hoare triple {2299#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L290 TraceCheckUtils]: 1: Hoare triple {2299#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L272 TraceCheckUtils]: 0: Hoare triple {2299#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2299#true} is VALID [2022-04-27 21:05:58,267 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 1 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:58,268 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [378504927] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:58,268 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:58,268 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 11 [2022-04-27 21:05:58,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1391511884] [2022-04-27 21:05:58,268 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:58,268 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2022-04-27 21:05:58,269 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:58,269 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:58,300 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 35 edges. 35 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:58,300 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 11 states [2022-04-27 21:05:58,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:58,300 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2022-04-27 21:05:58,300 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2022-04-27 21:05:58,301 INFO L87 Difference]: Start difference. First operand 52 states and 63 transitions. Second operand has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:58,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:58,730 INFO L93 Difference]: Finished difference Result 107 states and 134 transitions. [2022-04-27 21:05:58,730 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2022-04-27 21:05:58,730 INFO L78 Accepts]: Start accepts. Automaton has has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 28 [2022-04-27 21:05:58,731 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:05:58,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:58,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 84 transitions. [2022-04-27 21:05:58,733 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:58,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 84 transitions. [2022-04-27 21:05:58,734 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 11 states and 84 transitions. [2022-04-27 21:05:58,810 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 84 edges. 84 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:58,811 INFO L225 Difference]: With dead ends: 107 [2022-04-27 21:05:58,811 INFO L226 Difference]: Without dead ends: 76 [2022-04-27 21:05:58,812 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 54 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=98, Invalid=244, Unknown=0, NotChecked=0, Total=342 [2022-04-27 21:05:58,812 INFO L413 NwaCegarLoop]: 28 mSDtfsCounter, 67 mSDsluCounter, 17 mSDsCounter, 0 mSdLazyCounter, 147 mSolverCounterSat, 23 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 68 SdHoareTripleChecker+Valid, 45 SdHoareTripleChecker+Invalid, 170 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 23 IncrementalHoareTripleChecker+Valid, 147 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:05:58,813 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [68 Valid, 45 Invalid, 170 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [23 Valid, 147 Invalid, 0 Unknown, 0 Unchecked, 0.1s Time] [2022-04-27 21:05:58,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2022-04-27 21:05:58,869 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 55. [2022-04-27 21:05:58,869 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:05:58,869 INFO L82 GeneralOperation]: Start isEquivalent. First operand 76 states. Second operand has 55 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 48 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:58,869 INFO L74 IsIncluded]: Start isIncluded. First operand 76 states. Second operand has 55 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 48 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:58,870 INFO L87 Difference]: Start difference. First operand 76 states. Second operand has 55 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 48 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:58,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:58,872 INFO L93 Difference]: Finished difference Result 76 states and 92 transitions. [2022-04-27 21:05:58,872 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 92 transitions. [2022-04-27 21:05:58,872 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:58,872 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:58,873 INFO L74 IsIncluded]: Start isIncluded. First operand has 55 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 48 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 76 states. [2022-04-27 21:05:58,873 INFO L87 Difference]: Start difference. First operand has 55 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 48 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 76 states. [2022-04-27 21:05:58,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:05:58,875 INFO L93 Difference]: Finished difference Result 76 states and 92 transitions. [2022-04-27 21:05:58,875 INFO L276 IsEmpty]: Start isEmpty. Operand 76 states and 92 transitions. [2022-04-27 21:05:58,875 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:05:58,875 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:05:58,875 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:05:58,875 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:05:58,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 55 states, 47 states have (on average 1.2340425531914894) internal successors, (58), 48 states have internal predecessors, (58), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:05:58,877 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 55 states to 55 states and 65 transitions. [2022-04-27 21:05:58,877 INFO L78 Accepts]: Start accepts. Automaton has 55 states and 65 transitions. Word has length 28 [2022-04-27 21:05:58,877 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:05:58,877 INFO L495 AbstractCegarLoop]: Abstraction has 55 states and 65 transitions. [2022-04-27 21:05:58,877 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 11 states, 11 states have (on average 2.727272727272727) internal successors, (30), 10 states have internal predecessors, (30), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:58,877 INFO L276 IsEmpty]: Start isEmpty. Operand 55 states and 65 transitions. [2022-04-27 21:05:58,878 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2022-04-27 21:05:58,878 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:05:58,878 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:05:58,899 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (6)] Forceful destruction successful, exit code 0 [2022-04-27 21:05:59,091 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable7,6 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:59,091 INFO L420 AbstractCegarLoop]: === Iteration 9 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:05:59,092 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:05:59,092 INFO L85 PathProgramCache]: Analyzing trace with hash -551964914, now seen corresponding path program 1 times [2022-04-27 21:05:59,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:05:59,092 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [51771492] [2022-04-27 21:05:59,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:59,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:05:59,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:59,154 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:05:59,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:59,158 INFO L290 TraceCheckUtils]: 0: Hoare triple {2883#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2874#true} is VALID [2022-04-27 21:05:59,159 INFO L290 TraceCheckUtils]: 1: Hoare triple {2874#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,159 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {2874#true} {2874#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,159 INFO L272 TraceCheckUtils]: 0: Hoare triple {2874#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2883#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:05:59,159 INFO L290 TraceCheckUtils]: 1: Hoare triple {2883#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2874#true} is VALID [2022-04-27 21:05:59,159 INFO L290 TraceCheckUtils]: 2: Hoare triple {2874#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2874#true} {2874#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L272 TraceCheckUtils]: 4: Hoare triple {2874#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L290 TraceCheckUtils]: 5: Hoare triple {2874#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L290 TraceCheckUtils]: 6: Hoare triple {2874#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L290 TraceCheckUtils]: 7: Hoare triple {2874#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L290 TraceCheckUtils]: 8: Hoare triple {2874#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L290 TraceCheckUtils]: 9: Hoare triple {2874#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2874#true} is VALID [2022-04-27 21:05:59,160 INFO L290 TraceCheckUtils]: 10: Hoare triple {2874#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,161 INFO L290 TraceCheckUtils]: 11: Hoare triple {2874#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2879#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:59,161 INFO L290 TraceCheckUtils]: 12: Hoare triple {2879#(= (+ (- 1) main_~j~0) 0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2879#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:59,162 INFO L290 TraceCheckUtils]: 13: Hoare triple {2879#(= (+ (- 1) main_~j~0) 0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2879#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:59,163 INFO L290 TraceCheckUtils]: 14: Hoare triple {2879#(= (+ (- 1) main_~j~0) 0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2879#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:59,163 INFO L290 TraceCheckUtils]: 15: Hoare triple {2879#(= (+ (- 1) main_~j~0) 0)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2879#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:59,163 INFO L290 TraceCheckUtils]: 16: Hoare triple {2879#(= (+ (- 1) main_~j~0) 0)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2879#(= (+ (- 1) main_~j~0) 0)} is VALID [2022-04-27 21:05:59,165 INFO L290 TraceCheckUtils]: 17: Hoare triple {2879#(= (+ (- 1) main_~j~0) 0)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2880#(<= 2 main_~j~0)} is VALID [2022-04-27 21:05:59,166 INFO L290 TraceCheckUtils]: 18: Hoare triple {2880#(<= 2 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2881#(<= 1 main_~i~0)} is VALID [2022-04-27 21:05:59,166 INFO L290 TraceCheckUtils]: 19: Hoare triple {2881#(<= 1 main_~i~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2882#|main_#t~short10|} is VALID [2022-04-27 21:05:59,166 INFO L290 TraceCheckUtils]: 20: Hoare triple {2882#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 21: Hoare triple {2875#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 22: Hoare triple {2875#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 23: Hoare triple {2875#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 24: Hoare triple {2875#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 25: Hoare triple {2875#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 26: Hoare triple {2875#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L272 TraceCheckUtils]: 27: Hoare triple {2875#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 28: Hoare triple {2875#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2875#false} is VALID [2022-04-27 21:05:59,167 INFO L290 TraceCheckUtils]: 29: Hoare triple {2875#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,168 INFO L290 TraceCheckUtils]: 30: Hoare triple {2875#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,168 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:59,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:05:59,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [51771492] [2022-04-27 21:05:59,168 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [51771492] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:05:59,168 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [536110501] [2022-04-27 21:05:59,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:05:59,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:05:59,168 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:05:59,169 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:05:59,170 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Waiting until timeout for monitored process [2022-04-27 21:05:59,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:59,219 INFO L263 TraceCheckSpWp]: Trace formula consists of 128 conjuncts, 5 conjunts are in the unsatisfiable core [2022-04-27 21:05:59,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:05:59,228 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:05:59,336 INFO L272 TraceCheckUtils]: 0: Hoare triple {2874#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,336 INFO L290 TraceCheckUtils]: 1: Hoare triple {2874#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2874#true} is VALID [2022-04-27 21:05:59,336 INFO L290 TraceCheckUtils]: 2: Hoare triple {2874#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2874#true} {2874#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L272 TraceCheckUtils]: 4: Hoare triple {2874#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L290 TraceCheckUtils]: 5: Hoare triple {2874#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L290 TraceCheckUtils]: 6: Hoare triple {2874#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L290 TraceCheckUtils]: 7: Hoare triple {2874#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L290 TraceCheckUtils]: 8: Hoare triple {2874#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L290 TraceCheckUtils]: 9: Hoare triple {2874#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2874#true} is VALID [2022-04-27 21:05:59,337 INFO L290 TraceCheckUtils]: 10: Hoare triple {2874#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,338 INFO L290 TraceCheckUtils]: 11: Hoare triple {2874#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,338 INFO L290 TraceCheckUtils]: 12: Hoare triple {2920#(<= 1 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,340 INFO L290 TraceCheckUtils]: 13: Hoare triple {2920#(<= 1 main_~j~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,340 INFO L290 TraceCheckUtils]: 14: Hoare triple {2920#(<= 1 main_~j~0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,341 INFO L290 TraceCheckUtils]: 15: Hoare triple {2920#(<= 1 main_~j~0)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,341 INFO L290 TraceCheckUtils]: 16: Hoare triple {2920#(<= 1 main_~j~0)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,342 INFO L290 TraceCheckUtils]: 17: Hoare triple {2920#(<= 1 main_~j~0)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2880#(<= 2 main_~j~0)} is VALID [2022-04-27 21:05:59,342 INFO L290 TraceCheckUtils]: 18: Hoare triple {2880#(<= 2 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {2881#(<= 1 main_~i~0)} is VALID [2022-04-27 21:05:59,343 INFO L290 TraceCheckUtils]: 19: Hoare triple {2881#(<= 1 main_~i~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2882#|main_#t~short10|} is VALID [2022-04-27 21:05:59,343 INFO L290 TraceCheckUtils]: 20: Hoare triple {2882#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,343 INFO L290 TraceCheckUtils]: 21: Hoare triple {2875#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2875#false} is VALID [2022-04-27 21:05:59,343 INFO L290 TraceCheckUtils]: 22: Hoare triple {2875#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 23: Hoare triple {2875#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 24: Hoare triple {2875#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 25: Hoare triple {2875#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 26: Hoare triple {2875#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L272 TraceCheckUtils]: 27: Hoare triple {2875#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 28: Hoare triple {2875#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 29: Hoare triple {2875#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,344 INFO L290 TraceCheckUtils]: 30: Hoare triple {2875#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,345 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:59,345 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 30: Hoare triple {2875#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 29: Hoare triple {2875#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 28: Hoare triple {2875#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L272 TraceCheckUtils]: 27: Hoare triple {2875#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 26: Hoare triple {2875#false} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 25: Hoare triple {2875#false} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 24: Hoare triple {2875#false} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 23: Hoare triple {2875#false} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 22: Hoare triple {2875#false} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {2875#false} is VALID [2022-04-27 21:05:59,456 INFO L290 TraceCheckUtils]: 21: Hoare triple {2875#false} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {2875#false} is VALID [2022-04-27 21:05:59,457 INFO L290 TraceCheckUtils]: 20: Hoare triple {2882#|main_#t~short10|} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {2875#false} is VALID [2022-04-27 21:05:59,457 INFO L290 TraceCheckUtils]: 19: Hoare triple {3011#(<= 0 main_~i~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {2882#|main_#t~short10|} is VALID [2022-04-27 21:05:59,458 INFO L290 TraceCheckUtils]: 18: Hoare triple {2920#(<= 1 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3011#(<= 0 main_~i~0)} is VALID [2022-04-27 21:05:59,458 INFO L290 TraceCheckUtils]: 17: Hoare triple {3018#(<= 0 main_~j~0)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {2920#(<= 1 main_~j~0)} is VALID [2022-04-27 21:05:59,459 INFO L290 TraceCheckUtils]: 16: Hoare triple {3018#(<= 0 main_~j~0)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3018#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:59,459 INFO L290 TraceCheckUtils]: 15: Hoare triple {3018#(<= 0 main_~j~0)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3018#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:59,459 INFO L290 TraceCheckUtils]: 14: Hoare triple {3018#(<= 0 main_~j~0)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3018#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:59,459 INFO L290 TraceCheckUtils]: 13: Hoare triple {3018#(<= 0 main_~j~0)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3018#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:59,460 INFO L290 TraceCheckUtils]: 12: Hoare triple {3018#(<= 0 main_~j~0)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3018#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:59,460 INFO L290 TraceCheckUtils]: 11: Hoare triple {2874#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3018#(<= 0 main_~j~0)} is VALID [2022-04-27 21:05:59,460 INFO L290 TraceCheckUtils]: 10: Hoare triple {2874#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,460 INFO L290 TraceCheckUtils]: 9: Hoare triple {2874#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L290 TraceCheckUtils]: 8: Hoare triple {2874#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L290 TraceCheckUtils]: 7: Hoare triple {2874#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L290 TraceCheckUtils]: 6: Hoare triple {2874#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L290 TraceCheckUtils]: 5: Hoare triple {2874#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L272 TraceCheckUtils]: 4: Hoare triple {2874#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {2874#true} {2874#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,461 INFO L290 TraceCheckUtils]: 2: Hoare triple {2874#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,462 INFO L290 TraceCheckUtils]: 1: Hoare triple {2874#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {2874#true} is VALID [2022-04-27 21:05:59,462 INFO L272 TraceCheckUtils]: 0: Hoare triple {2874#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {2874#true} is VALID [2022-04-27 21:05:59,462 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2022-04-27 21:05:59,462 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [536110501] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:05:59,462 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:05:59,462 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6] total 10 [2022-04-27 21:05:59,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299356003] [2022-04-27 21:05:59,462 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:05:59,464 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 21:05:59,464 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:05:59,464 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:05:59,500 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 47 edges. 47 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:05:59,500 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 10 states [2022-04-27 21:05:59,500 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:05:59,500 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2022-04-27 21:05:59,500 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2022-04-27 21:05:59,500 INFO L87 Difference]: Start difference. First operand 55 states and 65 transitions. Second operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:00,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:00,153 INFO L93 Difference]: Finished difference Result 118 states and 143 transitions. [2022-04-27 21:06:00,153 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2022-04-27 21:06:00,153 INFO L78 Accepts]: Start accepts. Automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 31 [2022-04-27 21:06:00,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:06:00,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:00,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 96 transitions. [2022-04-27 21:06:00,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:00,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 96 transitions. [2022-04-27 21:06:00,157 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 13 states and 96 transitions. [2022-04-27 21:06:00,285 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 96 edges. 96 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:00,287 INFO L225 Difference]: With dead ends: 118 [2022-04-27 21:06:00,287 INFO L226 Difference]: Without dead ends: 87 [2022-04-27 21:06:00,288 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=260, Unknown=0, NotChecked=0, Total=380 [2022-04-27 21:06:00,288 INFO L413 NwaCegarLoop]: 26 mSDtfsCounter, 88 mSDsluCounter, 27 mSDsCounter, 0 mSdLazyCounter, 204 mSolverCounterSat, 47 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.2s Time, 0 mProtectedPredicate, 0 mProtectedAction, 88 SdHoareTripleChecker+Valid, 53 SdHoareTripleChecker+Invalid, 251 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 47 IncrementalHoareTripleChecker+Valid, 204 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.2s IncrementalHoareTripleChecker+Time [2022-04-27 21:06:00,289 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [88 Valid, 53 Invalid, 251 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [47 Valid, 204 Invalid, 0 Unknown, 0 Unchecked, 0.2s Time] [2022-04-27 21:06:00,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2022-04-27 21:06:00,367 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 57. [2022-04-27 21:06:00,367 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:06:00,367 INFO L82 GeneralOperation]: Start isEquivalent. First operand 87 states. Second operand has 57 states, 49 states have (on average 1.2040816326530612) internal successors, (59), 50 states have internal predecessors, (59), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:00,369 INFO L74 IsIncluded]: Start isIncluded. First operand 87 states. Second operand has 57 states, 49 states have (on average 1.2040816326530612) internal successors, (59), 50 states have internal predecessors, (59), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:00,369 INFO L87 Difference]: Start difference. First operand 87 states. Second operand has 57 states, 49 states have (on average 1.2040816326530612) internal successors, (59), 50 states have internal predecessors, (59), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:00,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:00,371 INFO L93 Difference]: Finished difference Result 87 states and 104 transitions. [2022-04-27 21:06:00,371 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 104 transitions. [2022-04-27 21:06:00,372 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:00,372 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:00,372 INFO L74 IsIncluded]: Start isIncluded. First operand has 57 states, 49 states have (on average 1.2040816326530612) internal successors, (59), 50 states have internal predecessors, (59), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 87 states. [2022-04-27 21:06:00,372 INFO L87 Difference]: Start difference. First operand has 57 states, 49 states have (on average 1.2040816326530612) internal successors, (59), 50 states have internal predecessors, (59), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 87 states. [2022-04-27 21:06:00,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:00,379 INFO L93 Difference]: Finished difference Result 87 states and 104 transitions. [2022-04-27 21:06:00,379 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 104 transitions. [2022-04-27 21:06:00,379 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:00,379 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:00,379 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:06:00,379 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:06:00,380 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 57 states, 49 states have (on average 1.2040816326530612) internal successors, (59), 50 states have internal predecessors, (59), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:00,388 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 66 transitions. [2022-04-27 21:06:00,388 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 66 transitions. Word has length 31 [2022-04-27 21:06:00,388 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:06:00,388 INFO L495 AbstractCegarLoop]: Abstraction has 57 states and 66 transitions. [2022-04-27 21:06:00,388 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 10 states, 10 states have (on average 4.2) internal successors, (42), 9 states have internal predecessors, (42), 2 states have call successors, (4), 3 states have call predecessors, (4), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:00,388 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 66 transitions. [2022-04-27 21:06:00,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2022-04-27 21:06:00,389 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:06:00,389 INFO L195 NwaCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:06:00,406 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (7)] Forceful destruction successful, exit code 0 [2022-04-27 21:06:00,595 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable8,7 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:00,595 INFO L420 AbstractCegarLoop]: === Iteration 10 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:06:00,596 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:06:00,596 INFO L85 PathProgramCache]: Analyzing trace with hash 567979469, now seen corresponding path program 1 times [2022-04-27 21:06:00,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:06:00,596 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1971021850] [2022-04-27 21:06:00,596 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:06:00,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:06:00,615 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:00,703 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:06:00,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:00,707 INFO L290 TraceCheckUtils]: 0: Hoare triple {3524#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3509#true} is VALID [2022-04-27 21:06:00,707 INFO L290 TraceCheckUtils]: 1: Hoare triple {3509#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,707 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {3509#true} {3509#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,707 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 21 [2022-04-27 21:06:00,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:00,716 INFO L290 TraceCheckUtils]: 0: Hoare triple {3509#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3509#true} is VALID [2022-04-27 21:06:00,716 INFO L290 TraceCheckUtils]: 1: Hoare triple {3509#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,716 INFO L290 TraceCheckUtils]: 2: Hoare triple {3509#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,717 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3509#true} {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:00,718 INFO L272 TraceCheckUtils]: 0: Hoare triple {3509#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3524#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:06:00,718 INFO L290 TraceCheckUtils]: 1: Hoare triple {3524#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3509#true} is VALID [2022-04-27 21:06:00,718 INFO L290 TraceCheckUtils]: 2: Hoare triple {3509#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,718 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3509#true} {3509#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,718 INFO L272 TraceCheckUtils]: 4: Hoare triple {3509#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,718 INFO L290 TraceCheckUtils]: 5: Hoare triple {3509#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3514#(= main_~j~0 0)} is VALID [2022-04-27 21:06:00,719 INFO L290 TraceCheckUtils]: 6: Hoare triple {3514#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3514#(= main_~j~0 0)} is VALID [2022-04-27 21:06:00,719 INFO L290 TraceCheckUtils]: 7: Hoare triple {3514#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:00,720 INFO L290 TraceCheckUtils]: 8: Hoare triple {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:00,720 INFO L290 TraceCheckUtils]: 9: Hoare triple {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3516#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:06:00,721 INFO L290 TraceCheckUtils]: 10: Hoare triple {3516#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,722 INFO L290 TraceCheckUtils]: 11: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,722 INFO L290 TraceCheckUtils]: 12: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,722 INFO L290 TraceCheckUtils]: 13: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,723 INFO L290 TraceCheckUtils]: 14: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,723 INFO L290 TraceCheckUtils]: 15: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,723 INFO L290 TraceCheckUtils]: 16: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,724 INFO L290 TraceCheckUtils]: 17: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,724 INFO L290 TraceCheckUtils]: 18: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:00,725 INFO L290 TraceCheckUtils]: 19: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:00,725 INFO L290 TraceCheckUtils]: 20: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:00,725 INFO L272 TraceCheckUtils]: 21: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3509#true} is VALID [2022-04-27 21:06:00,725 INFO L290 TraceCheckUtils]: 22: Hoare triple {3509#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3509#true} is VALID [2022-04-27 21:06:00,726 INFO L290 TraceCheckUtils]: 23: Hoare triple {3509#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,726 INFO L290 TraceCheckUtils]: 24: Hoare triple {3509#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:00,726 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3509#true} {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:00,727 INFO L290 TraceCheckUtils]: 26: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [119] L29-1-->L28-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:00,728 INFO L290 TraceCheckUtils]: 27: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [121] L28-2-->L28-3: Formula: (= (+ v_main_~k~0_6 1) v_main_~k~0_5) InVars {main_~k~0=v_main_~k~0_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3523#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:06:00,728 INFO L290 TraceCheckUtils]: 28: Hoare triple {3523#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3510#false} is VALID [2022-04-27 21:06:00,728 INFO L272 TraceCheckUtils]: 29: Hoare triple {3510#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3510#false} is VALID [2022-04-27 21:06:00,729 INFO L290 TraceCheckUtils]: 30: Hoare triple {3510#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3510#false} is VALID [2022-04-27 21:06:00,729 INFO L290 TraceCheckUtils]: 31: Hoare triple {3510#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3510#false} is VALID [2022-04-27 21:06:00,729 INFO L290 TraceCheckUtils]: 32: Hoare triple {3510#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3510#false} is VALID [2022-04-27 21:06:00,729 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:00,729 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:06:00,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1971021850] [2022-04-27 21:06:00,729 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1971021850] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:06:00,729 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [440827231] [2022-04-27 21:06:00,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:06:00,730 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:00,730 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:06:00,730 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:06:00,732 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Waiting until timeout for monitored process [2022-04-27 21:06:00,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:00,778 INFO L263 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 12 conjunts are in the unsatisfiable core [2022-04-27 21:06:00,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:00,788 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:06:01,988 INFO L272 TraceCheckUtils]: 0: Hoare triple {3509#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:01,988 INFO L290 TraceCheckUtils]: 1: Hoare triple {3509#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3509#true} is VALID [2022-04-27 21:06:01,988 INFO L290 TraceCheckUtils]: 2: Hoare triple {3509#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:01,988 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3509#true} {3509#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:01,988 INFO L272 TraceCheckUtils]: 4: Hoare triple {3509#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:01,989 INFO L290 TraceCheckUtils]: 5: Hoare triple {3509#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3514#(= main_~j~0 0)} is VALID [2022-04-27 21:06:01,989 INFO L290 TraceCheckUtils]: 6: Hoare triple {3514#(= main_~j~0 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3514#(= main_~j~0 0)} is VALID [2022-04-27 21:06:01,989 INFO L290 TraceCheckUtils]: 7: Hoare triple {3514#(= main_~j~0 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:01,990 INFO L290 TraceCheckUtils]: 8: Hoare triple {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:01,990 INFO L290 TraceCheckUtils]: 9: Hoare triple {3515#(and (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3516#(and (<= main_~j~0 2) (<= 2 main_~j~0))} is VALID [2022-04-27 21:06:01,991 INFO L290 TraceCheckUtils]: 10: Hoare triple {3516#(and (<= main_~j~0 2) (<= 2 main_~j~0))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,991 INFO L290 TraceCheckUtils]: 11: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,995 INFO L290 TraceCheckUtils]: 12: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,996 INFO L290 TraceCheckUtils]: 13: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,996 INFO L290 TraceCheckUtils]: 14: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,996 INFO L290 TraceCheckUtils]: 15: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,997 INFO L290 TraceCheckUtils]: 16: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,997 INFO L290 TraceCheckUtils]: 17: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,997 INFO L290 TraceCheckUtils]: 18: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:01,998 INFO L290 TraceCheckUtils]: 19: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:01,998 INFO L290 TraceCheckUtils]: 20: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:01,998 INFO L272 TraceCheckUtils]: 21: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3509#true} is VALID [2022-04-27 21:06:01,998 INFO L290 TraceCheckUtils]: 22: Hoare triple {3509#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3509#true} is VALID [2022-04-27 21:06:01,998 INFO L290 TraceCheckUtils]: 23: Hoare triple {3509#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:01,999 INFO L290 TraceCheckUtils]: 24: Hoare triple {3509#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:01,999 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3509#true} {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:02,000 INFO L290 TraceCheckUtils]: 26: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [119] L29-1-->L28-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} is VALID [2022-04-27 21:06:02,000 INFO L290 TraceCheckUtils]: 27: Hoare triple {3518#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= (+ (- 1) main_~k~0) 0))} [121] L28-2-->L28-3: Formula: (= (+ v_main_~k~0_6 1) v_main_~k~0_5) InVars {main_~k~0=v_main_~k~0_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3609#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= main_~k~0 2))} is VALID [2022-04-27 21:06:02,001 INFO L290 TraceCheckUtils]: 28: Hoare triple {3609#(and (<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296)) (= main_~k~0 2))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3510#false} is VALID [2022-04-27 21:06:02,001 INFO L272 TraceCheckUtils]: 29: Hoare triple {3510#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3510#false} is VALID [2022-04-27 21:06:02,001 INFO L290 TraceCheckUtils]: 30: Hoare triple {3510#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3510#false} is VALID [2022-04-27 21:06:02,001 INFO L290 TraceCheckUtils]: 31: Hoare triple {3510#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3510#false} is VALID [2022-04-27 21:06:02,001 INFO L290 TraceCheckUtils]: 32: Hoare triple {3510#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3510#false} is VALID [2022-04-27 21:06:02,001 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:02,001 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:06:02,590 INFO L290 TraceCheckUtils]: 32: Hoare triple {3510#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3510#false} is VALID [2022-04-27 21:06:02,591 INFO L290 TraceCheckUtils]: 31: Hoare triple {3510#false} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {3510#false} is VALID [2022-04-27 21:06:02,591 INFO L290 TraceCheckUtils]: 30: Hoare triple {3510#false} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3510#false} is VALID [2022-04-27 21:06:02,591 INFO L272 TraceCheckUtils]: 29: Hoare triple {3510#false} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3510#false} is VALID [2022-04-27 21:06:02,591 INFO L290 TraceCheckUtils]: 28: Hoare triple {3523#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3510#false} is VALID [2022-04-27 21:06:02,592 INFO L290 TraceCheckUtils]: 27: Hoare triple {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [121] L28-2-->L28-3: Formula: (= (+ v_main_~k~0_6 1) v_main_~k~0_5) InVars {main_~k~0=v_main_~k~0_6} OutVars{main_#t~post12=|v_main_#t~post12_1|, main_~k~0=v_main_~k~0_5} AuxVars[] AssignedVars[main_~k~0, main_#t~post12] {3523#(<= (+ main_~SIZE~0 (* (div main_~k~0 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296)))} is VALID [2022-04-27 21:06:02,593 INFO L290 TraceCheckUtils]: 26: Hoare triple {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [119] L29-1-->L28-2: Formula: true InVars {} OutVars{main_#t~mem13=|v_main_#t~mem13_3|, main_#t~mem14=|v_main_#t~mem14_3|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:02,593 INFO L284 TraceCheckUtils]: 25: Hoare quadruple {3509#true} {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [129] __VERIFIER_assertEXIT-->L29-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:02,593 INFO L290 TraceCheckUtils]: 24: Hoare triple {3509#true} [126] L6-2-->__VERIFIER_assertEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:02,593 INFO L290 TraceCheckUtils]: 23: Hoare triple {3509#true} [123] L6-->L6-2: Formula: (not (= v___VERIFIER_assert_~cond_1 0)) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_1} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:02,593 INFO L290 TraceCheckUtils]: 22: Hoare triple {3509#true} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {3509#true} is VALID [2022-04-27 21:06:02,594 INFO L272 TraceCheckUtils]: 21: Hoare triple {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {3509#true} is VALID [2022-04-27 21:06:02,594 INFO L290 TraceCheckUtils]: 20: Hoare triple {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:02,595 INFO L290 TraceCheckUtils]: 19: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {3640#(<= (+ main_~SIZE~0 (* (div (+ main_~k~0 1) 4294967296) 4294967296)) (+ main_~k~0 (* (div main_~SIZE~0 4294967296) 4294967296) 1))} is VALID [2022-04-27 21:06:02,595 INFO L290 TraceCheckUtils]: 18: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,595 INFO L290 TraceCheckUtils]: 17: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,596 INFO L290 TraceCheckUtils]: 16: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,596 INFO L290 TraceCheckUtils]: 15: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,596 INFO L290 TraceCheckUtils]: 14: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,597 INFO L290 TraceCheckUtils]: 13: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,597 INFO L290 TraceCheckUtils]: 12: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,597 INFO L290 TraceCheckUtils]: 11: Hoare triple {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,598 INFO L290 TraceCheckUtils]: 10: Hoare triple {3692#(<= 0 (+ 1 (div (+ (- 4294967294) (* (- 1) (mod main_~j~0 4294967296))) 4294967296)))} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {3517#(<= 0 (div (+ 2 (* (div main_~SIZE~0 4294967296) 4294967296) (* (- 1) main_~SIZE~0)) 4294967296))} is VALID [2022-04-27 21:06:02,599 INFO L290 TraceCheckUtils]: 9: Hoare triple {3696#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3692#(<= 0 (+ 1 (div (+ (- 4294967294) (* (- 1) (mod main_~j~0 4294967296))) 4294967296)))} is VALID [2022-04-27 21:06:02,599 INFO L290 TraceCheckUtils]: 8: Hoare triple {3696#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3696#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:02,600 INFO L290 TraceCheckUtils]: 7: Hoare triple {3703#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {3696#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 1) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:02,600 INFO L290 TraceCheckUtils]: 6: Hoare triple {3703#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {3703#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:02,601 INFO L290 TraceCheckUtils]: 5: Hoare triple {3509#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {3703#(<= 0 (+ (div (+ (* (- 1) (mod (+ main_~j~0 2) 4294967296)) (- 4294967294)) 4294967296) 1))} is VALID [2022-04-27 21:06:02,601 INFO L272 TraceCheckUtils]: 4: Hoare triple {3509#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:02,601 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {3509#true} {3509#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:02,601 INFO L290 TraceCheckUtils]: 2: Hoare triple {3509#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:02,601 INFO L290 TraceCheckUtils]: 1: Hoare triple {3509#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {3509#true} is VALID [2022-04-27 21:06:02,601 INFO L272 TraceCheckUtils]: 0: Hoare triple {3509#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {3509#true} is VALID [2022-04-27 21:06:02,601 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:02,601 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [440827231] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:06:02,601 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:06:02,602 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 14 [2022-04-27 21:06:02,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948481641] [2022-04-27 21:06:02,602 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:06:02,602 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-27 21:06:02,603 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:06:02,603 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:02,643 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 49 edges. 49 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:02,644 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 14 states [2022-04-27 21:06:02,644 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:06:02,644 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2022-04-27 21:06:02,644 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2022-04-27 21:06:02,644 INFO L87 Difference]: Start difference. First operand 57 states and 66 transitions. Second operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:03,590 INFO L93 Difference]: Finished difference Result 144 states and 171 transitions. [2022-04-27 21:06:03,591 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2022-04-27 21:06:03,591 INFO L78 Accepts]: Start accepts. Automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Word has length 33 [2022-04-27 21:06:03,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:06:03,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 92 transitions. [2022-04-27 21:06:03,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10 states to 10 states and 92 transitions. [2022-04-27 21:06:03,594 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 10 states and 92 transitions. [2022-04-27 21:06:03,678 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 92 edges. 92 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:03,680 INFO L225 Difference]: With dead ends: 144 [2022-04-27 21:06:03,680 INFO L226 Difference]: Without dead ends: 85 [2022-04-27 21:06:03,681 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 60 SyntacticMatches, 5 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 46 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=90, Invalid=330, Unknown=0, NotChecked=0, Total=420 [2022-04-27 21:06:03,681 INFO L413 NwaCegarLoop]: 27 mSDtfsCounter, 89 mSDsluCounter, 47 mSDsCounter, 0 mSdLazyCounter, 306 mSolverCounterSat, 24 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 0.3s Time, 0 mProtectedPredicate, 0 mProtectedAction, 90 SdHoareTripleChecker+Valid, 74 SdHoareTripleChecker+Invalid, 330 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 24 IncrementalHoareTripleChecker+Valid, 306 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 0 IncrementalHoareTripleChecker+Unchecked, 0.3s IncrementalHoareTripleChecker+Time [2022-04-27 21:06:03,681 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [90 Valid, 74 Invalid, 330 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [24 Valid, 306 Invalid, 0 Unknown, 0 Unchecked, 0.3s Time] [2022-04-27 21:06:03,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2022-04-27 21:06:03,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 66. [2022-04-27 21:06:03,775 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:06:03,776 INFO L82 GeneralOperation]: Start isEquivalent. First operand 85 states. Second operand has 66 states, 58 states have (on average 1.1724137931034482) internal successors, (68), 59 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,776 INFO L74 IsIncluded]: Start isIncluded. First operand 85 states. Second operand has 66 states, 58 states have (on average 1.1724137931034482) internal successors, (68), 59 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,776 INFO L87 Difference]: Start difference. First operand 85 states. Second operand has 66 states, 58 states have (on average 1.1724137931034482) internal successors, (68), 59 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:03,778 INFO L93 Difference]: Finished difference Result 85 states and 98 transitions. [2022-04-27 21:06:03,778 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 98 transitions. [2022-04-27 21:06:03,778 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:03,778 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:03,778 INFO L74 IsIncluded]: Start isIncluded. First operand has 66 states, 58 states have (on average 1.1724137931034482) internal successors, (68), 59 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 85 states. [2022-04-27 21:06:03,778 INFO L87 Difference]: Start difference. First operand has 66 states, 58 states have (on average 1.1724137931034482) internal successors, (68), 59 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 85 states. [2022-04-27 21:06:03,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:03,780 INFO L93 Difference]: Finished difference Result 85 states and 98 transitions. [2022-04-27 21:06:03,780 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 98 transitions. [2022-04-27 21:06:03,780 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:03,780 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:03,780 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:06:03,780 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:06:03,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 58 states have (on average 1.1724137931034482) internal successors, (68), 59 states have internal predecessors, (68), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 75 transitions. [2022-04-27 21:06:03,782 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 75 transitions. Word has length 33 [2022-04-27 21:06:03,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:06:03,782 INFO L495 AbstractCegarLoop]: Abstraction has 66 states and 75 transitions. [2022-04-27 21:06:03,782 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 14 states, 14 states have (on average 2.857142857142857) internal successors, (40), 13 states have internal predecessors, (40), 4 states have call successors, (6), 3 states have call predecessors, (6), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:03,782 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 75 transitions. [2022-04-27 21:06:03,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-04-27 21:06:03,782 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:06:03,782 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:06:03,799 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (8)] Forceful destruction successful, exit code 0 [2022-04-27 21:06:03,987 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: SelfDestructingSolverStorable9,8 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:03,988 INFO L420 AbstractCegarLoop]: === Iteration 11 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:06:03,988 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:06:03,988 INFO L85 PathProgramCache]: Analyzing trace with hash -954574653, now seen corresponding path program 2 times [2022-04-27 21:06:03,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:06:03,988 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082155047] [2022-04-27 21:06:03,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:06:03,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:06:04,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:04,363 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:06:04,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:04,368 INFO L290 TraceCheckUtils]: 0: Hoare triple {4216#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4198#true} is VALID [2022-04-27 21:06:04,368 INFO L290 TraceCheckUtils]: 1: Hoare triple {4198#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:04,368 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {4198#true} {4198#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:04,368 INFO L272 TraceCheckUtils]: 0: Hoare triple {4198#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4216#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:06:04,368 INFO L290 TraceCheckUtils]: 1: Hoare triple {4216#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4198#true} is VALID [2022-04-27 21:06:04,369 INFO L290 TraceCheckUtils]: 2: Hoare triple {4198#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:04,369 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4198#true} {4198#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:04,369 INFO L272 TraceCheckUtils]: 4: Hoare triple {4198#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:04,369 INFO L290 TraceCheckUtils]: 5: Hoare triple {4198#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4203#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:04,370 INFO L290 TraceCheckUtils]: 6: Hoare triple {4203#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4203#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:04,370 INFO L290 TraceCheckUtils]: 7: Hoare triple {4203#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,371 INFO L290 TraceCheckUtils]: 8: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,372 INFO L290 TraceCheckUtils]: 9: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:04,372 INFO L290 TraceCheckUtils]: 10: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:04,375 INFO L290 TraceCheckUtils]: 11: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:04,375 INFO L290 TraceCheckUtils]: 12: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:04,376 INFO L290 TraceCheckUtils]: 13: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,376 INFO L290 TraceCheckUtils]: 14: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,377 INFO L290 TraceCheckUtils]: 15: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,377 INFO L290 TraceCheckUtils]: 16: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,377 INFO L290 TraceCheckUtils]: 17: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,378 INFO L290 TraceCheckUtils]: 18: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:04,378 INFO L290 TraceCheckUtils]: 19: Hoare triple {4204#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4206#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} is VALID [2022-04-27 21:06:04,379 INFO L290 TraceCheckUtils]: 20: Hoare triple {4206#(and (= |main_~#v~0.offset| 0) (= (* main_~j~0 4) 8))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4207#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:04,379 INFO L290 TraceCheckUtils]: 21: Hoare triple {4207#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4207#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:04,380 INFO L290 TraceCheckUtils]: 22: Hoare triple {4207#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4207#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:04,380 INFO L290 TraceCheckUtils]: 23: Hoare triple {4207#(and (= |main_~#v~0.offset| 0) (= 4 (* main_~i~0 4)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {4208#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:04,381 INFO L290 TraceCheckUtils]: 24: Hoare triple {4208#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4208#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:04,381 INFO L290 TraceCheckUtils]: 25: Hoare triple {4208#(and (= |main_~#v~0.offset| 0) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4209#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:06:04,382 INFO L290 TraceCheckUtils]: 26: Hoare triple {4209#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4210#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:06:04,382 INFO L290 TraceCheckUtils]: 27: Hoare triple {4210#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:04,383 INFO L290 TraceCheckUtils]: 28: Hoare triple {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:04,383 INFO L290 TraceCheckUtils]: 29: Hoare triple {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:04,384 INFO L290 TraceCheckUtils]: 30: Hoare triple {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4212#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:06:04,384 INFO L290 TraceCheckUtils]: 31: Hoare triple {4212#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4213#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:04,385 INFO L272 TraceCheckUtils]: 32: Hoare triple {4213#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4214#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:06:04,385 INFO L290 TraceCheckUtils]: 33: Hoare triple {4214#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4215#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:06:04,385 INFO L290 TraceCheckUtils]: 34: Hoare triple {4215#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4199#false} is VALID [2022-04-27 21:06:04,386 INFO L290 TraceCheckUtils]: 35: Hoare triple {4199#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4199#false} is VALID [2022-04-27 21:06:04,386 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:04,386 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:06:04,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082155047] [2022-04-27 21:06:04,386 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082155047] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:06:04,386 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [74880011] [2022-04-27 21:06:04,386 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:06:04,386 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:04,386 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:06:04,387 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:06:04,388 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2022-04-27 21:06:04,450 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:06:04,450 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:06:04,451 INFO L263 TraceCheckSpWp]: Trace formula consists of 152 conjuncts, 21 conjunts are in the unsatisfiable core [2022-04-27 21:06:04,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:04,474 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:06:04,936 INFO L190 IndexEqualityManager]: detected not equals via solver [2022-04-27 21:06:04,937 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2022-04-27 21:06:05,076 INFO L356 Elim1Store]: treesize reduction 0, result has 100.0 percent of original size [2022-04-27 21:06:05,076 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 26 treesize of output 10 [2022-04-27 21:06:05,149 INFO L272 TraceCheckUtils]: 0: Hoare triple {4198#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,149 INFO L290 TraceCheckUtils]: 1: Hoare triple {4198#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4198#true} is VALID [2022-04-27 21:06:05,149 INFO L290 TraceCheckUtils]: 2: Hoare triple {4198#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,149 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4198#true} {4198#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,149 INFO L272 TraceCheckUtils]: 4: Hoare triple {4198#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,150 INFO L290 TraceCheckUtils]: 5: Hoare triple {4198#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,150 INFO L290 TraceCheckUtils]: 6: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,150 INFO L290 TraceCheckUtils]: 7: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,151 INFO L290 TraceCheckUtils]: 8: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,151 INFO L290 TraceCheckUtils]: 9: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,152 INFO L290 TraceCheckUtils]: 10: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,152 INFO L290 TraceCheckUtils]: 11: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,153 INFO L290 TraceCheckUtils]: 12: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4205#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:05,153 INFO L290 TraceCheckUtils]: 13: Hoare triple {4205#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,154 INFO L290 TraceCheckUtils]: 14: Hoare triple {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,154 INFO L290 TraceCheckUtils]: 15: Hoare triple {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,154 INFO L290 TraceCheckUtils]: 16: Hoare triple {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,155 INFO L290 TraceCheckUtils]: 17: Hoare triple {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,155 INFO L290 TraceCheckUtils]: 18: Hoare triple {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:05,156 INFO L290 TraceCheckUtils]: 19: Hoare triple {4259#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 1))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4278#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} is VALID [2022-04-27 21:06:05,156 INFO L290 TraceCheckUtils]: 20: Hoare triple {4278#(and (= |main_~#v~0.offset| 0) (<= main_~j~0 2))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4282#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:05,157 INFO L290 TraceCheckUtils]: 21: Hoare triple {4282#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4282#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:05,157 INFO L290 TraceCheckUtils]: 22: Hoare triple {4282#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4282#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} is VALID [2022-04-27 21:06:05,158 INFO L290 TraceCheckUtils]: 23: Hoare triple {4282#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 1))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {4292#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} is VALID [2022-04-27 21:06:05,158 INFO L290 TraceCheckUtils]: 24: Hoare triple {4292#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4296#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:06:05,159 INFO L290 TraceCheckUtils]: 25: Hoare triple {4296#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4209#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} is VALID [2022-04-27 21:06:05,159 INFO L290 TraceCheckUtils]: 26: Hoare triple {4209#(and (= |main_~#v~0.offset| 0) (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4)) (or (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) |main_#t~short10|))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4210#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} is VALID [2022-04-27 21:06:05,160 INFO L290 TraceCheckUtils]: 27: Hoare triple {4210#(and (= |main_~#v~0.offset| 0) (<= main_~i~0 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))) main_~key~0) (<= 0 main_~i~0))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:05,160 INFO L290 TraceCheckUtils]: 28: Hoare triple {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:05,161 INFO L290 TraceCheckUtils]: 29: Hoare triple {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:05,161 INFO L290 TraceCheckUtils]: 30: Hoare triple {4211#(and (= |main_~#v~0.offset| 0) (<= (select (select |#memory_int| |main_~#v~0.base|) 0) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4212#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:06:05,162 INFO L290 TraceCheckUtils]: 31: Hoare triple {4212#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4213#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:05,162 INFO L272 TraceCheckUtils]: 32: Hoare triple {4213#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4321#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:06:05,163 INFO L290 TraceCheckUtils]: 33: Hoare triple {4321#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4325#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:06:05,163 INFO L290 TraceCheckUtils]: 34: Hoare triple {4325#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4199#false} is VALID [2022-04-27 21:06:05,163 INFO L290 TraceCheckUtils]: 35: Hoare triple {4199#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4199#false} is VALID [2022-04-27 21:06:05,164 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 3 proven. 11 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:06:05,164 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:06:05,516 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 35 [2022-04-27 21:06:05,549 INFO L356 Elim1Store]: treesize reduction 21, result has 43.2 percent of original size [2022-04-27 21:06:05,549 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 93 treesize of output 90 [2022-04-27 21:06:05,838 INFO L290 TraceCheckUtils]: 35: Hoare triple {4199#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4199#false} is VALID [2022-04-27 21:06:05,838 INFO L290 TraceCheckUtils]: 34: Hoare triple {4325#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {4199#false} is VALID [2022-04-27 21:06:05,838 INFO L290 TraceCheckUtils]: 33: Hoare triple {4321#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {4325#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:06:05,839 INFO L272 TraceCheckUtils]: 32: Hoare triple {4213#(<= |main_#t~mem13| |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {4321#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:06:05,840 INFO L290 TraceCheckUtils]: 31: Hoare triple {4344#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {4213#(<= |main_#t~mem13| |main_#t~mem14|)} is VALID [2022-04-27 21:06:05,840 INFO L290 TraceCheckUtils]: 30: Hoare triple {4348#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {4344#(<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4))))} is VALID [2022-04-27 21:06:05,840 INFO L290 TraceCheckUtils]: 29: Hoare triple {4348#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {4348#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:06:05,841 INFO L290 TraceCheckUtils]: 28: Hoare triple {4348#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4348#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:06:05,847 INFO L290 TraceCheckUtils]: 27: Hoare triple {4358#(forall ((v_ArrVal_161 Int)) (or (not (<= main_~key~0 v_ArrVal_161)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) (+ |main_~#v~0.offset| 4)))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4348#(<= (select (select |#memory_int| |main_~#v~0.base|) |main_~#v~0.offset|) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4)))} is VALID [2022-04-27 21:06:05,848 INFO L290 TraceCheckUtils]: 26: Hoare triple {4362#(or (forall ((v_ArrVal_161 Int)) (or (not (<= main_~key~0 v_ArrVal_161)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4358#(forall ((v_ArrVal_161 Int)) (or (not (<= main_~key~0 v_ArrVal_161)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) (+ |main_~#v~0.offset| 4)))))} is VALID [2022-04-27 21:06:05,849 INFO L290 TraceCheckUtils]: 25: Hoare triple {4366#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4362#(or (forall ((v_ArrVal_161 Int)) (or (not (<= main_~key~0 v_ArrVal_161)) (<= (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) |main_~#v~0.offset|) (select (store (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) v_ArrVal_161) (+ |main_~#v~0.offset| 4))))) |main_#t~short10|)} is VALID [2022-04-27 21:06:05,849 INFO L290 TraceCheckUtils]: 24: Hoare triple {4370#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4366#(or (not |main_#t~short10|) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,850 INFO L290 TraceCheckUtils]: 23: Hoare triple {4374#(<= main_~i~0 1)} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {4370#(or (not (<= 0 main_~i~0)) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:05,851 INFO L290 TraceCheckUtils]: 22: Hoare triple {4374#(<= main_~i~0 1)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4374#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:05,851 INFO L290 TraceCheckUtils]: 21: Hoare triple {4374#(<= main_~i~0 1)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4374#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:05,852 INFO L290 TraceCheckUtils]: 20: Hoare triple {4384#(<= main_~j~0 2)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4374#(<= main_~i~0 1)} is VALID [2022-04-27 21:06:05,852 INFO L290 TraceCheckUtils]: 19: Hoare triple {4388#(<= main_~j~0 1)} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {4384#(<= main_~j~0 2)} is VALID [2022-04-27 21:06:05,853 INFO L290 TraceCheckUtils]: 18: Hoare triple {4388#(<= main_~j~0 1)} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {4388#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:05,853 INFO L290 TraceCheckUtils]: 17: Hoare triple {4388#(<= main_~j~0 1)} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4388#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:05,853 INFO L290 TraceCheckUtils]: 16: Hoare triple {4388#(<= main_~j~0 1)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {4388#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:05,854 INFO L290 TraceCheckUtils]: 15: Hoare triple {4388#(<= main_~j~0 1)} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {4388#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:05,854 INFO L290 TraceCheckUtils]: 14: Hoare triple {4388#(<= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {4388#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:05,854 INFO L290 TraceCheckUtils]: 13: Hoare triple {4198#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {4388#(<= main_~j~0 1)} is VALID [2022-04-27 21:06:05,854 INFO L290 TraceCheckUtils]: 12: Hoare triple {4198#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,854 INFO L290 TraceCheckUtils]: 11: Hoare triple {4198#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4198#true} is VALID [2022-04-27 21:06:05,854 INFO L290 TraceCheckUtils]: 10: Hoare triple {4198#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 9: Hoare triple {4198#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 8: Hoare triple {4198#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 7: Hoare triple {4198#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 6: Hoare triple {4198#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 5: Hoare triple {4198#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L272 TraceCheckUtils]: 4: Hoare triple {4198#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {4198#true} {4198#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 2: Hoare triple {4198#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L290 TraceCheckUtils]: 1: Hoare triple {4198#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L272 TraceCheckUtils]: 0: Hoare triple {4198#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {4198#true} is VALID [2022-04-27 21:06:05,855 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 1 proven. 13 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:06:05,855 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleZ3 [74880011] provided 0 perfect and 2 imperfect interpolant sequences [2022-04-27 21:06:05,856 INFO L184 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2022-04-27 21:06:05,856 INFO L197 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 14] total 32 [2022-04-27 21:06:05,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [878286294] [2022-04-27 21:06:05,856 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2022-04-27 21:06:05,856 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 36 [2022-04-27 21:06:05,856 INFO L84 Accepts]: Finished accepts. word is accepted. [2022-04-27 21:06:05,857 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:05,915 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 78 edges. 78 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:05,915 INFO L571 AbstractCegarLoop]: INTERPOLANT automaton has 32 states [2022-04-27 21:06:05,915 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2022-04-27 21:06:05,916 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2022-04-27 21:06:05,916 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=130, Invalid=862, Unknown=0, NotChecked=0, Total=992 [2022-04-27 21:06:05,916 INFO L87 Difference]: Start difference. First operand 66 states and 75 transitions. Second operand has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:09,051 INFO L93 Difference]: Finished difference Result 141 states and 166 transitions. [2022-04-27 21:06:09,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2022-04-27 21:06:09,052 INFO L78 Accepts]: Start accepts. Automaton has has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) Word has length 36 [2022-04-27 21:06:09,052 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2022-04-27 21:06:09,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 130 transitions. [2022-04-27 21:06:09,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,056 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 130 transitions. [2022-04-27 21:06:09,056 INFO L86 InductivityCheck]: Starting inductivity check of a Floyd-Hoare automaton with 42 states and 130 transitions. [2022-04-27 21:06:09,196 INFO L122 InductivityCheck]: Floyd-Hoare automaton has 130 edges. 130 inductive. 0 not inductive. 0 times theorem prover too weak to decide inductivity. [2022-04-27 21:06:09,198 INFO L225 Difference]: With dead ends: 141 [2022-04-27 21:06:09,198 INFO L226 Difference]: Without dead ends: 139 [2022-04-27 21:06:09,199 INFO L412 NwaCegarLoop]: 0 DeclaredPredicates, 133 GetRequests, 57 SyntacticMatches, 8 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1294 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=779, Invalid=4051, Unknown=0, NotChecked=0, Total=4830 [2022-04-27 21:06:09,200 INFO L413 NwaCegarLoop]: 22 mSDtfsCounter, 174 mSDsluCounter, 87 mSDsCounter, 0 mSdLazyCounter, 955 mSolverCounterSat, 169 mSolverCounterUnsat, 0 mSolverCounterUnknown, 0 mSolverCounterNotChecked, 1.1s Time, 0 mProtectedPredicate, 0 mProtectedAction, 176 SdHoareTripleChecker+Valid, 109 SdHoareTripleChecker+Invalid, 1268 SdHoareTripleChecker+Unknown, 0 SdHoareTripleChecker+Unchecked, 0.0s SdHoareTripleChecker+Time, 169 IncrementalHoareTripleChecker+Valid, 955 IncrementalHoareTripleChecker+Invalid, 0 IncrementalHoareTripleChecker+Unknown, 144 IncrementalHoareTripleChecker+Unchecked, 1.1s IncrementalHoareTripleChecker+Time [2022-04-27 21:06:09,200 INFO L414 NwaCegarLoop]: SdHoareTripleChecker [176 Valid, 109 Invalid, 1268 Unknown, 0 Unchecked, 0.0s Time], IncrementalHoareTripleChecker [169 Valid, 955 Invalid, 0 Unknown, 144 Unchecked, 1.1s Time] [2022-04-27 21:06:09,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2022-04-27 21:06:09,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 77. [2022-04-27 21:06:09,321 INFO L214 AbstractMinimizeNwa]: Start testing correctness of minimizeSevpa [2022-04-27 21:06:09,321 INFO L82 GeneralOperation]: Start isEquivalent. First operand 139 states. Second operand has 77 states, 69 states have (on average 1.2028985507246377) internal successors, (83), 70 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:09,321 INFO L74 IsIncluded]: Start isIncluded. First operand 139 states. Second operand has 77 states, 69 states have (on average 1.2028985507246377) internal successors, (83), 70 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:09,321 INFO L87 Difference]: Start difference. First operand 139 states. Second operand has 77 states, 69 states have (on average 1.2028985507246377) internal successors, (83), 70 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:09,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:09,324 INFO L93 Difference]: Finished difference Result 139 states and 164 transitions. [2022-04-27 21:06:09,324 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 164 transitions. [2022-04-27 21:06:09,325 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:09,325 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:09,325 INFO L74 IsIncluded]: Start isIncluded. First operand has 77 states, 69 states have (on average 1.2028985507246377) internal successors, (83), 70 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 139 states. [2022-04-27 21:06:09,325 INFO L87 Difference]: Start difference. First operand has 77 states, 69 states have (on average 1.2028985507246377) internal successors, (83), 70 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) Second operand 139 states. [2022-04-27 21:06:09,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2022-04-27 21:06:09,328 INFO L93 Difference]: Finished difference Result 139 states and 164 transitions. [2022-04-27 21:06:09,328 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 164 transitions. [2022-04-27 21:06:09,328 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2022-04-27 21:06:09,328 INFO L83 IsIncluded]: Finished isIncluded. Language is included [2022-04-27 21:06:09,328 INFO L88 GeneralOperation]: Finished isEquivalent. [2022-04-27 21:06:09,328 INFO L221 AbstractMinimizeNwa]: Finished testing correctness of minimizeSevpa [2022-04-27 21:06:09,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77 states, 69 states have (on average 1.2028985507246377) internal successors, (83), 70 states have internal predecessors, (83), 4 states have call successors, (4), 4 states have call predecessors, (4), 3 states have return successors, (3), 2 states have call predecessors, (3), 3 states have call successors, (3) [2022-04-27 21:06:09,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 90 transitions. [2022-04-27 21:06:09,330 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 90 transitions. Word has length 36 [2022-04-27 21:06:09,330 INFO L84 Accepts]: Finished accepts. word is rejected. [2022-04-27 21:06:09,330 INFO L495 AbstractCegarLoop]: Abstraction has 77 states and 90 transitions. [2022-04-27 21:06:09,330 INFO L496 AbstractCegarLoop]: INTERPOLANT automaton has has 32 states, 31 states have (on average 2.3225806451612905) internal successors, (72), 29 states have internal predecessors, (72), 2 states have call successors, (5), 4 states have call predecessors, (5), 1 states have return successors, (1), 1 states have call predecessors, (1), 1 states have call successors, (1) [2022-04-27 21:06:09,330 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 90 transitions. [2022-04-27 21:06:09,331 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2022-04-27 21:06:09,331 INFO L187 NwaCegarLoop]: Found error trace [2022-04-27 21:06:09,331 INFO L195 NwaCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2022-04-27 21:06:09,355 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Ended with exit code 0 [2022-04-27 21:06:09,544 WARN L477 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 9 /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true,SelfDestructingSolverStorable10 [2022-04-27 21:06:09,545 INFO L420 AbstractCegarLoop]: === Iteration 12 === Targeting __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION] === [2022-04-27 21:06:09,545 INFO L144 PredicateUnifier]: Initialized classic predicate unifier [2022-04-27 21:06:09,545 INFO L85 PathProgramCache]: Analyzing trace with hash -392015670, now seen corresponding path program 2 times [2022-04-27 21:06:09,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2022-04-27 21:06:09,545 INFO L333 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [10205637] [2022-04-27 21:06:09,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2022-04-27 21:06:09,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2022-04-27 21:06:09,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:10,141 INFO L376 atingTraceCheckCraig]: Compute interpolants for subsequence at non-pending call position 0 [2022-04-27 21:06:10,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:10,146 INFO L290 TraceCheckUtils]: 0: Hoare triple {5130#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5108#true} is VALID [2022-04-27 21:06:10,146 INFO L290 TraceCheckUtils]: 1: Hoare triple {5108#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:10,146 INFO L284 TraceCheckUtils]: 2: Hoare quadruple {5108#true} {5108#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:10,146 INFO L272 TraceCheckUtils]: 0: Hoare triple {5108#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5130#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} is VALID [2022-04-27 21:06:10,147 INFO L290 TraceCheckUtils]: 1: Hoare triple {5130#(and (= |#NULL.offset| |old(#NULL.offset)|) (= |old(#NULL.base)| |#NULL.base|))} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5108#true} is VALID [2022-04-27 21:06:10,147 INFO L290 TraceCheckUtils]: 2: Hoare triple {5108#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:10,147 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5108#true} {5108#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:10,147 INFO L272 TraceCheckUtils]: 4: Hoare triple {5108#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:10,147 INFO L290 TraceCheckUtils]: 5: Hoare triple {5108#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5113#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:10,148 INFO L290 TraceCheckUtils]: 6: Hoare triple {5113#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5113#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} is VALID [2022-04-27 21:06:10,148 INFO L290 TraceCheckUtils]: 7: Hoare triple {5113#(and (= |main_~#v~0.offset| 0) (= main_~j~0 0))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5114#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:10,149 INFO L290 TraceCheckUtils]: 8: Hoare triple {5114#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5114#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:10,149 INFO L290 TraceCheckUtils]: 9: Hoare triple {5114#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5115#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:10,150 INFO L290 TraceCheckUtils]: 10: Hoare triple {5115#(= |main_~#v~0.offset| 0)} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5115#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:10,150 INFO L290 TraceCheckUtils]: 11: Hoare triple {5115#(= |main_~#v~0.offset| 0)} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5115#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:10,151 INFO L290 TraceCheckUtils]: 12: Hoare triple {5115#(= |main_~#v~0.offset| 0)} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5115#(= |main_~#v~0.offset| 0)} is VALID [2022-04-27 21:06:10,151 INFO L290 TraceCheckUtils]: 13: Hoare triple {5115#(= |main_~#v~0.offset| 0)} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5114#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} is VALID [2022-04-27 21:06:10,152 INFO L290 TraceCheckUtils]: 14: Hoare triple {5114#(and (= |main_~#v~0.offset| 0) (<= 1 main_~j~0) (<= main_~j~0 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5116#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} is VALID [2022-04-27 21:06:10,152 INFO L290 TraceCheckUtils]: 15: Hoare triple {5116#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~i~0 1) main_~j~0))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5117#(or (and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0)) (not |main_#t~short10|))} is VALID [2022-04-27 21:06:10,153 INFO L290 TraceCheckUtils]: 16: Hoare triple {5117#(or (and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= 0 main_~i~0) (<= (+ main_~i~0 1) main_~j~0)) (not |main_#t~short10|))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5118#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} is VALID [2022-04-27 21:06:10,154 INFO L290 TraceCheckUtils]: 17: Hoare triple {5118#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (or (not |main_#t~short10|) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4))))) (= 0 (* main_~i~0 4)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {5119#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= 0 (* main_~i~0 4))) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:06:10,155 INFO L290 TraceCheckUtils]: 18: Hoare triple {5119#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~j~0) 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= 0 (* main_~i~0 4))) (<= 0 (+ main_~i~0 1)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5120#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1))) |main_#t~short10|))} is VALID [2022-04-27 21:06:10,156 INFO L290 TraceCheckUtils]: 19: Hoare triple {5120#(and (= (+ (- 1) main_~j~0) 0) (or (and (= |main_~#v~0.offset| 0) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1))) |main_#t~short10|))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5121#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:06:10,156 INFO L290 TraceCheckUtils]: 20: Hoare triple {5121#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5121#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:06:10,157 INFO L290 TraceCheckUtils]: 21: Hoare triple {5121#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ main_~key~0 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0) (<= 0 (+ main_~i~0 1)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5122#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,158 INFO L290 TraceCheckUtils]: 22: Hoare triple {5122#(and (= |main_~#v~0.offset| 0) (= main_~j~0 1) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5123#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,159 INFO L290 TraceCheckUtils]: 23: Hoare triple {5123#(and (= |main_~#v~0.offset| 0) (<= 2 main_~j~0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,159 INFO L290 TraceCheckUtils]: 24: Hoare triple {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,160 INFO L290 TraceCheckUtils]: 25: Hoare triple {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,161 INFO L290 TraceCheckUtils]: 26: Hoare triple {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} is VALID [2022-04-27 21:06:10,162 INFO L290 TraceCheckUtils]: 27: Hoare triple {5124#(and (= |main_~#v~0.offset| 0) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) (+ |main_~#v~0.offset| 4))) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (not (= (+ |main_~#v~0.offset| 4 (* main_~i~0 4)) 0)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5125#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,162 INFO L290 TraceCheckUtils]: 28: Hoare triple {5125#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5125#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,163 INFO L290 TraceCheckUtils]: 29: Hoare triple {5125#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5125#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} is VALID [2022-04-27 21:06:10,163 INFO L290 TraceCheckUtils]: 30: Hoare triple {5125#(and (= |main_~#v~0.offset| 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) 0) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {5126#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} is VALID [2022-04-27 21:06:10,164 INFO L290 TraceCheckUtils]: 31: Hoare triple {5126#(and (= |main_~#v~0.offset| 0) (= (+ (- 1) main_~k~0) 0) (<= (+ (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4) (- 4))) 1) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~k~0 4)))))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5127#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:06:10,165 INFO L272 TraceCheckUtils]: 32: Hoare triple {5127#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5128#(not (= |__VERIFIER_assert_#in~cond| 0))} is VALID [2022-04-27 21:06:10,165 INFO L290 TraceCheckUtils]: 33: Hoare triple {5128#(not (= |__VERIFIER_assert_#in~cond| 0))} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5129#(not (= __VERIFIER_assert_~cond 0))} is VALID [2022-04-27 21:06:10,166 INFO L290 TraceCheckUtils]: 34: Hoare triple {5129#(not (= __VERIFIER_assert_~cond 0))} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5109#false} is VALID [2022-04-27 21:06:10,166 INFO L290 TraceCheckUtils]: 35: Hoare triple {5109#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5109#false} is VALID [2022-04-27 21:06:10,166 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2022-04-27 21:06:10,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2022-04-27 21:06:10,166 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [10205637] [2022-04-27 21:06:10,166 INFO L157 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [10205637] provided 0 perfect and 1 imperfect interpolant sequences [2022-04-27 21:06:10,167 INFO L333 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [521352484] [2022-04-27 21:06:10,167 INFO L93 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2022-04-27 21:06:10,167 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2022-04-27 21:06:10,167 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2022-04-27 21:06:10,172 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2022-04-27 21:06:10,173 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2022-04-27 21:06:10,231 INFO L228 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2022-04-27 21:06:10,231 INFO L229 tOrderPrioritization]: Conjunction of SSA is unsat [2022-04-27 21:06:10,232 INFO L263 TraceCheckSpWp]: Trace formula consists of 149 conjuncts, 31 conjunts are in the unsatisfiable core [2022-04-27 21:06:10,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2022-04-27 21:06:10,249 INFO L286 TraceCheckSpWp]: Computing forward predicates... [2022-04-27 21:06:10,550 INFO L356 Elim1Store]: treesize reduction 40, result has 23.1 percent of original size [2022-04-27 21:06:10,550 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 40 treesize of output 30 [2022-04-27 21:06:10,942 INFO L356 Elim1Store]: treesize reduction 109, result has 9.2 percent of original size [2022-04-27 21:06:10,943 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 49 treesize of output 30 [2022-04-27 21:06:11,664 INFO L356 Elim1Store]: treesize reduction 76, result has 22.4 percent of original size [2022-04-27 21:06:11,664 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 32 treesize of output 34 [2022-04-27 21:06:12,086 INFO L356 Elim1Store]: treesize reduction 36, result has 7.7 percent of original size [2022-04-27 21:06:12,086 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 13 [2022-04-27 21:06:12,214 INFO L272 TraceCheckUtils]: 0: Hoare triple {5108#true} [90] ULTIMATE.startENTRY-->ULTIMATE.initENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:12,214 INFO L290 TraceCheckUtils]: 1: Hoare triple {5108#true} [92] ULTIMATE.initENTRY-->ULTIMATE.initFINAL: Formula: (let ((.cse0 (select |v_#memory_int_10| 1))) (and (= 19 (select |v_#length_3| 2)) (= (select |v_#valid_5| 1) 1) (= (select .cse0 1) 0) (= 2 (select |v_#length_3| 1)) (< 0 |v_#StackHeapBarrier_2|) (= 48 (select .cse0 0)) (= |v_#NULL.base_1| 0) (= (select |v_#valid_5| 2) 1) (= 1 (select |v_#valid_5| 3)) (= (select |v_#valid_5| 0) 0) (= |v_#NULL.offset_1| 0) (= 12 (select |v_#length_3| 3)))) InVars {#memory_int=|v_#memory_int_10|, #StackHeapBarrier=|v_#StackHeapBarrier_2|, #length=|v_#length_3|, #valid=|v_#valid_5|} OutVars{#StackHeapBarrier=|v_#StackHeapBarrier_2|, #valid=|v_#valid_5|, #memory_int=|v_#memory_int_10|, #NULL.offset=|v_#NULL.offset_1|, #length=|v_#length_3|, #NULL.base=|v_#NULL.base_1|} AuxVars[] AssignedVars[#NULL.offset, #NULL.base] {5108#true} is VALID [2022-04-27 21:06:12,214 INFO L290 TraceCheckUtils]: 2: Hoare triple {5108#true} [95] ULTIMATE.initFINAL-->ULTIMATE.initEXIT: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:12,214 INFO L284 TraceCheckUtils]: 3: Hoare quadruple {5108#true} {5108#true} [127] ULTIMATE.initEXIT-->L-1: AOR: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] LVA: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:12,214 INFO L272 TraceCheckUtils]: 4: Hoare triple {5108#true} [91] L-1-->mainENTRY: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 5: Hoare triple {5108#true} [94] mainENTRY-->L17-3: Formula: (and (= |v_#valid_1| (store |v_#valid_2| |v_main_~#v~0.base_1| 1)) (= v_main_~j~0_1 0) (not (= |v_main_~#v~0.base_1| 0)) (= |v_main_#t~nondet4_2| v_main_~SIZE~0_1) (= (store |v_#length_2| |v_main_~#v~0.base_1| (* (mod v_main_~SIZE~0_1 4294967296) 4)) |v_#length_1|) (< |v_#StackHeapBarrier_1| |v_main_~#v~0.base_1|) (= |v_main_~#v~0.offset_1| 0) (= (select |v_#valid_2| |v_main_~#v~0.base_1|) 0)) InVars {main_#t~nondet4=|v_main_#t~nondet4_2|, #StackHeapBarrier=|v_#StackHeapBarrier_1|, #length=|v_#length_2|, #valid=|v_#valid_2|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_1|, main_~SIZE~0=v_main_~SIZE~0_1, #StackHeapBarrier=|v_#StackHeapBarrier_1|, main_~k~0=v_main_~k~0_1, main_~j~0=v_main_~j~0_1, #valid=|v_#valid_1|, main_~i~0=v_main_~i~0_1, main_~key~0=v_main_~key~0_1, main_~#v~0.offset=|v_main_~#v~0.offset_1|, #length=|v_#length_1|} AuxVars[] AssignedVars[main_~#v~0.base, main_~SIZE~0, main_#t~nondet4, main_~k~0, main_~j~0, #valid, main_~i~0, main_~key~0, main_~#v~0.offset, #length] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 6: Hoare triple {5108#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 7: Hoare triple {5108#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 8: Hoare triple {5108#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 9: Hoare triple {5108#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 10: Hoare triple {5108#true} [98] L17-3-->L17-2: Formula: (and (<= |v_main_#t~nondet6_2| 2147483647) (< (mod v_main_~j~0_4 4294967296) (mod v_main_~SIZE~0_3 4294967296)) (= (store |v_#memory_int_2| |v_main_~#v~0.base_4| (store (select |v_#memory_int_2| |v_main_~#v~0.base_4|) (+ (* v_main_~j~0_4 4) |v_main_~#v~0.offset_4|) |v_main_#t~nondet6_2|)) |v_#memory_int_1|) (<= 0 (+ |v_main_#t~nondet6_2| 2147483648))) InVars {main_~#v~0.base=|v_main_~#v~0.base_4|, main_~SIZE~0=v_main_~SIZE~0_3, main_#t~nondet6=|v_main_#t~nondet6_2|, main_~j~0=v_main_~j~0_4, #memory_int=|v_#memory_int_2|, main_~#v~0.offset=|v_main_~#v~0.offset_4|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_4|, #memory_int=|v_#memory_int_1|, main_~SIZE~0=v_main_~SIZE~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_4|, main_~j~0=v_main_~j~0_4} AuxVars[] AssignedVars[main_#t~nondet6, #memory_int] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 11: Hoare triple {5108#true} [100] L17-2-->L17-3: Formula: (= v_main_~j~0_5 (+ v_main_~j~0_6 1)) InVars {main_~j~0=v_main_~j~0_6} OutVars{main_#t~post5=|v_main_#t~post5_1|, main_~j~0=v_main_~j~0_5} AuxVars[] AssignedVars[main_~j~0, main_#t~post5] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 12: Hoare triple {5108#true} [97] L17-3-->L17-4: Formula: (not (< (mod v_main_~j~0_3 4294967296) (mod v_main_~SIZE~0_2 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} OutVars{main_~SIZE~0=v_main_~SIZE~0_2, main_~j~0=v_main_~j~0_3} AuxVars[] AssignedVars[] {5108#true} is VALID [2022-04-27 21:06:12,215 INFO L290 TraceCheckUtils]: 13: Hoare triple {5108#true} [99] L17-4-->L19-3: Formula: (= v_main_~j~0_7 1) InVars {} OutVars{main_~j~0=v_main_~j~0_7} AuxVars[] AssignedVars[main_~j~0] {5173#(= main_~j~0 1)} is VALID [2022-04-27 21:06:12,216 INFO L290 TraceCheckUtils]: 14: Hoare triple {5173#(= main_~j~0 1)} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5177#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} is VALID [2022-04-27 21:06:12,216 INFO L290 TraceCheckUtils]: 15: Hoare triple {5177#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5181#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) |main_#t~short10|)} is VALID [2022-04-27 21:06:12,217 INFO L290 TraceCheckUtils]: 16: Hoare triple {5181#(and (= (+ (- 1) main_~j~0) main_~i~0) (= main_~j~0 1) |main_#t~short10|)} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5185#(and (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (= main_~j~0 (+ main_~i~0 1)))} is VALID [2022-04-27 21:06:12,218 INFO L290 TraceCheckUtils]: 17: Hoare triple {5185#(and (= main_~j~0 1) (or (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (not |main_#t~short10|)) (= main_~j~0 (+ main_~i~0 1)))} [117] L22-3-->L22-5: Formula: (and (= (+ (- 1) v_main_~i~0_6) v_main_~i~0_5) |v_main_#t~short10_8| (= |v_#memory_int_5| (store |v_#memory_int_6| |v_main_~#v~0.base_7| (let ((.cse0 (select |v_#memory_int_6| |v_main_~#v~0.base_7|)) (.cse1 (* v_main_~i~0_6 4))) (store .cse0 (+ |v_main_~#v~0.offset_7| .cse1 4) (select .cse0 (+ |v_main_~#v~0.offset_7| .cse1))))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_7|, main_~i~0=v_main_~i~0_6, #memory_int=|v_#memory_int_6|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~short10=|v_main_#t~short10_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_7|, main_#t~mem11=|v_main_#t~mem11_1|, main_~i~0=v_main_~i~0_5, #memory_int=|v_#memory_int_5|, main_~#v~0.offset=|v_main_~#v~0.offset_7|, main_#t~mem9=|v_main_#t~mem9_3|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem11, main_~i~0, #memory_int, main_#t~mem9] {5189#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 21:06:12,218 INFO L290 TraceCheckUtils]: 18: Hoare triple {5189#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5193#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} is VALID [2022-04-27 21:06:12,219 INFO L290 TraceCheckUtils]: 19: Hoare triple {5193#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (<= main_~j~0 (+ main_~i~0 2)) (or (and (<= 0 main_~i~0) |main_#t~short10|) (and (not (<= 0 main_~i~0)) (not |main_#t~short10|))))} [112] L22-1-->L22-3: Formula: (not |v_main_#t~short10_4|) InVars {main_#t~short10=|v_main_#t~short10_4|} OutVars{main_#t~short10=|v_main_#t~short10_4|} AuxVars[] AssignedVars[] {5197#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 21:06:12,219 INFO L290 TraceCheckUtils]: 20: Hoare triple {5197#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5197#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} is VALID [2022-04-27 21:06:12,220 INFO L290 TraceCheckUtils]: 21: Hoare triple {5197#(and (< main_~key~0 (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))) (<= (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (= main_~j~0 1) (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 2)))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5204#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} is VALID [2022-04-27 21:06:12,221 INFO L290 TraceCheckUtils]: 22: Hoare triple {5204#(and (= main_~j~0 1) (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4)))) (<= main_~j~0 (+ main_~i~0 2)))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5208#(and (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))) (= (+ (- 1) main_~j~0) 1))} is VALID [2022-04-27 21:06:12,222 INFO L290 TraceCheckUtils]: 23: Hoare triple {5208#(and (exists ((main_~i~0 Int)) (and (< main_~i~0 0) (<= main_~j~0 (+ main_~i~0 3)) (< (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4 (* main_~i~0 4))) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~j~0 4) (- 4)))))) (= (+ (- 1) main_~j~0) 1))} [103] L19-3-->L22-5: Formula: (and (< (mod v_main_~j~0_9 4294967296) (mod v_main_~SIZE~0_5 4294967296)) (= (select (select |v_#memory_int_3| |v_main_~#v~0.base_5|) (+ (* v_main_~j~0_9 4) |v_main_~#v~0.offset_5|)) v_main_~key~0_2) (= v_main_~i~0_2 (+ (- 1) v_main_~j~0_9))) InVars {main_~#v~0.base=|v_main_~#v~0.base_5|, #memory_int=|v_#memory_int_3|, main_~SIZE~0=v_main_~SIZE~0_5, main_~#v~0.offset=|v_main_~#v~0.offset_5|, main_~j~0=v_main_~j~0_9} OutVars{main_~#v~0.base=|v_main_~#v~0.base_5|, main_~SIZE~0=v_main_~SIZE~0_5, main_~j~0=v_main_~j~0_9, main_~i~0=v_main_~i~0_2, #memory_int=|v_#memory_int_3|, main_#t~mem8=|v_main_#t~mem8_1|, main_~key~0=v_main_~key~0_2, main_~#v~0.offset=|v_main_~#v~0.offset_5|} AuxVars[] AssignedVars[main_~i~0, main_#t~mem8, main_~key~0] {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} is VALID [2022-04-27 21:06:12,223 INFO L290 TraceCheckUtils]: 24: Hoare triple {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} [106] L22-5-->L22-1: Formula: (let ((.cse0 (<= 0 v_main_~i~0_3))) (or (and .cse0 |v_main_#t~short10_1|) (and (not |v_main_#t~short10_1|) (not .cse0)))) InVars {main_~i~0=v_main_~i~0_3} OutVars{main_~i~0=v_main_~i~0_3, main_#t~short10=|v_main_#t~short10_1|} AuxVars[] AssignedVars[main_#t~short10] {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} is VALID [2022-04-27 21:06:12,223 INFO L290 TraceCheckUtils]: 25: Hoare triple {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} [111] L22-1-->L22-3: Formula: (and (let ((.cse0 (< v_main_~key~0_3 |v_main_#t~mem9_1|))) (or (and (not .cse0) (not |v_main_#t~short10_2|)) (and .cse0 |v_main_#t~short10_2|))) |v_main_#t~short10_3| (= (select (select |v_#memory_int_4| |v_main_~#v~0.base_6|) (+ (* v_main_~i~0_4 4) |v_main_~#v~0.offset_6|)) |v_main_#t~mem9_1|)) InVars {main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_3|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_6|, main_#t~short10=|v_main_#t~short10_2|, main_~i~0=v_main_~i~0_4, #memory_int=|v_#memory_int_4|, main_~key~0=v_main_~key~0_3, main_~#v~0.offset=|v_main_~#v~0.offset_6|, main_#t~mem9=|v_main_#t~mem9_1|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} is VALID [2022-04-27 21:06:12,224 INFO L290 TraceCheckUtils]: 26: Hoare triple {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} [116] L22-3-->L22-6: Formula: (not |v_main_#t~short10_6|) InVars {main_#t~short10=|v_main_#t~short10_6|} OutVars{main_#t~mem9=|v_main_#t~mem9_2|} AuxVars[] AssignedVars[main_#t~short10, main_#t~mem9] {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} is VALID [2022-04-27 21:06:12,225 INFO L290 TraceCheckUtils]: 27: Hoare triple {5212#(and (= main_~i~0 1) (exists ((v_main_~i~0_25 Int)) (and (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| (* main_~i~0 4)))) (< v_main_~i~0_25 0) (<= main_~i~0 (+ v_main_~i~0_25 2)))))} [110] L22-6-->L19-2: Formula: (= (store |v_#memory_int_8| |v_main_~#v~0.base_8| (store (select |v_#memory_int_8| |v_main_~#v~0.base_8|) (+ (* v_main_~i~0_7 4) |v_main_~#v~0.offset_8| 4) v_main_~key~0_4)) |v_#memory_int_7|) InVars {main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_8|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} OutVars{main_~#v~0.base=|v_main_~#v~0.base_8|, #memory_int=|v_#memory_int_7|, main_~i~0=v_main_~i~0_7, main_~key~0=v_main_~key~0_4, main_~#v~0.offset=|v_main_~#v~0.offset_8|} AuxVars[] AssignedVars[#memory_int] {5225#(exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1))))} is VALID [2022-04-27 21:06:12,225 INFO L290 TraceCheckUtils]: 28: Hoare triple {5225#(exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1))))} [115] L19-2-->L19-3: Formula: (= v_main_~j~0_10 (+ v_main_~j~0_11 1)) InVars {main_~j~0=v_main_~j~0_11} OutVars{main_~j~0=v_main_~j~0_10, main_#t~post7=|v_main_#t~post7_1|} AuxVars[] AssignedVars[main_~j~0, main_#t~post7] {5225#(exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1))))} is VALID [2022-04-27 21:06:12,225 INFO L290 TraceCheckUtils]: 29: Hoare triple {5225#(exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1))))} [102] L19-3-->L19-4: Formula: (not (< (mod v_main_~j~0_8 4294967296) (mod v_main_~SIZE~0_4 4294967296))) InVars {main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} OutVars{main_~SIZE~0=v_main_~SIZE~0_4, main_~j~0=v_main_~j~0_8} AuxVars[] AssignedVars[] {5225#(exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1))))} is VALID [2022-04-27 21:06:12,226 INFO L290 TraceCheckUtils]: 30: Hoare triple {5225#(exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1))))} [104] L19-4-->L28-3: Formula: (= v_main_~k~0_2 1) InVars {} OutVars{main_~k~0=v_main_~k~0_2} AuxVars[] AssignedVars[main_~k~0] {5235#(and (exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1)))) (= main_~k~0 1))} is VALID [2022-04-27 21:06:12,227 INFO L290 TraceCheckUtils]: 31: Hoare triple {5235#(and (exists ((v_main_~i~0_25 Int)) (and (< v_main_~i~0_25 0) (< (select (select |#memory_int| |main_~#v~0.base|) (+ (* v_main_~i~0_25 4) |main_~#v~0.offset| 4)) (select (select |#memory_int| |main_~#v~0.base|) (+ |main_~#v~0.offset| 4))) (<= 0 (+ v_main_~i~0_25 1)))) (= main_~k~0 1))} [109] L28-3-->L29: Formula: (let ((.cse0 (select |v_#memory_int_9| |v_main_~#v~0.base_9|)) (.cse1 (* v_main_~k~0_4 4))) (and (< (mod v_main_~k~0_4 4294967296) (mod v_main_~SIZE~0_7 4294967296)) (= (select .cse0 (+ (- 4) |v_main_~#v~0.offset_9| .cse1)) |v_main_#t~mem13_1|) (= |v_main_#t~mem14_1| (select .cse0 (+ |v_main_~#v~0.offset_9| .cse1))))) InVars {main_~#v~0.base=|v_main_~#v~0.base_9|, #memory_int=|v_#memory_int_9|, main_~SIZE~0=v_main_~SIZE~0_7, main_~#v~0.offset=|v_main_~#v~0.offset_9|, main_~k~0=v_main_~k~0_4} OutVars{main_~#v~0.base=|v_main_~#v~0.base_9|, main_#t~mem13=|v_main_#t~mem13_1|, main_~SIZE~0=v_main_~SIZE~0_7, main_#t~mem14=|v_main_#t~mem14_1|, main_~k~0=v_main_~k~0_4, #memory_int=|v_#memory_int_9|, main_~#v~0.offset=|v_main_~#v~0.offset_9|} AuxVars[] AssignedVars[main_#t~mem13, main_#t~mem14] {5127#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} is VALID [2022-04-27 21:06:12,227 INFO L272 TraceCheckUtils]: 32: Hoare triple {5127#(<= (+ |main_#t~mem13| 1) |main_#t~mem14|)} [114] L29-->__VERIFIER_assertENTRY: Formula: (= (ite (<= |v_main_#t~mem13_4| |v_main_#t~mem14_4|) 1 0) |v___VERIFIER_assert_#in~condInParam_1|) InVars {main_#t~mem13=|v_main_#t~mem13_4|, main_#t~mem14=|v_main_#t~mem14_4|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~condInParam_1|} AuxVars[] AssignedVars[main_#t~mem13, __VERIFIER_assert_#in~cond, main_#t~mem14] {5242#(<= 1 |__VERIFIER_assert_#in~cond|)} is VALID [2022-04-27 21:06:12,228 INFO L290 TraceCheckUtils]: 33: Hoare triple {5242#(<= 1 |__VERIFIER_assert_#in~cond|)} [120] __VERIFIER_assertENTRY-->L6: Formula: (= v___VERIFIER_assert_~cond_2 |v___VERIFIER_assert_#in~cond_1|) InVars {__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|} OutVars{__VERIFIER_assert_#in~cond=|v___VERIFIER_assert_#in~cond_1|, __VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_2} AuxVars[] AssignedVars[__VERIFIER_assert_~cond] {5246#(<= 1 __VERIFIER_assert_~cond)} is VALID [2022-04-27 21:06:12,228 INFO L290 TraceCheckUtils]: 34: Hoare triple {5246#(<= 1 __VERIFIER_assert_~cond)} [122] L6-->L7: Formula: (= v___VERIFIER_assert_~cond_3 0) InVars {__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} OutVars{__VERIFIER_assert_~cond=v___VERIFIER_assert_~cond_3} AuxVars[] AssignedVars[] {5109#false} is VALID [2022-04-27 21:06:12,228 INFO L290 TraceCheckUtils]: 35: Hoare triple {5109#false} [124] L7-->__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION: Formula: true InVars {} OutVars{} AuxVars[] AssignedVars[] {5109#false} is VALID [2022-04-27 21:06:12,228 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2022-04-27 21:06:12,228 INFO L328 TraceCheckSpWp]: Computing backward predicates... [2022-04-27 21:06:16,209 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 85 treesize of output 77 [2022-04-27 21:06:16,355 INFO L356 Elim1Store]: treesize reduction 27, result has 27.0 percent of original size [2022-04-27 21:06:16,355 INFO L390 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 3 new quantified variables, introduced 3 case distinctions, treesize of input 21667 treesize of output 20897